1/*
 2 * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 *
 8 * This program is distributed in the hope that it will be useful,
 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
15#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
16
17/* INFRACFG resets */
18#define MT2701_INFRA_EMI_REG_RST		0
19#define MT2701_INFRA_DRAMC0_A0_RST		1
20#define MT2701_INFRA_FHCTL_RST			2
21#define MT2701_INFRA_APCIRQ_EINT_RST		3
22#define MT2701_INFRA_APXGPT_RST			4
23#define MT2701_INFRA_SCPSYS_RST			5
24#define MT2701_INFRA_KP_RST			6
25#define MT2701_INFRA_PMIC_WRAP_RST		7
26#define MT2701_INFRA_MIPI_RST			8
27#define MT2701_INFRA_IRRX_RST			9
28#define MT2701_INFRA_CEC_RST			10
29#define MT2701_INFRA_EMI_RST			32
30#define MT2701_INFRA_DRAMC0_RST			34
31#define MT2701_INFRA_TRNG_RST			37
32#define MT2701_INFRA_SYSIRQ_RST			38
33
34/*  PERICFG resets */
35#define MT2701_PERI_UART0_SW_RST		0
36#define MT2701_PERI_UART1_SW_RST		1
37#define MT2701_PERI_UART2_SW_RST		2
38#define MT2701_PERI_UART3_SW_RST		3
39#define MT2701_PERI_GCPU_SW_RST			5
40#define MT2701_PERI_BTIF_SW_RST			6
41#define MT2701_PERI_PWM_SW_RST			8
42#define MT2701_PERI_AUXADC_SW_RST		10
43#define MT2701_PERI_DMA_SW_RST			11
44#define MT2701_PERI_NFI_SW_RST			14
45#define MT2701_PERI_NLI_SW_RST			15
46#define MT2701_PERI_THERM_SW_RST		16
47#define MT2701_PERI_MSDC2_SW_RST		17
48#define MT2701_PERI_MSDC0_SW_RST		19
49#define MT2701_PERI_MSDC1_SW_RST		20
50#define MT2701_PERI_I2C0_SW_RST			22
51#define MT2701_PERI_I2C1_SW_RST			23
52#define MT2701_PERI_I2C2_SW_RST			24
53#define MT2701_PERI_I2C3_SW_RST			25
54#define MT2701_PERI_USB_SW_RST			28
55#define MT2701_PERI_ETH_SW_RST			29
56#define MT2701_PERI_SPI0_SW_RST			33
57
58/* TOPRGU resets */
59#define MT2701_TOPRGU_INFRA_RST			0
60#define MT2701_TOPRGU_MM_RST			1
61#define MT2701_TOPRGU_MFG_RST			2
62#define MT2701_TOPRGU_ETHDMA_RST		3
63#define MT2701_TOPRGU_VDEC_RST			4
64#define MT2701_TOPRGU_VENC_IMG_RST		5
65#define MT2701_TOPRGU_DDRPHY_RST		6
66#define MT2701_TOPRGU_MD_RST			7
67#define MT2701_TOPRGU_INFRA_AO_RST		8
68#define MT2701_TOPRGU_CONN_RST			9
69#define MT2701_TOPRGU_APMIXED_RST		10
70#define MT2701_TOPRGU_HIFSYS_RST		11
71#define MT2701_TOPRGU_CONN_MCU_RST		12
72#define MT2701_TOPRGU_BDP_DISP_RST		13
73
74/* HIFSYS resets */
75#define MT2701_HIFSYS_UHOST0_RST		3
76#define MT2701_HIFSYS_UHOST1_RST		4
77#define MT2701_HIFSYS_UPHY0_RST			21
78#define MT2701_HIFSYS_UPHY1_RST			22
79#define MT2701_HIFSYS_PCIE0_RST			24
80#define MT2701_HIFSYS_PCIE1_RST			25
81#define MT2701_HIFSYS_PCIE2_RST			26
82
83/* ETHSYS resets */
84#define MT2701_ETHSYS_SYS_RST			0
85#define MT2701_ETHSYS_MCM_RST			2
86#define MT2701_ETHSYS_FE_RST			6
87#define MT2701_ETHSYS_GMAC_RST			23
88#define MT2701_ETHSYS_PPE_RST			31
89
90#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */