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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
8 */
9
10#include <linux/err.h>
11#include <linux/mm.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/export.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/msi.h>
19#include <linux/smp.h>
20#include <linux/errno.h>
21#include <linux/io.h>
22#include <linux/acpi_iort.h>
23#include <linux/slab.h>
24#include <linux/irqdomain.h>
25#include <linux/of_irq.h>
26
27#include "pci.h"
28
29static int pci_msi_enable = 1;
30int pci_msi_ignore_mask;
31
32#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33
34#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
35static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
36{
37 struct irq_domain *domain;
38
39 domain = dev_get_msi_domain(&dev->dev);
40 if (domain && irq_domain_is_hierarchy(domain))
41 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
42
43 return arch_setup_msi_irqs(dev, nvec, type);
44}
45
46static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
47{
48 struct irq_domain *domain;
49
50 domain = dev_get_msi_domain(&dev->dev);
51 if (domain && irq_domain_is_hierarchy(domain))
52 msi_domain_free_irqs(domain, &dev->dev);
53 else
54 arch_teardown_msi_irqs(dev);
55}
56#else
57#define pci_msi_setup_msi_irqs arch_setup_msi_irqs
58#define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
59#endif
60
61/* Arch hooks */
62
63int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
64{
65 struct msi_controller *chip = dev->bus->msi;
66 int err;
67
68 if (!chip || !chip->setup_irq)
69 return -EINVAL;
70
71 err = chip->setup_irq(chip, dev, desc);
72 if (err < 0)
73 return err;
74
75 irq_set_chip_data(desc->irq, chip);
76
77 return 0;
78}
79
80void __weak arch_teardown_msi_irq(unsigned int irq)
81{
82 struct msi_controller *chip = irq_get_chip_data(irq);
83
84 if (!chip || !chip->teardown_irq)
85 return;
86
87 chip->teardown_irq(chip, irq);
88}
89
90int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
91{
92 struct msi_controller *chip = dev->bus->msi;
93 struct msi_desc *entry;
94 int ret;
95
96 if (chip && chip->setup_irqs)
97 return chip->setup_irqs(chip, dev, nvec, type);
98 /*
99 * If an architecture wants to support multiple MSI, it needs to
100 * override arch_setup_msi_irqs()
101 */
102 if (type == PCI_CAP_ID_MSI && nvec > 1)
103 return 1;
104
105 for_each_pci_msi_entry(entry, dev) {
106 ret = arch_setup_msi_irq(dev, entry);
107 if (ret < 0)
108 return ret;
109 if (ret > 0)
110 return -ENOSPC;
111 }
112
113 return 0;
114}
115
116/*
117 * We have a default implementation available as a separate non-weak
118 * function, as it is used by the Xen x86 PCI code
119 */
120void default_teardown_msi_irqs(struct pci_dev *dev)
121{
122 int i;
123 struct msi_desc *entry;
124
125 for_each_pci_msi_entry(entry, dev)
126 if (entry->irq)
127 for (i = 0; i < entry->nvec_used; i++)
128 arch_teardown_msi_irq(entry->irq + i);
129}
130
131void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
132{
133 return default_teardown_msi_irqs(dev);
134}
135
136static void default_restore_msi_irq(struct pci_dev *dev, int irq)
137{
138 struct msi_desc *entry;
139
140 entry = NULL;
141 if (dev->msix_enabled) {
142 for_each_pci_msi_entry(entry, dev) {
143 if (irq == entry->irq)
144 break;
145 }
146 } else if (dev->msi_enabled) {
147 entry = irq_get_msi_desc(irq);
148 }
149
150 if (entry)
151 __pci_write_msi_msg(entry, &entry->msg);
152}
153
154void __weak arch_restore_msi_irqs(struct pci_dev *dev)
155{
156 return default_restore_msi_irqs(dev);
157}
158
159static inline __attribute_const__ u32 msi_mask(unsigned x)
160{
161 /* Don't shift by >= width of type */
162 if (x >= 5)
163 return 0xffffffff;
164 return (1 << (1 << x)) - 1;
165}
166
167/*
168 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
169 * mask all MSI interrupts by clearing the MSI enable bit does not work
170 * reliably as devices without an INTx disable bit will then generate a
171 * level IRQ which will never be cleared.
172 */
173u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
174{
175 u32 mask_bits = desc->masked;
176
177 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
178 return 0;
179
180 mask_bits &= ~mask;
181 mask_bits |= flag;
182 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
183 mask_bits);
184
185 return mask_bits;
186}
187
188static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
189{
190 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
191}
192
193static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
194{
195 if (desc->msi_attrib.is_virtual)
196 return NULL;
197
198 return desc->mask_base +
199 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
200}
201
202/*
203 * This internal function does not flush PCI writes to the device.
204 * All users must ensure that they read from the device before either
205 * assuming that the device state is up to date, or returning out of this
206 * file. This saves a few milliseconds when initialising devices with lots
207 * of MSI-X interrupts.
208 */
209u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
210{
211 u32 mask_bits = desc->masked;
212 void __iomem *desc_addr;
213
214 if (pci_msi_ignore_mask)
215 return 0;
216 desc_addr = pci_msix_desc_addr(desc);
217 if (!desc_addr)
218 return 0;
219
220 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
221 if (flag)
222 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
223
224 writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
225
226 return mask_bits;
227}
228
229static void msix_mask_irq(struct msi_desc *desc, u32 flag)
230{
231 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
232}
233
234static void msi_set_mask_bit(struct irq_data *data, u32 flag)
235{
236 struct msi_desc *desc = irq_data_get_msi_desc(data);
237
238 if (desc->msi_attrib.is_msix) {
239 msix_mask_irq(desc, flag);
240 readl(desc->mask_base); /* Flush write to device */
241 } else {
242 unsigned offset = data->irq - desc->irq;
243 msi_mask_irq(desc, 1 << offset, flag << offset);
244 }
245}
246
247/**
248 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
249 * @data: pointer to irqdata associated to that interrupt
250 */
251void pci_msi_mask_irq(struct irq_data *data)
252{
253 msi_set_mask_bit(data, 1);
254}
255EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
256
257/**
258 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
259 * @data: pointer to irqdata associated to that interrupt
260 */
261void pci_msi_unmask_irq(struct irq_data *data)
262{
263 msi_set_mask_bit(data, 0);
264}
265EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
266
267void default_restore_msi_irqs(struct pci_dev *dev)
268{
269 struct msi_desc *entry;
270
271 for_each_pci_msi_entry(entry, dev)
272 default_restore_msi_irq(dev, entry->irq);
273}
274
275void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
276{
277 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
278
279 BUG_ON(dev->current_state != PCI_D0);
280
281 if (entry->msi_attrib.is_msix) {
282 void __iomem *base = pci_msix_desc_addr(entry);
283
284 if (!base) {
285 WARN_ON(1);
286 return;
287 }
288
289 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
290 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
291 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
292 } else {
293 int pos = dev->msi_cap;
294 u16 data;
295
296 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
297 &msg->address_lo);
298 if (entry->msi_attrib.is_64) {
299 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
300 &msg->address_hi);
301 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
302 } else {
303 msg->address_hi = 0;
304 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
305 }
306 msg->data = data;
307 }
308}
309
310void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
311{
312 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
313
314 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
315 /* Don't touch the hardware now */
316 } else if (entry->msi_attrib.is_msix) {
317 void __iomem *base = pci_msix_desc_addr(entry);
318
319 if (!base)
320 goto skip;
321
322 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
323 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
324 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
325 } else {
326 int pos = dev->msi_cap;
327 u16 msgctl;
328
329 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
330 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
331 msgctl |= entry->msi_attrib.multiple << 4;
332 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
333
334 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
335 msg->address_lo);
336 if (entry->msi_attrib.is_64) {
337 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
338 msg->address_hi);
339 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
340 msg->data);
341 } else {
342 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
343 msg->data);
344 }
345 }
346
347skip:
348 entry->msg = *msg;
349
350 if (entry->write_msi_msg)
351 entry->write_msi_msg(entry, entry->write_msi_msg_data);
352
353}
354
355void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
356{
357 struct msi_desc *entry = irq_get_msi_desc(irq);
358
359 __pci_write_msi_msg(entry, msg);
360}
361EXPORT_SYMBOL_GPL(pci_write_msi_msg);
362
363static void free_msi_irqs(struct pci_dev *dev)
364{
365 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
366 struct msi_desc *entry, *tmp;
367 struct attribute **msi_attrs;
368 struct device_attribute *dev_attr;
369 int i, count = 0;
370
371 for_each_pci_msi_entry(entry, dev)
372 if (entry->irq)
373 for (i = 0; i < entry->nvec_used; i++)
374 BUG_ON(irq_has_action(entry->irq + i));
375
376 pci_msi_teardown_msi_irqs(dev);
377
378 list_for_each_entry_safe(entry, tmp, msi_list, list) {
379 if (entry->msi_attrib.is_msix) {
380 if (list_is_last(&entry->list, msi_list))
381 iounmap(entry->mask_base);
382 }
383
384 list_del(&entry->list);
385 free_msi_entry(entry);
386 }
387
388 if (dev->msi_irq_groups) {
389 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
390 msi_attrs = dev->msi_irq_groups[0]->attrs;
391 while (msi_attrs[count]) {
392 dev_attr = container_of(msi_attrs[count],
393 struct device_attribute, attr);
394 kfree(dev_attr->attr.name);
395 kfree(dev_attr);
396 ++count;
397 }
398 kfree(msi_attrs);
399 kfree(dev->msi_irq_groups[0]);
400 kfree(dev->msi_irq_groups);
401 dev->msi_irq_groups = NULL;
402 }
403}
404
405static void pci_intx_for_msi(struct pci_dev *dev, int enable)
406{
407 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
408 pci_intx(dev, enable);
409}
410
411static void __pci_restore_msi_state(struct pci_dev *dev)
412{
413 u16 control;
414 struct msi_desc *entry;
415
416 if (!dev->msi_enabled)
417 return;
418
419 entry = irq_get_msi_desc(dev->irq);
420
421 pci_intx_for_msi(dev, 0);
422 pci_msi_set_enable(dev, 0);
423 arch_restore_msi_irqs(dev);
424
425 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
426 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
427 entry->masked);
428 control &= ~PCI_MSI_FLAGS_QSIZE;
429 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
430 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
431}
432
433static void __pci_restore_msix_state(struct pci_dev *dev)
434{
435 struct msi_desc *entry;
436
437 if (!dev->msix_enabled)
438 return;
439 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
440
441 /* route the table */
442 pci_intx_for_msi(dev, 0);
443 pci_msix_clear_and_set_ctrl(dev, 0,
444 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
445
446 arch_restore_msi_irqs(dev);
447 for_each_pci_msi_entry(entry, dev)
448 msix_mask_irq(entry, entry->masked);
449
450 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
451}
452
453void pci_restore_msi_state(struct pci_dev *dev)
454{
455 __pci_restore_msi_state(dev);
456 __pci_restore_msix_state(dev);
457}
458EXPORT_SYMBOL_GPL(pci_restore_msi_state);
459
460static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
461 char *buf)
462{
463 struct msi_desc *entry;
464 unsigned long irq;
465 int retval;
466
467 retval = kstrtoul(attr->attr.name, 10, &irq);
468 if (retval)
469 return retval;
470
471 entry = irq_get_msi_desc(irq);
472 if (entry)
473 return sprintf(buf, "%s\n",
474 entry->msi_attrib.is_msix ? "msix" : "msi");
475
476 return -ENODEV;
477}
478
479static int populate_msi_sysfs(struct pci_dev *pdev)
480{
481 struct attribute **msi_attrs;
482 struct attribute *msi_attr;
483 struct device_attribute *msi_dev_attr;
484 struct attribute_group *msi_irq_group;
485 const struct attribute_group **msi_irq_groups;
486 struct msi_desc *entry;
487 int ret = -ENOMEM;
488 int num_msi = 0;
489 int count = 0;
490 int i;
491
492 /* Determine how many msi entries we have */
493 for_each_pci_msi_entry(entry, pdev)
494 num_msi += entry->nvec_used;
495 if (!num_msi)
496 return 0;
497
498 /* Dynamically create the MSI attributes for the PCI device */
499 msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
500 if (!msi_attrs)
501 return -ENOMEM;
502 for_each_pci_msi_entry(entry, pdev) {
503 for (i = 0; i < entry->nvec_used; i++) {
504 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
505 if (!msi_dev_attr)
506 goto error_attrs;
507 msi_attrs[count] = &msi_dev_attr->attr;
508
509 sysfs_attr_init(&msi_dev_attr->attr);
510 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
511 entry->irq + i);
512 if (!msi_dev_attr->attr.name)
513 goto error_attrs;
514 msi_dev_attr->attr.mode = S_IRUGO;
515 msi_dev_attr->show = msi_mode_show;
516 ++count;
517 }
518 }
519
520 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
521 if (!msi_irq_group)
522 goto error_attrs;
523 msi_irq_group->name = "msi_irqs";
524 msi_irq_group->attrs = msi_attrs;
525
526 msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
527 if (!msi_irq_groups)
528 goto error_irq_group;
529 msi_irq_groups[0] = msi_irq_group;
530
531 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
532 if (ret)
533 goto error_irq_groups;
534 pdev->msi_irq_groups = msi_irq_groups;
535
536 return 0;
537
538error_irq_groups:
539 kfree(msi_irq_groups);
540error_irq_group:
541 kfree(msi_irq_group);
542error_attrs:
543 count = 0;
544 msi_attr = msi_attrs[count];
545 while (msi_attr) {
546 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
547 kfree(msi_attr->name);
548 kfree(msi_dev_attr);
549 ++count;
550 msi_attr = msi_attrs[count];
551 }
552 kfree(msi_attrs);
553 return ret;
554}
555
556static struct msi_desc *
557msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
558{
559 struct irq_affinity_desc *masks = NULL;
560 struct msi_desc *entry;
561 u16 control;
562
563 if (affd)
564 masks = irq_create_affinity_masks(nvec, affd);
565
566 /* MSI Entry Initialization */
567 entry = alloc_msi_entry(&dev->dev, nvec, masks);
568 if (!entry)
569 goto out;
570
571 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
572
573 entry->msi_attrib.is_msix = 0;
574 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
575 entry->msi_attrib.is_virtual = 0;
576 entry->msi_attrib.entry_nr = 0;
577 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
578 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
579 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
580 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
581
582 if (control & PCI_MSI_FLAGS_64BIT)
583 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
584 else
585 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
586
587 /* Save the initial mask status */
588 if (entry->msi_attrib.maskbit)
589 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
590
591out:
592 kfree(masks);
593 return entry;
594}
595
596static int msi_verify_entries(struct pci_dev *dev)
597{
598 struct msi_desc *entry;
599
600 for_each_pci_msi_entry(entry, dev) {
601 if (!dev->no_64bit_msi || !entry->msg.address_hi)
602 continue;
603 pci_err(dev, "Device has broken 64-bit MSI but arch"
604 " tried to assign one above 4G\n");
605 return -EIO;
606 }
607 return 0;
608}
609
610/**
611 * msi_capability_init - configure device's MSI capability structure
612 * @dev: pointer to the pci_dev data structure of MSI device function
613 * @nvec: number of interrupts to allocate
614 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
615 *
616 * Setup the MSI capability structure of the device with the requested
617 * number of interrupts. A return value of zero indicates the successful
618 * setup of an entry with the new MSI IRQ. A negative return value indicates
619 * an error, and a positive return value indicates the number of interrupts
620 * which could have been allocated.
621 */
622static int msi_capability_init(struct pci_dev *dev, int nvec,
623 struct irq_affinity *affd)
624{
625 struct msi_desc *entry;
626 int ret;
627 unsigned mask;
628
629 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
630
631 entry = msi_setup_entry(dev, nvec, affd);
632 if (!entry)
633 return -ENOMEM;
634
635 /* All MSIs are unmasked by default; mask them all */
636 mask = msi_mask(entry->msi_attrib.multi_cap);
637 msi_mask_irq(entry, mask, mask);
638
639 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
640
641 /* Configure MSI capability structure */
642 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
643 if (ret) {
644 msi_mask_irq(entry, mask, ~mask);
645 free_msi_irqs(dev);
646 return ret;
647 }
648
649 ret = msi_verify_entries(dev);
650 if (ret) {
651 msi_mask_irq(entry, mask, ~mask);
652 free_msi_irqs(dev);
653 return ret;
654 }
655
656 ret = populate_msi_sysfs(dev);
657 if (ret) {
658 msi_mask_irq(entry, mask, ~mask);
659 free_msi_irqs(dev);
660 return ret;
661 }
662
663 /* Set MSI enabled bits */
664 pci_intx_for_msi(dev, 0);
665 pci_msi_set_enable(dev, 1);
666 dev->msi_enabled = 1;
667
668 pcibios_free_irq(dev);
669 dev->irq = entry->irq;
670 return 0;
671}
672
673static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
674{
675 resource_size_t phys_addr;
676 u32 table_offset;
677 unsigned long flags;
678 u8 bir;
679
680 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
681 &table_offset);
682 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
683 flags = pci_resource_flags(dev, bir);
684 if (!flags || (flags & IORESOURCE_UNSET))
685 return NULL;
686
687 table_offset &= PCI_MSIX_TABLE_OFFSET;
688 phys_addr = pci_resource_start(dev, bir) + table_offset;
689
690 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
691}
692
693static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
694 struct msix_entry *entries, int nvec,
695 struct irq_affinity *affd)
696{
697 struct irq_affinity_desc *curmsk, *masks = NULL;
698 struct msi_desc *entry;
699 int ret, i;
700 int vec_count = pci_msix_vec_count(dev);
701
702 if (affd)
703 masks = irq_create_affinity_masks(nvec, affd);
704
705 for (i = 0, curmsk = masks; i < nvec; i++) {
706 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
707 if (!entry) {
708 if (!i)
709 iounmap(base);
710 else
711 free_msi_irqs(dev);
712 /* No enough memory. Don't try again */
713 ret = -ENOMEM;
714 goto out;
715 }
716
717 entry->msi_attrib.is_msix = 1;
718 entry->msi_attrib.is_64 = 1;
719 if (entries)
720 entry->msi_attrib.entry_nr = entries[i].entry;
721 else
722 entry->msi_attrib.entry_nr = i;
723
724 entry->msi_attrib.is_virtual =
725 entry->msi_attrib.entry_nr >= vec_count;
726
727 entry->msi_attrib.default_irq = dev->irq;
728 entry->mask_base = base;
729
730 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
731 if (masks)
732 curmsk++;
733 }
734 ret = 0;
735out:
736 kfree(masks);
737 return ret;
738}
739
740static void msix_program_entries(struct pci_dev *dev,
741 struct msix_entry *entries)
742{
743 struct msi_desc *entry;
744 int i = 0;
745 void __iomem *desc_addr;
746
747 for_each_pci_msi_entry(entry, dev) {
748 if (entries)
749 entries[i++].vector = entry->irq;
750
751 desc_addr = pci_msix_desc_addr(entry);
752 if (desc_addr)
753 entry->masked = readl(desc_addr +
754 PCI_MSIX_ENTRY_VECTOR_CTRL);
755 else
756 entry->masked = 0;
757
758 msix_mask_irq(entry, 1);
759 }
760}
761
762/**
763 * msix_capability_init - configure device's MSI-X capability
764 * @dev: pointer to the pci_dev data structure of MSI-X device function
765 * @entries: pointer to an array of struct msix_entry entries
766 * @nvec: number of @entries
767 * @affd: Optional pointer to enable automatic affinity assignment
768 *
769 * Setup the MSI-X capability structure of device function with a
770 * single MSI-X IRQ. A return of zero indicates the successful setup of
771 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
772 **/
773static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
774 int nvec, struct irq_affinity *affd)
775{
776 int ret;
777 u16 control;
778 void __iomem *base;
779
780 /* Ensure MSI-X is disabled while it is set up */
781 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
782
783 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
784 /* Request & Map MSI-X table region */
785 base = msix_map_region(dev, msix_table_size(control));
786 if (!base)
787 return -ENOMEM;
788
789 ret = msix_setup_entries(dev, base, entries, nvec, affd);
790 if (ret)
791 return ret;
792
793 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
794 if (ret)
795 goto out_avail;
796
797 /* Check if all MSI entries honor device restrictions */
798 ret = msi_verify_entries(dev);
799 if (ret)
800 goto out_free;
801
802 /*
803 * Some devices require MSI-X to be enabled before we can touch the
804 * MSI-X registers. We need to mask all the vectors to prevent
805 * interrupts coming in before they're fully set up.
806 */
807 pci_msix_clear_and_set_ctrl(dev, 0,
808 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
809
810 msix_program_entries(dev, entries);
811
812 ret = populate_msi_sysfs(dev);
813 if (ret)
814 goto out_free;
815
816 /* Set MSI-X enabled bits and unmask the function */
817 pci_intx_for_msi(dev, 0);
818 dev->msix_enabled = 1;
819 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
820
821 pcibios_free_irq(dev);
822 return 0;
823
824out_avail:
825 if (ret < 0) {
826 /*
827 * If we had some success, report the number of IRQs
828 * we succeeded in setting up.
829 */
830 struct msi_desc *entry;
831 int avail = 0;
832
833 for_each_pci_msi_entry(entry, dev) {
834 if (entry->irq != 0)
835 avail++;
836 }
837 if (avail != 0)
838 ret = avail;
839 }
840
841out_free:
842 free_msi_irqs(dev);
843
844 return ret;
845}
846
847/**
848 * pci_msi_supported - check whether MSI may be enabled on a device
849 * @dev: pointer to the pci_dev data structure of MSI device function
850 * @nvec: how many MSIs have been requested?
851 *
852 * Look at global flags, the device itself, and its parent buses
853 * to determine if MSI/-X are supported for the device. If MSI/-X is
854 * supported return 1, else return 0.
855 **/
856static int pci_msi_supported(struct pci_dev *dev, int nvec)
857{
858 struct pci_bus *bus;
859
860 /* MSI must be globally enabled and supported by the device */
861 if (!pci_msi_enable)
862 return 0;
863
864 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
865 return 0;
866
867 /*
868 * You can't ask to have 0 or less MSIs configured.
869 * a) it's stupid ..
870 * b) the list manipulation code assumes nvec >= 1.
871 */
872 if (nvec < 1)
873 return 0;
874
875 /*
876 * Any bridge which does NOT route MSI transactions from its
877 * secondary bus to its primary bus must set NO_MSI flag on
878 * the secondary pci_bus.
879 * We expect only arch-specific PCI host bus controller driver
880 * or quirks for specific PCI bridges to be setting NO_MSI.
881 */
882 for (bus = dev->bus; bus; bus = bus->parent)
883 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
884 return 0;
885
886 return 1;
887}
888
889/**
890 * pci_msi_vec_count - Return the number of MSI vectors a device can send
891 * @dev: device to report about
892 *
893 * This function returns the number of MSI vectors a device requested via
894 * Multiple Message Capable register. It returns a negative errno if the
895 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
896 * and returns a power of two, up to a maximum of 2^5 (32), according to the
897 * MSI specification.
898 **/
899int pci_msi_vec_count(struct pci_dev *dev)
900{
901 int ret;
902 u16 msgctl;
903
904 if (!dev->msi_cap)
905 return -EINVAL;
906
907 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
908 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
909
910 return ret;
911}
912EXPORT_SYMBOL(pci_msi_vec_count);
913
914static void pci_msi_shutdown(struct pci_dev *dev)
915{
916 struct msi_desc *desc;
917 u32 mask;
918
919 if (!pci_msi_enable || !dev || !dev->msi_enabled)
920 return;
921
922 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
923 desc = first_pci_msi_entry(dev);
924
925 pci_msi_set_enable(dev, 0);
926 pci_intx_for_msi(dev, 1);
927 dev->msi_enabled = 0;
928
929 /* Return the device with MSI unmasked as initial states */
930 mask = msi_mask(desc->msi_attrib.multi_cap);
931 /* Keep cached state to be restored */
932 __pci_msi_desc_mask_irq(desc, mask, ~mask);
933
934 /* Restore dev->irq to its default pin-assertion IRQ */
935 dev->irq = desc->msi_attrib.default_irq;
936 pcibios_alloc_irq(dev);
937}
938
939void pci_disable_msi(struct pci_dev *dev)
940{
941 if (!pci_msi_enable || !dev || !dev->msi_enabled)
942 return;
943
944 pci_msi_shutdown(dev);
945 free_msi_irqs(dev);
946}
947EXPORT_SYMBOL(pci_disable_msi);
948
949/**
950 * pci_msix_vec_count - return the number of device's MSI-X table entries
951 * @dev: pointer to the pci_dev data structure of MSI-X device function
952 * This function returns the number of device's MSI-X table entries and
953 * therefore the number of MSI-X vectors device is capable of sending.
954 * It returns a negative errno if the device is not capable of sending MSI-X
955 * interrupts.
956 **/
957int pci_msix_vec_count(struct pci_dev *dev)
958{
959 u16 control;
960
961 if (!dev->msix_cap)
962 return -EINVAL;
963
964 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
965 return msix_table_size(control);
966}
967EXPORT_SYMBOL(pci_msix_vec_count);
968
969static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
970 int nvec, struct irq_affinity *affd, int flags)
971{
972 int nr_entries;
973 int i, j;
974
975 if (!pci_msi_supported(dev, nvec))
976 return -EINVAL;
977
978 nr_entries = pci_msix_vec_count(dev);
979 if (nr_entries < 0)
980 return nr_entries;
981 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
982 return nr_entries;
983
984 if (entries) {
985 /* Check for any invalid entries */
986 for (i = 0; i < nvec; i++) {
987 if (entries[i].entry >= nr_entries)
988 return -EINVAL; /* invalid entry */
989 for (j = i + 1; j < nvec; j++) {
990 if (entries[i].entry == entries[j].entry)
991 return -EINVAL; /* duplicate entry */
992 }
993 }
994 }
995
996 /* Check whether driver already requested for MSI IRQ */
997 if (dev->msi_enabled) {
998 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
999 return -EINVAL;
1000 }
1001 return msix_capability_init(dev, entries, nvec, affd);
1002}
1003
1004static void pci_msix_shutdown(struct pci_dev *dev)
1005{
1006 struct msi_desc *entry;
1007
1008 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1009 return;
1010
1011 if (pci_dev_is_disconnected(dev)) {
1012 dev->msix_enabled = 0;
1013 return;
1014 }
1015
1016 /* Return the device with MSI-X masked as initial states */
1017 for_each_pci_msi_entry(entry, dev) {
1018 /* Keep cached states to be restored */
1019 __pci_msix_desc_mask_irq(entry, 1);
1020 }
1021
1022 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1023 pci_intx_for_msi(dev, 1);
1024 dev->msix_enabled = 0;
1025 pcibios_alloc_irq(dev);
1026}
1027
1028void pci_disable_msix(struct pci_dev *dev)
1029{
1030 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1031 return;
1032
1033 pci_msix_shutdown(dev);
1034 free_msi_irqs(dev);
1035}
1036EXPORT_SYMBOL(pci_disable_msix);
1037
1038void pci_no_msi(void)
1039{
1040 pci_msi_enable = 0;
1041}
1042
1043/**
1044 * pci_msi_enabled - is MSI enabled?
1045 *
1046 * Returns true if MSI has not been disabled by the command-line option
1047 * pci=nomsi.
1048 **/
1049int pci_msi_enabled(void)
1050{
1051 return pci_msi_enable;
1052}
1053EXPORT_SYMBOL(pci_msi_enabled);
1054
1055static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1056 struct irq_affinity *affd)
1057{
1058 int nvec;
1059 int rc;
1060
1061 if (!pci_msi_supported(dev, minvec))
1062 return -EINVAL;
1063
1064 /* Check whether driver already requested MSI-X IRQs */
1065 if (dev->msix_enabled) {
1066 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
1067 return -EINVAL;
1068 }
1069
1070 if (maxvec < minvec)
1071 return -ERANGE;
1072
1073 if (WARN_ON_ONCE(dev->msi_enabled))
1074 return -EINVAL;
1075
1076 nvec = pci_msi_vec_count(dev);
1077 if (nvec < 0)
1078 return nvec;
1079 if (nvec < minvec)
1080 return -ENOSPC;
1081
1082 if (nvec > maxvec)
1083 nvec = maxvec;
1084
1085 for (;;) {
1086 if (affd) {
1087 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1088 if (nvec < minvec)
1089 return -ENOSPC;
1090 }
1091
1092 rc = msi_capability_init(dev, nvec, affd);
1093 if (rc == 0)
1094 return nvec;
1095
1096 if (rc < 0)
1097 return rc;
1098 if (rc < minvec)
1099 return -ENOSPC;
1100
1101 nvec = rc;
1102 }
1103}
1104
1105/* deprecated, don't use */
1106int pci_enable_msi(struct pci_dev *dev)
1107{
1108 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1109 if (rc < 0)
1110 return rc;
1111 return 0;
1112}
1113EXPORT_SYMBOL(pci_enable_msi);
1114
1115static int __pci_enable_msix_range(struct pci_dev *dev,
1116 struct msix_entry *entries, int minvec,
1117 int maxvec, struct irq_affinity *affd,
1118 int flags)
1119{
1120 int rc, nvec = maxvec;
1121
1122 if (maxvec < minvec)
1123 return -ERANGE;
1124
1125 if (WARN_ON_ONCE(dev->msix_enabled))
1126 return -EINVAL;
1127
1128 for (;;) {
1129 if (affd) {
1130 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1131 if (nvec < minvec)
1132 return -ENOSPC;
1133 }
1134
1135 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
1136 if (rc == 0)
1137 return nvec;
1138
1139 if (rc < 0)
1140 return rc;
1141 if (rc < minvec)
1142 return -ENOSPC;
1143
1144 nvec = rc;
1145 }
1146}
1147
1148/**
1149 * pci_enable_msix_range - configure device's MSI-X capability structure
1150 * @dev: pointer to the pci_dev data structure of MSI-X device function
1151 * @entries: pointer to an array of MSI-X entries
1152 * @minvec: minimum number of MSI-X IRQs requested
1153 * @maxvec: maximum number of MSI-X IRQs requested
1154 *
1155 * Setup the MSI-X capability structure of device function with a maximum
1156 * possible number of interrupts in the range between @minvec and @maxvec
1157 * upon its software driver call to request for MSI-X mode enabled on its
1158 * hardware device function. It returns a negative errno if an error occurs.
1159 * If it succeeds, it returns the actual number of interrupts allocated and
1160 * indicates the successful configuration of MSI-X capability structure
1161 * with new allocated MSI-X interrupts.
1162 **/
1163int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1164 int minvec, int maxvec)
1165{
1166 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
1167}
1168EXPORT_SYMBOL(pci_enable_msix_range);
1169
1170/**
1171 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1172 * @dev: PCI device to operate on
1173 * @min_vecs: minimum number of vectors required (must be >= 1)
1174 * @max_vecs: maximum (desired) number of vectors
1175 * @flags: flags or quirks for the allocation
1176 * @affd: optional description of the affinity requirements
1177 *
1178 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1179 * vectors if available, and fall back to a single legacy vector
1180 * if neither is available. Return the number of vectors allocated,
1181 * (which might be smaller than @max_vecs) if successful, or a negative
1182 * error code on error. If less than @min_vecs interrupt vectors are
1183 * available for @dev the function will fail with -ENOSPC.
1184 *
1185 * To get the Linux IRQ number used for a vector that can be passed to
1186 * request_irq() use the pci_irq_vector() helper.
1187 */
1188int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1189 unsigned int max_vecs, unsigned int flags,
1190 struct irq_affinity *affd)
1191{
1192 struct irq_affinity msi_default_affd = {0};
1193 int msix_vecs = -ENOSPC;
1194 int msi_vecs = -ENOSPC;
1195
1196 if (flags & PCI_IRQ_AFFINITY) {
1197 if (!affd)
1198 affd = &msi_default_affd;
1199 } else {
1200 if (WARN_ON(affd))
1201 affd = NULL;
1202 }
1203
1204 if (flags & PCI_IRQ_MSIX) {
1205 msix_vecs = __pci_enable_msix_range(dev, NULL, min_vecs,
1206 max_vecs, affd, flags);
1207 if (msix_vecs > 0)
1208 return msix_vecs;
1209 }
1210
1211 if (flags & PCI_IRQ_MSI) {
1212 msi_vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs,
1213 affd);
1214 if (msi_vecs > 0)
1215 return msi_vecs;
1216 }
1217
1218 /* use legacy IRQ if allowed */
1219 if (flags & PCI_IRQ_LEGACY) {
1220 if (min_vecs == 1 && dev->irq) {
1221 /*
1222 * Invoke the affinity spreading logic to ensure that
1223 * the device driver can adjust queue configuration
1224 * for the single interrupt case.
1225 */
1226 if (affd)
1227 irq_create_affinity_masks(1, affd);
1228 pci_intx(dev, 1);
1229 return 1;
1230 }
1231 }
1232
1233 if (msix_vecs == -ENOSPC)
1234 return -ENOSPC;
1235 return msi_vecs;
1236}
1237EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1238
1239/**
1240 * pci_free_irq_vectors - free previously allocated IRQs for a device
1241 * @dev: PCI device to operate on
1242 *
1243 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1244 */
1245void pci_free_irq_vectors(struct pci_dev *dev)
1246{
1247 pci_disable_msix(dev);
1248 pci_disable_msi(dev);
1249}
1250EXPORT_SYMBOL(pci_free_irq_vectors);
1251
1252/**
1253 * pci_irq_vector - return Linux IRQ number of a device vector
1254 * @dev: PCI device to operate on
1255 * @nr: device-relative interrupt vector index (0-based).
1256 */
1257int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1258{
1259 if (dev->msix_enabled) {
1260 struct msi_desc *entry;
1261 int i = 0;
1262
1263 for_each_pci_msi_entry(entry, dev) {
1264 if (i == nr)
1265 return entry->irq;
1266 i++;
1267 }
1268 WARN_ON_ONCE(1);
1269 return -EINVAL;
1270 }
1271
1272 if (dev->msi_enabled) {
1273 struct msi_desc *entry = first_pci_msi_entry(dev);
1274
1275 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1276 return -EINVAL;
1277 } else {
1278 if (WARN_ON_ONCE(nr > 0))
1279 return -EINVAL;
1280 }
1281
1282 return dev->irq + nr;
1283}
1284EXPORT_SYMBOL(pci_irq_vector);
1285
1286/**
1287 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1288 * @dev: PCI device to operate on
1289 * @nr: device-relative interrupt vector index (0-based).
1290 */
1291const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1292{
1293 if (dev->msix_enabled) {
1294 struct msi_desc *entry;
1295 int i = 0;
1296
1297 for_each_pci_msi_entry(entry, dev) {
1298 if (i == nr)
1299 return &entry->affinity->mask;
1300 i++;
1301 }
1302 WARN_ON_ONCE(1);
1303 return NULL;
1304 } else if (dev->msi_enabled) {
1305 struct msi_desc *entry = first_pci_msi_entry(dev);
1306
1307 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1308 nr >= entry->nvec_used))
1309 return NULL;
1310
1311 return &entry->affinity[nr].mask;
1312 } else {
1313 return cpu_possible_mask;
1314 }
1315}
1316EXPORT_SYMBOL(pci_irq_get_affinity);
1317
1318/**
1319 * pci_irq_get_node - return the NUMA node of a particular MSI vector
1320 * @pdev: PCI device to operate on
1321 * @vec: device-relative interrupt vector index (0-based).
1322 */
1323int pci_irq_get_node(struct pci_dev *pdev, int vec)
1324{
1325 const struct cpumask *mask;
1326
1327 mask = pci_irq_get_affinity(pdev, vec);
1328 if (mask)
1329 return local_memory_node(cpu_to_node(cpumask_first(mask)));
1330 return dev_to_node(&pdev->dev);
1331}
1332EXPORT_SYMBOL(pci_irq_get_node);
1333
1334struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1335{
1336 return to_pci_dev(desc->dev);
1337}
1338EXPORT_SYMBOL(msi_desc_to_pci_dev);
1339
1340void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1341{
1342 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1343
1344 return dev->bus->sysdata;
1345}
1346EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1347
1348#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1349/**
1350 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1351 * @irq_data: Pointer to interrupt data of the MSI interrupt
1352 * @msg: Pointer to the message
1353 */
1354void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1355{
1356 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1357
1358 /*
1359 * For MSI-X desc->irq is always equal to irq_data->irq. For
1360 * MSI only the first interrupt of MULTI MSI passes the test.
1361 */
1362 if (desc->irq == irq_data->irq)
1363 __pci_write_msi_msg(desc, msg);
1364}
1365
1366/**
1367 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1368 * @dev: Pointer to the PCI device
1369 * @desc: Pointer to the MSI descriptor
1370 *
1371 * The ID number is only used within the irqdomain.
1372 */
1373irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1374 struct msi_desc *desc)
1375{
1376 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1377 pci_dev_id(dev) << 11 |
1378 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1379}
1380
1381static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1382{
1383 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1384}
1385
1386/**
1387 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1388 * for @dev
1389 * @domain: The interrupt domain to check
1390 * @info: The domain info for verification
1391 * @dev: The device to check
1392 *
1393 * Returns:
1394 * 0 if the functionality is supported
1395 * 1 if Multi MSI is requested, but the domain does not support it
1396 * -ENOTSUPP otherwise
1397 */
1398int pci_msi_domain_check_cap(struct irq_domain *domain,
1399 struct msi_domain_info *info, struct device *dev)
1400{
1401 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1402
1403 /* Special handling to support __pci_enable_msi_range() */
1404 if (pci_msi_desc_is_multi_msi(desc) &&
1405 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1406 return 1;
1407 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1408 return -ENOTSUPP;
1409
1410 return 0;
1411}
1412
1413static int pci_msi_domain_handle_error(struct irq_domain *domain,
1414 struct msi_desc *desc, int error)
1415{
1416 /* Special handling to support __pci_enable_msi_range() */
1417 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1418 return 1;
1419
1420 return error;
1421}
1422
1423#ifdef GENERIC_MSI_DOMAIN_OPS
1424static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1425 struct msi_desc *desc)
1426{
1427 arg->desc = desc;
1428 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1429 desc);
1430}
1431#else
1432#define pci_msi_domain_set_desc NULL
1433#endif
1434
1435static struct msi_domain_ops pci_msi_domain_ops_default = {
1436 .set_desc = pci_msi_domain_set_desc,
1437 .msi_check = pci_msi_domain_check_cap,
1438 .handle_error = pci_msi_domain_handle_error,
1439};
1440
1441static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1442{
1443 struct msi_domain_ops *ops = info->ops;
1444
1445 if (ops == NULL) {
1446 info->ops = &pci_msi_domain_ops_default;
1447 } else {
1448 if (ops->set_desc == NULL)
1449 ops->set_desc = pci_msi_domain_set_desc;
1450 if (ops->msi_check == NULL)
1451 ops->msi_check = pci_msi_domain_check_cap;
1452 if (ops->handle_error == NULL)
1453 ops->handle_error = pci_msi_domain_handle_error;
1454 }
1455}
1456
1457static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1458{
1459 struct irq_chip *chip = info->chip;
1460
1461 BUG_ON(!chip);
1462 if (!chip->irq_write_msi_msg)
1463 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1464 if (!chip->irq_mask)
1465 chip->irq_mask = pci_msi_mask_irq;
1466 if (!chip->irq_unmask)
1467 chip->irq_unmask = pci_msi_unmask_irq;
1468}
1469
1470/**
1471 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1472 * @fwnode: Optional fwnode of the interrupt controller
1473 * @info: MSI domain info
1474 * @parent: Parent irq domain
1475 *
1476 * Updates the domain and chip ops and creates a MSI interrupt domain.
1477 *
1478 * Returns:
1479 * A domain pointer or NULL in case of failure.
1480 */
1481struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1482 struct msi_domain_info *info,
1483 struct irq_domain *parent)
1484{
1485 struct irq_domain *domain;
1486
1487 if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
1488 info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
1489
1490 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1491 pci_msi_domain_update_dom_ops(info);
1492 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1493 pci_msi_domain_update_chip_ops(info);
1494
1495 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1496 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
1497 info->flags |= MSI_FLAG_MUST_REACTIVATE;
1498
1499 /* PCI-MSI is oneshot-safe */
1500 info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
1501
1502 domain = msi_create_irq_domain(fwnode, info, parent);
1503 if (!domain)
1504 return NULL;
1505
1506 irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1507 return domain;
1508}
1509EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1510
1511/*
1512 * Users of the generic MSI infrastructure expect a device to have a single ID,
1513 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1514 * DMA phantom functions tend to still emit MSIs from the real function number,
1515 * so we ignore those and only consider topological aliases where either the
1516 * alias device or RID appears on a different bus number. We also make the
1517 * reasonable assumption that bridges are walked in an upstream direction (so
1518 * the last one seen wins), and the much braver assumption that the most likely
1519 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1520 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1521 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1522 * for taking ownership all we can really do is close our eyes and hope...
1523 */
1524static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1525{
1526 u32 *pa = data;
1527 u8 bus = PCI_BUS_NUM(*pa);
1528
1529 if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1530 *pa = alias;
1531
1532 return 0;
1533}
1534
1535/**
1536 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1537 * @domain: The interrupt domain
1538 * @pdev: The PCI device.
1539 *
1540 * The RID for a device is formed from the alias, with a firmware
1541 * supplied mapping applied
1542 *
1543 * Returns: The RID.
1544 */
1545u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1546{
1547 struct device_node *of_node;
1548 u32 rid = pci_dev_id(pdev);
1549
1550 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1551
1552 of_node = irq_domain_get_of_node(domain);
1553 rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) :
1554 iort_msi_map_rid(&pdev->dev, rid);
1555
1556 return rid;
1557}
1558
1559/**
1560 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1561 * @pdev: The PCI device
1562 *
1563 * Use the firmware data to find a device-specific MSI domain
1564 * (i.e. not one that is set as a default).
1565 *
1566 * Returns: The corresponding MSI domain or NULL if none has been found.
1567 */
1568struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1569{
1570 struct irq_domain *dom;
1571 u32 rid = pci_dev_id(pdev);
1572
1573 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1574 dom = of_msi_map_get_device_domain(&pdev->dev, rid);
1575 if (!dom)
1576 dom = iort_get_device_domain(&pdev->dev, rid);
1577 return dom;
1578}
1579#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1/*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
8 */
9
10#include <linux/err.h>
11#include <linux/mm.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/export.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/msi.h>
19#include <linux/smp.h>
20#include <linux/errno.h>
21#include <linux/io.h>
22#include <linux/acpi_iort.h>
23#include <linux/slab.h>
24#include <linux/irqdomain.h>
25#include <linux/of_irq.h>
26
27#include "pci.h"
28
29static int pci_msi_enable = 1;
30int pci_msi_ignore_mask;
31
32#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33
34#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
35static struct irq_domain *pci_msi_default_domain;
36static DEFINE_MUTEX(pci_msi_domain_lock);
37
38struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
39{
40 return pci_msi_default_domain;
41}
42
43static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
44{
45 struct irq_domain *domain;
46
47 domain = dev_get_msi_domain(&dev->dev);
48 if (domain)
49 return domain;
50
51 return arch_get_pci_msi_domain(dev);
52}
53
54static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
55{
56 struct irq_domain *domain;
57
58 domain = pci_msi_get_domain(dev);
59 if (domain && irq_domain_is_hierarchy(domain))
60 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
61
62 return arch_setup_msi_irqs(dev, nvec, type);
63}
64
65static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
66{
67 struct irq_domain *domain;
68
69 domain = pci_msi_get_domain(dev);
70 if (domain && irq_domain_is_hierarchy(domain))
71 pci_msi_domain_free_irqs(domain, dev);
72 else
73 arch_teardown_msi_irqs(dev);
74}
75#else
76#define pci_msi_setup_msi_irqs arch_setup_msi_irqs
77#define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
78#endif
79
80/* Arch hooks */
81
82int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
83{
84 struct msi_controller *chip = dev->bus->msi;
85 int err;
86
87 if (!chip || !chip->setup_irq)
88 return -EINVAL;
89
90 err = chip->setup_irq(chip, dev, desc);
91 if (err < 0)
92 return err;
93
94 irq_set_chip_data(desc->irq, chip);
95
96 return 0;
97}
98
99void __weak arch_teardown_msi_irq(unsigned int irq)
100{
101 struct msi_controller *chip = irq_get_chip_data(irq);
102
103 if (!chip || !chip->teardown_irq)
104 return;
105
106 chip->teardown_irq(chip, irq);
107}
108
109int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
110{
111 struct msi_controller *chip = dev->bus->msi;
112 struct msi_desc *entry;
113 int ret;
114
115 if (chip && chip->setup_irqs)
116 return chip->setup_irqs(chip, dev, nvec, type);
117 /*
118 * If an architecture wants to support multiple MSI, it needs to
119 * override arch_setup_msi_irqs()
120 */
121 if (type == PCI_CAP_ID_MSI && nvec > 1)
122 return 1;
123
124 for_each_pci_msi_entry(entry, dev) {
125 ret = arch_setup_msi_irq(dev, entry);
126 if (ret < 0)
127 return ret;
128 if (ret > 0)
129 return -ENOSPC;
130 }
131
132 return 0;
133}
134
135/*
136 * We have a default implementation available as a separate non-weak
137 * function, as it is used by the Xen x86 PCI code
138 */
139void default_teardown_msi_irqs(struct pci_dev *dev)
140{
141 int i;
142 struct msi_desc *entry;
143
144 for_each_pci_msi_entry(entry, dev)
145 if (entry->irq)
146 for (i = 0; i < entry->nvec_used; i++)
147 arch_teardown_msi_irq(entry->irq + i);
148}
149
150void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
151{
152 return default_teardown_msi_irqs(dev);
153}
154
155static void default_restore_msi_irq(struct pci_dev *dev, int irq)
156{
157 struct msi_desc *entry;
158
159 entry = NULL;
160 if (dev->msix_enabled) {
161 for_each_pci_msi_entry(entry, dev) {
162 if (irq == entry->irq)
163 break;
164 }
165 } else if (dev->msi_enabled) {
166 entry = irq_get_msi_desc(irq);
167 }
168
169 if (entry)
170 __pci_write_msi_msg(entry, &entry->msg);
171}
172
173void __weak arch_restore_msi_irqs(struct pci_dev *dev)
174{
175 return default_restore_msi_irqs(dev);
176}
177
178static inline __attribute_const__ u32 msi_mask(unsigned x)
179{
180 /* Don't shift by >= width of type */
181 if (x >= 5)
182 return 0xffffffff;
183 return (1 << (1 << x)) - 1;
184}
185
186/*
187 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
188 * mask all MSI interrupts by clearing the MSI enable bit does not work
189 * reliably as devices without an INTx disable bit will then generate a
190 * level IRQ which will never be cleared.
191 */
192u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
193{
194 u32 mask_bits = desc->masked;
195
196 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
197 return 0;
198
199 mask_bits &= ~mask;
200 mask_bits |= flag;
201 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
202 mask_bits);
203
204 return mask_bits;
205}
206
207static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
208{
209 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
210}
211
212static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
213{
214 return desc->mask_base +
215 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
216}
217
218/*
219 * This internal function does not flush PCI writes to the device.
220 * All users must ensure that they read from the device before either
221 * assuming that the device state is up to date, or returning out of this
222 * file. This saves a few milliseconds when initialising devices with lots
223 * of MSI-X interrupts.
224 */
225u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
226{
227 u32 mask_bits = desc->masked;
228
229 if (pci_msi_ignore_mask)
230 return 0;
231
232 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
233 if (flag)
234 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
235 writel(mask_bits, pci_msix_desc_addr(desc) + PCI_MSIX_ENTRY_VECTOR_CTRL);
236
237 return mask_bits;
238}
239
240static void msix_mask_irq(struct msi_desc *desc, u32 flag)
241{
242 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
243}
244
245static void msi_set_mask_bit(struct irq_data *data, u32 flag)
246{
247 struct msi_desc *desc = irq_data_get_msi_desc(data);
248
249 if (desc->msi_attrib.is_msix) {
250 msix_mask_irq(desc, flag);
251 readl(desc->mask_base); /* Flush write to device */
252 } else {
253 unsigned offset = data->irq - desc->irq;
254 msi_mask_irq(desc, 1 << offset, flag << offset);
255 }
256}
257
258/**
259 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
260 * @data: pointer to irqdata associated to that interrupt
261 */
262void pci_msi_mask_irq(struct irq_data *data)
263{
264 msi_set_mask_bit(data, 1);
265}
266EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
267
268/**
269 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
270 * @data: pointer to irqdata associated to that interrupt
271 */
272void pci_msi_unmask_irq(struct irq_data *data)
273{
274 msi_set_mask_bit(data, 0);
275}
276EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
277
278void default_restore_msi_irqs(struct pci_dev *dev)
279{
280 struct msi_desc *entry;
281
282 for_each_pci_msi_entry(entry, dev)
283 default_restore_msi_irq(dev, entry->irq);
284}
285
286void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
287{
288 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
289
290 BUG_ON(dev->current_state != PCI_D0);
291
292 if (entry->msi_attrib.is_msix) {
293 void __iomem *base = pci_msix_desc_addr(entry);
294
295 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
296 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
297 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
298 } else {
299 int pos = dev->msi_cap;
300 u16 data;
301
302 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
303 &msg->address_lo);
304 if (entry->msi_attrib.is_64) {
305 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
306 &msg->address_hi);
307 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
308 } else {
309 msg->address_hi = 0;
310 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
311 }
312 msg->data = data;
313 }
314}
315
316void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
317{
318 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
319
320 if (dev->current_state != PCI_D0) {
321 /* Don't touch the hardware now */
322 } else if (entry->msi_attrib.is_msix) {
323 void __iomem *base = pci_msix_desc_addr(entry);
324
325 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
326 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
327 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
328 } else {
329 int pos = dev->msi_cap;
330 u16 msgctl;
331
332 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
333 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
334 msgctl |= entry->msi_attrib.multiple << 4;
335 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
336
337 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
338 msg->address_lo);
339 if (entry->msi_attrib.is_64) {
340 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
341 msg->address_hi);
342 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
343 msg->data);
344 } else {
345 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
346 msg->data);
347 }
348 }
349 entry->msg = *msg;
350}
351
352void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
353{
354 struct msi_desc *entry = irq_get_msi_desc(irq);
355
356 __pci_write_msi_msg(entry, msg);
357}
358EXPORT_SYMBOL_GPL(pci_write_msi_msg);
359
360static void free_msi_irqs(struct pci_dev *dev)
361{
362 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
363 struct msi_desc *entry, *tmp;
364 struct attribute **msi_attrs;
365 struct device_attribute *dev_attr;
366 int i, count = 0;
367
368 for_each_pci_msi_entry(entry, dev)
369 if (entry->irq)
370 for (i = 0; i < entry->nvec_used; i++)
371 BUG_ON(irq_has_action(entry->irq + i));
372
373 pci_msi_teardown_msi_irqs(dev);
374
375 list_for_each_entry_safe(entry, tmp, msi_list, list) {
376 if (entry->msi_attrib.is_msix) {
377 if (list_is_last(&entry->list, msi_list))
378 iounmap(entry->mask_base);
379 }
380
381 list_del(&entry->list);
382 kfree(entry);
383 }
384
385 if (dev->msi_irq_groups) {
386 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
387 msi_attrs = dev->msi_irq_groups[0]->attrs;
388 while (msi_attrs[count]) {
389 dev_attr = container_of(msi_attrs[count],
390 struct device_attribute, attr);
391 kfree(dev_attr->attr.name);
392 kfree(dev_attr);
393 ++count;
394 }
395 kfree(msi_attrs);
396 kfree(dev->msi_irq_groups[0]);
397 kfree(dev->msi_irq_groups);
398 dev->msi_irq_groups = NULL;
399 }
400}
401
402static void pci_intx_for_msi(struct pci_dev *dev, int enable)
403{
404 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
405 pci_intx(dev, enable);
406}
407
408static void __pci_restore_msi_state(struct pci_dev *dev)
409{
410 u16 control;
411 struct msi_desc *entry;
412
413 if (!dev->msi_enabled)
414 return;
415
416 entry = irq_get_msi_desc(dev->irq);
417
418 pci_intx_for_msi(dev, 0);
419 pci_msi_set_enable(dev, 0);
420 arch_restore_msi_irqs(dev);
421
422 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
423 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
424 entry->masked);
425 control &= ~PCI_MSI_FLAGS_QSIZE;
426 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
427 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
428}
429
430static void __pci_restore_msix_state(struct pci_dev *dev)
431{
432 struct msi_desc *entry;
433
434 if (!dev->msix_enabled)
435 return;
436 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
437
438 /* route the table */
439 pci_intx_for_msi(dev, 0);
440 pci_msix_clear_and_set_ctrl(dev, 0,
441 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
442
443 arch_restore_msi_irqs(dev);
444 for_each_pci_msi_entry(entry, dev)
445 msix_mask_irq(entry, entry->masked);
446
447 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
448}
449
450void pci_restore_msi_state(struct pci_dev *dev)
451{
452 __pci_restore_msi_state(dev);
453 __pci_restore_msix_state(dev);
454}
455EXPORT_SYMBOL_GPL(pci_restore_msi_state);
456
457static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
458 char *buf)
459{
460 struct msi_desc *entry;
461 unsigned long irq;
462 int retval;
463
464 retval = kstrtoul(attr->attr.name, 10, &irq);
465 if (retval)
466 return retval;
467
468 entry = irq_get_msi_desc(irq);
469 if (entry)
470 return sprintf(buf, "%s\n",
471 entry->msi_attrib.is_msix ? "msix" : "msi");
472
473 return -ENODEV;
474}
475
476static int populate_msi_sysfs(struct pci_dev *pdev)
477{
478 struct attribute **msi_attrs;
479 struct attribute *msi_attr;
480 struct device_attribute *msi_dev_attr;
481 struct attribute_group *msi_irq_group;
482 const struct attribute_group **msi_irq_groups;
483 struct msi_desc *entry;
484 int ret = -ENOMEM;
485 int num_msi = 0;
486 int count = 0;
487 int i;
488
489 /* Determine how many msi entries we have */
490 for_each_pci_msi_entry(entry, pdev)
491 num_msi += entry->nvec_used;
492 if (!num_msi)
493 return 0;
494
495 /* Dynamically create the MSI attributes for the PCI device */
496 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
497 if (!msi_attrs)
498 return -ENOMEM;
499 for_each_pci_msi_entry(entry, pdev) {
500 for (i = 0; i < entry->nvec_used; i++) {
501 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
502 if (!msi_dev_attr)
503 goto error_attrs;
504 msi_attrs[count] = &msi_dev_attr->attr;
505
506 sysfs_attr_init(&msi_dev_attr->attr);
507 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
508 entry->irq + i);
509 if (!msi_dev_attr->attr.name)
510 goto error_attrs;
511 msi_dev_attr->attr.mode = S_IRUGO;
512 msi_dev_attr->show = msi_mode_show;
513 ++count;
514 }
515 }
516
517 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
518 if (!msi_irq_group)
519 goto error_attrs;
520 msi_irq_group->name = "msi_irqs";
521 msi_irq_group->attrs = msi_attrs;
522
523 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
524 if (!msi_irq_groups)
525 goto error_irq_group;
526 msi_irq_groups[0] = msi_irq_group;
527
528 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
529 if (ret)
530 goto error_irq_groups;
531 pdev->msi_irq_groups = msi_irq_groups;
532
533 return 0;
534
535error_irq_groups:
536 kfree(msi_irq_groups);
537error_irq_group:
538 kfree(msi_irq_group);
539error_attrs:
540 count = 0;
541 msi_attr = msi_attrs[count];
542 while (msi_attr) {
543 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
544 kfree(msi_attr->name);
545 kfree(msi_dev_attr);
546 ++count;
547 msi_attr = msi_attrs[count];
548 }
549 kfree(msi_attrs);
550 return ret;
551}
552
553static struct msi_desc *
554msi_setup_entry(struct pci_dev *dev, int nvec, const struct irq_affinity *affd)
555{
556 struct cpumask *masks = NULL;
557 struct msi_desc *entry;
558 u16 control;
559
560 if (affd) {
561 masks = irq_create_affinity_masks(nvec, affd);
562 if (!masks)
563 pr_err("Unable to allocate affinity masks, ignoring\n");
564 }
565
566 /* MSI Entry Initialization */
567 entry = alloc_msi_entry(&dev->dev, nvec, masks);
568 if (!entry)
569 goto out;
570
571 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
572
573 entry->msi_attrib.is_msix = 0;
574 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
575 entry->msi_attrib.entry_nr = 0;
576 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
577 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
578 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
579 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
580
581 if (control & PCI_MSI_FLAGS_64BIT)
582 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
583 else
584 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
585
586 /* Save the initial mask status */
587 if (entry->msi_attrib.maskbit)
588 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
589
590out:
591 kfree(masks);
592 return entry;
593}
594
595static int msi_verify_entries(struct pci_dev *dev)
596{
597 struct msi_desc *entry;
598
599 for_each_pci_msi_entry(entry, dev) {
600 if (!dev->no_64bit_msi || !entry->msg.address_hi)
601 continue;
602 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
603 " tried to assign one above 4G\n");
604 return -EIO;
605 }
606 return 0;
607}
608
609/**
610 * msi_capability_init - configure device's MSI capability structure
611 * @dev: pointer to the pci_dev data structure of MSI device function
612 * @nvec: number of interrupts to allocate
613 * @affinity: flag to indicate cpu irq affinity mask should be set
614 *
615 * Setup the MSI capability structure of the device with the requested
616 * number of interrupts. A return value of zero indicates the successful
617 * setup of an entry with the new MSI irq. A negative return value indicates
618 * an error, and a positive return value indicates the number of interrupts
619 * which could have been allocated.
620 */
621static int msi_capability_init(struct pci_dev *dev, int nvec,
622 const struct irq_affinity *affd)
623{
624 struct msi_desc *entry;
625 int ret;
626 unsigned mask;
627
628 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
629
630 entry = msi_setup_entry(dev, nvec, affd);
631 if (!entry)
632 return -ENOMEM;
633
634 /* All MSIs are unmasked by default, Mask them all */
635 mask = msi_mask(entry->msi_attrib.multi_cap);
636 msi_mask_irq(entry, mask, mask);
637
638 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
639
640 /* Configure MSI capability structure */
641 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
642 if (ret) {
643 msi_mask_irq(entry, mask, ~mask);
644 free_msi_irqs(dev);
645 return ret;
646 }
647
648 ret = msi_verify_entries(dev);
649 if (ret) {
650 msi_mask_irq(entry, mask, ~mask);
651 free_msi_irqs(dev);
652 return ret;
653 }
654
655 ret = populate_msi_sysfs(dev);
656 if (ret) {
657 msi_mask_irq(entry, mask, ~mask);
658 free_msi_irqs(dev);
659 return ret;
660 }
661
662 /* Set MSI enabled bits */
663 pci_intx_for_msi(dev, 0);
664 pci_msi_set_enable(dev, 1);
665 dev->msi_enabled = 1;
666
667 pcibios_free_irq(dev);
668 dev->irq = entry->irq;
669 return 0;
670}
671
672static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
673{
674 resource_size_t phys_addr;
675 u32 table_offset;
676 unsigned long flags;
677 u8 bir;
678
679 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
680 &table_offset);
681 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
682 flags = pci_resource_flags(dev, bir);
683 if (!flags || (flags & IORESOURCE_UNSET))
684 return NULL;
685
686 table_offset &= PCI_MSIX_TABLE_OFFSET;
687 phys_addr = pci_resource_start(dev, bir) + table_offset;
688
689 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
690}
691
692static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
693 struct msix_entry *entries, int nvec,
694 const struct irq_affinity *affd)
695{
696 struct cpumask *curmsk, *masks = NULL;
697 struct msi_desc *entry;
698 int ret, i;
699
700 if (affd) {
701 masks = irq_create_affinity_masks(nvec, affd);
702 if (!masks)
703 pr_err("Unable to allocate affinity masks, ignoring\n");
704 }
705
706 for (i = 0, curmsk = masks; i < nvec; i++) {
707 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
708 if (!entry) {
709 if (!i)
710 iounmap(base);
711 else
712 free_msi_irqs(dev);
713 /* No enough memory. Don't try again */
714 ret = -ENOMEM;
715 goto out;
716 }
717
718 entry->msi_attrib.is_msix = 1;
719 entry->msi_attrib.is_64 = 1;
720 if (entries)
721 entry->msi_attrib.entry_nr = entries[i].entry;
722 else
723 entry->msi_attrib.entry_nr = i;
724 entry->msi_attrib.default_irq = dev->irq;
725 entry->mask_base = base;
726
727 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
728 if (masks)
729 curmsk++;
730 }
731 ret = 0;
732out:
733 kfree(masks);
734 return 0;
735}
736
737static void msix_program_entries(struct pci_dev *dev,
738 struct msix_entry *entries)
739{
740 struct msi_desc *entry;
741 int i = 0;
742
743 for_each_pci_msi_entry(entry, dev) {
744 if (entries)
745 entries[i++].vector = entry->irq;
746 entry->masked = readl(pci_msix_desc_addr(entry) +
747 PCI_MSIX_ENTRY_VECTOR_CTRL);
748 msix_mask_irq(entry, 1);
749 }
750}
751
752/**
753 * msix_capability_init - configure device's MSI-X capability
754 * @dev: pointer to the pci_dev data structure of MSI-X device function
755 * @entries: pointer to an array of struct msix_entry entries
756 * @nvec: number of @entries
757 * @affd: Optional pointer to enable automatic affinity assignement
758 *
759 * Setup the MSI-X capability structure of device function with a
760 * single MSI-X irq. A return of zero indicates the successful setup of
761 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
762 **/
763static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
764 int nvec, const struct irq_affinity *affd)
765{
766 int ret;
767 u16 control;
768 void __iomem *base;
769
770 /* Ensure MSI-X is disabled while it is set up */
771 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
772
773 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
774 /* Request & Map MSI-X table region */
775 base = msix_map_region(dev, msix_table_size(control));
776 if (!base)
777 return -ENOMEM;
778
779 ret = msix_setup_entries(dev, base, entries, nvec, affd);
780 if (ret)
781 return ret;
782
783 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
784 if (ret)
785 goto out_avail;
786
787 /* Check if all MSI entries honor device restrictions */
788 ret = msi_verify_entries(dev);
789 if (ret)
790 goto out_free;
791
792 /*
793 * Some devices require MSI-X to be enabled before we can touch the
794 * MSI-X registers. We need to mask all the vectors to prevent
795 * interrupts coming in before they're fully set up.
796 */
797 pci_msix_clear_and_set_ctrl(dev, 0,
798 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
799
800 msix_program_entries(dev, entries);
801
802 ret = populate_msi_sysfs(dev);
803 if (ret)
804 goto out_free;
805
806 /* Set MSI-X enabled bits and unmask the function */
807 pci_intx_for_msi(dev, 0);
808 dev->msix_enabled = 1;
809 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
810
811 pcibios_free_irq(dev);
812 return 0;
813
814out_avail:
815 if (ret < 0) {
816 /*
817 * If we had some success, report the number of irqs
818 * we succeeded in setting up.
819 */
820 struct msi_desc *entry;
821 int avail = 0;
822
823 for_each_pci_msi_entry(entry, dev) {
824 if (entry->irq != 0)
825 avail++;
826 }
827 if (avail != 0)
828 ret = avail;
829 }
830
831out_free:
832 free_msi_irqs(dev);
833
834 return ret;
835}
836
837/**
838 * pci_msi_supported - check whether MSI may be enabled on a device
839 * @dev: pointer to the pci_dev data structure of MSI device function
840 * @nvec: how many MSIs have been requested ?
841 *
842 * Look at global flags, the device itself, and its parent buses
843 * to determine if MSI/-X are supported for the device. If MSI/-X is
844 * supported return 1, else return 0.
845 **/
846static int pci_msi_supported(struct pci_dev *dev, int nvec)
847{
848 struct pci_bus *bus;
849
850 /* MSI must be globally enabled and supported by the device */
851 if (!pci_msi_enable)
852 return 0;
853
854 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
855 return 0;
856
857 /*
858 * You can't ask to have 0 or less MSIs configured.
859 * a) it's stupid ..
860 * b) the list manipulation code assumes nvec >= 1.
861 */
862 if (nvec < 1)
863 return 0;
864
865 /*
866 * Any bridge which does NOT route MSI transactions from its
867 * secondary bus to its primary bus must set NO_MSI flag on
868 * the secondary pci_bus.
869 * We expect only arch-specific PCI host bus controller driver
870 * or quirks for specific PCI bridges to be setting NO_MSI.
871 */
872 for (bus = dev->bus; bus; bus = bus->parent)
873 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
874 return 0;
875
876 return 1;
877}
878
879/**
880 * pci_msi_vec_count - Return the number of MSI vectors a device can send
881 * @dev: device to report about
882 *
883 * This function returns the number of MSI vectors a device requested via
884 * Multiple Message Capable register. It returns a negative errno if the
885 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
886 * and returns a power of two, up to a maximum of 2^5 (32), according to the
887 * MSI specification.
888 **/
889int pci_msi_vec_count(struct pci_dev *dev)
890{
891 int ret;
892 u16 msgctl;
893
894 if (!dev->msi_cap)
895 return -EINVAL;
896
897 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
898 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
899
900 return ret;
901}
902EXPORT_SYMBOL(pci_msi_vec_count);
903
904void pci_msi_shutdown(struct pci_dev *dev)
905{
906 struct msi_desc *desc;
907 u32 mask;
908
909 if (!pci_msi_enable || !dev || !dev->msi_enabled)
910 return;
911
912 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
913 desc = first_pci_msi_entry(dev);
914
915 pci_msi_set_enable(dev, 0);
916 pci_intx_for_msi(dev, 1);
917 dev->msi_enabled = 0;
918
919 /* Return the device with MSI unmasked as initial states */
920 mask = msi_mask(desc->msi_attrib.multi_cap);
921 /* Keep cached state to be restored */
922 __pci_msi_desc_mask_irq(desc, mask, ~mask);
923
924 /* Restore dev->irq to its default pin-assertion irq */
925 dev->irq = desc->msi_attrib.default_irq;
926 pcibios_alloc_irq(dev);
927}
928
929void pci_disable_msi(struct pci_dev *dev)
930{
931 if (!pci_msi_enable || !dev || !dev->msi_enabled)
932 return;
933
934 pci_msi_shutdown(dev);
935 free_msi_irqs(dev);
936}
937EXPORT_SYMBOL(pci_disable_msi);
938
939/**
940 * pci_msix_vec_count - return the number of device's MSI-X table entries
941 * @dev: pointer to the pci_dev data structure of MSI-X device function
942 * This function returns the number of device's MSI-X table entries and
943 * therefore the number of MSI-X vectors device is capable of sending.
944 * It returns a negative errno if the device is not capable of sending MSI-X
945 * interrupts.
946 **/
947int pci_msix_vec_count(struct pci_dev *dev)
948{
949 u16 control;
950
951 if (!dev->msix_cap)
952 return -EINVAL;
953
954 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
955 return msix_table_size(control);
956}
957EXPORT_SYMBOL(pci_msix_vec_count);
958
959static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
960 int nvec, const struct irq_affinity *affd)
961{
962 int nr_entries;
963 int i, j;
964
965 if (!pci_msi_supported(dev, nvec))
966 return -EINVAL;
967
968 nr_entries = pci_msix_vec_count(dev);
969 if (nr_entries < 0)
970 return nr_entries;
971 if (nvec > nr_entries)
972 return nr_entries;
973
974 if (entries) {
975 /* Check for any invalid entries */
976 for (i = 0; i < nvec; i++) {
977 if (entries[i].entry >= nr_entries)
978 return -EINVAL; /* invalid entry */
979 for (j = i + 1; j < nvec; j++) {
980 if (entries[i].entry == entries[j].entry)
981 return -EINVAL; /* duplicate entry */
982 }
983 }
984 }
985 WARN_ON(!!dev->msix_enabled);
986
987 /* Check whether driver already requested for MSI irq */
988 if (dev->msi_enabled) {
989 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
990 return -EINVAL;
991 }
992 return msix_capability_init(dev, entries, nvec, affd);
993}
994
995/**
996 * pci_enable_msix - configure device's MSI-X capability structure
997 * @dev: pointer to the pci_dev data structure of MSI-X device function
998 * @entries: pointer to an array of MSI-X entries (optional)
999 * @nvec: number of MSI-X irqs requested for allocation by device driver
1000 *
1001 * Setup the MSI-X capability structure of device function with the number
1002 * of requested irqs upon its software driver call to request for
1003 * MSI-X mode enabled on its hardware device function. A return of zero
1004 * indicates the successful configuration of MSI-X capability structure
1005 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
1006 * Or a return of > 0 indicates that driver request is exceeding the number
1007 * of irqs or MSI-X vectors available. Driver should use the returned value to
1008 * re-send its request.
1009 **/
1010int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
1011{
1012 return __pci_enable_msix(dev, entries, nvec, NULL);
1013}
1014EXPORT_SYMBOL(pci_enable_msix);
1015
1016void pci_msix_shutdown(struct pci_dev *dev)
1017{
1018 struct msi_desc *entry;
1019
1020 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1021 return;
1022
1023 /* Return the device with MSI-X masked as initial states */
1024 for_each_pci_msi_entry(entry, dev) {
1025 /* Keep cached states to be restored */
1026 __pci_msix_desc_mask_irq(entry, 1);
1027 }
1028
1029 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1030 pci_intx_for_msi(dev, 1);
1031 dev->msix_enabled = 0;
1032 pcibios_alloc_irq(dev);
1033}
1034
1035void pci_disable_msix(struct pci_dev *dev)
1036{
1037 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1038 return;
1039
1040 pci_msix_shutdown(dev);
1041 free_msi_irqs(dev);
1042}
1043EXPORT_SYMBOL(pci_disable_msix);
1044
1045void pci_no_msi(void)
1046{
1047 pci_msi_enable = 0;
1048}
1049
1050/**
1051 * pci_msi_enabled - is MSI enabled?
1052 *
1053 * Returns true if MSI has not been disabled by the command-line option
1054 * pci=nomsi.
1055 **/
1056int pci_msi_enabled(void)
1057{
1058 return pci_msi_enable;
1059}
1060EXPORT_SYMBOL(pci_msi_enabled);
1061
1062static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1063 const struct irq_affinity *affd)
1064{
1065 int nvec;
1066 int rc;
1067
1068 if (!pci_msi_supported(dev, minvec))
1069 return -EINVAL;
1070
1071 WARN_ON(!!dev->msi_enabled);
1072
1073 /* Check whether driver already requested MSI-X irqs */
1074 if (dev->msix_enabled) {
1075 dev_info(&dev->dev,
1076 "can't enable MSI (MSI-X already enabled)\n");
1077 return -EINVAL;
1078 }
1079
1080 if (maxvec < minvec)
1081 return -ERANGE;
1082
1083 nvec = pci_msi_vec_count(dev);
1084 if (nvec < 0)
1085 return nvec;
1086 if (nvec < minvec)
1087 return -EINVAL;
1088
1089 if (nvec > maxvec)
1090 nvec = maxvec;
1091
1092 for (;;) {
1093 if (affd) {
1094 nvec = irq_calc_affinity_vectors(nvec, affd);
1095 if (nvec < minvec)
1096 return -ENOSPC;
1097 }
1098
1099 rc = msi_capability_init(dev, nvec, affd);
1100 if (rc == 0)
1101 return nvec;
1102
1103 if (rc < 0)
1104 return rc;
1105 if (rc < minvec)
1106 return -ENOSPC;
1107
1108 nvec = rc;
1109 }
1110}
1111
1112/**
1113 * pci_enable_msi_range - configure device's MSI capability structure
1114 * @dev: device to configure
1115 * @minvec: minimal number of interrupts to configure
1116 * @maxvec: maximum number of interrupts to configure
1117 *
1118 * This function tries to allocate a maximum possible number of interrupts in a
1119 * range between @minvec and @maxvec. It returns a negative errno if an error
1120 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1121 * and updates the @dev's irq member to the lowest new interrupt number;
1122 * the other interrupt numbers allocated to this device are consecutive.
1123 **/
1124int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1125{
1126 return __pci_enable_msi_range(dev, minvec, maxvec, NULL);
1127}
1128EXPORT_SYMBOL(pci_enable_msi_range);
1129
1130static int __pci_enable_msix_range(struct pci_dev *dev,
1131 struct msix_entry *entries, int minvec,
1132 int maxvec, const struct irq_affinity *affd)
1133{
1134 int rc, nvec = maxvec;
1135
1136 if (maxvec < minvec)
1137 return -ERANGE;
1138
1139 for (;;) {
1140 if (affd) {
1141 nvec = irq_calc_affinity_vectors(nvec, affd);
1142 if (nvec < minvec)
1143 return -ENOSPC;
1144 }
1145
1146 rc = __pci_enable_msix(dev, entries, nvec, affd);
1147 if (rc == 0)
1148 return nvec;
1149
1150 if (rc < 0)
1151 return rc;
1152 if (rc < minvec)
1153 return -ENOSPC;
1154
1155 nvec = rc;
1156 }
1157}
1158
1159/**
1160 * pci_enable_msix_range - configure device's MSI-X capability structure
1161 * @dev: pointer to the pci_dev data structure of MSI-X device function
1162 * @entries: pointer to an array of MSI-X entries
1163 * @minvec: minimum number of MSI-X irqs requested
1164 * @maxvec: maximum number of MSI-X irqs requested
1165 *
1166 * Setup the MSI-X capability structure of device function with a maximum
1167 * possible number of interrupts in the range between @minvec and @maxvec
1168 * upon its software driver call to request for MSI-X mode enabled on its
1169 * hardware device function. It returns a negative errno if an error occurs.
1170 * If it succeeds, it returns the actual number of interrupts allocated and
1171 * indicates the successful configuration of MSI-X capability structure
1172 * with new allocated MSI-X interrupts.
1173 **/
1174int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1175 int minvec, int maxvec)
1176{
1177 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL);
1178}
1179EXPORT_SYMBOL(pci_enable_msix_range);
1180
1181/**
1182 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1183 * @dev: PCI device to operate on
1184 * @min_vecs: minimum number of vectors required (must be >= 1)
1185 * @max_vecs: maximum (desired) number of vectors
1186 * @flags: flags or quirks for the allocation
1187 * @affd: optional description of the affinity requirements
1188 *
1189 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1190 * vectors if available, and fall back to a single legacy vector
1191 * if neither is available. Return the number of vectors allocated,
1192 * (which might be smaller than @max_vecs) if successful, or a negative
1193 * error code on error. If less than @min_vecs interrupt vectors are
1194 * available for @dev the function will fail with -ENOSPC.
1195 *
1196 * To get the Linux IRQ number used for a vector that can be passed to
1197 * request_irq() use the pci_irq_vector() helper.
1198 */
1199int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1200 unsigned int max_vecs, unsigned int flags,
1201 const struct irq_affinity *affd)
1202{
1203 static const struct irq_affinity msi_default_affd;
1204 int vecs = -ENOSPC;
1205
1206 if (flags & PCI_IRQ_AFFINITY) {
1207 if (!affd)
1208 affd = &msi_default_affd;
1209
1210 if (affd->pre_vectors + affd->post_vectors > min_vecs)
1211 return -EINVAL;
1212
1213 /*
1214 * If there aren't any vectors left after applying the pre/post
1215 * vectors don't bother with assigning affinity.
1216 */
1217 if (affd->pre_vectors + affd->post_vectors == min_vecs)
1218 affd = NULL;
1219 } else {
1220 if (WARN_ON(affd))
1221 affd = NULL;
1222 }
1223
1224 if (flags & PCI_IRQ_MSIX) {
1225 vecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1226 affd);
1227 if (vecs > 0)
1228 return vecs;
1229 }
1230
1231 if (flags & PCI_IRQ_MSI) {
1232 vecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1233 if (vecs > 0)
1234 return vecs;
1235 }
1236
1237 /* use legacy irq if allowed */
1238 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1) {
1239 pci_intx(dev, 1);
1240 return 1;
1241 }
1242
1243 return vecs;
1244}
1245EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1246
1247/**
1248 * pci_free_irq_vectors - free previously allocated IRQs for a device
1249 * @dev: PCI device to operate on
1250 *
1251 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1252 */
1253void pci_free_irq_vectors(struct pci_dev *dev)
1254{
1255 pci_disable_msix(dev);
1256 pci_disable_msi(dev);
1257}
1258EXPORT_SYMBOL(pci_free_irq_vectors);
1259
1260/**
1261 * pci_irq_vector - return Linux IRQ number of a device vector
1262 * @dev: PCI device to operate on
1263 * @nr: device-relative interrupt vector index (0-based).
1264 */
1265int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1266{
1267 if (dev->msix_enabled) {
1268 struct msi_desc *entry;
1269 int i = 0;
1270
1271 for_each_pci_msi_entry(entry, dev) {
1272 if (i == nr)
1273 return entry->irq;
1274 i++;
1275 }
1276 WARN_ON_ONCE(1);
1277 return -EINVAL;
1278 }
1279
1280 if (dev->msi_enabled) {
1281 struct msi_desc *entry = first_pci_msi_entry(dev);
1282
1283 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1284 return -EINVAL;
1285 } else {
1286 if (WARN_ON_ONCE(nr > 0))
1287 return -EINVAL;
1288 }
1289
1290 return dev->irq + nr;
1291}
1292EXPORT_SYMBOL(pci_irq_vector);
1293
1294/**
1295 * pci_irq_get_affinity - return the affinity of a particular msi vector
1296 * @dev: PCI device to operate on
1297 * @nr: device-relative interrupt vector index (0-based).
1298 */
1299const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1300{
1301 if (dev->msix_enabled) {
1302 struct msi_desc *entry;
1303 int i = 0;
1304
1305 for_each_pci_msi_entry(entry, dev) {
1306 if (i == nr)
1307 return entry->affinity;
1308 i++;
1309 }
1310 WARN_ON_ONCE(1);
1311 return NULL;
1312 } else if (dev->msi_enabled) {
1313 struct msi_desc *entry = first_pci_msi_entry(dev);
1314
1315 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1316 nr >= entry->nvec_used))
1317 return NULL;
1318
1319 return &entry->affinity[nr];
1320 } else {
1321 return cpu_possible_mask;
1322 }
1323}
1324EXPORT_SYMBOL(pci_irq_get_affinity);
1325
1326struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1327{
1328 return to_pci_dev(desc->dev);
1329}
1330EXPORT_SYMBOL(msi_desc_to_pci_dev);
1331
1332void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1333{
1334 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1335
1336 return dev->bus->sysdata;
1337}
1338EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1339
1340#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1341/**
1342 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1343 * @irq_data: Pointer to interrupt data of the MSI interrupt
1344 * @msg: Pointer to the message
1345 */
1346void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1347{
1348 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1349
1350 /*
1351 * For MSI-X desc->irq is always equal to irq_data->irq. For
1352 * MSI only the first interrupt of MULTI MSI passes the test.
1353 */
1354 if (desc->irq == irq_data->irq)
1355 __pci_write_msi_msg(desc, msg);
1356}
1357
1358/**
1359 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1360 * @dev: Pointer to the PCI device
1361 * @desc: Pointer to the msi descriptor
1362 *
1363 * The ID number is only used within the irqdomain.
1364 */
1365irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1366 struct msi_desc *desc)
1367{
1368 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1369 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1370 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1371}
1372
1373static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1374{
1375 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1376}
1377
1378/**
1379 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1380 * @domain: The interrupt domain to check
1381 * @info: The domain info for verification
1382 * @dev: The device to check
1383 *
1384 * Returns:
1385 * 0 if the functionality is supported
1386 * 1 if Multi MSI is requested, but the domain does not support it
1387 * -ENOTSUPP otherwise
1388 */
1389int pci_msi_domain_check_cap(struct irq_domain *domain,
1390 struct msi_domain_info *info, struct device *dev)
1391{
1392 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1393
1394 /* Special handling to support pci_enable_msi_range() */
1395 if (pci_msi_desc_is_multi_msi(desc) &&
1396 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1397 return 1;
1398 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1399 return -ENOTSUPP;
1400
1401 return 0;
1402}
1403
1404static int pci_msi_domain_handle_error(struct irq_domain *domain,
1405 struct msi_desc *desc, int error)
1406{
1407 /* Special handling to support pci_enable_msi_range() */
1408 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1409 return 1;
1410
1411 return error;
1412}
1413
1414#ifdef GENERIC_MSI_DOMAIN_OPS
1415static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1416 struct msi_desc *desc)
1417{
1418 arg->desc = desc;
1419 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1420 desc);
1421}
1422#else
1423#define pci_msi_domain_set_desc NULL
1424#endif
1425
1426static struct msi_domain_ops pci_msi_domain_ops_default = {
1427 .set_desc = pci_msi_domain_set_desc,
1428 .msi_check = pci_msi_domain_check_cap,
1429 .handle_error = pci_msi_domain_handle_error,
1430};
1431
1432static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1433{
1434 struct msi_domain_ops *ops = info->ops;
1435
1436 if (ops == NULL) {
1437 info->ops = &pci_msi_domain_ops_default;
1438 } else {
1439 if (ops->set_desc == NULL)
1440 ops->set_desc = pci_msi_domain_set_desc;
1441 if (ops->msi_check == NULL)
1442 ops->msi_check = pci_msi_domain_check_cap;
1443 if (ops->handle_error == NULL)
1444 ops->handle_error = pci_msi_domain_handle_error;
1445 }
1446}
1447
1448static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1449{
1450 struct irq_chip *chip = info->chip;
1451
1452 BUG_ON(!chip);
1453 if (!chip->irq_write_msi_msg)
1454 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1455 if (!chip->irq_mask)
1456 chip->irq_mask = pci_msi_mask_irq;
1457 if (!chip->irq_unmask)
1458 chip->irq_unmask = pci_msi_unmask_irq;
1459}
1460
1461/**
1462 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1463 * @fwnode: Optional fwnode of the interrupt controller
1464 * @info: MSI domain info
1465 * @parent: Parent irq domain
1466 *
1467 * Updates the domain and chip ops and creates a MSI interrupt domain.
1468 *
1469 * Returns:
1470 * A domain pointer or NULL in case of failure.
1471 */
1472struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1473 struct msi_domain_info *info,
1474 struct irq_domain *parent)
1475{
1476 struct irq_domain *domain;
1477
1478 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1479 pci_msi_domain_update_dom_ops(info);
1480 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1481 pci_msi_domain_update_chip_ops(info);
1482
1483 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1484
1485 domain = msi_create_irq_domain(fwnode, info, parent);
1486 if (!domain)
1487 return NULL;
1488
1489 domain->bus_token = DOMAIN_BUS_PCI_MSI;
1490 return domain;
1491}
1492EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1493
1494/**
1495 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1496 * @domain: The interrupt domain to allocate from
1497 * @dev: The device for which to allocate
1498 * @nvec: The number of interrupts to allocate
1499 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1500 *
1501 * Returns:
1502 * A virtual interrupt number or an error code in case of failure
1503 */
1504int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1505 int nvec, int type)
1506{
1507 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1508}
1509
1510/**
1511 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1512 * @domain: The interrupt domain
1513 * @dev: The device for which to free interrupts
1514 */
1515void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1516{
1517 msi_domain_free_irqs(domain, &dev->dev);
1518}
1519
1520/**
1521 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1522 * @fwnode: Optional fwnode of the interrupt controller
1523 * @info: MSI domain info
1524 * @parent: Parent irq domain
1525 *
1526 * Returns: A domain pointer or NULL in case of failure. If successful
1527 * the default PCI/MSI irqdomain pointer is updated.
1528 */
1529struct irq_domain *pci_msi_create_default_irq_domain(struct fwnode_handle *fwnode,
1530 struct msi_domain_info *info, struct irq_domain *parent)
1531{
1532 struct irq_domain *domain;
1533
1534 mutex_lock(&pci_msi_domain_lock);
1535 if (pci_msi_default_domain) {
1536 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1537 domain = NULL;
1538 } else {
1539 domain = pci_msi_create_irq_domain(fwnode, info, parent);
1540 pci_msi_default_domain = domain;
1541 }
1542 mutex_unlock(&pci_msi_domain_lock);
1543
1544 return domain;
1545}
1546
1547static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1548{
1549 u32 *pa = data;
1550
1551 *pa = alias;
1552 return 0;
1553}
1554/**
1555 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1556 * @domain: The interrupt domain
1557 * @pdev: The PCI device.
1558 *
1559 * The RID for a device is formed from the alias, with a firmware
1560 * supplied mapping applied
1561 *
1562 * Returns: The RID.
1563 */
1564u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1565{
1566 struct device_node *of_node;
1567 u32 rid = 0;
1568
1569 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1570
1571 of_node = irq_domain_get_of_node(domain);
1572 rid = of_node ? of_msi_map_rid(&pdev->dev, of_node, rid) :
1573 iort_msi_map_rid(&pdev->dev, rid);
1574
1575 return rid;
1576}
1577
1578/**
1579 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1580 * @pdev: The PCI device
1581 *
1582 * Use the firmware data to find a device-specific MSI domain
1583 * (i.e. not one that is ste as a default).
1584 *
1585 * Returns: The coresponding MSI domain or NULL if none has been found.
1586 */
1587struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1588{
1589 struct irq_domain *dom;
1590 u32 rid = 0;
1591
1592 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1593 dom = of_msi_map_get_device_domain(&pdev->dev, rid);
1594 if (!dom)
1595 dom = iort_get_device_domain(&pdev->dev, rid);
1596 return dom;
1597}
1598#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */