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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12#include <dt-bindings/clock/omap5.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1500000 1250000
49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55
56 /* cooling options */
57 #cooling-cells = <2>; /* min followed by max */
58 };
59 cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0x1>;
63
64 operating-points = <
65 /* kHz uV */
66 1000000 1060000
67 1500000 1250000
68 >;
69
70 clocks = <&dpll_mpu_ck>;
71 clock-names = "cpu";
72
73 clock-latency = <300000>; /* From omap-cpufreq driver */
74
75 /* cooling options */
76 #cooling-cells = <2>; /* min followed by max */
77 };
78 };
79
80 thermal-zones {
81 #include "omap4-cpu-thermal.dtsi"
82 #include "omap5-gpu-thermal.dtsi"
83 #include "omap5-core-thermal.dtsi"
84 };
85
86 timer {
87 compatible = "arm,armv7-timer";
88 /* PPI secure/nonsecure IRQ */
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
93 interrupt-parent = <&gic>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a15-pmu";
98 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 gic: interrupt-controller@48211000 {
103 compatible = "arm,cortex-a15-gic";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0 0x48211000 0 0x1000>,
107 <0 0x48212000 0 0x2000>,
108 <0 0x48214000 0 0x2000>,
109 <0 0x48216000 0 0x2000>;
110 interrupt-parent = <&gic>;
111 };
112
113 wakeupgen: interrupt-controller@48281000 {
114 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
115 interrupt-controller;
116 #interrupt-cells = <3>;
117 reg = <0 0x48281000 0 0x1000>;
118 interrupt-parent = <&gic>;
119 };
120
121 /*
122 * The soc node represents the soc top level view. It is used for IPs
123 * that are not memory mapped in the MPU view or for the MPU itself.
124 */
125 soc {
126 compatible = "ti,omap-infra";
127 mpu {
128 compatible = "ti,omap4-mpu";
129 ti,hwmods = "mpu";
130 sram = <&ocmcram>;
131 };
132 };
133
134 /*
135 * XXX: Use a flat representation of the OMAP3 interconnect.
136 * The real OMAP interconnect network is quite complex.
137 * Since it will not bring real advantage to represent that in DT for
138 * the moment, just use a fake OCP bus entry to represent the whole bus
139 * hierarchy.
140 */
141 ocp {
142 compatible = "ti,omap5-l3-noc", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0 0 0xc0000000>;
146 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
147 reg = <0 0x44000000 0 0x2000>,
148 <0 0x44800000 0 0x3000>,
149 <0 0x45000000 0 0x4000>;
150 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
152
153 l4_wkup: interconnect@4ae00000 {
154 };
155
156 l4_cfg: interconnect@4a000000 {
157 };
158
159 l4_per: interconnect@48000000 {
160 };
161
162 l4_abe: interconnect@40100000 {
163 };
164
165 ocmcram: ocmcram@40300000 {
166 compatible = "mmio-sram";
167 reg = <0x40300000 0x20000>; /* 128k */
168 };
169
170 gpmc: gpmc@50000000 {
171 compatible = "ti,omap4430-gpmc";
172 reg = <0x50000000 0x1000>;
173 #address-cells = <2>;
174 #size-cells = <1>;
175 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
176 dmas = <&sdma 4>;
177 dma-names = "rxtx";
178 gpmc,num-cs = <8>;
179 gpmc,num-waitpins = <4>;
180 ti,hwmods = "gpmc";
181 clocks = <&l3_iclk_div>;
182 clock-names = "fck";
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 gpio-controller;
186 #gpio-cells = <2>;
187 };
188
189 mmu_dsp: mmu@4a066000 {
190 compatible = "ti,omap4-iommu";
191 reg = <0x4a066000 0x100>;
192 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "mmu_dsp";
194 #iommu-cells = <0>;
195 };
196
197 mmu_ipu: mmu@55082000 {
198 compatible = "ti,omap4-iommu";
199 reg = <0x55082000 0x100>;
200 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
201 ti,hwmods = "mmu_ipu";
202 #iommu-cells = <0>;
203 ti,iommu-bus-err-back;
204 };
205
206 dmm@4e000000 {
207 compatible = "ti,omap5-dmm";
208 reg = <0x4e000000 0x800>;
209 interrupts = <0 113 0x4>;
210 ti,hwmods = "dmm";
211 };
212
213 emif1: emif@4c000000 {
214 compatible = "ti,emif-4d5";
215 ti,hwmods = "emif1";
216 ti,no-idle-on-init;
217 phy-type = <2>; /* DDR PHY type: Intelli PHY */
218 reg = <0x4c000000 0x400>;
219 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
220 hw-caps-read-idle-ctrl;
221 hw-caps-ll-interface;
222 hw-caps-temp-alert;
223 };
224
225 emif2: emif@4d000000 {
226 compatible = "ti,emif-4d5";
227 ti,hwmods = "emif2";
228 ti,no-idle-on-init;
229 phy-type = <2>; /* DDR PHY type: Intelli PHY */
230 reg = <0x4d000000 0x400>;
231 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
232 hw-caps-read-idle-ctrl;
233 hw-caps-ll-interface;
234 hw-caps-temp-alert;
235 };
236
237 bandgap: bandgap@4a0021e0 {
238 reg = <0x4a0021e0 0xc
239 0x4a00232c 0xc
240 0x4a002380 0x2c
241 0x4a0023C0 0x3c>;
242 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
243 compatible = "ti,omap5430-bandgap";
244
245 #thermal-sensor-cells = <1>;
246 };
247
248 /* OCP2SCP3 */
249 sata: sata@4a141100 {
250 compatible = "snps,dwc-ahci";
251 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
252 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
253 phys = <&sata_phy>;
254 phy-names = "sata-phy";
255 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
256 ti,hwmods = "sata";
257 ports-implemented = <0x1>;
258 };
259
260 target-module@56000000 {
261 compatible = "ti,sysc-omap4", "ti,sysc";
262 reg = <0x5600fe00 0x4>,
263 <0x5600fe10 0x4>;
264 reg-names = "rev", "sysc";
265 ti,sysc-midle = <SYSC_IDLE_FORCE>,
266 <SYSC_IDLE_NO>,
267 <SYSC_IDLE_SMART>;
268 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
269 <SYSC_IDLE_NO>,
270 <SYSC_IDLE_SMART>;
271 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
272 clock-names = "fck";
273 #address-cells = <1>;
274 #size-cells = <1>;
275 ranges = <0 0x56000000 0x2000000>;
276
277 /*
278 * Closed source PowerVR driver, no child device
279 * binding or driver in mainline
280 */
281 };
282
283 dss: dss@58000000 {
284 compatible = "ti,omap5-dss";
285 reg = <0x58000000 0x80>;
286 status = "disabled";
287 ti,hwmods = "dss_core";
288 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
289 clock-names = "fck";
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293
294 dispc@58001000 {
295 compatible = "ti,omap5-dispc";
296 reg = <0x58001000 0x1000>;
297 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
298 ti,hwmods = "dss_dispc";
299 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
300 clock-names = "fck";
301 };
302
303 rfbi: encoder@58002000 {
304 compatible = "ti,omap5-rfbi";
305 reg = <0x58002000 0x100>;
306 status = "disabled";
307 ti,hwmods = "dss_rfbi";
308 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
309 clock-names = "fck", "ick";
310 };
311
312 dsi1: encoder@58004000 {
313 compatible = "ti,omap5-dsi";
314 reg = <0x58004000 0x200>,
315 <0x58004200 0x40>,
316 <0x58004300 0x40>;
317 reg-names = "proto", "phy", "pll";
318 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
319 status = "disabled";
320 ti,hwmods = "dss_dsi1";
321 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
322 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
323 clock-names = "fck", "sys_clk";
324 };
325
326 dsi2: encoder@58005000 {
327 compatible = "ti,omap5-dsi";
328 reg = <0x58009000 0x200>,
329 <0x58009200 0x40>,
330 <0x58009300 0x40>;
331 reg-names = "proto", "phy", "pll";
332 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
333 status = "disabled";
334 ti,hwmods = "dss_dsi2";
335 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
336 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
337 clock-names = "fck", "sys_clk";
338 };
339
340 hdmi: encoder@58060000 {
341 compatible = "ti,omap5-hdmi";
342 reg = <0x58040000 0x200>,
343 <0x58040200 0x80>,
344 <0x58040300 0x80>,
345 <0x58060000 0x19000>;
346 reg-names = "wp", "pll", "phy", "core";
347 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
348 status = "disabled";
349 ti,hwmods = "dss_hdmi";
350 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
351 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
352 clock-names = "fck", "sys_clk";
353 dmas = <&sdma 76>;
354 dma-names = "audio_tx";
355 };
356 };
357
358 abb_mpu: regulator-abb-mpu {
359 compatible = "ti,abb-v2";
360 regulator-name = "abb_mpu";
361 #address-cells = <0>;
362 #size-cells = <0>;
363 clocks = <&sys_clkin>;
364 ti,settling-time = <50>;
365 ti,clock-cycles = <16>;
366
367 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
368 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
369 reg-names = "base-address", "int-address",
370 "efuse-address", "ldo-address";
371 ti,tranxdone-status-mask = <0x80>;
372 /* LDOVBBMPU_MUX_CTRL */
373 ti,ldovbb-override-mask = <0x400>;
374 /* LDOVBBMPU_VSET_OUT */
375 ti,ldovbb-vset-mask = <0x1F>;
376
377 /*
378 * NOTE: only FBB mode used but actual vset will
379 * determine final biasing
380 */
381 ti,abb_info = <
382 /*uV ABB efuse rbb_m fbb_m vset_m*/
383 1060000 0 0x0 0 0x02000000 0x01F00000
384 1250000 0 0x4 0 0x02000000 0x01F00000
385 >;
386 };
387
388 abb_mm: regulator-abb-mm {
389 compatible = "ti,abb-v2";
390 regulator-name = "abb_mm";
391 #address-cells = <0>;
392 #size-cells = <0>;
393 clocks = <&sys_clkin>;
394 ti,settling-time = <50>;
395 ti,clock-cycles = <16>;
396
397 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
398 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
399 reg-names = "base-address", "int-address",
400 "efuse-address", "ldo-address";
401 ti,tranxdone-status-mask = <0x80000000>;
402 /* LDOVBBMM_MUX_CTRL */
403 ti,ldovbb-override-mask = <0x400>;
404 /* LDOVBBMM_VSET_OUT */
405 ti,ldovbb-vset-mask = <0x1F>;
406
407 /*
408 * NOTE: only FBB mode used but actual vset will
409 * determine final biasing
410 */
411 ti,abb_info = <
412 /*uV ABB efuse rbb_m fbb_m vset_m*/
413 1025000 0 0x0 0 0x02000000 0x01F00000
414 1120000 0 0x4 0 0x02000000 0x01F00000
415 >;
416 };
417 };
418};
419
420&cpu_thermal {
421 polling-delay = <500>; /* milliseconds */
422 coefficients = <65 (-1791)>;
423};
424
425#include "omap5-l4.dtsi"
426#include "omap54xx-clocks.dtsi"
427
428&gpu_thermal {
429 coefficients = <117 (-2992)>;
430};
431
432&core_thermal {
433 coefficients = <0 2000>;
434};
435
436#include "omap5-l4-abe.dtsi"
437#include "omap54xx-clocks.dtsi"
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/pinctrl/omap.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1500000 1250000
49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55
56 /* cooling options */
57 cooling-min-level = <0>;
58 cooling-max-level = <2>;
59 #cooling-cells = <2>; /* min followed by max */
60 };
61 cpu@1 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0x1>;
65 };
66 };
67
68 thermal-zones {
69 #include "omap4-cpu-thermal.dtsi"
70 #include "omap5-gpu-thermal.dtsi"
71 #include "omap5-core-thermal.dtsi"
72 };
73
74 timer {
75 compatible = "arm,armv7-timer";
76 /* PPI secure/nonsecure IRQ */
77 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
78 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
81 interrupt-parent = <&gic>;
82 };
83
84 pmu {
85 compatible = "arm,cortex-a15-pmu";
86 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
88 };
89
90 gic: interrupt-controller@48211000 {
91 compatible = "arm,cortex-a15-gic";
92 interrupt-controller;
93 #interrupt-cells = <3>;
94 reg = <0 0x48211000 0 0x1000>,
95 <0 0x48212000 0 0x1000>,
96 <0 0x48214000 0 0x2000>,
97 <0 0x48216000 0 0x2000>;
98 interrupt-parent = <&gic>;
99 };
100
101 wakeupgen: interrupt-controller@48281000 {
102 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
103 interrupt-controller;
104 #interrupt-cells = <3>;
105 reg = <0 0x48281000 0 0x1000>;
106 interrupt-parent = <&gic>;
107 };
108
109 /*
110 * The soc node represents the soc top level view. It is used for IPs
111 * that are not memory mapped in the MPU view or for the MPU itself.
112 */
113 soc {
114 compatible = "ti,omap-infra";
115 mpu {
116 compatible = "ti,omap4-mpu";
117 ti,hwmods = "mpu";
118 sram = <&ocmcram>;
119 };
120 };
121
122 /*
123 * XXX: Use a flat representation of the OMAP3 interconnect.
124 * The real OMAP interconnect network is quite complex.
125 * Since it will not bring real advantage to represent that in DT for
126 * the moment, just use a fake OCP bus entry to represent the whole bus
127 * hierarchy.
128 */
129 ocp {
130 compatible = "ti,omap5-l3-noc", "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
133 ranges = <0 0 0 0xc0000000>;
134 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
135 reg = <0 0x44000000 0 0x2000>,
136 <0 0x44800000 0 0x3000>,
137 <0 0x45000000 0 0x4000>;
138 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
140
141 l4_cfg: l4@4a000000 {
142 compatible = "ti,omap5-l4-cfg", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0x4a000000 0x22a000>;
146
147 scm_core: scm@2000 {
148 compatible = "ti,omap5-scm-core", "simple-bus";
149 reg = <0x2000 0x1000>;
150 #address-cells = <1>;
151 #size-cells = <1>;
152 ranges = <0 0x2000 0x800>;
153
154 scm_conf: scm_conf@0 {
155 compatible = "syscon";
156 reg = <0x0 0x800>;
157 #address-cells = <1>;
158 #size-cells = <1>;
159 };
160 };
161
162 scm_padconf_core: scm@2800 {
163 compatible = "ti,omap5-scm-padconf-core",
164 "simple-bus";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0 0x2800 0x800>;
168
169 omap5_pmx_core: pinmux@40 {
170 compatible = "ti,omap5-padconf",
171 "pinctrl-single";
172 reg = <0x40 0x01b6>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 #pinctrl-cells = <1>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <16>;
179 pinctrl-single,function-mask = <0x7fff>;
180 };
181
182 omap5_padconf_global: omap5_padconf_global@5a0 {
183 compatible = "syscon",
184 "simple-bus";
185 reg = <0x5a0 0xec>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188 ranges = <0 0x5a0 0xec>;
189
190 pbias_regulator: pbias_regulator@60 {
191 compatible = "ti,pbias-omap5", "ti,pbias-omap";
192 reg = <0x60 0x4>;
193 syscon = <&omap5_padconf_global>;
194 pbias_mmc_reg: pbias_mmc_omap5 {
195 regulator-name = "pbias_mmc_omap5";
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <3000000>;
198 };
199 };
200 };
201 };
202
203 cm_core_aon: cm_core_aon@4000 {
204 compatible = "ti,omap5-cm-core-aon";
205 reg = <0x4000 0x2000>;
206
207 cm_core_aon_clocks: clocks {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 };
211
212 cm_core_aon_clockdomains: clockdomains {
213 };
214 };
215
216 cm_core: cm_core@8000 {
217 compatible = "ti,omap5-cm-core";
218 reg = <0x8000 0x3000>;
219
220 cm_core_clocks: clocks {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 };
224
225 cm_core_clockdomains: clockdomains {
226 };
227 };
228 };
229
230 l4_wkup: l4@4ae00000 {
231 compatible = "ti,omap5-l4-wkup", "simple-bus";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges = <0 0x4ae00000 0x2b000>;
235
236 counter32k: counter@4000 {
237 compatible = "ti,omap-counter32k";
238 reg = <0x4000 0x40>;
239 ti,hwmods = "counter_32k";
240 };
241
242 prm: prm@6000 {
243 compatible = "ti,omap5-prm";
244 reg = <0x6000 0x3000>;
245 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
246
247 prm_clocks: clocks {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 };
251
252 prm_clockdomains: clockdomains {
253 };
254 };
255
256 scrm: scrm@a000 {
257 compatible = "ti,omap5-scrm";
258 reg = <0xa000 0x2000>;
259
260 scrm_clocks: clocks {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 };
264
265 scrm_clockdomains: clockdomains {
266 };
267 };
268
269 omap5_pmx_wkup: pinmux@c840 {
270 compatible = "ti,omap5-padconf",
271 "pinctrl-single";
272 reg = <0xc840 0x003c>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 #pinctrl-cells = <1>;
276 #interrupt-cells = <1>;
277 interrupt-controller;
278 pinctrl-single,register-width = <16>;
279 pinctrl-single,function-mask = <0x7fff>;
280 };
281 };
282
283 ocmcram: ocmcram@40300000 {
284 compatible = "mmio-sram";
285 reg = <0x40300000 0x20000>; /* 128k */
286 };
287
288 sdma: dma-controller@4a056000 {
289 compatible = "ti,omap4430-sdma";
290 reg = <0x4a056000 0x1000>;
291 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
295 #dma-cells = <1>;
296 dma-channels = <32>;
297 dma-requests = <127>;
298 };
299
300 gpio1: gpio@4ae10000 {
301 compatible = "ti,omap4-gpio";
302 reg = <0x4ae10000 0x200>;
303 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "gpio1";
305 ti,gpio-always-on;
306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 };
311
312 gpio2: gpio@48055000 {
313 compatible = "ti,omap4-gpio";
314 reg = <0x48055000 0x200>;
315 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
316 ti,hwmods = "gpio2";
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 };
322
323 gpio3: gpio@48057000 {
324 compatible = "ti,omap4-gpio";
325 reg = <0x48057000 0x200>;
326 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
327 ti,hwmods = "gpio3";
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 };
333
334 gpio4: gpio@48059000 {
335 compatible = "ti,omap4-gpio";
336 reg = <0x48059000 0x200>;
337 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
338 ti,hwmods = "gpio4";
339 gpio-controller;
340 #gpio-cells = <2>;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 };
344
345 gpio5: gpio@4805b000 {
346 compatible = "ti,omap4-gpio";
347 reg = <0x4805b000 0x200>;
348 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
349 ti,hwmods = "gpio5";
350 gpio-controller;
351 #gpio-cells = <2>;
352 interrupt-controller;
353 #interrupt-cells = <2>;
354 };
355
356 gpio6: gpio@4805d000 {
357 compatible = "ti,omap4-gpio";
358 reg = <0x4805d000 0x200>;
359 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
360 ti,hwmods = "gpio6";
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
365 };
366
367 gpio7: gpio@48051000 {
368 compatible = "ti,omap4-gpio";
369 reg = <0x48051000 0x200>;
370 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "gpio7";
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 };
377
378 gpio8: gpio@48053000 {
379 compatible = "ti,omap4-gpio";
380 reg = <0x48053000 0x200>;
381 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
382 ti,hwmods = "gpio8";
383 gpio-controller;
384 #gpio-cells = <2>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 };
388
389 gpmc: gpmc@50000000 {
390 compatible = "ti,omap4430-gpmc";
391 reg = <0x50000000 0x1000>;
392 #address-cells = <2>;
393 #size-cells = <1>;
394 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
395 dmas = <&sdma 4>;
396 dma-names = "rxtx";
397 gpmc,num-cs = <8>;
398 gpmc,num-waitpins = <4>;
399 ti,hwmods = "gpmc";
400 clocks = <&l3_iclk_div>;
401 clock-names = "fck";
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 gpio-controller;
405 #gpio-cells = <2>;
406 };
407
408 i2c1: i2c@48070000 {
409 compatible = "ti,omap4-i2c";
410 reg = <0x48070000 0x100>;
411 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 ti,hwmods = "i2c1";
415 };
416
417 i2c2: i2c@48072000 {
418 compatible = "ti,omap4-i2c";
419 reg = <0x48072000 0x100>;
420 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
421 #address-cells = <1>;
422 #size-cells = <0>;
423 ti,hwmods = "i2c2";
424 };
425
426 i2c3: i2c@48060000 {
427 compatible = "ti,omap4-i2c";
428 reg = <0x48060000 0x100>;
429 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
431 #size-cells = <0>;
432 ti,hwmods = "i2c3";
433 };
434
435 i2c4: i2c@4807a000 {
436 compatible = "ti,omap4-i2c";
437 reg = <0x4807a000 0x100>;
438 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 ti,hwmods = "i2c4";
442 };
443
444 i2c5: i2c@4807c000 {
445 compatible = "ti,omap4-i2c";
446 reg = <0x4807c000 0x100>;
447 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
448 #address-cells = <1>;
449 #size-cells = <0>;
450 ti,hwmods = "i2c5";
451 };
452
453 hwspinlock: spinlock@4a0f6000 {
454 compatible = "ti,omap4-hwspinlock";
455 reg = <0x4a0f6000 0x1000>;
456 ti,hwmods = "spinlock";
457 #hwlock-cells = <1>;
458 };
459
460 mcspi1: spi@48098000 {
461 compatible = "ti,omap4-mcspi";
462 reg = <0x48098000 0x200>;
463 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 ti,hwmods = "mcspi1";
467 ti,spi-num-cs = <4>;
468 dmas = <&sdma 35>,
469 <&sdma 36>,
470 <&sdma 37>,
471 <&sdma 38>,
472 <&sdma 39>,
473 <&sdma 40>,
474 <&sdma 41>,
475 <&sdma 42>;
476 dma-names = "tx0", "rx0", "tx1", "rx1",
477 "tx2", "rx2", "tx3", "rx3";
478 };
479
480 mcspi2: spi@4809a000 {
481 compatible = "ti,omap4-mcspi";
482 reg = <0x4809a000 0x200>;
483 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
484 #address-cells = <1>;
485 #size-cells = <0>;
486 ti,hwmods = "mcspi2";
487 ti,spi-num-cs = <2>;
488 dmas = <&sdma 43>,
489 <&sdma 44>,
490 <&sdma 45>,
491 <&sdma 46>;
492 dma-names = "tx0", "rx0", "tx1", "rx1";
493 };
494
495 mcspi3: spi@480b8000 {
496 compatible = "ti,omap4-mcspi";
497 reg = <0x480b8000 0x200>;
498 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
500 #size-cells = <0>;
501 ti,hwmods = "mcspi3";
502 ti,spi-num-cs = <2>;
503 dmas = <&sdma 15>, <&sdma 16>;
504 dma-names = "tx0", "rx0";
505 };
506
507 mcspi4: spi@480ba000 {
508 compatible = "ti,omap4-mcspi";
509 reg = <0x480ba000 0x200>;
510 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 ti,hwmods = "mcspi4";
514 ti,spi-num-cs = <1>;
515 dmas = <&sdma 70>, <&sdma 71>;
516 dma-names = "tx0", "rx0";
517 };
518
519 uart1: serial@4806a000 {
520 compatible = "ti,omap4-uart";
521 reg = <0x4806a000 0x100>;
522 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
523 ti,hwmods = "uart1";
524 clock-frequency = <48000000>;
525 };
526
527 uart2: serial@4806c000 {
528 compatible = "ti,omap4-uart";
529 reg = <0x4806c000 0x100>;
530 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
531 ti,hwmods = "uart2";
532 clock-frequency = <48000000>;
533 };
534
535 uart3: serial@48020000 {
536 compatible = "ti,omap4-uart";
537 reg = <0x48020000 0x100>;
538 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
539 ti,hwmods = "uart3";
540 clock-frequency = <48000000>;
541 };
542
543 uart4: serial@4806e000 {
544 compatible = "ti,omap4-uart";
545 reg = <0x4806e000 0x100>;
546 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
547 ti,hwmods = "uart4";
548 clock-frequency = <48000000>;
549 };
550
551 uart5: serial@48066000 {
552 compatible = "ti,omap4-uart";
553 reg = <0x48066000 0x100>;
554 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
555 ti,hwmods = "uart5";
556 clock-frequency = <48000000>;
557 };
558
559 uart6: serial@48068000 {
560 compatible = "ti,omap4-uart";
561 reg = <0x48068000 0x100>;
562 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "uart6";
564 clock-frequency = <48000000>;
565 };
566
567 mmc1: mmc@4809c000 {
568 compatible = "ti,omap4-hsmmc";
569 reg = <0x4809c000 0x400>;
570 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
571 ti,hwmods = "mmc1";
572 ti,dual-volt;
573 ti,needs-special-reset;
574 dmas = <&sdma 61>, <&sdma 62>;
575 dma-names = "tx", "rx";
576 pbias-supply = <&pbias_mmc_reg>;
577 };
578
579 mmc2: mmc@480b4000 {
580 compatible = "ti,omap4-hsmmc";
581 reg = <0x480b4000 0x400>;
582 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
583 ti,hwmods = "mmc2";
584 ti,needs-special-reset;
585 dmas = <&sdma 47>, <&sdma 48>;
586 dma-names = "tx", "rx";
587 };
588
589 mmc3: mmc@480ad000 {
590 compatible = "ti,omap4-hsmmc";
591 reg = <0x480ad000 0x400>;
592 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
593 ti,hwmods = "mmc3";
594 ti,needs-special-reset;
595 dmas = <&sdma 77>, <&sdma 78>;
596 dma-names = "tx", "rx";
597 };
598
599 mmc4: mmc@480d1000 {
600 compatible = "ti,omap4-hsmmc";
601 reg = <0x480d1000 0x400>;
602 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
603 ti,hwmods = "mmc4";
604 ti,needs-special-reset;
605 dmas = <&sdma 57>, <&sdma 58>;
606 dma-names = "tx", "rx";
607 };
608
609 mmc5: mmc@480d5000 {
610 compatible = "ti,omap4-hsmmc";
611 reg = <0x480d5000 0x400>;
612 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
613 ti,hwmods = "mmc5";
614 ti,needs-special-reset;
615 dmas = <&sdma 59>, <&sdma 60>;
616 dma-names = "tx", "rx";
617 };
618
619 mmu_dsp: mmu@4a066000 {
620 compatible = "ti,omap4-iommu";
621 reg = <0x4a066000 0x100>;
622 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
623 ti,hwmods = "mmu_dsp";
624 #iommu-cells = <0>;
625 };
626
627 mmu_ipu: mmu@55082000 {
628 compatible = "ti,omap4-iommu";
629 reg = <0x55082000 0x100>;
630 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
631 ti,hwmods = "mmu_ipu";
632 #iommu-cells = <0>;
633 ti,iommu-bus-err-back;
634 };
635
636 keypad: keypad@4ae1c000 {
637 compatible = "ti,omap4-keypad";
638 reg = <0x4ae1c000 0x400>;
639 ti,hwmods = "kbd";
640 };
641
642 mcpdm: mcpdm@40132000 {
643 compatible = "ti,omap4-mcpdm";
644 reg = <0x40132000 0x7f>, /* MPU private access */
645 <0x49032000 0x7f>; /* L3 Interconnect */
646 reg-names = "mpu", "dma";
647 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
648 ti,hwmods = "mcpdm";
649 dmas = <&sdma 65>,
650 <&sdma 66>;
651 dma-names = "up_link", "dn_link";
652 status = "disabled";
653 };
654
655 dmic: dmic@4012e000 {
656 compatible = "ti,omap4-dmic";
657 reg = <0x4012e000 0x7f>, /* MPU private access */
658 <0x4902e000 0x7f>; /* L3 Interconnect */
659 reg-names = "mpu", "dma";
660 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
661 ti,hwmods = "dmic";
662 dmas = <&sdma 67>;
663 dma-names = "up_link";
664 status = "disabled";
665 };
666
667 mcbsp1: mcbsp@40122000 {
668 compatible = "ti,omap4-mcbsp";
669 reg = <0x40122000 0xff>, /* MPU private access */
670 <0x49022000 0xff>; /* L3 Interconnect */
671 reg-names = "mpu", "dma";
672 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
673 interrupt-names = "common";
674 ti,buffer-size = <128>;
675 ti,hwmods = "mcbsp1";
676 dmas = <&sdma 33>,
677 <&sdma 34>;
678 dma-names = "tx", "rx";
679 status = "disabled";
680 };
681
682 mcbsp2: mcbsp@40124000 {
683 compatible = "ti,omap4-mcbsp";
684 reg = <0x40124000 0xff>, /* MPU private access */
685 <0x49024000 0xff>; /* L3 Interconnect */
686 reg-names = "mpu", "dma";
687 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
688 interrupt-names = "common";
689 ti,buffer-size = <128>;
690 ti,hwmods = "mcbsp2";
691 dmas = <&sdma 17>,
692 <&sdma 18>;
693 dma-names = "tx", "rx";
694 status = "disabled";
695 };
696
697 mcbsp3: mcbsp@40126000 {
698 compatible = "ti,omap4-mcbsp";
699 reg = <0x40126000 0xff>, /* MPU private access */
700 <0x49026000 0xff>; /* L3 Interconnect */
701 reg-names = "mpu", "dma";
702 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
703 interrupt-names = "common";
704 ti,buffer-size = <128>;
705 ti,hwmods = "mcbsp3";
706 dmas = <&sdma 19>,
707 <&sdma 20>;
708 dma-names = "tx", "rx";
709 status = "disabled";
710 };
711
712 mailbox: mailbox@4a0f4000 {
713 compatible = "ti,omap4-mailbox";
714 reg = <0x4a0f4000 0x200>;
715 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
716 ti,hwmods = "mailbox";
717 #mbox-cells = <1>;
718 ti,mbox-num-users = <3>;
719 ti,mbox-num-fifos = <8>;
720 mbox_ipu: mbox_ipu {
721 ti,mbox-tx = <0 0 0>;
722 ti,mbox-rx = <1 0 0>;
723 };
724 mbox_dsp: mbox_dsp {
725 ti,mbox-tx = <3 0 0>;
726 ti,mbox-rx = <2 0 0>;
727 };
728 };
729
730 timer1: timer@4ae18000 {
731 compatible = "ti,omap5430-timer";
732 reg = <0x4ae18000 0x80>;
733 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
734 ti,hwmods = "timer1";
735 ti,timer-alwon;
736 };
737
738 timer2: timer@48032000 {
739 compatible = "ti,omap5430-timer";
740 reg = <0x48032000 0x80>;
741 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
742 ti,hwmods = "timer2";
743 };
744
745 timer3: timer@48034000 {
746 compatible = "ti,omap5430-timer";
747 reg = <0x48034000 0x80>;
748 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
749 ti,hwmods = "timer3";
750 };
751
752 timer4: timer@48036000 {
753 compatible = "ti,omap5430-timer";
754 reg = <0x48036000 0x80>;
755 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
756 ti,hwmods = "timer4";
757 };
758
759 timer5: timer@40138000 {
760 compatible = "ti,omap5430-timer";
761 reg = <0x40138000 0x80>,
762 <0x49038000 0x80>;
763 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
764 ti,hwmods = "timer5";
765 ti,timer-dsp;
766 ti,timer-pwm;
767 };
768
769 timer6: timer@4013a000 {
770 compatible = "ti,omap5430-timer";
771 reg = <0x4013a000 0x80>,
772 <0x4903a000 0x80>;
773 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
774 ti,hwmods = "timer6";
775 ti,timer-dsp;
776 ti,timer-pwm;
777 };
778
779 timer7: timer@4013c000 {
780 compatible = "ti,omap5430-timer";
781 reg = <0x4013c000 0x80>,
782 <0x4903c000 0x80>;
783 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
784 ti,hwmods = "timer7";
785 ti,timer-dsp;
786 };
787
788 timer8: timer@4013e000 {
789 compatible = "ti,omap5430-timer";
790 reg = <0x4013e000 0x80>,
791 <0x4903e000 0x80>;
792 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
793 ti,hwmods = "timer8";
794 ti,timer-dsp;
795 ti,timer-pwm;
796 };
797
798 timer9: timer@4803e000 {
799 compatible = "ti,omap5430-timer";
800 reg = <0x4803e000 0x80>;
801 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
802 ti,hwmods = "timer9";
803 ti,timer-pwm;
804 };
805
806 timer10: timer@48086000 {
807 compatible = "ti,omap5430-timer";
808 reg = <0x48086000 0x80>;
809 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
810 ti,hwmods = "timer10";
811 ti,timer-pwm;
812 };
813
814 timer11: timer@48088000 {
815 compatible = "ti,omap5430-timer";
816 reg = <0x48088000 0x80>;
817 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
818 ti,hwmods = "timer11";
819 ti,timer-pwm;
820 };
821
822 wdt2: wdt@4ae14000 {
823 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
824 reg = <0x4ae14000 0x80>;
825 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
826 ti,hwmods = "wd_timer2";
827 };
828
829 dmm@4e000000 {
830 compatible = "ti,omap5-dmm";
831 reg = <0x4e000000 0x800>;
832 interrupts = <0 113 0x4>;
833 ti,hwmods = "dmm";
834 };
835
836 emif1: emif@4c000000 {
837 compatible = "ti,emif-4d5";
838 ti,hwmods = "emif1";
839 ti,no-idle-on-init;
840 phy-type = <2>; /* DDR PHY type: Intelli PHY */
841 reg = <0x4c000000 0x400>;
842 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
843 hw-caps-read-idle-ctrl;
844 hw-caps-ll-interface;
845 hw-caps-temp-alert;
846 };
847
848 emif2: emif@4d000000 {
849 compatible = "ti,emif-4d5";
850 ti,hwmods = "emif2";
851 ti,no-idle-on-init;
852 phy-type = <2>; /* DDR PHY type: Intelli PHY */
853 reg = <0x4d000000 0x400>;
854 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
855 hw-caps-read-idle-ctrl;
856 hw-caps-ll-interface;
857 hw-caps-temp-alert;
858 };
859
860 usb3: omap_dwc3@4a020000 {
861 compatible = "ti,dwc3";
862 ti,hwmods = "usb_otg_ss";
863 reg = <0x4a020000 0x10000>;
864 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
865 #address-cells = <1>;
866 #size-cells = <1>;
867 utmi-mode = <2>;
868 ranges;
869 dwc3: dwc3@4a030000 {
870 compatible = "snps,dwc3";
871 reg = <0x4a030000 0x10000>;
872 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
874 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
875 interrupt-names = "peripheral",
876 "host",
877 "otg";
878 phys = <&usb2_phy>, <&usb3_phy>;
879 phy-names = "usb2-phy", "usb3-phy";
880 dr_mode = "peripheral";
881 };
882 };
883
884 ocp2scp@4a080000 {
885 compatible = "ti,omap-ocp2scp";
886 #address-cells = <1>;
887 #size-cells = <1>;
888 reg = <0x4a080000 0x20>;
889 ranges;
890 ti,hwmods = "ocp2scp1";
891 usb2_phy: usb2phy@4a084000 {
892 compatible = "ti,omap-usb2";
893 reg = <0x4a084000 0x7c>;
894 syscon-phy-power = <&scm_conf 0x300>;
895 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
896 clock-names = "wkupclk", "refclk";
897 #phy-cells = <0>;
898 };
899
900 usb3_phy: usb3phy@4a084400 {
901 compatible = "ti,omap-usb3";
902 reg = <0x4a084400 0x80>,
903 <0x4a084800 0x64>,
904 <0x4a084c00 0x40>;
905 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
906 syscon-phy-power = <&scm_conf 0x370>;
907 clocks = <&usb_phy_cm_clk32k>,
908 <&sys_clkin>,
909 <&usb_otg_ss_refclk960m>;
910 clock-names = "wkupclk",
911 "sysclk",
912 "refclk";
913 #phy-cells = <0>;
914 };
915 };
916
917 usbhstll: usbhstll@4a062000 {
918 compatible = "ti,usbhs-tll";
919 reg = <0x4a062000 0x1000>;
920 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
921 ti,hwmods = "usb_tll_hs";
922 };
923
924 usbhshost: usbhshost@4a064000 {
925 compatible = "ti,usbhs-host";
926 reg = <0x4a064000 0x800>;
927 ti,hwmods = "usb_host_hs";
928 #address-cells = <1>;
929 #size-cells = <1>;
930 ranges;
931 clocks = <&l3init_60m_fclk>,
932 <&xclk60mhsp1_ck>,
933 <&xclk60mhsp2_ck>;
934 clock-names = "refclk_60m_int",
935 "refclk_60m_ext_p1",
936 "refclk_60m_ext_p2";
937
938 usbhsohci: ohci@4a064800 {
939 compatible = "ti,ohci-omap3";
940 reg = <0x4a064800 0x400>;
941 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
942 };
943
944 usbhsehci: ehci@4a064c00 {
945 compatible = "ti,ehci-omap";
946 reg = <0x4a064c00 0x400>;
947 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
948 };
949 };
950
951 bandgap: bandgap@4a0021e0 {
952 reg = <0x4a0021e0 0xc
953 0x4a00232c 0xc
954 0x4a002380 0x2c
955 0x4a0023C0 0x3c>;
956 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
957 compatible = "ti,omap5430-bandgap";
958
959 #thermal-sensor-cells = <1>;
960 };
961
962 /* OCP2SCP3 */
963 ocp2scp@4a090000 {
964 compatible = "ti,omap-ocp2scp";
965 #address-cells = <1>;
966 #size-cells = <1>;
967 reg = <0x4a090000 0x20>;
968 ranges;
969 ti,hwmods = "ocp2scp3";
970 sata_phy: phy@4a096000 {
971 compatible = "ti,phy-pipe3-sata";
972 reg = <0x4A096000 0x80>, /* phy_rx */
973 <0x4A096400 0x64>, /* phy_tx */
974 <0x4A096800 0x40>; /* pll_ctrl */
975 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
976 syscon-phy-power = <&scm_conf 0x374>;
977 clocks = <&sys_clkin>, <&sata_ref_clk>;
978 clock-names = "sysclk", "refclk";
979 #phy-cells = <0>;
980 };
981 };
982
983 sata: sata@4a141100 {
984 compatible = "snps,dwc-ahci";
985 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
986 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
987 phys = <&sata_phy>;
988 phy-names = "sata-phy";
989 clocks = <&sata_ref_clk>;
990 ti,hwmods = "sata";
991 ports-implemented = <0x1>;
992 };
993
994 dss: dss@58000000 {
995 compatible = "ti,omap5-dss";
996 reg = <0x58000000 0x80>;
997 status = "disabled";
998 ti,hwmods = "dss_core";
999 clocks = <&dss_dss_clk>;
1000 clock-names = "fck";
1001 #address-cells = <1>;
1002 #size-cells = <1>;
1003 ranges;
1004
1005 dispc@58001000 {
1006 compatible = "ti,omap5-dispc";
1007 reg = <0x58001000 0x1000>;
1008 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1009 ti,hwmods = "dss_dispc";
1010 clocks = <&dss_dss_clk>;
1011 clock-names = "fck";
1012 };
1013
1014 rfbi: encoder@58002000 {
1015 compatible = "ti,omap5-rfbi";
1016 reg = <0x58002000 0x100>;
1017 status = "disabled";
1018 ti,hwmods = "dss_rfbi";
1019 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1020 clock-names = "fck", "ick";
1021 };
1022
1023 dsi1: encoder@58004000 {
1024 compatible = "ti,omap5-dsi";
1025 reg = <0x58004000 0x200>,
1026 <0x58004200 0x40>,
1027 <0x58004300 0x40>;
1028 reg-names = "proto", "phy", "pll";
1029 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1030 status = "disabled";
1031 ti,hwmods = "dss_dsi1";
1032 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1033 clock-names = "fck", "sys_clk";
1034 };
1035
1036 dsi2: encoder@58005000 {
1037 compatible = "ti,omap5-dsi";
1038 reg = <0x58009000 0x200>,
1039 <0x58009200 0x40>,
1040 <0x58009300 0x40>;
1041 reg-names = "proto", "phy", "pll";
1042 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1043 status = "disabled";
1044 ti,hwmods = "dss_dsi2";
1045 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1046 clock-names = "fck", "sys_clk";
1047 };
1048
1049 hdmi: encoder@58060000 {
1050 compatible = "ti,omap5-hdmi";
1051 reg = <0x58040000 0x200>,
1052 <0x58040200 0x80>,
1053 <0x58040300 0x80>,
1054 <0x58060000 0x19000>;
1055 reg-names = "wp", "pll", "phy", "core";
1056 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1057 status = "disabled";
1058 ti,hwmods = "dss_hdmi";
1059 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1060 clock-names = "fck", "sys_clk";
1061 dmas = <&sdma 76>;
1062 dma-names = "audio_tx";
1063 };
1064 };
1065
1066 abb_mpu: regulator-abb-mpu {
1067 compatible = "ti,abb-v2";
1068 regulator-name = "abb_mpu";
1069 #address-cells = <0>;
1070 #size-cells = <0>;
1071 clocks = <&sys_clkin>;
1072 ti,settling-time = <50>;
1073 ti,clock-cycles = <16>;
1074
1075 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1076 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1077 reg-names = "base-address", "int-address",
1078 "efuse-address", "ldo-address";
1079 ti,tranxdone-status-mask = <0x80>;
1080 /* LDOVBBMPU_MUX_CTRL */
1081 ti,ldovbb-override-mask = <0x400>;
1082 /* LDOVBBMPU_VSET_OUT */
1083 ti,ldovbb-vset-mask = <0x1F>;
1084
1085 /*
1086 * NOTE: only FBB mode used but actual vset will
1087 * determine final biasing
1088 */
1089 ti,abb_info = <
1090 /*uV ABB efuse rbb_m fbb_m vset_m*/
1091 1060000 0 0x0 0 0x02000000 0x01F00000
1092 1250000 0 0x4 0 0x02000000 0x01F00000
1093 >;
1094 };
1095
1096 abb_mm: regulator-abb-mm {
1097 compatible = "ti,abb-v2";
1098 regulator-name = "abb_mm";
1099 #address-cells = <0>;
1100 #size-cells = <0>;
1101 clocks = <&sys_clkin>;
1102 ti,settling-time = <50>;
1103 ti,clock-cycles = <16>;
1104
1105 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1106 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1107 reg-names = "base-address", "int-address",
1108 "efuse-address", "ldo-address";
1109 ti,tranxdone-status-mask = <0x80000000>;
1110 /* LDOVBBMM_MUX_CTRL */
1111 ti,ldovbb-override-mask = <0x400>;
1112 /* LDOVBBMM_VSET_OUT */
1113 ti,ldovbb-vset-mask = <0x1F>;
1114
1115 /*
1116 * NOTE: only FBB mode used but actual vset will
1117 * determine final biasing
1118 */
1119 ti,abb_info = <
1120 /*uV ABB efuse rbb_m fbb_m vset_m*/
1121 1025000 0 0x0 0 0x02000000 0x01F00000
1122 1120000 0 0x4 0 0x02000000 0x01F00000
1123 >;
1124 };
1125 };
1126};
1127
1128&cpu_thermal {
1129 polling-delay = <500>; /* milliseconds */
1130};
1131
1132/include/ "omap54xx-clocks.dtsi"