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1// SPDX-License-Identifier: GPL-2.0
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/sched.h>
8#include <linux/sched/clock.h>
9#include <linux/thread_info.h>
10#include <linux/init.h>
11#include <linux/uaccess.h>
12
13#include <asm/cpufeature.h>
14#include <asm/pgtable.h>
15#include <asm/msr.h>
16#include <asm/bugs.h>
17#include <asm/cpu.h>
18#include <asm/intel-family.h>
19#include <asm/microcode_intel.h>
20#include <asm/hwcap2.h>
21#include <asm/elf.h>
22
23#ifdef CONFIG_X86_64
24#include <linux/topology.h>
25#endif
26
27#include "cpu.h"
28
29#ifdef CONFIG_X86_LOCAL_APIC
30#include <asm/mpspec.h>
31#include <asm/apic.h>
32#endif
33
34/*
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
37 */
38static int forcempx;
39
40static int __init forcempx_setup(char *__unused)
41{
42 forcempx = 1;
43
44 return 1;
45}
46__setup("intel-skd-046-workaround=disable", forcempx_setup);
47
48void check_mpx_erratum(struct cpuinfo_x86 *c)
49{
50 if (forcempx)
51 return;
52 /*
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
55 *
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
58 *
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
62 */
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
66 }
67}
68
69/*
70 * Processors which have self-snooping capability can handle conflicting
71 * memory type across CPUs by snooping its own cache. However, there exists
72 * CPU models in which having conflicting memory types still leads to
73 * unpredictable behavior, machine check errors, or hangs. Clear this
74 * feature to prevent its use on machines with known erratas.
75 */
76static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
77{
78 switch (c->x86_model) {
79 case INTEL_FAM6_CORE_YONAH:
80 case INTEL_FAM6_CORE2_MEROM:
81 case INTEL_FAM6_CORE2_MEROM_L:
82 case INTEL_FAM6_CORE2_PENRYN:
83 case INTEL_FAM6_CORE2_DUNNINGTON:
84 case INTEL_FAM6_NEHALEM:
85 case INTEL_FAM6_NEHALEM_G:
86 case INTEL_FAM6_NEHALEM_EP:
87 case INTEL_FAM6_NEHALEM_EX:
88 case INTEL_FAM6_WESTMERE:
89 case INTEL_FAM6_WESTMERE_EP:
90 case INTEL_FAM6_SANDYBRIDGE:
91 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
92 }
93}
94
95static bool ring3mwait_disabled __read_mostly;
96
97static int __init ring3mwait_disable(char *__unused)
98{
99 ring3mwait_disabled = true;
100 return 0;
101}
102__setup("ring3mwait=disable", ring3mwait_disable);
103
104static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
105{
106 /*
107 * Ring 3 MONITOR/MWAIT feature cannot be detected without
108 * cpu model and family comparison.
109 */
110 if (c->x86 != 6)
111 return;
112 switch (c->x86_model) {
113 case INTEL_FAM6_XEON_PHI_KNL:
114 case INTEL_FAM6_XEON_PHI_KNM:
115 break;
116 default:
117 return;
118 }
119
120 if (ring3mwait_disabled)
121 return;
122
123 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
124 this_cpu_or(msr_misc_features_shadow,
125 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
126
127 if (c == &boot_cpu_data)
128 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
129}
130
131/*
132 * Early microcode releases for the Spectre v2 mitigation were broken.
133 * Information taken from;
134 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
135 * - https://kb.vmware.com/s/article/52345
136 * - Microcode revisions observed in the wild
137 * - Release note from 20180108 microcode release
138 */
139struct sku_microcode {
140 u8 model;
141 u8 stepping;
142 u32 microcode;
143};
144static const struct sku_microcode spectre_bad_microcodes[] = {
145 { INTEL_FAM6_KABYLAKE, 0x0B, 0x80 },
146 { INTEL_FAM6_KABYLAKE, 0x0A, 0x80 },
147 { INTEL_FAM6_KABYLAKE, 0x09, 0x80 },
148 { INTEL_FAM6_KABYLAKE_L, 0x0A, 0x80 },
149 { INTEL_FAM6_KABYLAKE_L, 0x09, 0x80 },
150 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
151 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
152 { INTEL_FAM6_BROADWELL, 0x04, 0x28 },
153 { INTEL_FAM6_BROADWELL_G, 0x01, 0x1b },
154 { INTEL_FAM6_BROADWELL_D, 0x02, 0x14 },
155 { INTEL_FAM6_BROADWELL_D, 0x03, 0x07000011 },
156 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
157 { INTEL_FAM6_HASWELL_L, 0x01, 0x21 },
158 { INTEL_FAM6_HASWELL_G, 0x01, 0x18 },
159 { INTEL_FAM6_HASWELL, 0x03, 0x23 },
160 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
161 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
162 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
163 /* Observed in the wild */
164 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
165 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
166};
167
168static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
169{
170 int i;
171
172 /*
173 * We know that the hypervisor lie to us on the microcode version so
174 * we may as well hope that it is running the correct version.
175 */
176 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
177 return false;
178
179 if (c->x86 != 6)
180 return false;
181
182 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
183 if (c->x86_model == spectre_bad_microcodes[i].model &&
184 c->x86_stepping == spectre_bad_microcodes[i].stepping)
185 return (c->microcode <= spectre_bad_microcodes[i].microcode);
186 }
187 return false;
188}
189
190static void early_init_intel(struct cpuinfo_x86 *c)
191{
192 u64 misc_enable;
193
194 /* Unmask CPUID levels if masked: */
195 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
196 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
197 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
198 c->cpuid_level = cpuid_eax(0);
199 get_cpu_cap(c);
200 }
201 }
202
203 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
204 (c->x86 == 0x6 && c->x86_model >= 0x0e))
205 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
206
207 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
208 c->microcode = intel_get_microcode_revision();
209
210 /* Now if any of them are set, check the blacklist and clear the lot */
211 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
212 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
213 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
214 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
215 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
216 setup_clear_cpu_cap(X86_FEATURE_IBRS);
217 setup_clear_cpu_cap(X86_FEATURE_IBPB);
218 setup_clear_cpu_cap(X86_FEATURE_STIBP);
219 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
220 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
221 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
222 setup_clear_cpu_cap(X86_FEATURE_SSBD);
223 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
224 }
225
226 /*
227 * Atom erratum AAE44/AAF40/AAG38/AAH41:
228 *
229 * A race condition between speculative fetches and invalidating
230 * a large page. This is worked around in microcode, but we
231 * need the microcode to have already been loaded... so if it is
232 * not, recommend a BIOS update and disable large pages.
233 */
234 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
235 c->microcode < 0x20e) {
236 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
237 clear_cpu_cap(c, X86_FEATURE_PSE);
238 }
239
240#ifdef CONFIG_X86_64
241 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
242#else
243 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
244 if (c->x86 == 15 && c->x86_cache_alignment == 64)
245 c->x86_cache_alignment = 128;
246#endif
247
248 /* CPUID workaround for 0F33/0F34 CPU */
249 if (c->x86 == 0xF && c->x86_model == 0x3
250 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
251 c->x86_phys_bits = 36;
252
253 /*
254 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
255 * with P/T states and does not stop in deep C-states.
256 *
257 * It is also reliable across cores and sockets. (but not across
258 * cabinets - we turn it off in that case explicitly.)
259 */
260 if (c->x86_power & (1 << 8)) {
261 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
262 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
263 }
264
265 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
266 if (c->x86 == 6) {
267 switch (c->x86_model) {
268 case INTEL_FAM6_ATOM_SALTWELL_MID:
269 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
270 case INTEL_FAM6_ATOM_SILVERMONT_MID:
271 case INTEL_FAM6_ATOM_AIRMONT_NP:
272 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
273 break;
274 default:
275 break;
276 }
277 }
278
279 /*
280 * There is a known erratum on Pentium III and Core Solo
281 * and Core Duo CPUs.
282 * " Page with PAT set to WC while associated MTRR is UC
283 * may consolidate to UC "
284 * Because of this erratum, it is better to stick with
285 * setting WC in MTRR rather than using PAT on these CPUs.
286 *
287 * Enable PAT WC only on P4, Core 2 or later CPUs.
288 */
289 if (c->x86 == 6 && c->x86_model < 15)
290 clear_cpu_cap(c, X86_FEATURE_PAT);
291
292 /*
293 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
294 * clear the fast string and enhanced fast string CPU capabilities.
295 */
296 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
297 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
298 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
299 pr_info("Disabled fast string operations\n");
300 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
301 setup_clear_cpu_cap(X86_FEATURE_ERMS);
302 }
303 }
304
305 /*
306 * Intel Quark Core DevMan_001.pdf section 6.4.11
307 * "The operating system also is required to invalidate (i.e., flush)
308 * the TLB when any changes are made to any of the page table entries.
309 * The operating system must reload CR3 to cause the TLB to be flushed"
310 *
311 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
312 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
313 * to be modified.
314 */
315 if (c->x86 == 5 && c->x86_model == 9) {
316 pr_info("Disabling PGE capability bit\n");
317 setup_clear_cpu_cap(X86_FEATURE_PGE);
318 }
319
320 if (c->cpuid_level >= 0x00000001) {
321 u32 eax, ebx, ecx, edx;
322
323 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
324 /*
325 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
326 * apicids which are reserved per package. Store the resulting
327 * shift value for the package management code.
328 */
329 if (edx & (1U << 28))
330 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
331 }
332
333 check_mpx_erratum(c);
334 check_memory_type_self_snoop_errata(c);
335
336 /*
337 * Get the number of SMT siblings early from the extended topology
338 * leaf, if available. Otherwise try the legacy SMT detection.
339 */
340 if (detect_extended_topology_early(c) < 0)
341 detect_ht_early(c);
342}
343
344#ifdef CONFIG_X86_32
345/*
346 * Early probe support logic for ppro memory erratum #50
347 *
348 * This is called before we do cpu ident work
349 */
350
351int ppro_with_ram_bug(void)
352{
353 /* Uses data from early_cpu_detect now */
354 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
355 boot_cpu_data.x86 == 6 &&
356 boot_cpu_data.x86_model == 1 &&
357 boot_cpu_data.x86_stepping < 8) {
358 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
359 return 1;
360 }
361 return 0;
362}
363
364static void intel_smp_check(struct cpuinfo_x86 *c)
365{
366 /* calling is from identify_secondary_cpu() ? */
367 if (!c->cpu_index)
368 return;
369
370 /*
371 * Mask B, Pentium, but not Pentium MMX
372 */
373 if (c->x86 == 5 &&
374 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
375 c->x86_model <= 3) {
376 /*
377 * Remember we have B step Pentia with bugs
378 */
379 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
380 "with B stepping processors.\n");
381 }
382}
383
384static int forcepae;
385static int __init forcepae_setup(char *__unused)
386{
387 forcepae = 1;
388 return 1;
389}
390__setup("forcepae", forcepae_setup);
391
392static void intel_workarounds(struct cpuinfo_x86 *c)
393{
394#ifdef CONFIG_X86_F00F_BUG
395 /*
396 * All models of Pentium and Pentium with MMX technology CPUs
397 * have the F0 0F bug, which lets nonprivileged users lock up the
398 * system. Announce that the fault handler will be checking for it.
399 * The Quark is also family 5, but does not have the same bug.
400 */
401 clear_cpu_bug(c, X86_BUG_F00F);
402 if (c->x86 == 5 && c->x86_model < 9) {
403 static int f00f_workaround_enabled;
404
405 set_cpu_bug(c, X86_BUG_F00F);
406 if (!f00f_workaround_enabled) {
407 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
408 f00f_workaround_enabled = 1;
409 }
410 }
411#endif
412
413 /*
414 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
415 * model 3 mask 3
416 */
417 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
418 clear_cpu_cap(c, X86_FEATURE_SEP);
419
420 /*
421 * PAE CPUID issue: many Pentium M report no PAE but may have a
422 * functionally usable PAE implementation.
423 * Forcefully enable PAE if kernel parameter "forcepae" is present.
424 */
425 if (forcepae) {
426 pr_warn("PAE forced!\n");
427 set_cpu_cap(c, X86_FEATURE_PAE);
428 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
429 }
430
431 /*
432 * P4 Xeon erratum 037 workaround.
433 * Hardware prefetcher may cause stale data to be loaded into the cache.
434 */
435 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
436 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
437 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
438 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
439 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
440 }
441 }
442
443 /*
444 * See if we have a good local APIC by checking for buggy Pentia,
445 * i.e. all B steppings and the C2 stepping of P54C when using their
446 * integrated APIC (see 11AP erratum in "Pentium Processor
447 * Specification Update").
448 */
449 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
450 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
451 set_cpu_bug(c, X86_BUG_11AP);
452
453
454#ifdef CONFIG_X86_INTEL_USERCOPY
455 /*
456 * Set up the preferred alignment for movsl bulk memory moves
457 */
458 switch (c->x86) {
459 case 4: /* 486: untested */
460 break;
461 case 5: /* Old Pentia: untested */
462 break;
463 case 6: /* PII/PIII only like movsl with 8-byte alignment */
464 movsl_mask.mask = 7;
465 break;
466 case 15: /* P4 is OK down to 8-byte alignment */
467 movsl_mask.mask = 7;
468 break;
469 }
470#endif
471
472 intel_smp_check(c);
473}
474#else
475static void intel_workarounds(struct cpuinfo_x86 *c)
476{
477}
478#endif
479
480static void srat_detect_node(struct cpuinfo_x86 *c)
481{
482#ifdef CONFIG_NUMA
483 unsigned node;
484 int cpu = smp_processor_id();
485
486 /* Don't do the funky fallback heuristics the AMD version employs
487 for now. */
488 node = numa_cpu_node(cpu);
489 if (node == NUMA_NO_NODE || !node_online(node)) {
490 /* reuse the value from init_cpu_to_node() */
491 node = cpu_to_node(cpu);
492 }
493 numa_set_node(cpu, node);
494#endif
495}
496
497static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
498{
499 /* Intel VMX MSR indicated features */
500#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
501#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
502#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
503#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
504#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
505#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
506#define x86_VMX_FEATURE_EPT_CAP_AD 0x00200000
507
508 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
509 u32 msr_vpid_cap, msr_ept_cap;
510
511 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
512 clear_cpu_cap(c, X86_FEATURE_VNMI);
513 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
514 clear_cpu_cap(c, X86_FEATURE_EPT);
515 clear_cpu_cap(c, X86_FEATURE_VPID);
516 clear_cpu_cap(c, X86_FEATURE_EPT_AD);
517
518 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
519 msr_ctl = vmx_msr_high | vmx_msr_low;
520 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
521 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
522 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
523 set_cpu_cap(c, X86_FEATURE_VNMI);
524 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
525 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
526 vmx_msr_low, vmx_msr_high);
527 msr_ctl2 = vmx_msr_high | vmx_msr_low;
528 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
529 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
530 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
531 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT) {
532 set_cpu_cap(c, X86_FEATURE_EPT);
533 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
534 msr_ept_cap, msr_vpid_cap);
535 if (msr_ept_cap & x86_VMX_FEATURE_EPT_CAP_AD)
536 set_cpu_cap(c, X86_FEATURE_EPT_AD);
537 }
538 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
539 set_cpu_cap(c, X86_FEATURE_VPID);
540 }
541}
542
543#define MSR_IA32_TME_ACTIVATE 0x982
544
545/* Helpers to access TME_ACTIVATE MSR */
546#define TME_ACTIVATE_LOCKED(x) (x & 0x1)
547#define TME_ACTIVATE_ENABLED(x) (x & 0x2)
548
549#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
550#define TME_ACTIVATE_POLICY_AES_XTS_128 0
551
552#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
553
554#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
555#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
556
557/* Values for mktme_status (SW only construct) */
558#define MKTME_ENABLED 0
559#define MKTME_DISABLED 1
560#define MKTME_UNINITIALIZED 2
561static int mktme_status = MKTME_UNINITIALIZED;
562
563static void detect_tme(struct cpuinfo_x86 *c)
564{
565 u64 tme_activate, tme_policy, tme_crypto_algs;
566 int keyid_bits = 0, nr_keyids = 0;
567 static u64 tme_activate_cpu0 = 0;
568
569 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
570
571 if (mktme_status != MKTME_UNINITIALIZED) {
572 if (tme_activate != tme_activate_cpu0) {
573 /* Broken BIOS? */
574 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
575 pr_err_once("x86/tme: MKTME is not usable\n");
576 mktme_status = MKTME_DISABLED;
577
578 /* Proceed. We may need to exclude bits from x86_phys_bits. */
579 }
580 } else {
581 tme_activate_cpu0 = tme_activate;
582 }
583
584 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
585 pr_info_once("x86/tme: not enabled by BIOS\n");
586 mktme_status = MKTME_DISABLED;
587 return;
588 }
589
590 if (mktme_status != MKTME_UNINITIALIZED)
591 goto detect_keyid_bits;
592
593 pr_info("x86/tme: enabled by BIOS\n");
594
595 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
596 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
597 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
598
599 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
600 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
601 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
602 tme_crypto_algs);
603 mktme_status = MKTME_DISABLED;
604 }
605detect_keyid_bits:
606 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
607 nr_keyids = (1UL << keyid_bits) - 1;
608 if (nr_keyids) {
609 pr_info_once("x86/mktme: enabled by BIOS\n");
610 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
611 } else {
612 pr_info_once("x86/mktme: disabled by BIOS\n");
613 }
614
615 if (mktme_status == MKTME_UNINITIALIZED) {
616 /* MKTME is usable */
617 mktme_status = MKTME_ENABLED;
618 }
619
620 /*
621 * KeyID bits effectively lower the number of physical address
622 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
623 */
624 c->x86_phys_bits -= keyid_bits;
625}
626
627static void init_cpuid_fault(struct cpuinfo_x86 *c)
628{
629 u64 msr;
630
631 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
632 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
633 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
634 }
635}
636
637static void init_intel_misc_features(struct cpuinfo_x86 *c)
638{
639 u64 msr;
640
641 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
642 return;
643
644 /* Clear all MISC features */
645 this_cpu_write(msr_misc_features_shadow, 0);
646
647 /* Check features and update capabilities and shadow control bits */
648 init_cpuid_fault(c);
649 probe_xeon_phi_r3mwait(c);
650
651 msr = this_cpu_read(msr_misc_features_shadow);
652 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
653}
654
655static void init_intel(struct cpuinfo_x86 *c)
656{
657 early_init_intel(c);
658
659 intel_workarounds(c);
660
661 /*
662 * Detect the extended topology information if available. This
663 * will reinitialise the initial_apicid which will be used
664 * in init_intel_cacheinfo()
665 */
666 detect_extended_topology(c);
667
668 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
669 /*
670 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
671 * detection.
672 */
673 detect_num_cpu_cores(c);
674#ifdef CONFIG_X86_32
675 detect_ht(c);
676#endif
677 }
678
679 init_intel_cacheinfo(c);
680
681 if (c->cpuid_level > 9) {
682 unsigned eax = cpuid_eax(10);
683 /* Check for version and the number of counters */
684 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
685 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
686 }
687
688 if (cpu_has(c, X86_FEATURE_XMM2))
689 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
690
691 if (boot_cpu_has(X86_FEATURE_DS)) {
692 unsigned int l1, l2;
693
694 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
695 if (!(l1 & (1<<11)))
696 set_cpu_cap(c, X86_FEATURE_BTS);
697 if (!(l1 & (1<<12)))
698 set_cpu_cap(c, X86_FEATURE_PEBS);
699 }
700
701 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
702 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
703 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
704
705 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
706 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
707 set_cpu_bug(c, X86_BUG_MONITOR);
708
709#ifdef CONFIG_X86_64
710 if (c->x86 == 15)
711 c->x86_cache_alignment = c->x86_clflush_size * 2;
712 if (c->x86 == 6)
713 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
714#else
715 /*
716 * Names for the Pentium II/Celeron processors
717 * detectable only by also checking the cache size.
718 * Dixon is NOT a Celeron.
719 */
720 if (c->x86 == 6) {
721 unsigned int l2 = c->x86_cache_size;
722 char *p = NULL;
723
724 switch (c->x86_model) {
725 case 5:
726 if (l2 == 0)
727 p = "Celeron (Covington)";
728 else if (l2 == 256)
729 p = "Mobile Pentium II (Dixon)";
730 break;
731
732 case 6:
733 if (l2 == 128)
734 p = "Celeron (Mendocino)";
735 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
736 p = "Celeron-A";
737 break;
738
739 case 8:
740 if (l2 == 128)
741 p = "Celeron (Coppermine)";
742 break;
743 }
744
745 if (p)
746 strcpy(c->x86_model_id, p);
747 }
748
749 if (c->x86 == 15)
750 set_cpu_cap(c, X86_FEATURE_P4);
751 if (c->x86 == 6)
752 set_cpu_cap(c, X86_FEATURE_P3);
753#endif
754
755 /* Work around errata */
756 srat_detect_node(c);
757
758 if (cpu_has(c, X86_FEATURE_VMX))
759 detect_vmx_virtcap(c);
760
761 if (cpu_has(c, X86_FEATURE_TME))
762 detect_tme(c);
763
764 init_intel_misc_features(c);
765
766 if (tsx_ctrl_state == TSX_CTRL_ENABLE)
767 tsx_enable();
768 if (tsx_ctrl_state == TSX_CTRL_DISABLE)
769 tsx_disable();
770}
771
772#ifdef CONFIG_X86_32
773static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
774{
775 /*
776 * Intel PIII Tualatin. This comes in two flavours.
777 * One has 256kb of cache, the other 512. We have no way
778 * to determine which, so we use a boottime override
779 * for the 512kb model, and assume 256 otherwise.
780 */
781 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
782 size = 256;
783
784 /*
785 * Intel Quark SoC X1000 contains a 4-way set associative
786 * 16K cache with a 16 byte cache line and 256 lines per tag
787 */
788 if ((c->x86 == 5) && (c->x86_model == 9))
789 size = 16;
790 return size;
791}
792#endif
793
794#define TLB_INST_4K 0x01
795#define TLB_INST_4M 0x02
796#define TLB_INST_2M_4M 0x03
797
798#define TLB_INST_ALL 0x05
799#define TLB_INST_1G 0x06
800
801#define TLB_DATA_4K 0x11
802#define TLB_DATA_4M 0x12
803#define TLB_DATA_2M_4M 0x13
804#define TLB_DATA_4K_4M 0x14
805
806#define TLB_DATA_1G 0x16
807
808#define TLB_DATA0_4K 0x21
809#define TLB_DATA0_4M 0x22
810#define TLB_DATA0_2M_4M 0x23
811
812#define STLB_4K 0x41
813#define STLB_4K_2M 0x42
814
815static const struct _tlb_table intel_tlb_table[] = {
816 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
817 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
818 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
819 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
820 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
821 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
822 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
823 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
824 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
825 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
826 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
827 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
828 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
829 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
830 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
831 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
832 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
833 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
834 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
835 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
836 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
837 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
838 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
839 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
840 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
841 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
842 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
843 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
844 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
845 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
846 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
847 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
848 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
849 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
850 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
851 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
852 { 0x00, 0, 0 }
853};
854
855static void intel_tlb_lookup(const unsigned char desc)
856{
857 unsigned char k;
858 if (desc == 0)
859 return;
860
861 /* look up this descriptor in the table */
862 for (k = 0; intel_tlb_table[k].descriptor != desc && \
863 intel_tlb_table[k].descriptor != 0; k++)
864 ;
865
866 if (intel_tlb_table[k].tlb_type == 0)
867 return;
868
869 switch (intel_tlb_table[k].tlb_type) {
870 case STLB_4K:
871 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
872 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
873 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
874 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
875 break;
876 case STLB_4K_2M:
877 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
878 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
879 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
880 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
881 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
882 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
883 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
884 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
885 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
886 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
887 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
888 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
889 break;
890 case TLB_INST_ALL:
891 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
892 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
893 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
894 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
895 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
896 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
897 break;
898 case TLB_INST_4K:
899 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
900 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
901 break;
902 case TLB_INST_4M:
903 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
904 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
905 break;
906 case TLB_INST_2M_4M:
907 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
908 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
909 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
910 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
911 break;
912 case TLB_DATA_4K:
913 case TLB_DATA0_4K:
914 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
915 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
916 break;
917 case TLB_DATA_4M:
918 case TLB_DATA0_4M:
919 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
920 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
921 break;
922 case TLB_DATA_2M_4M:
923 case TLB_DATA0_2M_4M:
924 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
925 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
926 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
927 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
928 break;
929 case TLB_DATA_4K_4M:
930 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
931 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
932 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
933 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
934 break;
935 case TLB_DATA_1G:
936 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
937 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
938 break;
939 }
940}
941
942static void intel_detect_tlb(struct cpuinfo_x86 *c)
943{
944 int i, j, n;
945 unsigned int regs[4];
946 unsigned char *desc = (unsigned char *)regs;
947
948 if (c->cpuid_level < 2)
949 return;
950
951 /* Number of times to iterate */
952 n = cpuid_eax(2) & 0xFF;
953
954 for (i = 0 ; i < n ; i++) {
955 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
956
957 /* If bit 31 is set, this is an unknown format */
958 for (j = 0 ; j < 3 ; j++)
959 if (regs[j] & (1 << 31))
960 regs[j] = 0;
961
962 /* Byte 0 is level count, not a descriptor */
963 for (j = 1 ; j < 16 ; j++)
964 intel_tlb_lookup(desc[j]);
965 }
966}
967
968static const struct cpu_dev intel_cpu_dev = {
969 .c_vendor = "Intel",
970 .c_ident = { "GenuineIntel" },
971#ifdef CONFIG_X86_32
972 .legacy_models = {
973 { .family = 4, .model_names =
974 {
975 [0] = "486 DX-25/33",
976 [1] = "486 DX-50",
977 [2] = "486 SX",
978 [3] = "486 DX/2",
979 [4] = "486 SL",
980 [5] = "486 SX/2",
981 [7] = "486 DX/2-WB",
982 [8] = "486 DX/4",
983 [9] = "486 DX/4-WB"
984 }
985 },
986 { .family = 5, .model_names =
987 {
988 [0] = "Pentium 60/66 A-step",
989 [1] = "Pentium 60/66",
990 [2] = "Pentium 75 - 200",
991 [3] = "OverDrive PODP5V83",
992 [4] = "Pentium MMX",
993 [7] = "Mobile Pentium 75 - 200",
994 [8] = "Mobile Pentium MMX",
995 [9] = "Quark SoC X1000",
996 }
997 },
998 { .family = 6, .model_names =
999 {
1000 [0] = "Pentium Pro A-step",
1001 [1] = "Pentium Pro",
1002 [3] = "Pentium II (Klamath)",
1003 [4] = "Pentium II (Deschutes)",
1004 [5] = "Pentium II (Deschutes)",
1005 [6] = "Mobile Pentium II",
1006 [7] = "Pentium III (Katmai)",
1007 [8] = "Pentium III (Coppermine)",
1008 [10] = "Pentium III (Cascades)",
1009 [11] = "Pentium III (Tualatin)",
1010 }
1011 },
1012 { .family = 15, .model_names =
1013 {
1014 [0] = "Pentium 4 (Unknown)",
1015 [1] = "Pentium 4 (Willamette)",
1016 [2] = "Pentium 4 (Northwood)",
1017 [4] = "Pentium 4 (Foster)",
1018 [5] = "Pentium 4 (Foster)",
1019 }
1020 },
1021 },
1022 .legacy_cache_size = intel_size_cache,
1023#endif
1024 .c_detect_tlb = intel_detect_tlb,
1025 .c_early_init = early_init_intel,
1026 .c_init = init_intel,
1027 .c_x86_vendor = X86_VENDOR_INTEL,
1028};
1029
1030cpu_dev_register(intel_cpu_dev);
1#include <linux/kernel.h>
2
3#include <linux/string.h>
4#include <linux/bitops.h>
5#include <linux/smp.h>
6#include <linux/sched.h>
7#include <linux/thread_info.h>
8#include <linux/init.h>
9#include <linux/uaccess.h>
10
11#include <asm/cpufeature.h>
12#include <asm/pgtable.h>
13#include <asm/msr.h>
14#include <asm/bugs.h>
15#include <asm/cpu.h>
16#include <asm/intel-family.h>
17#include <asm/microcode_intel.h>
18
19#ifdef CONFIG_X86_64
20#include <linux/topology.h>
21#endif
22
23#include "cpu.h"
24
25#ifdef CONFIG_X86_LOCAL_APIC
26#include <asm/mpspec.h>
27#include <asm/apic.h>
28#endif
29
30/*
31 * Just in case our CPU detection goes bad, or you have a weird system,
32 * allow a way to override the automatic disabling of MPX.
33 */
34static int forcempx;
35
36static int __init forcempx_setup(char *__unused)
37{
38 forcempx = 1;
39
40 return 1;
41}
42__setup("intel-skd-046-workaround=disable", forcempx_setup);
43
44void check_mpx_erratum(struct cpuinfo_x86 *c)
45{
46 if (forcempx)
47 return;
48 /*
49 * Turn off the MPX feature on CPUs where SMEP is not
50 * available or disabled.
51 *
52 * Works around Intel Erratum SKD046: "Branch Instructions
53 * May Initialize MPX Bound Registers Incorrectly".
54 *
55 * This might falsely disable MPX on systems without
56 * SMEP, like Atom processors without SMEP. But there
57 * is no such hardware known at the moment.
58 */
59 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
60 setup_clear_cpu_cap(X86_FEATURE_MPX);
61 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
62 }
63}
64
65static void early_init_intel(struct cpuinfo_x86 *c)
66{
67 u64 misc_enable;
68
69 /* Unmask CPUID levels if masked: */
70 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
71 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
72 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
73 c->cpuid_level = cpuid_eax(0);
74 get_cpu_cap(c);
75 }
76 }
77
78 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
79 (c->x86 == 0x6 && c->x86_model >= 0x0e))
80 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
81
82 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
83 c->microcode = intel_get_microcode_revision();
84
85 /*
86 * Atom erratum AAE44/AAF40/AAG38/AAH41:
87 *
88 * A race condition between speculative fetches and invalidating
89 * a large page. This is worked around in microcode, but we
90 * need the microcode to have already been loaded... so if it is
91 * not, recommend a BIOS update and disable large pages.
92 */
93 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
94 c->microcode < 0x20e) {
95 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
96 clear_cpu_cap(c, X86_FEATURE_PSE);
97 }
98
99#ifdef CONFIG_X86_64
100 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
101#else
102 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
103 if (c->x86 == 15 && c->x86_cache_alignment == 64)
104 c->x86_cache_alignment = 128;
105#endif
106
107 /* CPUID workaround for 0F33/0F34 CPU */
108 if (c->x86 == 0xF && c->x86_model == 0x3
109 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
110 c->x86_phys_bits = 36;
111
112 /*
113 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
114 * with P/T states and does not stop in deep C-states.
115 *
116 * It is also reliable across cores and sockets. (but not across
117 * cabinets - we turn it off in that case explicitly.)
118 */
119 if (c->x86_power & (1 << 8)) {
120 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
121 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
122 if (!check_tsc_unstable())
123 set_sched_clock_stable();
124 }
125
126 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
127 if (c->x86 == 6) {
128 switch (c->x86_model) {
129 case 0x27: /* Penwell */
130 case 0x35: /* Cloverview */
131 case 0x4a: /* Merrifield */
132 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
133 break;
134 default:
135 break;
136 }
137 }
138
139 /*
140 * There is a known erratum on Pentium III and Core Solo
141 * and Core Duo CPUs.
142 * " Page with PAT set to WC while associated MTRR is UC
143 * may consolidate to UC "
144 * Because of this erratum, it is better to stick with
145 * setting WC in MTRR rather than using PAT on these CPUs.
146 *
147 * Enable PAT WC only on P4, Core 2 or later CPUs.
148 */
149 if (c->x86 == 6 && c->x86_model < 15)
150 clear_cpu_cap(c, X86_FEATURE_PAT);
151
152#ifdef CONFIG_KMEMCHECK
153 /*
154 * P4s have a "fast strings" feature which causes single-
155 * stepping REP instructions to only generate a #DB on
156 * cache-line boundaries.
157 *
158 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
159 * (model 2) with the same problem.
160 */
161 if (c->x86 == 15)
162 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
163 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
164 pr_info("kmemcheck: Disabling fast string operations\n");
165#endif
166
167 /*
168 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
169 * clear the fast string and enhanced fast string CPU capabilities.
170 */
171 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
172 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
173 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
174 pr_info("Disabled fast string operations\n");
175 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
176 setup_clear_cpu_cap(X86_FEATURE_ERMS);
177 }
178 }
179
180 /*
181 * Intel Quark Core DevMan_001.pdf section 6.4.11
182 * "The operating system also is required to invalidate (i.e., flush)
183 * the TLB when any changes are made to any of the page table entries.
184 * The operating system must reload CR3 to cause the TLB to be flushed"
185 *
186 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
187 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
188 * to be modified.
189 */
190 if (c->x86 == 5 && c->x86_model == 9) {
191 pr_info("Disabling PGE capability bit\n");
192 setup_clear_cpu_cap(X86_FEATURE_PGE);
193 }
194
195 if (c->cpuid_level >= 0x00000001) {
196 u32 eax, ebx, ecx, edx;
197
198 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
199 /*
200 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
201 * apicids which are reserved per package. Store the resulting
202 * shift value for the package management code.
203 */
204 if (edx & (1U << 28))
205 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
206 }
207
208 check_mpx_erratum(c);
209}
210
211#ifdef CONFIG_X86_32
212/*
213 * Early probe support logic for ppro memory erratum #50
214 *
215 * This is called before we do cpu ident work
216 */
217
218int ppro_with_ram_bug(void)
219{
220 /* Uses data from early_cpu_detect now */
221 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
222 boot_cpu_data.x86 == 6 &&
223 boot_cpu_data.x86_model == 1 &&
224 boot_cpu_data.x86_mask < 8) {
225 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
226 return 1;
227 }
228 return 0;
229}
230
231static void intel_smp_check(struct cpuinfo_x86 *c)
232{
233 /* calling is from identify_secondary_cpu() ? */
234 if (!c->cpu_index)
235 return;
236
237 /*
238 * Mask B, Pentium, but not Pentium MMX
239 */
240 if (c->x86 == 5 &&
241 c->x86_mask >= 1 && c->x86_mask <= 4 &&
242 c->x86_model <= 3) {
243 /*
244 * Remember we have B step Pentia with bugs
245 */
246 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
247 "with B stepping processors.\n");
248 }
249}
250
251static int forcepae;
252static int __init forcepae_setup(char *__unused)
253{
254 forcepae = 1;
255 return 1;
256}
257__setup("forcepae", forcepae_setup);
258
259static void intel_workarounds(struct cpuinfo_x86 *c)
260{
261#ifdef CONFIG_X86_F00F_BUG
262 /*
263 * All models of Pentium and Pentium with MMX technology CPUs
264 * have the F0 0F bug, which lets nonprivileged users lock up the
265 * system. Announce that the fault handler will be checking for it.
266 * The Quark is also family 5, but does not have the same bug.
267 */
268 clear_cpu_bug(c, X86_BUG_F00F);
269 if (c->x86 == 5 && c->x86_model < 9) {
270 static int f00f_workaround_enabled;
271
272 set_cpu_bug(c, X86_BUG_F00F);
273 if (!f00f_workaround_enabled) {
274 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
275 f00f_workaround_enabled = 1;
276 }
277 }
278#endif
279
280 /*
281 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
282 * model 3 mask 3
283 */
284 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
285 clear_cpu_cap(c, X86_FEATURE_SEP);
286
287 /*
288 * PAE CPUID issue: many Pentium M report no PAE but may have a
289 * functionally usable PAE implementation.
290 * Forcefully enable PAE if kernel parameter "forcepae" is present.
291 */
292 if (forcepae) {
293 pr_warn("PAE forced!\n");
294 set_cpu_cap(c, X86_FEATURE_PAE);
295 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
296 }
297
298 /*
299 * P4 Xeon erratum 037 workaround.
300 * Hardware prefetcher may cause stale data to be loaded into the cache.
301 */
302 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
303 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
304 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
305 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
306 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
307 }
308 }
309
310 /*
311 * See if we have a good local APIC by checking for buggy Pentia,
312 * i.e. all B steppings and the C2 stepping of P54C when using their
313 * integrated APIC (see 11AP erratum in "Pentium Processor
314 * Specification Update").
315 */
316 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
317 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
318 set_cpu_bug(c, X86_BUG_11AP);
319
320
321#ifdef CONFIG_X86_INTEL_USERCOPY
322 /*
323 * Set up the preferred alignment for movsl bulk memory moves
324 */
325 switch (c->x86) {
326 case 4: /* 486: untested */
327 break;
328 case 5: /* Old Pentia: untested */
329 break;
330 case 6: /* PII/PIII only like movsl with 8-byte alignment */
331 movsl_mask.mask = 7;
332 break;
333 case 15: /* P4 is OK down to 8-byte alignment */
334 movsl_mask.mask = 7;
335 break;
336 }
337#endif
338
339 intel_smp_check(c);
340}
341#else
342static void intel_workarounds(struct cpuinfo_x86 *c)
343{
344}
345#endif
346
347static void srat_detect_node(struct cpuinfo_x86 *c)
348{
349#ifdef CONFIG_NUMA
350 unsigned node;
351 int cpu = smp_processor_id();
352
353 /* Don't do the funky fallback heuristics the AMD version employs
354 for now. */
355 node = numa_cpu_node(cpu);
356 if (node == NUMA_NO_NODE || !node_online(node)) {
357 /* reuse the value from init_cpu_to_node() */
358 node = cpu_to_node(cpu);
359 }
360 numa_set_node(cpu, node);
361#endif
362}
363
364/*
365 * find out the number of processor cores on the die
366 */
367static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
368{
369 unsigned int eax, ebx, ecx, edx;
370
371 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
372 return 1;
373
374 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
375 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
376 if (eax & 0x1f)
377 return (eax >> 26) + 1;
378 else
379 return 1;
380}
381
382static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
383{
384 /* Intel VMX MSR indicated features */
385#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
386#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
387#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
388#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
389#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
390#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
391
392 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
393
394 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
395 clear_cpu_cap(c, X86_FEATURE_VNMI);
396 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
397 clear_cpu_cap(c, X86_FEATURE_EPT);
398 clear_cpu_cap(c, X86_FEATURE_VPID);
399
400 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
401 msr_ctl = vmx_msr_high | vmx_msr_low;
402 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
403 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
404 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
405 set_cpu_cap(c, X86_FEATURE_VNMI);
406 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
407 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
408 vmx_msr_low, vmx_msr_high);
409 msr_ctl2 = vmx_msr_high | vmx_msr_low;
410 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
411 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
412 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
413 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
414 set_cpu_cap(c, X86_FEATURE_EPT);
415 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
416 set_cpu_cap(c, X86_FEATURE_VPID);
417 }
418}
419
420static void init_intel_energy_perf(struct cpuinfo_x86 *c)
421{
422 u64 epb;
423
424 /*
425 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
426 * (x86_energy_perf_policy(8) is available to change it at run-time.)
427 */
428 if (!cpu_has(c, X86_FEATURE_EPB))
429 return;
430
431 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
432 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
433 return;
434
435 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
436 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
437 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
438 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
439}
440
441static void intel_bsp_resume(struct cpuinfo_x86 *c)
442{
443 /*
444 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
445 * so reinitialize it properly like during bootup:
446 */
447 init_intel_energy_perf(c);
448}
449
450static void init_intel(struct cpuinfo_x86 *c)
451{
452 unsigned int l2 = 0;
453
454 early_init_intel(c);
455
456 intel_workarounds(c);
457
458 /*
459 * Detect the extended topology information if available. This
460 * will reinitialise the initial_apicid which will be used
461 * in init_intel_cacheinfo()
462 */
463 detect_extended_topology(c);
464
465 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
466 /*
467 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
468 * detection.
469 */
470 c->x86_max_cores = intel_num_cpu_cores(c);
471#ifdef CONFIG_X86_32
472 detect_ht(c);
473#endif
474 }
475
476 l2 = init_intel_cacheinfo(c);
477
478 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
479 if (l2 == 0) {
480 cpu_detect_cache_sizes(c);
481 l2 = c->x86_cache_size;
482 }
483
484 if (c->cpuid_level > 9) {
485 unsigned eax = cpuid_eax(10);
486 /* Check for version and the number of counters */
487 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
488 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
489 }
490
491 if (cpu_has(c, X86_FEATURE_XMM2))
492 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
493
494 if (boot_cpu_has(X86_FEATURE_DS)) {
495 unsigned int l1;
496 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
497 if (!(l1 & (1<<11)))
498 set_cpu_cap(c, X86_FEATURE_BTS);
499 if (!(l1 & (1<<12)))
500 set_cpu_cap(c, X86_FEATURE_PEBS);
501 }
502
503 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
504 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
505 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
506
507 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
508 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
509 set_cpu_bug(c, X86_BUG_MONITOR);
510
511#ifdef CONFIG_X86_64
512 if (c->x86 == 15)
513 c->x86_cache_alignment = c->x86_clflush_size * 2;
514 if (c->x86 == 6)
515 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
516#else
517 /*
518 * Names for the Pentium II/Celeron processors
519 * detectable only by also checking the cache size.
520 * Dixon is NOT a Celeron.
521 */
522 if (c->x86 == 6) {
523 char *p = NULL;
524
525 switch (c->x86_model) {
526 case 5:
527 if (l2 == 0)
528 p = "Celeron (Covington)";
529 else if (l2 == 256)
530 p = "Mobile Pentium II (Dixon)";
531 break;
532
533 case 6:
534 if (l2 == 128)
535 p = "Celeron (Mendocino)";
536 else if (c->x86_mask == 0 || c->x86_mask == 5)
537 p = "Celeron-A";
538 break;
539
540 case 8:
541 if (l2 == 128)
542 p = "Celeron (Coppermine)";
543 break;
544 }
545
546 if (p)
547 strcpy(c->x86_model_id, p);
548 }
549
550 if (c->x86 == 15)
551 set_cpu_cap(c, X86_FEATURE_P4);
552 if (c->x86 == 6)
553 set_cpu_cap(c, X86_FEATURE_P3);
554#endif
555
556 /* Work around errata */
557 srat_detect_node(c);
558
559 if (cpu_has(c, X86_FEATURE_VMX))
560 detect_vmx_virtcap(c);
561
562 init_intel_energy_perf(c);
563}
564
565#ifdef CONFIG_X86_32
566static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
567{
568 /*
569 * Intel PIII Tualatin. This comes in two flavours.
570 * One has 256kb of cache, the other 512. We have no way
571 * to determine which, so we use a boottime override
572 * for the 512kb model, and assume 256 otherwise.
573 */
574 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
575 size = 256;
576
577 /*
578 * Intel Quark SoC X1000 contains a 4-way set associative
579 * 16K cache with a 16 byte cache line and 256 lines per tag
580 */
581 if ((c->x86 == 5) && (c->x86_model == 9))
582 size = 16;
583 return size;
584}
585#endif
586
587#define TLB_INST_4K 0x01
588#define TLB_INST_4M 0x02
589#define TLB_INST_2M_4M 0x03
590
591#define TLB_INST_ALL 0x05
592#define TLB_INST_1G 0x06
593
594#define TLB_DATA_4K 0x11
595#define TLB_DATA_4M 0x12
596#define TLB_DATA_2M_4M 0x13
597#define TLB_DATA_4K_4M 0x14
598
599#define TLB_DATA_1G 0x16
600
601#define TLB_DATA0_4K 0x21
602#define TLB_DATA0_4M 0x22
603#define TLB_DATA0_2M_4M 0x23
604
605#define STLB_4K 0x41
606#define STLB_4K_2M 0x42
607
608static const struct _tlb_table intel_tlb_table[] = {
609 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
610 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
611 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
612 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
613 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
614 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
615 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
616 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
617 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
618 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
619 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
620 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
621 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
622 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
623 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
624 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
625 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
626 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
627 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
628 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
629 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
630 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
631 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
632 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
633 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
634 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
635 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
636 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
637 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
638 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
639 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
640 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
641 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
642 { 0x00, 0, 0 }
643};
644
645static void intel_tlb_lookup(const unsigned char desc)
646{
647 unsigned char k;
648 if (desc == 0)
649 return;
650
651 /* look up this descriptor in the table */
652 for (k = 0; intel_tlb_table[k].descriptor != desc && \
653 intel_tlb_table[k].descriptor != 0; k++)
654 ;
655
656 if (intel_tlb_table[k].tlb_type == 0)
657 return;
658
659 switch (intel_tlb_table[k].tlb_type) {
660 case STLB_4K:
661 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
662 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
663 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
664 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
665 break;
666 case STLB_4K_2M:
667 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
668 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
669 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
670 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
671 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
672 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
673 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
674 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
675 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
676 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
677 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
678 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
679 break;
680 case TLB_INST_ALL:
681 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
682 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
683 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
684 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
685 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
686 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
687 break;
688 case TLB_INST_4K:
689 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
690 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
691 break;
692 case TLB_INST_4M:
693 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
694 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
695 break;
696 case TLB_INST_2M_4M:
697 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
698 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
699 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
700 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
701 break;
702 case TLB_DATA_4K:
703 case TLB_DATA0_4K:
704 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
705 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
706 break;
707 case TLB_DATA_4M:
708 case TLB_DATA0_4M:
709 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
710 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
711 break;
712 case TLB_DATA_2M_4M:
713 case TLB_DATA0_2M_4M:
714 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
715 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
716 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
717 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
718 break;
719 case TLB_DATA_4K_4M:
720 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
721 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
722 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
723 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
724 break;
725 case TLB_DATA_1G:
726 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
727 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
728 break;
729 }
730}
731
732static void intel_detect_tlb(struct cpuinfo_x86 *c)
733{
734 int i, j, n;
735 unsigned int regs[4];
736 unsigned char *desc = (unsigned char *)regs;
737
738 if (c->cpuid_level < 2)
739 return;
740
741 /* Number of times to iterate */
742 n = cpuid_eax(2) & 0xFF;
743
744 for (i = 0 ; i < n ; i++) {
745 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
746
747 /* If bit 31 is set, this is an unknown format */
748 for (j = 0 ; j < 3 ; j++)
749 if (regs[j] & (1 << 31))
750 regs[j] = 0;
751
752 /* Byte 0 is level count, not a descriptor */
753 for (j = 1 ; j < 16 ; j++)
754 intel_tlb_lookup(desc[j]);
755 }
756}
757
758static const struct cpu_dev intel_cpu_dev = {
759 .c_vendor = "Intel",
760 .c_ident = { "GenuineIntel" },
761#ifdef CONFIG_X86_32
762 .legacy_models = {
763 { .family = 4, .model_names =
764 {
765 [0] = "486 DX-25/33",
766 [1] = "486 DX-50",
767 [2] = "486 SX",
768 [3] = "486 DX/2",
769 [4] = "486 SL",
770 [5] = "486 SX/2",
771 [7] = "486 DX/2-WB",
772 [8] = "486 DX/4",
773 [9] = "486 DX/4-WB"
774 }
775 },
776 { .family = 5, .model_names =
777 {
778 [0] = "Pentium 60/66 A-step",
779 [1] = "Pentium 60/66",
780 [2] = "Pentium 75 - 200",
781 [3] = "OverDrive PODP5V83",
782 [4] = "Pentium MMX",
783 [7] = "Mobile Pentium 75 - 200",
784 [8] = "Mobile Pentium MMX",
785 [9] = "Quark SoC X1000",
786 }
787 },
788 { .family = 6, .model_names =
789 {
790 [0] = "Pentium Pro A-step",
791 [1] = "Pentium Pro",
792 [3] = "Pentium II (Klamath)",
793 [4] = "Pentium II (Deschutes)",
794 [5] = "Pentium II (Deschutes)",
795 [6] = "Mobile Pentium II",
796 [7] = "Pentium III (Katmai)",
797 [8] = "Pentium III (Coppermine)",
798 [10] = "Pentium III (Cascades)",
799 [11] = "Pentium III (Tualatin)",
800 }
801 },
802 { .family = 15, .model_names =
803 {
804 [0] = "Pentium 4 (Unknown)",
805 [1] = "Pentium 4 (Willamette)",
806 [2] = "Pentium 4 (Northwood)",
807 [4] = "Pentium 4 (Foster)",
808 [5] = "Pentium 4 (Foster)",
809 }
810 },
811 },
812 .legacy_cache_size = intel_size_cache,
813#endif
814 .c_detect_tlb = intel_detect_tlb,
815 .c_early_init = early_init_intel,
816 .c_init = init_intel,
817 .c_bsp_resume = intel_bsp_resume,
818 .c_x86_vendor = X86_VENDOR_INTEL,
819};
820
821cpu_dev_register(intel_cpu_dev);
822