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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case TEST_J:
50 case TEST_K:
51 case TEST_SE0_NAK:
52 case TEST_PACKET:
53 case TEST_FORCE_EN:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (dwc->revision >= DWC3_REVISION_194A) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117
118 /*
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
121 */
122 if (dwc->revision >= DWC3_REVISION_194A)
123 return 0;
124
125 /* wait for a change in DSTS */
126 retries = 10000;
127 while (--retries) {
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
129
130 if (DWC3_DSTS_USBLNKST(reg) == state)
131 return 0;
132
133 udelay(5);
134 }
135
136 return -ETIMEDOUT;
137}
138
139/**
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
142 *
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
146 */
147static void dwc3_ep_inc_trb(u8 *index)
148{
149 (*index)++;
150 if (*index == (DWC3_TRB_NUM - 1))
151 *index = 0;
152}
153
154/**
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
157 */
158static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
159{
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
161}
162
163/**
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
166 */
167static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
168{
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
170}
171
172static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
174{
175 struct dwc3 *dwc = dep->dwc;
176
177 list_del(&req->list);
178 req->remaining = 0;
179 req->needs_extra_trb = false;
180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
184 if (req->trb)
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
187
188 req->trb = NULL;
189 trace_dwc3_gadget_giveback(req);
190
191 if (dep->number > 1)
192 pm_runtime_put(dwc->dev);
193}
194
195/**
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
200 *
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
204 */
205void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
206 int status)
207{
208 struct dwc3 *dwc = dep->dwc;
209
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
211 req->status = DWC3_REQUEST_STATUS_COMPLETED;
212
213 spin_unlock(&dwc->lock);
214 usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 spin_lock(&dwc->lock);
216}
217
218/**
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
223 *
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
226 */
227int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
228{
229 u32 timeout = 500;
230 int status = 0;
231 int ret = 0;
232 u32 reg;
233
234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
236
237 do {
238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 if (!(reg & DWC3_DGCMD_CMDACT)) {
240 status = DWC3_DGCMD_STATUS(reg);
241 if (status)
242 ret = -EINVAL;
243 break;
244 }
245 } while (--timeout);
246
247 if (!timeout) {
248 ret = -ETIMEDOUT;
249 status = -ETIMEDOUT;
250 }
251
252 trace_dwc3_gadget_generic_cmd(cmd, param, status);
253
254 return ret;
255}
256
257static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
258
259/**
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
264 *
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
267 */
268int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 struct dwc3_gadget_ep_cmd_params *params)
270{
271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 struct dwc3 *dwc = dep->dwc;
273 u32 timeout = 1000;
274 u32 saved_config = 0;
275 u32 reg;
276
277 int cmd_status = 0;
278 int ret = -EINVAL;
279
280 /*
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
283 * endpoint command.
284 *
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
287 *
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 */
290 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
295 }
296
297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
300 }
301
302 if (saved_config)
303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
304 }
305
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
307 int needs_wakeup;
308
309 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
310 dwc->link_state == DWC3_LINK_STATE_U2 ||
311 dwc->link_state == DWC3_LINK_STATE_U3);
312
313 if (unlikely(needs_wakeup)) {
314 ret = __dwc3_gadget_wakeup(dwc);
315 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
316 ret);
317 }
318 }
319
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
323
324 /*
325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 * not relying on XferNotReady, we can make use of a special "No
327 * Response Update Transfer" command where we should clear both CmdAct
328 * and CmdIOC bits.
329 *
330 * With this, we don't need to wait for command completion and can
331 * straight away issue further commands to the endpoint.
332 *
333 * NOTICE: We're making an assumption that control endpoints will never
334 * make use of Update Transfer command. This is a safe assumption
335 * because we can never have more than one request at a time with
336 * Control Endpoints. If anybody changes that assumption, this chunk
337 * needs to be updated accordingly.
338 */
339 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
340 !usb_endpoint_xfer_isoc(desc))
341 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 else
343 cmd |= DWC3_DEPCMD_CMDACT;
344
345 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 do {
347 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
348 if (!(reg & DWC3_DEPCMD_CMDACT)) {
349 cmd_status = DWC3_DEPCMD_STATUS(reg);
350
351 switch (cmd_status) {
352 case 0:
353 ret = 0;
354 break;
355 case DEPEVT_TRANSFER_NO_RESOURCE:
356 ret = -EINVAL;
357 break;
358 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 /*
360 * SW issues START TRANSFER command to
361 * isochronous ep with future frame interval. If
362 * future interval time has already passed when
363 * core receives the command, it will respond
364 * with an error status of 'Bus Expiry'.
365 *
366 * Instead of always returning -EINVAL, let's
367 * give a hint to the gadget driver that this is
368 * the case by returning -EAGAIN.
369 */
370 ret = -EAGAIN;
371 break;
372 default:
373 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
374 }
375
376 break;
377 }
378 } while (--timeout);
379
380 if (timeout == 0) {
381 ret = -ETIMEDOUT;
382 cmd_status = -ETIMEDOUT;
383 }
384
385 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
386
387 if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
388 dep->flags |= DWC3_EP_TRANSFER_STARTED;
389 dwc3_gadget_ep_get_transfer_index(dep);
390 }
391
392 if (saved_config) {
393 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
394 reg |= saved_config;
395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396 }
397
398 return ret;
399}
400
401static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402{
403 struct dwc3 *dwc = dep->dwc;
404 struct dwc3_gadget_ep_cmd_params params;
405 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
406
407 /*
408 * As of core revision 2.60a the recommended programming model
409 * is to set the ClearPendIN bit when issuing a Clear Stall EP
410 * command for IN endpoints. This is to prevent an issue where
411 * some (non-compliant) hosts may not send ACK TPs for pending
412 * IN transfers due to a mishandled error condition. Synopsys
413 * STAR 9000614252.
414 */
415 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
416 (dwc->gadget.speed >= USB_SPEED_SUPER))
417 cmd |= DWC3_DEPCMD_CLEARPENDIN;
418
419 memset(¶ms, 0, sizeof(params));
420
421 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
422}
423
424static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
425 struct dwc3_trb *trb)
426{
427 u32 offset = (char *) trb - (char *) dep->trb_pool;
428
429 return dep->trb_pool_dma + offset;
430}
431
432static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433{
434 struct dwc3 *dwc = dep->dwc;
435
436 if (dep->trb_pool)
437 return 0;
438
439 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
440 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
441 &dep->trb_pool_dma, GFP_KERNEL);
442 if (!dep->trb_pool) {
443 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
444 dep->name);
445 return -ENOMEM;
446 }
447
448 return 0;
449}
450
451static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452{
453 struct dwc3 *dwc = dep->dwc;
454
455 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
456 dep->trb_pool, dep->trb_pool_dma);
457
458 dep->trb_pool = NULL;
459 dep->trb_pool_dma = 0;
460}
461
462static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463{
464 struct dwc3_gadget_ep_cmd_params params;
465
466 memset(¶ms, 0x00, sizeof(params));
467
468 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469
470 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
471 ¶ms);
472}
473
474/**
475 * dwc3_gadget_start_config - configure ep resources
476 * @dep: endpoint that is being enabled
477 *
478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479 * completion, it will set Transfer Resource for all available endpoints.
480 *
481 * The assignment of transfer resources cannot perfectly follow the data book
482 * due to the fact that the controller driver does not have all knowledge of the
483 * configuration in advance. It is given this information piecemeal by the
484 * composite gadget framework after every SET_CONFIGURATION and
485 * SET_INTERFACE. Trying to follow the databook programming model in this
486 * scenario can cause errors. For two reasons:
487 *
488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490 * incorrect in the scenario of multiple interfaces.
491 *
492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493 * endpoint on alt setting (8.1.6).
494 *
495 * The following simplified method is used instead:
496 *
497 * All hardware endpoints can be assigned a transfer resource and this setting
498 * will stay persistent until either a core reset or hibernation. So whenever we
499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501 * guaranteed that there are as many transfer resources as endpoints.
502 *
503 * This function is called for each endpoint when it is being enabled but is
504 * triggered only when called for EP0-out, which always happens first, and which
505 * should only happen in one of the above conditions.
506 */
507static int dwc3_gadget_start_config(struct dwc3_ep *dep)
508{
509 struct dwc3_gadget_ep_cmd_params params;
510 struct dwc3 *dwc;
511 u32 cmd;
512 int i;
513 int ret;
514
515 if (dep->number)
516 return 0;
517
518 memset(¶ms, 0x00, sizeof(params));
519 cmd = DWC3_DEPCMD_DEPSTARTCFG;
520 dwc = dep->dwc;
521
522 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
523 if (ret)
524 return ret;
525
526 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
527 struct dwc3_ep *dep = dwc->eps[i];
528
529 if (!dep)
530 continue;
531
532 ret = dwc3_gadget_set_xfer_resource(dep);
533 if (ret)
534 return ret;
535 }
536
537 return 0;
538}
539
540static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
541{
542 const struct usb_ss_ep_comp_descriptor *comp_desc;
543 const struct usb_endpoint_descriptor *desc;
544 struct dwc3_gadget_ep_cmd_params params;
545 struct dwc3 *dwc = dep->dwc;
546
547 comp_desc = dep->endpoint.comp_desc;
548 desc = dep->endpoint.desc;
549
550 memset(¶ms, 0x00, sizeof(params));
551
552 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
554
555 /* Burst size is only needed in SuperSpeed mode */
556 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
557 u32 burst = dep->endpoint.maxburst;
558 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
559 }
560
561 params.param0 |= action;
562 if (action == DWC3_DEPCFG_ACTION_RESTORE)
563 params.param2 |= dep->saved_state;
564
565 if (usb_endpoint_xfer_control(desc))
566 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
567
568 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
569 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
570
571 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
572 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
573 | DWC3_DEPCFG_STREAM_EVENT_EN;
574 dep->stream_capable = true;
575 }
576
577 if (!usb_endpoint_xfer_control(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
579
580 /*
581 * We are doing 1:1 mapping for endpoints, meaning
582 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 * so on. We consider the direction bit as part of the physical
584 * endpoint number. So USB endpoint 0x81 is 0x03.
585 */
586 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
587
588 /*
589 * We must use the lower 16 TX FIFOs even though
590 * HW might have more
591 */
592 if (dep->direction)
593 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
594
595 if (desc->bInterval) {
596 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
597 dep->interval = 1 << (desc->bInterval - 1);
598 }
599
600 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
601}
602
603/**
604 * __dwc3_gadget_ep_enable - initializes a hw endpoint
605 * @dep: endpoint to be initialized
606 * @action: one of INIT, MODIFY or RESTORE
607 *
608 * Caller should take care of locking. Execute all necessary commands to
609 * initialize a HW endpoint so it can be used by a gadget driver.
610 */
611static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
612{
613 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
614 struct dwc3 *dwc = dep->dwc;
615
616 u32 reg;
617 int ret;
618
619 if (!(dep->flags & DWC3_EP_ENABLED)) {
620 ret = dwc3_gadget_start_config(dep);
621 if (ret)
622 return ret;
623 }
624
625 ret = dwc3_gadget_set_ep_config(dep, action);
626 if (ret)
627 return ret;
628
629 if (!(dep->flags & DWC3_EP_ENABLED)) {
630 struct dwc3_trb *trb_st_hw;
631 struct dwc3_trb *trb_link;
632
633 dep->type = usb_endpoint_type(desc);
634 dep->flags |= DWC3_EP_ENABLED;
635
636 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
637 reg |= DWC3_DALEPENA_EP(dep->number);
638 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
639
640 if (usb_endpoint_xfer_control(desc))
641 goto out;
642
643 /* Initialize the TRB ring */
644 dep->trb_dequeue = 0;
645 dep->trb_enqueue = 0;
646 memset(dep->trb_pool, 0,
647 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
648
649 /* Link TRB. The HWO bit is never reset */
650 trb_st_hw = &dep->trb_pool[0];
651
652 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
653 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
654 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
655 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
656 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
657 }
658
659 /*
660 * Issue StartTransfer here with no-op TRB so we can always rely on No
661 * Response Update Transfer command.
662 */
663 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
664 usb_endpoint_xfer_int(desc)) {
665 struct dwc3_gadget_ep_cmd_params params;
666 struct dwc3_trb *trb;
667 dma_addr_t trb_dma;
668 u32 cmd;
669
670 memset(¶ms, 0, sizeof(params));
671 trb = &dep->trb_pool[0];
672 trb_dma = dwc3_trb_dma_offset(dep, trb);
673
674 params.param0 = upper_32_bits(trb_dma);
675 params.param1 = lower_32_bits(trb_dma);
676
677 cmd = DWC3_DEPCMD_STARTTRANSFER;
678
679 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
680 if (ret < 0)
681 return ret;
682 }
683
684out:
685 trace_dwc3_gadget_ep_enable(dep);
686
687 return 0;
688}
689
690static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
691 bool interrupt);
692static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
693{
694 struct dwc3_request *req;
695
696 dwc3_stop_active_transfer(dep, true, false);
697
698 /* - giveback all requests to gadget driver */
699 while (!list_empty(&dep->started_list)) {
700 req = next_request(&dep->started_list);
701
702 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
703 }
704
705 while (!list_empty(&dep->pending_list)) {
706 req = next_request(&dep->pending_list);
707
708 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
709 }
710
711 while (!list_empty(&dep->cancelled_list)) {
712 req = next_request(&dep->cancelled_list);
713
714 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 }
716}
717
718/**
719 * __dwc3_gadget_ep_disable - disables a hw endpoint
720 * @dep: the endpoint to disable
721 *
722 * This function undoes what __dwc3_gadget_ep_enable did and also removes
723 * requests which are currently being processed by the hardware and those which
724 * are not yet scheduled.
725 *
726 * Caller should take care of locking.
727 */
728static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
729{
730 struct dwc3 *dwc = dep->dwc;
731 u32 reg;
732
733 trace_dwc3_gadget_ep_disable(dep);
734
735 dwc3_remove_requests(dwc, dep);
736
737 /* make sure HW endpoint isn't stalled */
738 if (dep->flags & DWC3_EP_STALL)
739 __dwc3_gadget_ep_set_halt(dep, 0, false);
740
741 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
742 reg &= ~DWC3_DALEPENA_EP(dep->number);
743 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
744
745 dep->stream_capable = false;
746 dep->type = 0;
747 dep->flags = 0;
748
749 /* Clear out the ep descriptors for non-ep0 */
750 if (dep->number > 1) {
751 dep->endpoint.comp_desc = NULL;
752 dep->endpoint.desc = NULL;
753 }
754
755 return 0;
756}
757
758/* -------------------------------------------------------------------------- */
759
760static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
761 const struct usb_endpoint_descriptor *desc)
762{
763 return -EINVAL;
764}
765
766static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
767{
768 return -EINVAL;
769}
770
771/* -------------------------------------------------------------------------- */
772
773static int dwc3_gadget_ep_enable(struct usb_ep *ep,
774 const struct usb_endpoint_descriptor *desc)
775{
776 struct dwc3_ep *dep;
777 struct dwc3 *dwc;
778 unsigned long flags;
779 int ret;
780
781 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
782 pr_debug("dwc3: invalid parameters\n");
783 return -EINVAL;
784 }
785
786 if (!desc->wMaxPacketSize) {
787 pr_debug("dwc3: missing wMaxPacketSize\n");
788 return -EINVAL;
789 }
790
791 dep = to_dwc3_ep(ep);
792 dwc = dep->dwc;
793
794 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
795 "%s is already enabled\n",
796 dep->name))
797 return 0;
798
799 spin_lock_irqsave(&dwc->lock, flags);
800 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
801 spin_unlock_irqrestore(&dwc->lock, flags);
802
803 return ret;
804}
805
806static int dwc3_gadget_ep_disable(struct usb_ep *ep)
807{
808 struct dwc3_ep *dep;
809 struct dwc3 *dwc;
810 unsigned long flags;
811 int ret;
812
813 if (!ep) {
814 pr_debug("dwc3: invalid parameters\n");
815 return -EINVAL;
816 }
817
818 dep = to_dwc3_ep(ep);
819 dwc = dep->dwc;
820
821 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
822 "%s is already disabled\n",
823 dep->name))
824 return 0;
825
826 spin_lock_irqsave(&dwc->lock, flags);
827 ret = __dwc3_gadget_ep_disable(dep);
828 spin_unlock_irqrestore(&dwc->lock, flags);
829
830 return ret;
831}
832
833static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
834 gfp_t gfp_flags)
835{
836 struct dwc3_request *req;
837 struct dwc3_ep *dep = to_dwc3_ep(ep);
838
839 req = kzalloc(sizeof(*req), gfp_flags);
840 if (!req)
841 return NULL;
842
843 req->direction = dep->direction;
844 req->epnum = dep->number;
845 req->dep = dep;
846 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
847
848 trace_dwc3_alloc_request(req);
849
850 return &req->request;
851}
852
853static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
854 struct usb_request *request)
855{
856 struct dwc3_request *req = to_dwc3_request(request);
857
858 trace_dwc3_free_request(req);
859 kfree(req);
860}
861
862/**
863 * dwc3_ep_prev_trb - returns the previous TRB in the ring
864 * @dep: The endpoint with the TRB ring
865 * @index: The index of the current TRB in the ring
866 *
867 * Returns the TRB prior to the one pointed to by the index. If the
868 * index is 0, we will wrap backwards, skip the link TRB, and return
869 * the one just before that.
870 */
871static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
872{
873 u8 tmp = index;
874
875 if (!tmp)
876 tmp = DWC3_TRB_NUM - 1;
877
878 return &dep->trb_pool[tmp - 1];
879}
880
881static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
882{
883 struct dwc3_trb *tmp;
884 u8 trbs_left;
885
886 /*
887 * If enqueue & dequeue are equal than it is either full or empty.
888 *
889 * One way to know for sure is if the TRB right before us has HWO bit
890 * set or not. If it has, then we're definitely full and can't fit any
891 * more transfers in our ring.
892 */
893 if (dep->trb_enqueue == dep->trb_dequeue) {
894 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
895 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
896 return 0;
897
898 return DWC3_TRB_NUM - 1;
899 }
900
901 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
902 trbs_left &= (DWC3_TRB_NUM - 1);
903
904 if (dep->trb_dequeue < dep->trb_enqueue)
905 trbs_left--;
906
907 return trbs_left;
908}
909
910static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
911 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
912 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
913{
914 struct dwc3 *dwc = dep->dwc;
915 struct usb_gadget *gadget = &dwc->gadget;
916 enum usb_device_speed speed = gadget->speed;
917
918 trb->size = DWC3_TRB_SIZE_LENGTH(length);
919 trb->bpl = lower_32_bits(dma);
920 trb->bph = upper_32_bits(dma);
921
922 switch (usb_endpoint_type(dep->endpoint.desc)) {
923 case USB_ENDPOINT_XFER_CONTROL:
924 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 break;
926
927 case USB_ENDPOINT_XFER_ISOC:
928 if (!node) {
929 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930
931 /*
932 * USB Specification 2.0 Section 5.9.2 states that: "If
933 * there is only a single transaction in the microframe,
934 * only a DATA0 data packet PID is used. If there are
935 * two transactions per microframe, DATA1 is used for
936 * the first transaction data packet and DATA0 is used
937 * for the second transaction data packet. If there are
938 * three transactions per microframe, DATA2 is used for
939 * the first transaction data packet, DATA1 is used for
940 * the second, and DATA0 is used for the third."
941 *
942 * IOW, we should satisfy the following cases:
943 *
944 * 1) length <= maxpacket
945 * - DATA0
946 *
947 * 2) maxpacket < length <= (2 * maxpacket)
948 * - DATA1, DATA0
949 *
950 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
951 * - DATA2, DATA1, DATA0
952 */
953 if (speed == USB_SPEED_HIGH) {
954 struct usb_ep *ep = &dep->endpoint;
955 unsigned int mult = 2;
956 unsigned int maxp = usb_endpoint_maxp(ep->desc);
957
958 if (length <= (2 * maxp))
959 mult--;
960
961 if (length <= maxp)
962 mult--;
963
964 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 }
966 } else {
967 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 }
969
970 /* always enable Interrupt on Missed ISOC */
971 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 break;
973
974 case USB_ENDPOINT_XFER_BULK:
975 case USB_ENDPOINT_XFER_INT:
976 trb->ctrl = DWC3_TRBCTL_NORMAL;
977 break;
978 default:
979 /*
980 * This is only possible with faulty memory because we
981 * checked it already :)
982 */
983 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
984 usb_endpoint_type(dep->endpoint.desc));
985 }
986
987 /*
988 * Enable Continue on Short Packet
989 * when endpoint is not a stream capable
990 */
991 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
992 if (!dep->stream_capable)
993 trb->ctrl |= DWC3_TRB_CTRL_CSP;
994
995 if (short_not_ok)
996 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 }
998
999 if ((!no_interrupt && !chain) ||
1000 (dwc3_calc_trbs_left(dep) == 1))
1001 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002
1003 if (chain)
1004 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1005
1006 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1007 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1008
1009 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1010
1011 dwc3_ep_inc_enq(dep);
1012
1013 trace_dwc3_prepare_trb(dep, trb);
1014}
1015
1016/**
1017 * dwc3_prepare_one_trb - setup one TRB from one request
1018 * @dep: endpoint for which this request is prepared
1019 * @req: dwc3_request pointer
1020 * @chain: should this TRB be chained to the next?
1021 * @node: only for isochronous endpoints. First TRB needs different type.
1022 */
1023static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024 struct dwc3_request *req, unsigned chain, unsigned node)
1025{
1026 struct dwc3_trb *trb;
1027 unsigned int length;
1028 dma_addr_t dma;
1029 unsigned stream_id = req->request.stream_id;
1030 unsigned short_not_ok = req->request.short_not_ok;
1031 unsigned no_interrupt = req->request.no_interrupt;
1032
1033 if (req->request.num_sgs > 0) {
1034 length = sg_dma_len(req->start_sg);
1035 dma = sg_dma_address(req->start_sg);
1036 } else {
1037 length = req->request.length;
1038 dma = req->request.dma;
1039 }
1040
1041 trb = &dep->trb_pool[dep->trb_enqueue];
1042
1043 if (!req->trb) {
1044 dwc3_gadget_move_started_request(req);
1045 req->trb = trb;
1046 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1047 }
1048
1049 req->num_trbs++;
1050
1051 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1052 stream_id, short_not_ok, no_interrupt);
1053}
1054
1055static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1057{
1058 struct scatterlist *sg = req->start_sg;
1059 struct scatterlist *s;
1060 int i;
1061
1062 unsigned int remaining = req->request.num_mapped_sgs
1063 - req->num_queued_sgs;
1064
1065 for_each_sg(sg, s, remaining, i) {
1066 unsigned int length = req->request.length;
1067 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1068 unsigned int rem = length % maxp;
1069 unsigned chain = true;
1070
1071 if (sg_is_last(s))
1072 chain = false;
1073
1074 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1075 struct dwc3 *dwc = dep->dwc;
1076 struct dwc3_trb *trb;
1077
1078 req->needs_extra_trb = true;
1079
1080 /* prepare normal TRB */
1081 dwc3_prepare_one_trb(dep, req, true, i);
1082
1083 /* Now prepare one extra TRB to align transfer size */
1084 trb = &dep->trb_pool[dep->trb_enqueue];
1085 req->num_trbs++;
1086 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1087 maxp - rem, false, 1,
1088 req->request.stream_id,
1089 req->request.short_not_ok,
1090 req->request.no_interrupt);
1091 } else {
1092 dwc3_prepare_one_trb(dep, req, chain, i);
1093 }
1094
1095 /*
1096 * There can be a situation where all sgs in sglist are not
1097 * queued because of insufficient trb number. To handle this
1098 * case, update start_sg to next sg to be queued, so that
1099 * we have free trbs we can continue queuing from where we
1100 * previously stopped
1101 */
1102 if (chain)
1103 req->start_sg = sg_next(s);
1104
1105 req->num_queued_sgs++;
1106
1107 if (!dwc3_calc_trbs_left(dep))
1108 break;
1109 }
1110}
1111
1112static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1113 struct dwc3_request *req)
1114{
1115 unsigned int length = req->request.length;
1116 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1117 unsigned int rem = length % maxp;
1118
1119 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1122
1123 req->needs_extra_trb = true;
1124
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1127
1128 /* Now prepare one extra TRB to align transfer size */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1130 req->num_trbs++;
1131 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1132 false, 1, req->request.stream_id,
1133 req->request.short_not_ok,
1134 req->request.no_interrupt);
1135 } else if (req->request.zero && req->request.length &&
1136 (IS_ALIGNED(req->request.length, maxp))) {
1137 struct dwc3 *dwc = dep->dwc;
1138 struct dwc3_trb *trb;
1139
1140 req->needs_extra_trb = true;
1141
1142 /* prepare normal TRB */
1143 dwc3_prepare_one_trb(dep, req, true, 0);
1144
1145 /* Now prepare one extra TRB to handle ZLP */
1146 trb = &dep->trb_pool[dep->trb_enqueue];
1147 req->num_trbs++;
1148 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1149 false, 1, req->request.stream_id,
1150 req->request.short_not_ok,
1151 req->request.no_interrupt);
1152 } else {
1153 dwc3_prepare_one_trb(dep, req, false, 0);
1154 }
1155}
1156
1157/*
1158 * dwc3_prepare_trbs - setup TRBs from requests
1159 * @dep: endpoint for which requests are being prepared
1160 *
1161 * The function goes through the requests list and sets up TRBs for the
1162 * transfers. The function returns once there are no more TRBs available or
1163 * it runs out of requests.
1164 */
1165static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1166{
1167 struct dwc3_request *req, *n;
1168
1169 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1170
1171 /*
1172 * We can get in a situation where there's a request in the started list
1173 * but there weren't enough TRBs to fully kick it in the first time
1174 * around, so it has been waiting for more TRBs to be freed up.
1175 *
1176 * In that case, we should check if we have a request with pending_sgs
1177 * in the started list and prepare TRBs for that request first,
1178 * otherwise we will prepare TRBs completely out of order and that will
1179 * break things.
1180 */
1181 list_for_each_entry(req, &dep->started_list, list) {
1182 if (req->num_pending_sgs > 0)
1183 dwc3_prepare_one_trb_sg(dep, req);
1184
1185 if (!dwc3_calc_trbs_left(dep))
1186 return;
1187 }
1188
1189 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1190 struct dwc3 *dwc = dep->dwc;
1191 int ret;
1192
1193 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1194 dep->direction);
1195 if (ret)
1196 return;
1197
1198 req->sg = req->request.sg;
1199 req->start_sg = req->sg;
1200 req->num_queued_sgs = 0;
1201 req->num_pending_sgs = req->request.num_mapped_sgs;
1202
1203 if (req->num_pending_sgs > 0)
1204 dwc3_prepare_one_trb_sg(dep, req);
1205 else
1206 dwc3_prepare_one_trb_linear(dep, req);
1207
1208 if (!dwc3_calc_trbs_left(dep))
1209 return;
1210 }
1211}
1212
1213static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1214{
1215 struct dwc3_gadget_ep_cmd_params params;
1216 struct dwc3_request *req;
1217 int starting;
1218 int ret;
1219 u32 cmd;
1220
1221 if (!dwc3_calc_trbs_left(dep))
1222 return 0;
1223
1224 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1225
1226 dwc3_prepare_trbs(dep);
1227 req = next_request(&dep->started_list);
1228 if (!req) {
1229 dep->flags |= DWC3_EP_PENDING_REQUEST;
1230 return 0;
1231 }
1232
1233 memset(¶ms, 0, sizeof(params));
1234
1235 if (starting) {
1236 params.param0 = upper_32_bits(req->trb_dma);
1237 params.param1 = lower_32_bits(req->trb_dma);
1238 cmd = DWC3_DEPCMD_STARTTRANSFER;
1239
1240 if (dep->stream_capable)
1241 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1242
1243 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1244 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1245 } else {
1246 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1247 DWC3_DEPCMD_PARAM(dep->resource_index);
1248 }
1249
1250 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1251 if (ret < 0) {
1252 /*
1253 * FIXME we need to iterate over the list of requests
1254 * here and stop, unmap, free and del each of the linked
1255 * requests instead of what we do now.
1256 */
1257 if (req->trb)
1258 memset(req->trb, 0, sizeof(struct dwc3_trb));
1259 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1260 return ret;
1261 }
1262
1263 return 0;
1264}
1265
1266static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1267{
1268 u32 reg;
1269
1270 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1271 return DWC3_DSTS_SOFFN(reg);
1272}
1273
1274/**
1275 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1276 * @dep: isoc endpoint
1277 *
1278 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1279 * microframe number reported by the XferNotReady event for the future frame
1280 * number to start the isoc transfer.
1281 *
1282 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1283 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1284 * XferNotReady event are invalid. The driver uses this number to schedule the
1285 * isochronous transfer and passes it to the START TRANSFER command. Because
1286 * this number is invalid, the command may fail. If BIT[15:14] matches the
1287 * internal 16-bit microframe, the START TRANSFER command will pass and the
1288 * transfer will start at the scheduled time, if it is off by 1, the command
1289 * will still pass, but the transfer will start 2 seconds in the future. For all
1290 * other conditions, the START TRANSFER command will fail with bus-expiry.
1291 *
1292 * In order to workaround this issue, we can test for the correct combination of
1293 * BIT[15:14] by sending START TRANSFER commands with different values of
1294 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1295 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1296 * As the result, within the 4 possible combinations for BIT[15:14], there will
1297 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1298 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1299 * value is the correct combination.
1300 *
1301 * Since there are only 4 outcomes and the results are ordered, we can simply
1302 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1303 * deduce the smaller successful combination.
1304 *
1305 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1306 * of BIT[15:14]. The correct combination is as follow:
1307 *
1308 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1309 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1310 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1311 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1312 *
1313 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1314 * endpoints.
1315 */
1316static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1317{
1318 int cmd_status = 0;
1319 bool test0;
1320 bool test1;
1321
1322 while (dep->combo_num < 2) {
1323 struct dwc3_gadget_ep_cmd_params params;
1324 u32 test_frame_number;
1325 u32 cmd;
1326
1327 /*
1328 * Check if we can start isoc transfer on the next interval or
1329 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1330 */
1331 test_frame_number = dep->frame_number & 0x3fff;
1332 test_frame_number |= dep->combo_num << 14;
1333 test_frame_number += max_t(u32, 4, dep->interval);
1334
1335 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1336 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1337
1338 cmd = DWC3_DEPCMD_STARTTRANSFER;
1339 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1340 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1341
1342 /* Redo if some other failure beside bus-expiry is received */
1343 if (cmd_status && cmd_status != -EAGAIN) {
1344 dep->start_cmd_status = 0;
1345 dep->combo_num = 0;
1346 return 0;
1347 }
1348
1349 /* Store the first test status */
1350 if (dep->combo_num == 0)
1351 dep->start_cmd_status = cmd_status;
1352
1353 dep->combo_num++;
1354
1355 /*
1356 * End the transfer if the START_TRANSFER command is successful
1357 * to wait for the next XferNotReady to test the command again
1358 */
1359 if (cmd_status == 0) {
1360 dwc3_stop_active_transfer(dep, true, true);
1361 return 0;
1362 }
1363 }
1364
1365 /* test0 and test1 are both completed at this point */
1366 test0 = (dep->start_cmd_status == 0);
1367 test1 = (cmd_status == 0);
1368
1369 if (!test0 && test1)
1370 dep->combo_num = 1;
1371 else if (!test0 && !test1)
1372 dep->combo_num = 2;
1373 else if (test0 && !test1)
1374 dep->combo_num = 3;
1375 else if (test0 && test1)
1376 dep->combo_num = 0;
1377
1378 dep->frame_number &= 0x3fff;
1379 dep->frame_number |= dep->combo_num << 14;
1380 dep->frame_number += max_t(u32, 4, dep->interval);
1381
1382 /* Reinitialize test variables */
1383 dep->start_cmd_status = 0;
1384 dep->combo_num = 0;
1385
1386 return __dwc3_gadget_kick_transfer(dep);
1387}
1388
1389static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1390{
1391 struct dwc3 *dwc = dep->dwc;
1392 int ret;
1393 int i;
1394
1395 if (list_empty(&dep->pending_list)) {
1396 dep->flags |= DWC3_EP_PENDING_REQUEST;
1397 return -EAGAIN;
1398 }
1399
1400 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1401 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1402 (dwc->revision == DWC3_USB31_REVISION_170A &&
1403 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1404 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1405
1406 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1407 return dwc3_gadget_start_isoc_quirk(dep);
1408 }
1409
1410 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1411 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1412
1413 ret = __dwc3_gadget_kick_transfer(dep);
1414 if (ret != -EAGAIN)
1415 break;
1416 }
1417
1418 return ret;
1419}
1420
1421static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1422{
1423 struct dwc3 *dwc = dep->dwc;
1424
1425 if (!dep->endpoint.desc) {
1426 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1427 dep->name);
1428 return -ESHUTDOWN;
1429 }
1430
1431 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1432 &req->request, req->dep->name))
1433 return -EINVAL;
1434
1435 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1436 "%s: request %pK already in flight\n",
1437 dep->name, &req->request))
1438 return -EINVAL;
1439
1440 pm_runtime_get(dwc->dev);
1441
1442 req->request.actual = 0;
1443 req->request.status = -EINPROGRESS;
1444
1445 trace_dwc3_ep_queue(req);
1446
1447 list_add_tail(&req->list, &dep->pending_list);
1448 req->status = DWC3_REQUEST_STATUS_QUEUED;
1449
1450 /*
1451 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1452 * wait for a XferNotReady event so we will know what's the current
1453 * (micro-)frame number.
1454 *
1455 * Without this trick, we are very, very likely gonna get Bus Expiry
1456 * errors which will force us issue EndTransfer command.
1457 */
1458 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1459 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1460 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1461 return 0;
1462
1463 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1464 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1465 return __dwc3_gadget_start_isoc(dep);
1466 }
1467 }
1468 }
1469
1470 return __dwc3_gadget_kick_transfer(dep);
1471}
1472
1473static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1474 gfp_t gfp_flags)
1475{
1476 struct dwc3_request *req = to_dwc3_request(request);
1477 struct dwc3_ep *dep = to_dwc3_ep(ep);
1478 struct dwc3 *dwc = dep->dwc;
1479
1480 unsigned long flags;
1481
1482 int ret;
1483
1484 spin_lock_irqsave(&dwc->lock, flags);
1485 ret = __dwc3_gadget_ep_queue(dep, req);
1486 spin_unlock_irqrestore(&dwc->lock, flags);
1487
1488 return ret;
1489}
1490
1491static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1492{
1493 int i;
1494
1495 /*
1496 * If request was already started, this means we had to
1497 * stop the transfer. With that we also need to ignore
1498 * all TRBs used by the request, however TRBs can only
1499 * be modified after completion of END_TRANSFER
1500 * command. So what we do here is that we wait for
1501 * END_TRANSFER completion and only after that, we jump
1502 * over TRBs by clearing HWO and incrementing dequeue
1503 * pointer.
1504 */
1505 for (i = 0; i < req->num_trbs; i++) {
1506 struct dwc3_trb *trb;
1507
1508 trb = req->trb + i;
1509 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 dwc3_ep_inc_deq(dep);
1511 }
1512
1513 req->num_trbs = 0;
1514}
1515
1516static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1517{
1518 struct dwc3_request *req;
1519 struct dwc3_request *tmp;
1520
1521 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1522 dwc3_gadget_ep_skip_trbs(dep, req);
1523 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1524 }
1525}
1526
1527static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1528 struct usb_request *request)
1529{
1530 struct dwc3_request *req = to_dwc3_request(request);
1531 struct dwc3_request *r = NULL;
1532
1533 struct dwc3_ep *dep = to_dwc3_ep(ep);
1534 struct dwc3 *dwc = dep->dwc;
1535
1536 unsigned long flags;
1537 int ret = 0;
1538
1539 trace_dwc3_ep_dequeue(req);
1540
1541 spin_lock_irqsave(&dwc->lock, flags);
1542
1543 list_for_each_entry(r, &dep->pending_list, list) {
1544 if (r == req)
1545 break;
1546 }
1547
1548 if (r != req) {
1549 list_for_each_entry(r, &dep->started_list, list) {
1550 if (r == req)
1551 break;
1552 }
1553 if (r == req) {
1554 /* wait until it is processed */
1555 dwc3_stop_active_transfer(dep, true, true);
1556
1557 if (!r->trb)
1558 goto out0;
1559
1560 dwc3_gadget_move_cancelled_request(req);
1561 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
1562 goto out0;
1563 else
1564 goto out1;
1565 }
1566 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1567 request, ep->name);
1568 ret = -EINVAL;
1569 goto out0;
1570 }
1571
1572out1:
1573 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1574
1575out0:
1576 spin_unlock_irqrestore(&dwc->lock, flags);
1577
1578 return ret;
1579}
1580
1581int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1582{
1583 struct dwc3_gadget_ep_cmd_params params;
1584 struct dwc3 *dwc = dep->dwc;
1585 int ret;
1586
1587 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1588 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1589 return -EINVAL;
1590 }
1591
1592 memset(¶ms, 0x00, sizeof(params));
1593
1594 if (value) {
1595 struct dwc3_trb *trb;
1596
1597 unsigned transfer_in_flight;
1598 unsigned started;
1599
1600 if (dep->number > 1)
1601 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1602 else
1603 trb = &dwc->ep0_trb[dep->trb_enqueue];
1604
1605 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1606 started = !list_empty(&dep->started_list);
1607
1608 if (!protocol && ((dep->direction && transfer_in_flight) ||
1609 (!dep->direction && started))) {
1610 return -EAGAIN;
1611 }
1612
1613 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1614 ¶ms);
1615 if (ret)
1616 dev_err(dwc->dev, "failed to set STALL on %s\n",
1617 dep->name);
1618 else
1619 dep->flags |= DWC3_EP_STALL;
1620 } else {
1621
1622 ret = dwc3_send_clear_stall_ep_cmd(dep);
1623 if (ret)
1624 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1625 dep->name);
1626 else
1627 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1628 }
1629
1630 return ret;
1631}
1632
1633static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1634{
1635 struct dwc3_ep *dep = to_dwc3_ep(ep);
1636 struct dwc3 *dwc = dep->dwc;
1637
1638 unsigned long flags;
1639
1640 int ret;
1641
1642 spin_lock_irqsave(&dwc->lock, flags);
1643 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1644 spin_unlock_irqrestore(&dwc->lock, flags);
1645
1646 return ret;
1647}
1648
1649static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1650{
1651 struct dwc3_ep *dep = to_dwc3_ep(ep);
1652 struct dwc3 *dwc = dep->dwc;
1653 unsigned long flags;
1654 int ret;
1655
1656 spin_lock_irqsave(&dwc->lock, flags);
1657 dep->flags |= DWC3_EP_WEDGE;
1658
1659 if (dep->number == 0 || dep->number == 1)
1660 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1661 else
1662 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1663 spin_unlock_irqrestore(&dwc->lock, flags);
1664
1665 return ret;
1666}
1667
1668/* -------------------------------------------------------------------------- */
1669
1670static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1671 .bLength = USB_DT_ENDPOINT_SIZE,
1672 .bDescriptorType = USB_DT_ENDPOINT,
1673 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1674};
1675
1676static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1677 .enable = dwc3_gadget_ep0_enable,
1678 .disable = dwc3_gadget_ep0_disable,
1679 .alloc_request = dwc3_gadget_ep_alloc_request,
1680 .free_request = dwc3_gadget_ep_free_request,
1681 .queue = dwc3_gadget_ep0_queue,
1682 .dequeue = dwc3_gadget_ep_dequeue,
1683 .set_halt = dwc3_gadget_ep0_set_halt,
1684 .set_wedge = dwc3_gadget_ep_set_wedge,
1685};
1686
1687static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1688 .enable = dwc3_gadget_ep_enable,
1689 .disable = dwc3_gadget_ep_disable,
1690 .alloc_request = dwc3_gadget_ep_alloc_request,
1691 .free_request = dwc3_gadget_ep_free_request,
1692 .queue = dwc3_gadget_ep_queue,
1693 .dequeue = dwc3_gadget_ep_dequeue,
1694 .set_halt = dwc3_gadget_ep_set_halt,
1695 .set_wedge = dwc3_gadget_ep_set_wedge,
1696};
1697
1698/* -------------------------------------------------------------------------- */
1699
1700static int dwc3_gadget_get_frame(struct usb_gadget *g)
1701{
1702 struct dwc3 *dwc = gadget_to_dwc(g);
1703
1704 return __dwc3_gadget_get_frame(dwc);
1705}
1706
1707static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1708{
1709 int retries;
1710
1711 int ret;
1712 u32 reg;
1713
1714 u8 link_state;
1715 u8 speed;
1716
1717 /*
1718 * According to the Databook Remote wakeup request should
1719 * be issued only when the device is in early suspend state.
1720 *
1721 * We can check that via USB Link State bits in DSTS register.
1722 */
1723 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724
1725 speed = reg & DWC3_DSTS_CONNECTSPD;
1726 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1727 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1728 return 0;
1729
1730 link_state = DWC3_DSTS_USBLNKST(reg);
1731
1732 switch (link_state) {
1733 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1734 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1735 break;
1736 default:
1737 return -EINVAL;
1738 }
1739
1740 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1741 if (ret < 0) {
1742 dev_err(dwc->dev, "failed to put link in Recovery\n");
1743 return ret;
1744 }
1745
1746 /* Recent versions do this automatically */
1747 if (dwc->revision < DWC3_REVISION_194A) {
1748 /* write zeroes to Link Change Request */
1749 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1750 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1751 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1752 }
1753
1754 /* poll until Link State changes to ON */
1755 retries = 20000;
1756
1757 while (retries--) {
1758 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1759
1760 /* in HS, means ON */
1761 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1762 break;
1763 }
1764
1765 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1766 dev_err(dwc->dev, "failed to send remote wakeup\n");
1767 return -EINVAL;
1768 }
1769
1770 return 0;
1771}
1772
1773static int dwc3_gadget_wakeup(struct usb_gadget *g)
1774{
1775 struct dwc3 *dwc = gadget_to_dwc(g);
1776 unsigned long flags;
1777 int ret;
1778
1779 spin_lock_irqsave(&dwc->lock, flags);
1780 ret = __dwc3_gadget_wakeup(dwc);
1781 spin_unlock_irqrestore(&dwc->lock, flags);
1782
1783 return ret;
1784}
1785
1786static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1787 int is_selfpowered)
1788{
1789 struct dwc3 *dwc = gadget_to_dwc(g);
1790 unsigned long flags;
1791
1792 spin_lock_irqsave(&dwc->lock, flags);
1793 g->is_selfpowered = !!is_selfpowered;
1794 spin_unlock_irqrestore(&dwc->lock, flags);
1795
1796 return 0;
1797}
1798
1799static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1800{
1801 u32 reg;
1802 u32 timeout = 500;
1803
1804 if (pm_runtime_suspended(dwc->dev))
1805 return 0;
1806
1807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1808 if (is_on) {
1809 if (dwc->revision <= DWC3_REVISION_187A) {
1810 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1811 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1812 }
1813
1814 if (dwc->revision >= DWC3_REVISION_194A)
1815 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1816 reg |= DWC3_DCTL_RUN_STOP;
1817
1818 if (dwc->has_hibernation)
1819 reg |= DWC3_DCTL_KEEP_CONNECT;
1820
1821 dwc->pullups_connected = true;
1822 } else {
1823 reg &= ~DWC3_DCTL_RUN_STOP;
1824
1825 if (dwc->has_hibernation && !suspend)
1826 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1827
1828 dwc->pullups_connected = false;
1829 }
1830
1831 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1832
1833 do {
1834 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1835 reg &= DWC3_DSTS_DEVCTRLHLT;
1836 } while (--timeout && !(!is_on ^ !reg));
1837
1838 if (!timeout)
1839 return -ETIMEDOUT;
1840
1841 return 0;
1842}
1843
1844static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1845{
1846 struct dwc3 *dwc = gadget_to_dwc(g);
1847 unsigned long flags;
1848 int ret;
1849
1850 is_on = !!is_on;
1851
1852 /*
1853 * Per databook, when we want to stop the gadget, if a control transfer
1854 * is still in process, complete it and get the core into setup phase.
1855 */
1856 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1857 reinit_completion(&dwc->ep0_in_setup);
1858
1859 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1860 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1861 if (ret == 0) {
1862 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1863 return -ETIMEDOUT;
1864 }
1865 }
1866
1867 spin_lock_irqsave(&dwc->lock, flags);
1868 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1869 spin_unlock_irqrestore(&dwc->lock, flags);
1870
1871 return ret;
1872}
1873
1874static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1875{
1876 u32 reg;
1877
1878 /* Enable all but Start and End of Frame IRQs */
1879 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1880 DWC3_DEVTEN_EVNTOVERFLOWEN |
1881 DWC3_DEVTEN_CMDCMPLTEN |
1882 DWC3_DEVTEN_ERRTICERREN |
1883 DWC3_DEVTEN_WKUPEVTEN |
1884 DWC3_DEVTEN_CONNECTDONEEN |
1885 DWC3_DEVTEN_USBRSTEN |
1886 DWC3_DEVTEN_DISCONNEVTEN);
1887
1888 if (dwc->revision < DWC3_REVISION_250A)
1889 reg |= DWC3_DEVTEN_ULSTCNGEN;
1890
1891 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1892}
1893
1894static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1895{
1896 /* mask all interrupts */
1897 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1898}
1899
1900static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1901static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1902
1903/**
1904 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1905 * @dwc: pointer to our context structure
1906 *
1907 * The following looks like complex but it's actually very simple. In order to
1908 * calculate the number of packets we can burst at once on OUT transfers, we're
1909 * gonna use RxFIFO size.
1910 *
1911 * To calculate RxFIFO size we need two numbers:
1912 * MDWIDTH = size, in bits, of the internal memory bus
1913 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1914 *
1915 * Given these two numbers, the formula is simple:
1916 *
1917 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1918 *
1919 * 24 bytes is for 3x SETUP packets
1920 * 16 bytes is a clock domain crossing tolerance
1921 *
1922 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1923 */
1924static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1925{
1926 u32 ram2_depth;
1927 u32 mdwidth;
1928 u32 nump;
1929 u32 reg;
1930
1931 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1932 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1933
1934 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1935 nump = min_t(u32, nump, 16);
1936
1937 /* update NumP */
1938 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1939 reg &= ~DWC3_DCFG_NUMP_MASK;
1940 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1941 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1942}
1943
1944static int __dwc3_gadget_start(struct dwc3 *dwc)
1945{
1946 struct dwc3_ep *dep;
1947 int ret = 0;
1948 u32 reg;
1949
1950 /*
1951 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1952 * the core supports IMOD, disable it.
1953 */
1954 if (dwc->imod_interval) {
1955 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1956 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1957 } else if (dwc3_has_imod(dwc)) {
1958 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1959 }
1960
1961 /*
1962 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1963 * field instead of letting dwc3 itself calculate that automatically.
1964 *
1965 * This way, we maximize the chances that we'll be able to get several
1966 * bursts of data without going through any sort of endpoint throttling.
1967 */
1968 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1969 if (dwc3_is_usb31(dwc))
1970 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1971 else
1972 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1973
1974 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1975
1976 dwc3_gadget_setup_nump(dwc);
1977
1978 /* Start with SuperSpeed Default */
1979 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1980
1981 dep = dwc->eps[0];
1982 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1983 if (ret) {
1984 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1985 goto err0;
1986 }
1987
1988 dep = dwc->eps[1];
1989 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1990 if (ret) {
1991 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1992 goto err1;
1993 }
1994
1995 /* begin to receive SETUP packets */
1996 dwc->ep0state = EP0_SETUP_PHASE;
1997 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1998 dwc3_ep0_out_start(dwc);
1999
2000 dwc3_gadget_enable_irq(dwc);
2001
2002 return 0;
2003
2004err1:
2005 __dwc3_gadget_ep_disable(dwc->eps[0]);
2006
2007err0:
2008 return ret;
2009}
2010
2011static int dwc3_gadget_start(struct usb_gadget *g,
2012 struct usb_gadget_driver *driver)
2013{
2014 struct dwc3 *dwc = gadget_to_dwc(g);
2015 unsigned long flags;
2016 int ret = 0;
2017 int irq;
2018
2019 irq = dwc->irq_gadget;
2020 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2021 IRQF_SHARED, "dwc3", dwc->ev_buf);
2022 if (ret) {
2023 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2024 irq, ret);
2025 goto err0;
2026 }
2027
2028 spin_lock_irqsave(&dwc->lock, flags);
2029 if (dwc->gadget_driver) {
2030 dev_err(dwc->dev, "%s is already bound to %s\n",
2031 dwc->gadget.name,
2032 dwc->gadget_driver->driver.name);
2033 ret = -EBUSY;
2034 goto err1;
2035 }
2036
2037 dwc->gadget_driver = driver;
2038
2039 if (pm_runtime_active(dwc->dev))
2040 __dwc3_gadget_start(dwc);
2041
2042 spin_unlock_irqrestore(&dwc->lock, flags);
2043
2044 return 0;
2045
2046err1:
2047 spin_unlock_irqrestore(&dwc->lock, flags);
2048 free_irq(irq, dwc);
2049
2050err0:
2051 return ret;
2052}
2053
2054static void __dwc3_gadget_stop(struct dwc3 *dwc)
2055{
2056 dwc3_gadget_disable_irq(dwc);
2057 __dwc3_gadget_ep_disable(dwc->eps[0]);
2058 __dwc3_gadget_ep_disable(dwc->eps[1]);
2059}
2060
2061static int dwc3_gadget_stop(struct usb_gadget *g)
2062{
2063 struct dwc3 *dwc = gadget_to_dwc(g);
2064 unsigned long flags;
2065
2066 spin_lock_irqsave(&dwc->lock, flags);
2067
2068 if (pm_runtime_suspended(dwc->dev))
2069 goto out;
2070
2071 __dwc3_gadget_stop(dwc);
2072
2073out:
2074 dwc->gadget_driver = NULL;
2075 spin_unlock_irqrestore(&dwc->lock, flags);
2076
2077 free_irq(dwc->irq_gadget, dwc->ev_buf);
2078
2079 return 0;
2080}
2081
2082static void dwc3_gadget_config_params(struct usb_gadget *g,
2083 struct usb_dcd_config_params *params)
2084{
2085 struct dwc3 *dwc = gadget_to_dwc(g);
2086
2087 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2088 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2089
2090 /* Recommended BESL */
2091 if (!dwc->dis_enblslpm_quirk) {
2092 /*
2093 * If the recommended BESL baseline is 0 or if the BESL deep is
2094 * less than 2, Microsoft's Windows 10 host usb stack will issue
2095 * a usb reset immediately after it receives the extended BOS
2096 * descriptor and the enumeration will fail. To maintain
2097 * compatibility with the Windows' usb stack, let's set the
2098 * recommended BESL baseline to 1 and clamp the BESL deep to be
2099 * within 2 to 15.
2100 */
2101 params->besl_baseline = 1;
2102 if (dwc->is_utmi_l1_suspend)
2103 params->besl_deep =
2104 clamp_t(u8, dwc->hird_threshold, 2, 15);
2105 }
2106
2107 /* U1 Device exit Latency */
2108 if (dwc->dis_u1_entry_quirk)
2109 params->bU1devExitLat = 0;
2110 else
2111 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2112
2113 /* U2 Device exit Latency */
2114 if (dwc->dis_u2_entry_quirk)
2115 params->bU2DevExitLat = 0;
2116 else
2117 params->bU2DevExitLat =
2118 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2119}
2120
2121static void dwc3_gadget_set_speed(struct usb_gadget *g,
2122 enum usb_device_speed speed)
2123{
2124 struct dwc3 *dwc = gadget_to_dwc(g);
2125 unsigned long flags;
2126 u32 reg;
2127
2128 spin_lock_irqsave(&dwc->lock, flags);
2129 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2130 reg &= ~(DWC3_DCFG_SPEED_MASK);
2131
2132 /*
2133 * WORKAROUND: DWC3 revision < 2.20a have an issue
2134 * which would cause metastability state on Run/Stop
2135 * bit if we try to force the IP to USB2-only mode.
2136 *
2137 * Because of that, we cannot configure the IP to any
2138 * speed other than the SuperSpeed
2139 *
2140 * Refers to:
2141 *
2142 * STAR#9000525659: Clock Domain Crossing on DCTL in
2143 * USB 2.0 Mode
2144 */
2145 if (dwc->revision < DWC3_REVISION_220A &&
2146 !dwc->dis_metastability_quirk) {
2147 reg |= DWC3_DCFG_SUPERSPEED;
2148 } else {
2149 switch (speed) {
2150 case USB_SPEED_LOW:
2151 reg |= DWC3_DCFG_LOWSPEED;
2152 break;
2153 case USB_SPEED_FULL:
2154 reg |= DWC3_DCFG_FULLSPEED;
2155 break;
2156 case USB_SPEED_HIGH:
2157 reg |= DWC3_DCFG_HIGHSPEED;
2158 break;
2159 case USB_SPEED_SUPER:
2160 reg |= DWC3_DCFG_SUPERSPEED;
2161 break;
2162 case USB_SPEED_SUPER_PLUS:
2163 if (dwc3_is_usb31(dwc))
2164 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2165 else
2166 reg |= DWC3_DCFG_SUPERSPEED;
2167 break;
2168 default:
2169 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2170
2171 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2172 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2173 else
2174 reg |= DWC3_DCFG_SUPERSPEED;
2175 }
2176 }
2177 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2178
2179 spin_unlock_irqrestore(&dwc->lock, flags);
2180}
2181
2182static const struct usb_gadget_ops dwc3_gadget_ops = {
2183 .get_frame = dwc3_gadget_get_frame,
2184 .wakeup = dwc3_gadget_wakeup,
2185 .set_selfpowered = dwc3_gadget_set_selfpowered,
2186 .pullup = dwc3_gadget_pullup,
2187 .udc_start = dwc3_gadget_start,
2188 .udc_stop = dwc3_gadget_stop,
2189 .udc_set_speed = dwc3_gadget_set_speed,
2190 .get_config_params = dwc3_gadget_config_params,
2191};
2192
2193/* -------------------------------------------------------------------------- */
2194
2195static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2196{
2197 struct dwc3 *dwc = dep->dwc;
2198
2199 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2200 dep->endpoint.maxburst = 1;
2201 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2202 if (!dep->direction)
2203 dwc->gadget.ep0 = &dep->endpoint;
2204
2205 dep->endpoint.caps.type_control = true;
2206
2207 return 0;
2208}
2209
2210static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2211{
2212 struct dwc3 *dwc = dep->dwc;
2213 int mdwidth;
2214 int kbytes;
2215 int size;
2216
2217 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2218 /* MDWIDTH is represented in bits, we need it in bytes */
2219 mdwidth /= 8;
2220
2221 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2222 if (dwc3_is_usb31(dwc))
2223 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2224 else
2225 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2226
2227 /* FIFO Depth is in MDWDITH bytes. Multiply */
2228 size *= mdwidth;
2229
2230 kbytes = size / 1024;
2231 if (kbytes == 0)
2232 kbytes = 1;
2233
2234 /*
2235 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2236 * internal overhead. We don't really know how these are used,
2237 * but documentation say it exists.
2238 */
2239 size -= mdwidth * (kbytes + 1);
2240 size /= kbytes;
2241
2242 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2243
2244 dep->endpoint.max_streams = 15;
2245 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2246 list_add_tail(&dep->endpoint.ep_list,
2247 &dwc->gadget.ep_list);
2248 dep->endpoint.caps.type_iso = true;
2249 dep->endpoint.caps.type_bulk = true;
2250 dep->endpoint.caps.type_int = true;
2251
2252 return dwc3_alloc_trb_pool(dep);
2253}
2254
2255static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2256{
2257 struct dwc3 *dwc = dep->dwc;
2258
2259 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2260 dep->endpoint.max_streams = 15;
2261 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2262 list_add_tail(&dep->endpoint.ep_list,
2263 &dwc->gadget.ep_list);
2264 dep->endpoint.caps.type_iso = true;
2265 dep->endpoint.caps.type_bulk = true;
2266 dep->endpoint.caps.type_int = true;
2267
2268 return dwc3_alloc_trb_pool(dep);
2269}
2270
2271static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2272{
2273 struct dwc3_ep *dep;
2274 bool direction = epnum & 1;
2275 int ret;
2276 u8 num = epnum >> 1;
2277
2278 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2279 if (!dep)
2280 return -ENOMEM;
2281
2282 dep->dwc = dwc;
2283 dep->number = epnum;
2284 dep->direction = direction;
2285 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2286 dwc->eps[epnum] = dep;
2287 dep->combo_num = 0;
2288 dep->start_cmd_status = 0;
2289
2290 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2291 direction ? "in" : "out");
2292
2293 dep->endpoint.name = dep->name;
2294
2295 if (!(dep->number > 1)) {
2296 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2297 dep->endpoint.comp_desc = NULL;
2298 }
2299
2300 if (num == 0)
2301 ret = dwc3_gadget_init_control_endpoint(dep);
2302 else if (direction)
2303 ret = dwc3_gadget_init_in_endpoint(dep);
2304 else
2305 ret = dwc3_gadget_init_out_endpoint(dep);
2306
2307 if (ret)
2308 return ret;
2309
2310 dep->endpoint.caps.dir_in = direction;
2311 dep->endpoint.caps.dir_out = !direction;
2312
2313 INIT_LIST_HEAD(&dep->pending_list);
2314 INIT_LIST_HEAD(&dep->started_list);
2315 INIT_LIST_HEAD(&dep->cancelled_list);
2316
2317 return 0;
2318}
2319
2320static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2321{
2322 u8 epnum;
2323
2324 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2325
2326 for (epnum = 0; epnum < total; epnum++) {
2327 int ret;
2328
2329 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2330 if (ret)
2331 return ret;
2332 }
2333
2334 return 0;
2335}
2336
2337static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2338{
2339 struct dwc3_ep *dep;
2340 u8 epnum;
2341
2342 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2343 dep = dwc->eps[epnum];
2344 if (!dep)
2345 continue;
2346 /*
2347 * Physical endpoints 0 and 1 are special; they form the
2348 * bi-directional USB endpoint 0.
2349 *
2350 * For those two physical endpoints, we don't allocate a TRB
2351 * pool nor do we add them the endpoints list. Due to that, we
2352 * shouldn't do these two operations otherwise we would end up
2353 * with all sorts of bugs when removing dwc3.ko.
2354 */
2355 if (epnum != 0 && epnum != 1) {
2356 dwc3_free_trb_pool(dep);
2357 list_del(&dep->endpoint.ep_list);
2358 }
2359
2360 kfree(dep);
2361 }
2362}
2363
2364/* -------------------------------------------------------------------------- */
2365
2366static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2367 struct dwc3_request *req, struct dwc3_trb *trb,
2368 const struct dwc3_event_depevt *event, int status, int chain)
2369{
2370 unsigned int count;
2371
2372 dwc3_ep_inc_deq(dep);
2373
2374 trace_dwc3_complete_trb(dep, trb);
2375 req->num_trbs--;
2376
2377 /*
2378 * If we're in the middle of series of chained TRBs and we
2379 * receive a short transfer along the way, DWC3 will skip
2380 * through all TRBs including the last TRB in the chain (the
2381 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2382 * bit and SW has to do it manually.
2383 *
2384 * We're going to do that here to avoid problems of HW trying
2385 * to use bogus TRBs for transfers.
2386 */
2387 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2388 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2389
2390 /*
2391 * For isochronous transfers, the first TRB in a service interval must
2392 * have the Isoc-First type. Track and report its interval frame number.
2393 */
2394 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2395 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2396 unsigned int frame_number;
2397
2398 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2399 frame_number &= ~(dep->interval - 1);
2400 req->request.frame_number = frame_number;
2401 }
2402
2403 /*
2404 * If we're dealing with unaligned size OUT transfer, we will be left
2405 * with one TRB pending in the ring. We need to manually clear HWO bit
2406 * from that TRB.
2407 */
2408
2409 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2410 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2411 return 1;
2412 }
2413
2414 count = trb->size & DWC3_TRB_SIZE_MASK;
2415 req->remaining += count;
2416
2417 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2418 return 1;
2419
2420 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2421 return 1;
2422
2423 if (event->status & DEPEVT_STATUS_IOC)
2424 return 1;
2425
2426 return 0;
2427}
2428
2429static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2430 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2431 int status)
2432{
2433 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2434 struct scatterlist *sg = req->sg;
2435 struct scatterlist *s;
2436 unsigned int pending = req->num_pending_sgs;
2437 unsigned int i;
2438 int ret = 0;
2439
2440 for_each_sg(sg, s, pending, i) {
2441 trb = &dep->trb_pool[dep->trb_dequeue];
2442
2443 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2444 break;
2445
2446 req->sg = sg_next(s);
2447 req->num_pending_sgs--;
2448
2449 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2450 trb, event, status, true);
2451 if (ret)
2452 break;
2453 }
2454
2455 return ret;
2456}
2457
2458static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2459 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2460 int status)
2461{
2462 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2463
2464 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2465 event, status, false);
2466}
2467
2468static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2469{
2470 return req->request.actual == req->request.length;
2471}
2472
2473static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2474 const struct dwc3_event_depevt *event,
2475 struct dwc3_request *req, int status)
2476{
2477 int ret;
2478
2479 if (req->num_pending_sgs)
2480 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2481 status);
2482 else
2483 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2484 status);
2485
2486 if (req->needs_extra_trb) {
2487 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2488 status);
2489 req->needs_extra_trb = false;
2490 }
2491
2492 req->request.actual = req->request.length - req->remaining;
2493
2494 if (!dwc3_gadget_ep_request_completed(req) &&
2495 req->num_pending_sgs) {
2496 __dwc3_gadget_kick_transfer(dep);
2497 goto out;
2498 }
2499
2500 dwc3_gadget_giveback(dep, req, status);
2501
2502out:
2503 return ret;
2504}
2505
2506static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2507 const struct dwc3_event_depevt *event, int status)
2508{
2509 struct dwc3_request *req;
2510 struct dwc3_request *tmp;
2511
2512 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2513 int ret;
2514
2515 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2516 req, status);
2517 if (ret)
2518 break;
2519 }
2520}
2521
2522static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2523 const struct dwc3_event_depevt *event)
2524{
2525 dep->frame_number = event->parameters;
2526}
2527
2528static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2529 const struct dwc3_event_depevt *event)
2530{
2531 struct dwc3 *dwc = dep->dwc;
2532 unsigned status = 0;
2533 bool stop = false;
2534
2535 dwc3_gadget_endpoint_frame_from_event(dep, event);
2536
2537 if (event->status & DEPEVT_STATUS_BUSERR)
2538 status = -ECONNRESET;
2539
2540 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2541 status = -EXDEV;
2542
2543 if (list_empty(&dep->started_list))
2544 stop = true;
2545 }
2546
2547 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2548
2549 if (stop) {
2550 dwc3_stop_active_transfer(dep, true, true);
2551 dep->flags = DWC3_EP_ENABLED;
2552 }
2553
2554 /*
2555 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2556 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2557 */
2558 if (dwc->revision < DWC3_REVISION_183A) {
2559 u32 reg;
2560 int i;
2561
2562 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2563 dep = dwc->eps[i];
2564
2565 if (!(dep->flags & DWC3_EP_ENABLED))
2566 continue;
2567
2568 if (!list_empty(&dep->started_list))
2569 return;
2570 }
2571
2572 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2573 reg |= dwc->u1u2;
2574 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2575
2576 dwc->u1u2 = 0;
2577 }
2578}
2579
2580static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2581 const struct dwc3_event_depevt *event)
2582{
2583 dwc3_gadget_endpoint_frame_from_event(dep, event);
2584 (void) __dwc3_gadget_start_isoc(dep);
2585}
2586
2587static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2588 const struct dwc3_event_depevt *event)
2589{
2590 struct dwc3_ep *dep;
2591 u8 epnum = event->endpoint_number;
2592 u8 cmd;
2593
2594 dep = dwc->eps[epnum];
2595
2596 if (!(dep->flags & DWC3_EP_ENABLED)) {
2597 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2598 return;
2599
2600 /* Handle only EPCMDCMPLT when EP disabled */
2601 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2602 return;
2603 }
2604
2605 if (epnum == 0 || epnum == 1) {
2606 dwc3_ep0_interrupt(dwc, event);
2607 return;
2608 }
2609
2610 switch (event->endpoint_event) {
2611 case DWC3_DEPEVT_XFERINPROGRESS:
2612 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2613 break;
2614 case DWC3_DEPEVT_XFERNOTREADY:
2615 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2616 break;
2617 case DWC3_DEPEVT_EPCMDCMPLT:
2618 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2619
2620 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2621 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2622 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2623 }
2624 break;
2625 case DWC3_DEPEVT_STREAMEVT:
2626 case DWC3_DEPEVT_XFERCOMPLETE:
2627 case DWC3_DEPEVT_RXTXFIFOEVT:
2628 break;
2629 }
2630}
2631
2632static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2633{
2634 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2635 spin_unlock(&dwc->lock);
2636 dwc->gadget_driver->disconnect(&dwc->gadget);
2637 spin_lock(&dwc->lock);
2638 }
2639}
2640
2641static void dwc3_suspend_gadget(struct dwc3 *dwc)
2642{
2643 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2644 spin_unlock(&dwc->lock);
2645 dwc->gadget_driver->suspend(&dwc->gadget);
2646 spin_lock(&dwc->lock);
2647 }
2648}
2649
2650static void dwc3_resume_gadget(struct dwc3 *dwc)
2651{
2652 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2653 spin_unlock(&dwc->lock);
2654 dwc->gadget_driver->resume(&dwc->gadget);
2655 spin_lock(&dwc->lock);
2656 }
2657}
2658
2659static void dwc3_reset_gadget(struct dwc3 *dwc)
2660{
2661 if (!dwc->gadget_driver)
2662 return;
2663
2664 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2665 spin_unlock(&dwc->lock);
2666 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2667 spin_lock(&dwc->lock);
2668 }
2669}
2670
2671static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2672 bool interrupt)
2673{
2674 struct dwc3 *dwc = dep->dwc;
2675 struct dwc3_gadget_ep_cmd_params params;
2676 u32 cmd;
2677 int ret;
2678
2679 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2680 return;
2681
2682 /*
2683 * NOTICE: We are violating what the Databook says about the
2684 * EndTransfer command. Ideally we would _always_ wait for the
2685 * EndTransfer Command Completion IRQ, but that's causing too
2686 * much trouble synchronizing between us and gadget driver.
2687 *
2688 * We have discussed this with the IP Provider and it was
2689 * suggested to giveback all requests here, but give HW some
2690 * extra time to synchronize with the interconnect. We're using
2691 * an arbitrary 100us delay for that.
2692 *
2693 * Note also that a similar handling was tested by Synopsys
2694 * (thanks a lot Paul) and nothing bad has come out of it.
2695 * In short, what we're doing is:
2696 *
2697 * - Issue EndTransfer WITH CMDIOC bit set
2698 * - Wait 100us
2699 *
2700 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2701 * supports a mode to work around the above limitation. The
2702 * software can poll the CMDACT bit in the DEPCMD register
2703 * after issuing a EndTransfer command. This mode is enabled
2704 * by writing GUCTL2[14]. This polling is already done in the
2705 * dwc3_send_gadget_ep_cmd() function so if the mode is
2706 * enabled, the EndTransfer command will have completed upon
2707 * returning from this function and we don't need to delay for
2708 * 100us.
2709 *
2710 * This mode is NOT available on the DWC_usb31 IP.
2711 */
2712
2713 cmd = DWC3_DEPCMD_ENDTRANSFER;
2714 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2715 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
2716 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2717 memset(¶ms, 0, sizeof(params));
2718 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2719 WARN_ON_ONCE(ret);
2720 dep->resource_index = 0;
2721
2722 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2723 udelay(100);
2724}
2725
2726static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2727{
2728 u32 epnum;
2729
2730 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2731 struct dwc3_ep *dep;
2732 int ret;
2733
2734 dep = dwc->eps[epnum];
2735 if (!dep)
2736 continue;
2737
2738 if (!(dep->flags & DWC3_EP_STALL))
2739 continue;
2740
2741 dep->flags &= ~DWC3_EP_STALL;
2742
2743 ret = dwc3_send_clear_stall_ep_cmd(dep);
2744 WARN_ON_ONCE(ret);
2745 }
2746}
2747
2748static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2749{
2750 int reg;
2751
2752 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2753 reg &= ~DWC3_DCTL_INITU1ENA;
2754 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2755
2756 reg &= ~DWC3_DCTL_INITU2ENA;
2757 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2758
2759 dwc3_disconnect_gadget(dwc);
2760
2761 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2762 dwc->setup_packet_pending = false;
2763 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2764
2765 dwc->connected = false;
2766}
2767
2768static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2769{
2770 u32 reg;
2771
2772 dwc->connected = true;
2773
2774 /*
2775 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2776 * would cause a missing Disconnect Event if there's a
2777 * pending Setup Packet in the FIFO.
2778 *
2779 * There's no suggested workaround on the official Bug
2780 * report, which states that "unless the driver/application
2781 * is doing any special handling of a disconnect event,
2782 * there is no functional issue".
2783 *
2784 * Unfortunately, it turns out that we _do_ some special
2785 * handling of a disconnect event, namely complete all
2786 * pending transfers, notify gadget driver of the
2787 * disconnection, and so on.
2788 *
2789 * Our suggested workaround is to follow the Disconnect
2790 * Event steps here, instead, based on a setup_packet_pending
2791 * flag. Such flag gets set whenever we have a SETUP_PENDING
2792 * status for EP0 TRBs and gets cleared on XferComplete for the
2793 * same endpoint.
2794 *
2795 * Refers to:
2796 *
2797 * STAR#9000466709: RTL: Device : Disconnect event not
2798 * generated if setup packet pending in FIFO
2799 */
2800 if (dwc->revision < DWC3_REVISION_188A) {
2801 if (dwc->setup_packet_pending)
2802 dwc3_gadget_disconnect_interrupt(dwc);
2803 }
2804
2805 dwc3_reset_gadget(dwc);
2806
2807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2808 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2809 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2810 dwc->test_mode = false;
2811 dwc3_clear_stall_all_ep(dwc);
2812
2813 /* Reset device address to zero */
2814 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2815 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2816 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2817}
2818
2819static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2820{
2821 struct dwc3_ep *dep;
2822 int ret;
2823 u32 reg;
2824 u8 speed;
2825
2826 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2827 speed = reg & DWC3_DSTS_CONNECTSPD;
2828 dwc->speed = speed;
2829
2830 /*
2831 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2832 * each time on Connect Done.
2833 *
2834 * Currently we always use the reset value. If any platform
2835 * wants to set this to a different value, we need to add a
2836 * setting and update GCTL.RAMCLKSEL here.
2837 */
2838
2839 switch (speed) {
2840 case DWC3_DSTS_SUPERSPEED_PLUS:
2841 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2842 dwc->gadget.ep0->maxpacket = 512;
2843 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2844 break;
2845 case DWC3_DSTS_SUPERSPEED:
2846 /*
2847 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2848 * would cause a missing USB3 Reset event.
2849 *
2850 * In such situations, we should force a USB3 Reset
2851 * event by calling our dwc3_gadget_reset_interrupt()
2852 * routine.
2853 *
2854 * Refers to:
2855 *
2856 * STAR#9000483510: RTL: SS : USB3 reset event may
2857 * not be generated always when the link enters poll
2858 */
2859 if (dwc->revision < DWC3_REVISION_190A)
2860 dwc3_gadget_reset_interrupt(dwc);
2861
2862 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2863 dwc->gadget.ep0->maxpacket = 512;
2864 dwc->gadget.speed = USB_SPEED_SUPER;
2865 break;
2866 case DWC3_DSTS_HIGHSPEED:
2867 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2868 dwc->gadget.ep0->maxpacket = 64;
2869 dwc->gadget.speed = USB_SPEED_HIGH;
2870 break;
2871 case DWC3_DSTS_FULLSPEED:
2872 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2873 dwc->gadget.ep0->maxpacket = 64;
2874 dwc->gadget.speed = USB_SPEED_FULL;
2875 break;
2876 case DWC3_DSTS_LOWSPEED:
2877 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2878 dwc->gadget.ep0->maxpacket = 8;
2879 dwc->gadget.speed = USB_SPEED_LOW;
2880 break;
2881 }
2882
2883 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2884
2885 /* Enable USB2 LPM Capability */
2886
2887 if ((dwc->revision > DWC3_REVISION_194A) &&
2888 (speed != DWC3_DSTS_SUPERSPEED) &&
2889 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2890 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2891 reg |= DWC3_DCFG_LPM_CAP;
2892 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2893
2894 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2895 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2896
2897 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
2898 (dwc->is_utmi_l1_suspend << 4));
2899
2900 /*
2901 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2902 * DCFG.LPMCap is set, core responses with an ACK and the
2903 * BESL value in the LPM token is less than or equal to LPM
2904 * NYET threshold.
2905 */
2906 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2907 && dwc->has_lpm_erratum,
2908 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2909
2910 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2911 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
2912
2913 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2914 } else {
2915 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2916 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2917 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2918 }
2919
2920 dep = dwc->eps[0];
2921 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2922 if (ret) {
2923 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2924 return;
2925 }
2926
2927 dep = dwc->eps[1];
2928 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2929 if (ret) {
2930 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2931 return;
2932 }
2933
2934 /*
2935 * Configure PHY via GUSB3PIPECTLn if required.
2936 *
2937 * Update GTXFIFOSIZn
2938 *
2939 * In both cases reset values should be sufficient.
2940 */
2941}
2942
2943static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2944{
2945 /*
2946 * TODO take core out of low power mode when that's
2947 * implemented.
2948 */
2949
2950 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2951 spin_unlock(&dwc->lock);
2952 dwc->gadget_driver->resume(&dwc->gadget);
2953 spin_lock(&dwc->lock);
2954 }
2955}
2956
2957static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2958 unsigned int evtinfo)
2959{
2960 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2961 unsigned int pwropt;
2962
2963 /*
2964 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2965 * Hibernation mode enabled which would show up when device detects
2966 * host-initiated U3 exit.
2967 *
2968 * In that case, device will generate a Link State Change Interrupt
2969 * from U3 to RESUME which is only necessary if Hibernation is
2970 * configured in.
2971 *
2972 * There are no functional changes due to such spurious event and we
2973 * just need to ignore it.
2974 *
2975 * Refers to:
2976 *
2977 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2978 * operational mode
2979 */
2980 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2981 if ((dwc->revision < DWC3_REVISION_250A) &&
2982 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2983 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2984 (next == DWC3_LINK_STATE_RESUME)) {
2985 return;
2986 }
2987 }
2988
2989 /*
2990 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2991 * on the link partner, the USB session might do multiple entry/exit
2992 * of low power states before a transfer takes place.
2993 *
2994 * Due to this problem, we might experience lower throughput. The
2995 * suggested workaround is to disable DCTL[12:9] bits if we're
2996 * transitioning from U1/U2 to U0 and enable those bits again
2997 * after a transfer completes and there are no pending transfers
2998 * on any of the enabled endpoints.
2999 *
3000 * This is the first half of that workaround.
3001 *
3002 * Refers to:
3003 *
3004 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3005 * core send LGO_Ux entering U0
3006 */
3007 if (dwc->revision < DWC3_REVISION_183A) {
3008 if (next == DWC3_LINK_STATE_U0) {
3009 u32 u1u2;
3010 u32 reg;
3011
3012 switch (dwc->link_state) {
3013 case DWC3_LINK_STATE_U1:
3014 case DWC3_LINK_STATE_U2:
3015 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3016 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3017 | DWC3_DCTL_ACCEPTU2ENA
3018 | DWC3_DCTL_INITU1ENA
3019 | DWC3_DCTL_ACCEPTU1ENA);
3020
3021 if (!dwc->u1u2)
3022 dwc->u1u2 = reg & u1u2;
3023
3024 reg &= ~u1u2;
3025
3026 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3027 break;
3028 default:
3029 /* do nothing */
3030 break;
3031 }
3032 }
3033 }
3034
3035 switch (next) {
3036 case DWC3_LINK_STATE_U1:
3037 if (dwc->speed == USB_SPEED_SUPER)
3038 dwc3_suspend_gadget(dwc);
3039 break;
3040 case DWC3_LINK_STATE_U2:
3041 case DWC3_LINK_STATE_U3:
3042 dwc3_suspend_gadget(dwc);
3043 break;
3044 case DWC3_LINK_STATE_RESUME:
3045 dwc3_resume_gadget(dwc);
3046 break;
3047 default:
3048 /* do nothing */
3049 break;
3050 }
3051
3052 dwc->link_state = next;
3053}
3054
3055static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3056 unsigned int evtinfo)
3057{
3058 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3059
3060 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3061 dwc3_suspend_gadget(dwc);
3062
3063 dwc->link_state = next;
3064}
3065
3066static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3067 unsigned int evtinfo)
3068{
3069 unsigned int is_ss = evtinfo & BIT(4);
3070
3071 /*
3072 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3073 * have a known issue which can cause USB CV TD.9.23 to fail
3074 * randomly.
3075 *
3076 * Because of this issue, core could generate bogus hibernation
3077 * events which SW needs to ignore.
3078 *
3079 * Refers to:
3080 *
3081 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3082 * Device Fallback from SuperSpeed
3083 */
3084 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3085 return;
3086
3087 /* enter hibernation here */
3088}
3089
3090static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3091 const struct dwc3_event_devt *event)
3092{
3093 switch (event->type) {
3094 case DWC3_DEVICE_EVENT_DISCONNECT:
3095 dwc3_gadget_disconnect_interrupt(dwc);
3096 break;
3097 case DWC3_DEVICE_EVENT_RESET:
3098 dwc3_gadget_reset_interrupt(dwc);
3099 break;
3100 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3101 dwc3_gadget_conndone_interrupt(dwc);
3102 break;
3103 case DWC3_DEVICE_EVENT_WAKEUP:
3104 dwc3_gadget_wakeup_interrupt(dwc);
3105 break;
3106 case DWC3_DEVICE_EVENT_HIBER_REQ:
3107 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3108 "unexpected hibernation event\n"))
3109 break;
3110
3111 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3112 break;
3113 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3114 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3115 break;
3116 case DWC3_DEVICE_EVENT_EOPF:
3117 /* It changed to be suspend event for version 2.30a and above */
3118 if (dwc->revision >= DWC3_REVISION_230A) {
3119 /*
3120 * Ignore suspend event until the gadget enters into
3121 * USB_STATE_CONFIGURED state.
3122 */
3123 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3124 dwc3_gadget_suspend_interrupt(dwc,
3125 event->event_info);
3126 }
3127 break;
3128 case DWC3_DEVICE_EVENT_SOF:
3129 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3130 case DWC3_DEVICE_EVENT_CMD_CMPL:
3131 case DWC3_DEVICE_EVENT_OVERFLOW:
3132 break;
3133 default:
3134 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3135 }
3136}
3137
3138static void dwc3_process_event_entry(struct dwc3 *dwc,
3139 const union dwc3_event *event)
3140{
3141 trace_dwc3_event(event->raw, dwc);
3142
3143 if (!event->type.is_devspec)
3144 dwc3_endpoint_interrupt(dwc, &event->depevt);
3145 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3146 dwc3_gadget_interrupt(dwc, &event->devt);
3147 else
3148 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3149}
3150
3151static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3152{
3153 struct dwc3 *dwc = evt->dwc;
3154 irqreturn_t ret = IRQ_NONE;
3155 int left;
3156 u32 reg;
3157
3158 left = evt->count;
3159
3160 if (!(evt->flags & DWC3_EVENT_PENDING))
3161 return IRQ_NONE;
3162
3163 while (left > 0) {
3164 union dwc3_event event;
3165
3166 event.raw = *(u32 *) (evt->cache + evt->lpos);
3167
3168 dwc3_process_event_entry(dwc, &event);
3169
3170 /*
3171 * FIXME we wrap around correctly to the next entry as
3172 * almost all entries are 4 bytes in size. There is one
3173 * entry which has 12 bytes which is a regular entry
3174 * followed by 8 bytes data. ATM I don't know how
3175 * things are organized if we get next to the a
3176 * boundary so I worry about that once we try to handle
3177 * that.
3178 */
3179 evt->lpos = (evt->lpos + 4) % evt->length;
3180 left -= 4;
3181 }
3182
3183 evt->count = 0;
3184 evt->flags &= ~DWC3_EVENT_PENDING;
3185 ret = IRQ_HANDLED;
3186
3187 /* Unmask interrupt */
3188 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3189 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3190 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3191
3192 if (dwc->imod_interval) {
3193 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3194 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3195 }
3196
3197 return ret;
3198}
3199
3200static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3201{
3202 struct dwc3_event_buffer *evt = _evt;
3203 struct dwc3 *dwc = evt->dwc;
3204 unsigned long flags;
3205 irqreturn_t ret = IRQ_NONE;
3206
3207 spin_lock_irqsave(&dwc->lock, flags);
3208 ret = dwc3_process_event_buf(evt);
3209 spin_unlock_irqrestore(&dwc->lock, flags);
3210
3211 return ret;
3212}
3213
3214static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3215{
3216 struct dwc3 *dwc = evt->dwc;
3217 u32 amount;
3218 u32 count;
3219 u32 reg;
3220
3221 if (pm_runtime_suspended(dwc->dev)) {
3222 pm_runtime_get(dwc->dev);
3223 disable_irq_nosync(dwc->irq_gadget);
3224 dwc->pending_events = true;
3225 return IRQ_HANDLED;
3226 }
3227
3228 /*
3229 * With PCIe legacy interrupt, test shows that top-half irq handler can
3230 * be called again after HW interrupt deassertion. Check if bottom-half
3231 * irq event handler completes before caching new event to prevent
3232 * losing events.
3233 */
3234 if (evt->flags & DWC3_EVENT_PENDING)
3235 return IRQ_HANDLED;
3236
3237 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3238 count &= DWC3_GEVNTCOUNT_MASK;
3239 if (!count)
3240 return IRQ_NONE;
3241
3242 evt->count = count;
3243 evt->flags |= DWC3_EVENT_PENDING;
3244
3245 /* Mask interrupt */
3246 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3247 reg |= DWC3_GEVNTSIZ_INTMASK;
3248 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3249
3250 amount = min(count, evt->length - evt->lpos);
3251 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3252
3253 if (amount < count)
3254 memcpy(evt->cache, evt->buf, count - amount);
3255
3256 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3257
3258 return IRQ_WAKE_THREAD;
3259}
3260
3261static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3262{
3263 struct dwc3_event_buffer *evt = _evt;
3264
3265 return dwc3_check_event_buf(evt);
3266}
3267
3268static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3269{
3270 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3271 int irq;
3272
3273 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3274 if (irq > 0)
3275 goto out;
3276
3277 if (irq == -EPROBE_DEFER)
3278 goto out;
3279
3280 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3281 if (irq > 0)
3282 goto out;
3283
3284 if (irq == -EPROBE_DEFER)
3285 goto out;
3286
3287 irq = platform_get_irq(dwc3_pdev, 0);
3288 if (irq > 0)
3289 goto out;
3290
3291 if (!irq)
3292 irq = -EINVAL;
3293
3294out:
3295 return irq;
3296}
3297
3298/**
3299 * dwc3_gadget_init - initializes gadget related registers
3300 * @dwc: pointer to our controller context structure
3301 *
3302 * Returns 0 on success otherwise negative errno.
3303 */
3304int dwc3_gadget_init(struct dwc3 *dwc)
3305{
3306 int ret;
3307 int irq;
3308
3309 irq = dwc3_gadget_get_irq(dwc);
3310 if (irq < 0) {
3311 ret = irq;
3312 goto err0;
3313 }
3314
3315 dwc->irq_gadget = irq;
3316
3317 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3318 sizeof(*dwc->ep0_trb) * 2,
3319 &dwc->ep0_trb_addr, GFP_KERNEL);
3320 if (!dwc->ep0_trb) {
3321 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3322 ret = -ENOMEM;
3323 goto err0;
3324 }
3325
3326 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3327 if (!dwc->setup_buf) {
3328 ret = -ENOMEM;
3329 goto err1;
3330 }
3331
3332 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3333 &dwc->bounce_addr, GFP_KERNEL);
3334 if (!dwc->bounce) {
3335 ret = -ENOMEM;
3336 goto err2;
3337 }
3338
3339 init_completion(&dwc->ep0_in_setup);
3340
3341 dwc->gadget.ops = &dwc3_gadget_ops;
3342 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3343 dwc->gadget.sg_supported = true;
3344 dwc->gadget.name = "dwc3-gadget";
3345 dwc->gadget.lpm_capable = true;
3346
3347 /*
3348 * FIXME We might be setting max_speed to <SUPER, however versions
3349 * <2.20a of dwc3 have an issue with metastability (documented
3350 * elsewhere in this driver) which tells us we can't set max speed to
3351 * anything lower than SUPER.
3352 *
3353 * Because gadget.max_speed is only used by composite.c and function
3354 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3355 * to happen so we avoid sending SuperSpeed Capability descriptor
3356 * together with our BOS descriptor as that could confuse host into
3357 * thinking we can handle super speed.
3358 *
3359 * Note that, in fact, we won't even support GetBOS requests when speed
3360 * is less than super speed because we don't have means, yet, to tell
3361 * composite.c that we are USB 2.0 + LPM ECN.
3362 */
3363 if (dwc->revision < DWC3_REVISION_220A &&
3364 !dwc->dis_metastability_quirk)
3365 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3366 dwc->revision);
3367
3368 dwc->gadget.max_speed = dwc->maximum_speed;
3369
3370 /*
3371 * REVISIT: Here we should clear all pending IRQs to be
3372 * sure we're starting from a well known location.
3373 */
3374
3375 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3376 if (ret)
3377 goto err3;
3378
3379 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3380 if (ret) {
3381 dev_err(dwc->dev, "failed to register udc\n");
3382 goto err4;
3383 }
3384
3385 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3386
3387 return 0;
3388
3389err4:
3390 dwc3_gadget_free_endpoints(dwc);
3391
3392err3:
3393 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3394 dwc->bounce_addr);
3395
3396err2:
3397 kfree(dwc->setup_buf);
3398
3399err1:
3400 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3401 dwc->ep0_trb, dwc->ep0_trb_addr);
3402
3403err0:
3404 return ret;
3405}
3406
3407/* -------------------------------------------------------------------------- */
3408
3409void dwc3_gadget_exit(struct dwc3 *dwc)
3410{
3411 usb_del_gadget_udc(&dwc->gadget);
3412 dwc3_gadget_free_endpoints(dwc);
3413 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3414 dwc->bounce_addr);
3415 kfree(dwc->setup_buf);
3416 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3417 dwc->ep0_trb, dwc->ep0_trb_addr);
3418}
3419
3420int dwc3_gadget_suspend(struct dwc3 *dwc)
3421{
3422 if (!dwc->gadget_driver)
3423 return 0;
3424
3425 dwc3_gadget_run_stop(dwc, false, false);
3426 dwc3_disconnect_gadget(dwc);
3427 __dwc3_gadget_stop(dwc);
3428
3429 return 0;
3430}
3431
3432int dwc3_gadget_resume(struct dwc3 *dwc)
3433{
3434 int ret;
3435
3436 if (!dwc->gadget_driver)
3437 return 0;
3438
3439 ret = __dwc3_gadget_start(dwc);
3440 if (ret < 0)
3441 goto err0;
3442
3443 ret = dwc3_gadget_run_stop(dwc, true, false);
3444 if (ret < 0)
3445 goto err1;
3446
3447 return 0;
3448
3449err1:
3450 __dwc3_gadget_stop(dwc);
3451
3452err0:
3453 return ret;
3454}
3455
3456void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3457{
3458 if (dwc->pending_events) {
3459 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3460 dwc->pending_events = false;
3461 enable_irq(dwc->irq_gadget);
3462 }
3463}
1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
100 int retries = 10000;
101 u32 reg;
102
103 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
104 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
105
106 /* set requested state */
107 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
108 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
109
110 /* wait for a change in DSTS */
111 while (--retries) {
112 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
113
114 if (DWC3_DSTS_USBLNKST(reg) == state)
115 return 0;
116
117 udelay(5);
118 }
119
120 dev_vdbg(dwc->dev, "link state change request timed out\n");
121
122 return -ETIMEDOUT;
123}
124
125/**
126 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
127 * @dwc: pointer to our context structure
128 *
129 * This function will a best effort FIFO allocation in order
130 * to improve FIFO usage and throughput, while still allowing
131 * us to enable as many endpoints as possible.
132 *
133 * Keep in mind that this operation will be highly dependent
134 * on the configured size for RAM1 - which contains TxFifo -,
135 * the amount of endpoints enabled on coreConsultant tool, and
136 * the width of the Master Bus.
137 *
138 * In the ideal world, we would always be able to satisfy the
139 * following equation:
140 *
141 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
142 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
143 *
144 * Unfortunately, due to many variables that's not always the case.
145 */
146int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
147{
148 int last_fifo_depth = 0;
149 int ram1_depth;
150 int fifo_size;
151 int mdwidth;
152 int num;
153
154 if (!dwc->needs_fifo_resize)
155 return 0;
156
157 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
158 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
159
160 /* MDWIDTH is represented in bits, we need it in bytes */
161 mdwidth >>= 3;
162
163 /*
164 * FIXME For now we will only allocate 1 wMaxPacketSize space
165 * for each enabled endpoint, later patches will come to
166 * improve this algorithm so that we better use the internal
167 * FIFO space
168 */
169 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
170 struct dwc3_ep *dep = dwc->eps[num];
171 int fifo_number = dep->number >> 1;
172 int mult = 1;
173 int tmp;
174
175 if (!(dep->number & 1))
176 continue;
177
178 if (!(dep->flags & DWC3_EP_ENABLED))
179 continue;
180
181 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
182 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
183 mult = 3;
184
185 /*
186 * REVISIT: the following assumes we will always have enough
187 * space available on the FIFO RAM for all possible use cases.
188 * Make sure that's true somehow and change FIFO allocation
189 * accordingly.
190 *
191 * If we have Bulk or Isochronous endpoints, we want
192 * them to be able to be very, very fast. So we're giving
193 * those endpoints a fifo_size which is enough for 3 full
194 * packets
195 */
196 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
197 tmp += mdwidth;
198
199 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
200
201 fifo_size |= (last_fifo_depth << 16);
202
203 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
204 dep->name, last_fifo_depth, fifo_size & 0xffff);
205
206 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
207 fifo_size);
208
209 last_fifo_depth += (fifo_size & 0xffff);
210 }
211
212 return 0;
213}
214
215void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
216 int status)
217{
218 struct dwc3 *dwc = dep->dwc;
219
220 if (req->queued) {
221 if (req->request.num_mapped_sgs)
222 dep->busy_slot += req->request.num_mapped_sgs;
223 else
224 dep->busy_slot++;
225
226 /*
227 * Skip LINK TRB. We can't use req->trb and check for
228 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
229 * completed (not the LINK TRB).
230 */
231 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
232 usb_endpoint_xfer_isoc(dep->endpoint.desc))
233 dep->busy_slot++;
234 }
235 list_del(&req->list);
236 req->trb = NULL;
237
238 if (req->request.status == -EINPROGRESS)
239 req->request.status = status;
240
241 if (dwc->ep0_bounced && dep->number == 0)
242 dwc->ep0_bounced = false;
243 else
244 usb_gadget_unmap_request(&dwc->gadget, &req->request,
245 req->direction);
246
247 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
248 req, dep->name, req->request.actual,
249 req->request.length, status);
250
251 spin_unlock(&dwc->lock);
252 req->request.complete(&dep->endpoint, &req->request);
253 spin_lock(&dwc->lock);
254}
255
256static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
257{
258 switch (cmd) {
259 case DWC3_DEPCMD_DEPSTARTCFG:
260 return "Start New Configuration";
261 case DWC3_DEPCMD_ENDTRANSFER:
262 return "End Transfer";
263 case DWC3_DEPCMD_UPDATETRANSFER:
264 return "Update Transfer";
265 case DWC3_DEPCMD_STARTTRANSFER:
266 return "Start Transfer";
267 case DWC3_DEPCMD_CLEARSTALL:
268 return "Clear Stall";
269 case DWC3_DEPCMD_SETSTALL:
270 return "Set Stall";
271 case DWC3_DEPCMD_GETSEQNUMBER:
272 return "Get Data Sequence Number";
273 case DWC3_DEPCMD_SETTRANSFRESOURCE:
274 return "Set Endpoint Transfer Resource";
275 case DWC3_DEPCMD_SETEPCONFIG:
276 return "Set Endpoint Configuration";
277 default:
278 return "UNKNOWN command";
279 }
280}
281
282int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
283{
284 u32 timeout = 500;
285 u32 reg;
286
287 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
288 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
289
290 do {
291 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
292 if (!(reg & DWC3_DGCMD_CMDACT)) {
293 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
294 DWC3_DGCMD_STATUS(reg));
295 return 0;
296 }
297
298 /*
299 * We can't sleep here, because it's also called from
300 * interrupt context.
301 */
302 timeout--;
303 if (!timeout)
304 return -ETIMEDOUT;
305 udelay(1);
306 } while (1);
307}
308
309int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
310 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
311{
312 struct dwc3_ep *dep = dwc->eps[ep];
313 u32 timeout = 500;
314 u32 reg;
315
316 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
317 dep->name,
318 dwc3_gadget_ep_cmd_string(cmd), params->param0,
319 params->param1, params->param2);
320
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
322 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
323 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
324
325 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
326 do {
327 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
328 if (!(reg & DWC3_DEPCMD_CMDACT)) {
329 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
330 DWC3_DEPCMD_STATUS(reg));
331 return 0;
332 }
333
334 /*
335 * We can't sleep here, because it is also called from
336 * interrupt context.
337 */
338 timeout--;
339 if (!timeout)
340 return -ETIMEDOUT;
341
342 udelay(1);
343 } while (1);
344}
345
346static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
347 struct dwc3_trb *trb)
348{
349 u32 offset = (char *) trb - (char *) dep->trb_pool;
350
351 return dep->trb_pool_dma + offset;
352}
353
354static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
355{
356 struct dwc3 *dwc = dep->dwc;
357
358 if (dep->trb_pool)
359 return 0;
360
361 if (dep->number == 0 || dep->number == 1)
362 return 0;
363
364 dep->trb_pool = dma_alloc_coherent(dwc->dev,
365 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
366 &dep->trb_pool_dma, GFP_KERNEL);
367 if (!dep->trb_pool) {
368 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
369 dep->name);
370 return -ENOMEM;
371 }
372
373 return 0;
374}
375
376static void dwc3_free_trb_pool(struct dwc3_ep *dep)
377{
378 struct dwc3 *dwc = dep->dwc;
379
380 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
381 dep->trb_pool, dep->trb_pool_dma);
382
383 dep->trb_pool = NULL;
384 dep->trb_pool_dma = 0;
385}
386
387static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
388{
389 struct dwc3_gadget_ep_cmd_params params;
390 u32 cmd;
391
392 memset(¶ms, 0x00, sizeof(params));
393
394 if (dep->number != 1) {
395 cmd = DWC3_DEPCMD_DEPSTARTCFG;
396 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
397 if (dep->number > 1) {
398 if (dwc->start_config_issued)
399 return 0;
400 dwc->start_config_issued = true;
401 cmd |= DWC3_DEPCMD_PARAM(2);
402 }
403
404 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
405 }
406
407 return 0;
408}
409
410static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
411 const struct usb_endpoint_descriptor *desc,
412 const struct usb_ss_ep_comp_descriptor *comp_desc)
413{
414 struct dwc3_gadget_ep_cmd_params params;
415
416 memset(¶ms, 0x00, sizeof(params));
417
418 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
419 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
420 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
421
422 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
423 | DWC3_DEPCFG_XFER_NOT_READY_EN;
424
425 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
426 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
427 | DWC3_DEPCFG_STREAM_EVENT_EN;
428 dep->stream_capable = true;
429 }
430
431 if (usb_endpoint_xfer_isoc(desc))
432 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
433
434 /*
435 * We are doing 1:1 mapping for endpoints, meaning
436 * Physical Endpoints 2 maps to Logical Endpoint 2 and
437 * so on. We consider the direction bit as part of the physical
438 * endpoint number. So USB endpoint 0x81 is 0x03.
439 */
440 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
441
442 /*
443 * We must use the lower 16 TX FIFOs even though
444 * HW might have more
445 */
446 if (dep->direction)
447 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
448
449 if (desc->bInterval) {
450 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
451 dep->interval = 1 << (desc->bInterval - 1);
452 }
453
454 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
455 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
456}
457
458static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
459{
460 struct dwc3_gadget_ep_cmd_params params;
461
462 memset(¶ms, 0x00, sizeof(params));
463
464 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
465
466 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
467 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
468}
469
470/**
471 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
472 * @dep: endpoint to be initialized
473 * @desc: USB Endpoint Descriptor
474 *
475 * Caller should take care of locking
476 */
477static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
478 const struct usb_endpoint_descriptor *desc,
479 const struct usb_ss_ep_comp_descriptor *comp_desc)
480{
481 struct dwc3 *dwc = dep->dwc;
482 u32 reg;
483 int ret = -ENOMEM;
484
485 if (!(dep->flags & DWC3_EP_ENABLED)) {
486 ret = dwc3_gadget_start_config(dwc, dep);
487 if (ret)
488 return ret;
489 }
490
491 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
492 if (ret)
493 return ret;
494
495 if (!(dep->flags & DWC3_EP_ENABLED)) {
496 struct dwc3_trb *trb_st_hw;
497 struct dwc3_trb *trb_link;
498
499 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
500 if (ret)
501 return ret;
502
503 dep->endpoint.desc = desc;
504 dep->comp_desc = comp_desc;
505 dep->type = usb_endpoint_type(desc);
506 dep->flags |= DWC3_EP_ENABLED;
507
508 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
509 reg |= DWC3_DALEPENA_EP(dep->number);
510 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
511
512 if (!usb_endpoint_xfer_isoc(desc))
513 return 0;
514
515 memset(&trb_link, 0, sizeof(trb_link));
516
517 /* Link TRB for ISOC. The HWO bit is never reset */
518 trb_st_hw = &dep->trb_pool[0];
519
520 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
521
522 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
523 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
524 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
525 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
526 }
527
528 return 0;
529}
530
531static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
532static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
533{
534 struct dwc3_request *req;
535
536 if (!list_empty(&dep->req_queued))
537 dwc3_stop_active_transfer(dwc, dep->number);
538
539 while (!list_empty(&dep->request_list)) {
540 req = next_request(&dep->request_list);
541
542 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
543 }
544}
545
546/**
547 * __dwc3_gadget_ep_disable - Disables a HW endpoint
548 * @dep: the endpoint to disable
549 *
550 * This function also removes requests which are currently processed ny the
551 * hardware and those which are not yet scheduled.
552 * Caller should take care of locking.
553 */
554static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
555{
556 struct dwc3 *dwc = dep->dwc;
557 u32 reg;
558
559 dwc3_remove_requests(dwc, dep);
560
561 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
562 reg &= ~DWC3_DALEPENA_EP(dep->number);
563 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
564
565 dep->stream_capable = false;
566 dep->endpoint.desc = NULL;
567 dep->comp_desc = NULL;
568 dep->type = 0;
569 dep->flags = 0;
570
571 return 0;
572}
573
574/* -------------------------------------------------------------------------- */
575
576static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
577 const struct usb_endpoint_descriptor *desc)
578{
579 return -EINVAL;
580}
581
582static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
583{
584 return -EINVAL;
585}
586
587/* -------------------------------------------------------------------------- */
588
589static int dwc3_gadget_ep_enable(struct usb_ep *ep,
590 const struct usb_endpoint_descriptor *desc)
591{
592 struct dwc3_ep *dep;
593 struct dwc3 *dwc;
594 unsigned long flags;
595 int ret;
596
597 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
598 pr_debug("dwc3: invalid parameters\n");
599 return -EINVAL;
600 }
601
602 if (!desc->wMaxPacketSize) {
603 pr_debug("dwc3: missing wMaxPacketSize\n");
604 return -EINVAL;
605 }
606
607 dep = to_dwc3_ep(ep);
608 dwc = dep->dwc;
609
610 switch (usb_endpoint_type(desc)) {
611 case USB_ENDPOINT_XFER_CONTROL:
612 strlcat(dep->name, "-control", sizeof(dep->name));
613 break;
614 case USB_ENDPOINT_XFER_ISOC:
615 strlcat(dep->name, "-isoc", sizeof(dep->name));
616 break;
617 case USB_ENDPOINT_XFER_BULK:
618 strlcat(dep->name, "-bulk", sizeof(dep->name));
619 break;
620 case USB_ENDPOINT_XFER_INT:
621 strlcat(dep->name, "-int", sizeof(dep->name));
622 break;
623 default:
624 dev_err(dwc->dev, "invalid endpoint transfer type\n");
625 }
626
627 if (dep->flags & DWC3_EP_ENABLED) {
628 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
629 dep->name);
630 return 0;
631 }
632
633 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
634
635 spin_lock_irqsave(&dwc->lock, flags);
636 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
637 spin_unlock_irqrestore(&dwc->lock, flags);
638
639 return ret;
640}
641
642static int dwc3_gadget_ep_disable(struct usb_ep *ep)
643{
644 struct dwc3_ep *dep;
645 struct dwc3 *dwc;
646 unsigned long flags;
647 int ret;
648
649 if (!ep) {
650 pr_debug("dwc3: invalid parameters\n");
651 return -EINVAL;
652 }
653
654 dep = to_dwc3_ep(ep);
655 dwc = dep->dwc;
656
657 if (!(dep->flags & DWC3_EP_ENABLED)) {
658 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
659 dep->name);
660 return 0;
661 }
662
663 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
664 dep->number >> 1,
665 (dep->number & 1) ? "in" : "out");
666
667 spin_lock_irqsave(&dwc->lock, flags);
668 ret = __dwc3_gadget_ep_disable(dep);
669 spin_unlock_irqrestore(&dwc->lock, flags);
670
671 return ret;
672}
673
674static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
675 gfp_t gfp_flags)
676{
677 struct dwc3_request *req;
678 struct dwc3_ep *dep = to_dwc3_ep(ep);
679 struct dwc3 *dwc = dep->dwc;
680
681 req = kzalloc(sizeof(*req), gfp_flags);
682 if (!req) {
683 dev_err(dwc->dev, "not enough memory\n");
684 return NULL;
685 }
686
687 req->epnum = dep->number;
688 req->dep = dep;
689
690 return &req->request;
691}
692
693static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
694 struct usb_request *request)
695{
696 struct dwc3_request *req = to_dwc3_request(request);
697
698 kfree(req);
699}
700
701/**
702 * dwc3_prepare_one_trb - setup one TRB from one request
703 * @dep: endpoint for which this request is prepared
704 * @req: dwc3_request pointer
705 */
706static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
707 struct dwc3_request *req, dma_addr_t dma,
708 unsigned length, unsigned last, unsigned chain)
709{
710 struct dwc3 *dwc = dep->dwc;
711 struct dwc3_trb *trb;
712
713 unsigned int cur_slot;
714
715 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
716 dep->name, req, (unsigned long long) dma,
717 length, last ? " last" : "",
718 chain ? " chain" : "");
719
720 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
721 cur_slot = dep->free_slot;
722 dep->free_slot++;
723
724 /* Skip the LINK-TRB on ISOC */
725 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
726 usb_endpoint_xfer_isoc(dep->endpoint.desc))
727 return;
728
729 if (!req->trb) {
730 dwc3_gadget_move_request_queued(req);
731 req->trb = trb;
732 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
733 }
734
735 trb->size = DWC3_TRB_SIZE_LENGTH(length);
736 trb->bpl = lower_32_bits(dma);
737 trb->bph = upper_32_bits(dma);
738
739 switch (usb_endpoint_type(dep->endpoint.desc)) {
740 case USB_ENDPOINT_XFER_CONTROL:
741 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
742 break;
743
744 case USB_ENDPOINT_XFER_ISOC:
745 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
746
747 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
748 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
749 trb->ctrl |= DWC3_TRB_CTRL_IOC;
750 break;
751
752 case USB_ENDPOINT_XFER_BULK:
753 case USB_ENDPOINT_XFER_INT:
754 trb->ctrl = DWC3_TRBCTL_NORMAL;
755 break;
756 default:
757 /*
758 * This is only possible with faulty memory because we
759 * checked it already :)
760 */
761 BUG();
762 }
763
764 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
765 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
766 trb->ctrl |= DWC3_TRB_CTRL_CSP;
767 } else {
768 if (chain)
769 trb->ctrl |= DWC3_TRB_CTRL_CHN;
770
771 if (last)
772 trb->ctrl |= DWC3_TRB_CTRL_LST;
773 }
774
775 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
776 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
777
778 trb->ctrl |= DWC3_TRB_CTRL_HWO;
779}
780
781/*
782 * dwc3_prepare_trbs - setup TRBs from requests
783 * @dep: endpoint for which requests are being prepared
784 * @starting: true if the endpoint is idle and no requests are queued.
785 *
786 * The function goes through the requests list and sets up TRBs for the
787 * transfers. The function returns once there are no more TRBs available or
788 * it runs out of requests.
789 */
790static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
791{
792 struct dwc3_request *req, *n;
793 u32 trbs_left;
794 u32 max;
795 unsigned int last_one = 0;
796
797 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
798
799 /* the first request must not be queued */
800 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
801
802 /* Can't wrap around on a non-isoc EP since there's no link TRB */
803 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
804 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
805 if (trbs_left > max)
806 trbs_left = max;
807 }
808
809 /*
810 * If busy & slot are equal than it is either full or empty. If we are
811 * starting to process requests then we are empty. Otherwise we are
812 * full and don't do anything
813 */
814 if (!trbs_left) {
815 if (!starting)
816 return;
817 trbs_left = DWC3_TRB_NUM;
818 /*
819 * In case we start from scratch, we queue the ISOC requests
820 * starting from slot 1. This is done because we use ring
821 * buffer and have no LST bit to stop us. Instead, we place
822 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
823 * after the first request so we start at slot 1 and have
824 * 7 requests proceed before we hit the first IOC.
825 * Other transfer types don't use the ring buffer and are
826 * processed from the first TRB until the last one. Since we
827 * don't wrap around we have to start at the beginning.
828 */
829 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
830 dep->busy_slot = 1;
831 dep->free_slot = 1;
832 } else {
833 dep->busy_slot = 0;
834 dep->free_slot = 0;
835 }
836 }
837
838 /* The last TRB is a link TRB, not used for xfer */
839 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
840 return;
841
842 list_for_each_entry_safe(req, n, &dep->request_list, list) {
843 unsigned length;
844 dma_addr_t dma;
845
846 if (req->request.num_mapped_sgs > 0) {
847 struct usb_request *request = &req->request;
848 struct scatterlist *sg = request->sg;
849 struct scatterlist *s;
850 int i;
851
852 for_each_sg(sg, s, request->num_mapped_sgs, i) {
853 unsigned chain = true;
854
855 length = sg_dma_len(s);
856 dma = sg_dma_address(s);
857
858 if (i == (request->num_mapped_sgs - 1) ||
859 sg_is_last(s)) {
860 last_one = true;
861 chain = false;
862 }
863
864 trbs_left--;
865 if (!trbs_left)
866 last_one = true;
867
868 if (last_one)
869 chain = false;
870
871 dwc3_prepare_one_trb(dep, req, dma, length,
872 last_one, chain);
873
874 if (last_one)
875 break;
876 }
877 } else {
878 dma = req->request.dma;
879 length = req->request.length;
880 trbs_left--;
881
882 if (!trbs_left)
883 last_one = 1;
884
885 /* Is this the last request? */
886 if (list_is_last(&req->list, &dep->request_list))
887 last_one = 1;
888
889 dwc3_prepare_one_trb(dep, req, dma, length,
890 last_one, false);
891
892 if (last_one)
893 break;
894 }
895 }
896}
897
898static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
899 int start_new)
900{
901 struct dwc3_gadget_ep_cmd_params params;
902 struct dwc3_request *req;
903 struct dwc3 *dwc = dep->dwc;
904 int ret;
905 u32 cmd;
906
907 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
908 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
909 return -EBUSY;
910 }
911 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
912
913 /*
914 * If we are getting here after a short-out-packet we don't enqueue any
915 * new requests as we try to set the IOC bit only on the last request.
916 */
917 if (start_new) {
918 if (list_empty(&dep->req_queued))
919 dwc3_prepare_trbs(dep, start_new);
920
921 /* req points to the first request which will be sent */
922 req = next_request(&dep->req_queued);
923 } else {
924 dwc3_prepare_trbs(dep, start_new);
925
926 /*
927 * req points to the first request where HWO changed from 0 to 1
928 */
929 req = next_request(&dep->req_queued);
930 }
931 if (!req) {
932 dep->flags |= DWC3_EP_PENDING_REQUEST;
933 return 0;
934 }
935
936 memset(¶ms, 0, sizeof(params));
937 params.param0 = upper_32_bits(req->trb_dma);
938 params.param1 = lower_32_bits(req->trb_dma);
939
940 if (start_new)
941 cmd = DWC3_DEPCMD_STARTTRANSFER;
942 else
943 cmd = DWC3_DEPCMD_UPDATETRANSFER;
944
945 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
946 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
947 if (ret < 0) {
948 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
949
950 /*
951 * FIXME we need to iterate over the list of requests
952 * here and stop, unmap, free and del each of the linked
953 * requests instead of what we do now.
954 */
955 usb_gadget_unmap_request(&dwc->gadget, &req->request,
956 req->direction);
957 list_del(&req->list);
958 return ret;
959 }
960
961 dep->flags |= DWC3_EP_BUSY;
962
963 if (start_new) {
964 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
965 dep->number);
966 WARN_ON_ONCE(!dep->res_trans_idx);
967 }
968
969 return 0;
970}
971
972static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
973{
974 struct dwc3 *dwc = dep->dwc;
975 int ret;
976
977 req->request.actual = 0;
978 req->request.status = -EINPROGRESS;
979 req->direction = dep->direction;
980 req->epnum = dep->number;
981
982 /*
983 * We only add to our list of requests now and
984 * start consuming the list once we get XferNotReady
985 * IRQ.
986 *
987 * That way, we avoid doing anything that we don't need
988 * to do now and defer it until the point we receive a
989 * particular token from the Host side.
990 *
991 * This will also avoid Host cancelling URBs due to too
992 * many NAKs.
993 */
994 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
995 dep->direction);
996 if (ret)
997 return ret;
998
999 list_add_tail(&req->list, &dep->request_list);
1000
1001 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY))
1002 dep->flags |= DWC3_EP_PENDING_REQUEST;
1003
1004 /*
1005 * There are two special cases:
1006 *
1007 * 1. XferNotReady with empty list of requests. We need to kick the
1008 * transfer here in that situation, otherwise we will be NAKing
1009 * forever. If we get XferNotReady before gadget driver has a
1010 * chance to queue a request, we will ACK the IRQ but won't be
1011 * able to receive the data until the next request is queued.
1012 * The following code is handling exactly that.
1013 *
1014 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1015 * kick the transfer here after queuing a request, otherwise the
1016 * core may not see the modified TRB(s).
1017 */
1018 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1019 int ret;
1020 int start_trans = 1;
1021 u8 trans_idx = dep->res_trans_idx;
1022
1023 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1024 (dep->flags & DWC3_EP_BUSY)) {
1025 start_trans = 0;
1026 WARN_ON_ONCE(!trans_idx);
1027 } else {
1028 trans_idx = 0;
1029 }
1030
1031 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
1032 if (ret && ret != -EBUSY) {
1033 struct dwc3 *dwc = dep->dwc;
1034
1035 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1036 dep->name);
1037 }
1038 };
1039
1040 return 0;
1041}
1042
1043static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1044 gfp_t gfp_flags)
1045{
1046 struct dwc3_request *req = to_dwc3_request(request);
1047 struct dwc3_ep *dep = to_dwc3_ep(ep);
1048 struct dwc3 *dwc = dep->dwc;
1049
1050 unsigned long flags;
1051
1052 int ret;
1053
1054 if (!dep->endpoint.desc) {
1055 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1056 request, ep->name);
1057 return -ESHUTDOWN;
1058 }
1059
1060 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1061 request, ep->name, request->length);
1062
1063 spin_lock_irqsave(&dwc->lock, flags);
1064 ret = __dwc3_gadget_ep_queue(dep, req);
1065 spin_unlock_irqrestore(&dwc->lock, flags);
1066
1067 return ret;
1068}
1069
1070static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1071 struct usb_request *request)
1072{
1073 struct dwc3_request *req = to_dwc3_request(request);
1074 struct dwc3_request *r = NULL;
1075
1076 struct dwc3_ep *dep = to_dwc3_ep(ep);
1077 struct dwc3 *dwc = dep->dwc;
1078
1079 unsigned long flags;
1080 int ret = 0;
1081
1082 spin_lock_irqsave(&dwc->lock, flags);
1083
1084 list_for_each_entry(r, &dep->request_list, list) {
1085 if (r == req)
1086 break;
1087 }
1088
1089 if (r != req) {
1090 list_for_each_entry(r, &dep->req_queued, list) {
1091 if (r == req)
1092 break;
1093 }
1094 if (r == req) {
1095 /* wait until it is processed */
1096 dwc3_stop_active_transfer(dwc, dep->number);
1097 goto out1;
1098 }
1099 dev_err(dwc->dev, "request %p was not queued to %s\n",
1100 request, ep->name);
1101 ret = -EINVAL;
1102 goto out0;
1103 }
1104
1105out1:
1106 /* giveback the request */
1107 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1108
1109out0:
1110 spin_unlock_irqrestore(&dwc->lock, flags);
1111
1112 return ret;
1113}
1114
1115int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1116{
1117 struct dwc3_gadget_ep_cmd_params params;
1118 struct dwc3 *dwc = dep->dwc;
1119 int ret;
1120
1121 memset(¶ms, 0x00, sizeof(params));
1122
1123 if (value) {
1124 if (dep->number == 0 || dep->number == 1) {
1125 /*
1126 * Whenever EP0 is stalled, we will restart
1127 * the state machine, thus moving back to
1128 * Setup Phase
1129 */
1130 dwc->ep0state = EP0_SETUP_PHASE;
1131 }
1132
1133 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1134 DWC3_DEPCMD_SETSTALL, ¶ms);
1135 if (ret)
1136 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1137 value ? "set" : "clear",
1138 dep->name);
1139 else
1140 dep->flags |= DWC3_EP_STALL;
1141 } else {
1142 if (dep->flags & DWC3_EP_WEDGE)
1143 return 0;
1144
1145 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1146 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1147 if (ret)
1148 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1149 value ? "set" : "clear",
1150 dep->name);
1151 else
1152 dep->flags &= ~DWC3_EP_STALL;
1153 }
1154
1155 return ret;
1156}
1157
1158static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1159{
1160 struct dwc3_ep *dep = to_dwc3_ep(ep);
1161 struct dwc3 *dwc = dep->dwc;
1162
1163 unsigned long flags;
1164
1165 int ret;
1166
1167 spin_lock_irqsave(&dwc->lock, flags);
1168
1169 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1170 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1171 ret = -EINVAL;
1172 goto out;
1173 }
1174
1175 ret = __dwc3_gadget_ep_set_halt(dep, value);
1176out:
1177 spin_unlock_irqrestore(&dwc->lock, flags);
1178
1179 return ret;
1180}
1181
1182static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1183{
1184 struct dwc3_ep *dep = to_dwc3_ep(ep);
1185 struct dwc3 *dwc = dep->dwc;
1186 unsigned long flags;
1187
1188 spin_lock_irqsave(&dwc->lock, flags);
1189 dep->flags |= DWC3_EP_WEDGE;
1190 spin_unlock_irqrestore(&dwc->lock, flags);
1191
1192 return dwc3_gadget_ep_set_halt(ep, 1);
1193}
1194
1195/* -------------------------------------------------------------------------- */
1196
1197static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1198 .bLength = USB_DT_ENDPOINT_SIZE,
1199 .bDescriptorType = USB_DT_ENDPOINT,
1200 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1201};
1202
1203static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1204 .enable = dwc3_gadget_ep0_enable,
1205 .disable = dwc3_gadget_ep0_disable,
1206 .alloc_request = dwc3_gadget_ep_alloc_request,
1207 .free_request = dwc3_gadget_ep_free_request,
1208 .queue = dwc3_gadget_ep0_queue,
1209 .dequeue = dwc3_gadget_ep_dequeue,
1210 .set_halt = dwc3_gadget_ep_set_halt,
1211 .set_wedge = dwc3_gadget_ep_set_wedge,
1212};
1213
1214static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1215 .enable = dwc3_gadget_ep_enable,
1216 .disable = dwc3_gadget_ep_disable,
1217 .alloc_request = dwc3_gadget_ep_alloc_request,
1218 .free_request = dwc3_gadget_ep_free_request,
1219 .queue = dwc3_gadget_ep_queue,
1220 .dequeue = dwc3_gadget_ep_dequeue,
1221 .set_halt = dwc3_gadget_ep_set_halt,
1222 .set_wedge = dwc3_gadget_ep_set_wedge,
1223};
1224
1225/* -------------------------------------------------------------------------- */
1226
1227static int dwc3_gadget_get_frame(struct usb_gadget *g)
1228{
1229 struct dwc3 *dwc = gadget_to_dwc(g);
1230 u32 reg;
1231
1232 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1233 return DWC3_DSTS_SOFFN(reg);
1234}
1235
1236static int dwc3_gadget_wakeup(struct usb_gadget *g)
1237{
1238 struct dwc3 *dwc = gadget_to_dwc(g);
1239
1240 unsigned long timeout;
1241 unsigned long flags;
1242
1243 u32 reg;
1244
1245 int ret = 0;
1246
1247 u8 link_state;
1248 u8 speed;
1249
1250 spin_lock_irqsave(&dwc->lock, flags);
1251
1252 /*
1253 * According to the Databook Remote wakeup request should
1254 * be issued only when the device is in early suspend state.
1255 *
1256 * We can check that via USB Link State bits in DSTS register.
1257 */
1258 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1259
1260 speed = reg & DWC3_DSTS_CONNECTSPD;
1261 if (speed == DWC3_DSTS_SUPERSPEED) {
1262 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1263 ret = -EINVAL;
1264 goto out;
1265 }
1266
1267 link_state = DWC3_DSTS_USBLNKST(reg);
1268
1269 switch (link_state) {
1270 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1271 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1272 break;
1273 default:
1274 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1275 link_state);
1276 ret = -EINVAL;
1277 goto out;
1278 }
1279
1280 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1281 if (ret < 0) {
1282 dev_err(dwc->dev, "failed to put link in Recovery\n");
1283 goto out;
1284 }
1285
1286 /* write zeroes to Link Change Request */
1287 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1288 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1289
1290 /* poll until Link State changes to ON */
1291 timeout = jiffies + msecs_to_jiffies(100);
1292
1293 while (!time_after(jiffies, timeout)) {
1294 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1295
1296 /* in HS, means ON */
1297 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1298 break;
1299 }
1300
1301 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1302 dev_err(dwc->dev, "failed to send remote wakeup\n");
1303 ret = -EINVAL;
1304 }
1305
1306out:
1307 spin_unlock_irqrestore(&dwc->lock, flags);
1308
1309 return ret;
1310}
1311
1312static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1313 int is_selfpowered)
1314{
1315 struct dwc3 *dwc = gadget_to_dwc(g);
1316 unsigned long flags;
1317
1318 spin_lock_irqsave(&dwc->lock, flags);
1319 dwc->is_selfpowered = !!is_selfpowered;
1320 spin_unlock_irqrestore(&dwc->lock, flags);
1321
1322 return 0;
1323}
1324
1325static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1326{
1327 u32 reg;
1328 u32 timeout = 500;
1329
1330 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1331 if (is_on) {
1332 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1333 reg |= (DWC3_DCTL_RUN_STOP
1334 | DWC3_DCTL_TRGTULST_RX_DET);
1335 } else {
1336 reg &= ~DWC3_DCTL_RUN_STOP;
1337 }
1338
1339 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1340
1341 do {
1342 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1343 if (is_on) {
1344 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1345 break;
1346 } else {
1347 if (reg & DWC3_DSTS_DEVCTRLHLT)
1348 break;
1349 }
1350 timeout--;
1351 if (!timeout)
1352 break;
1353 udelay(1);
1354 } while (1);
1355
1356 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1357 dwc->gadget_driver
1358 ? dwc->gadget_driver->function : "no-function",
1359 is_on ? "connect" : "disconnect");
1360}
1361
1362static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1363{
1364 struct dwc3 *dwc = gadget_to_dwc(g);
1365 unsigned long flags;
1366
1367 is_on = !!is_on;
1368
1369 spin_lock_irqsave(&dwc->lock, flags);
1370 dwc3_gadget_run_stop(dwc, is_on);
1371 spin_unlock_irqrestore(&dwc->lock, flags);
1372
1373 return 0;
1374}
1375
1376static int dwc3_gadget_start(struct usb_gadget *g,
1377 struct usb_gadget_driver *driver)
1378{
1379 struct dwc3 *dwc = gadget_to_dwc(g);
1380 struct dwc3_ep *dep;
1381 unsigned long flags;
1382 int ret = 0;
1383 u32 reg;
1384
1385 spin_lock_irqsave(&dwc->lock, flags);
1386
1387 if (dwc->gadget_driver) {
1388 dev_err(dwc->dev, "%s is already bound to %s\n",
1389 dwc->gadget.name,
1390 dwc->gadget_driver->driver.name);
1391 ret = -EBUSY;
1392 goto err0;
1393 }
1394
1395 dwc->gadget_driver = driver;
1396 dwc->gadget.dev.driver = &driver->driver;
1397
1398 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1399 reg &= ~(DWC3_DCFG_SPEED_MASK);
1400
1401 /**
1402 * WORKAROUND: DWC3 revision < 2.20a have an issue
1403 * which would cause metastability state on Run/Stop
1404 * bit if we try to force the IP to USB2-only mode.
1405 *
1406 * Because of that, we cannot configure the IP to any
1407 * speed other than the SuperSpeed
1408 *
1409 * Refers to:
1410 *
1411 * STAR#9000525659: Clock Domain Crossing on DCTL in
1412 * USB 2.0 Mode
1413 */
1414 if (dwc->revision < DWC3_REVISION_220A)
1415 reg |= DWC3_DCFG_SUPERSPEED;
1416 else
1417 reg |= dwc->maximum_speed;
1418 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1419
1420 dwc->start_config_issued = false;
1421
1422 /* Start with SuperSpeed Default */
1423 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1424
1425 dep = dwc->eps[0];
1426 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1427 if (ret) {
1428 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1429 goto err0;
1430 }
1431
1432 dep = dwc->eps[1];
1433 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1434 if (ret) {
1435 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1436 goto err1;
1437 }
1438
1439 /* begin to receive SETUP packets */
1440 dwc->ep0state = EP0_SETUP_PHASE;
1441 dwc3_ep0_out_start(dwc);
1442
1443 spin_unlock_irqrestore(&dwc->lock, flags);
1444
1445 return 0;
1446
1447err1:
1448 __dwc3_gadget_ep_disable(dwc->eps[0]);
1449
1450err0:
1451 spin_unlock_irqrestore(&dwc->lock, flags);
1452
1453 return ret;
1454}
1455
1456static int dwc3_gadget_stop(struct usb_gadget *g,
1457 struct usb_gadget_driver *driver)
1458{
1459 struct dwc3 *dwc = gadget_to_dwc(g);
1460 unsigned long flags;
1461
1462 spin_lock_irqsave(&dwc->lock, flags);
1463
1464 __dwc3_gadget_ep_disable(dwc->eps[0]);
1465 __dwc3_gadget_ep_disable(dwc->eps[1]);
1466
1467 dwc->gadget_driver = NULL;
1468 dwc->gadget.dev.driver = NULL;
1469
1470 spin_unlock_irqrestore(&dwc->lock, flags);
1471
1472 return 0;
1473}
1474static const struct usb_gadget_ops dwc3_gadget_ops = {
1475 .get_frame = dwc3_gadget_get_frame,
1476 .wakeup = dwc3_gadget_wakeup,
1477 .set_selfpowered = dwc3_gadget_set_selfpowered,
1478 .pullup = dwc3_gadget_pullup,
1479 .udc_start = dwc3_gadget_start,
1480 .udc_stop = dwc3_gadget_stop,
1481};
1482
1483/* -------------------------------------------------------------------------- */
1484
1485static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1486{
1487 struct dwc3_ep *dep;
1488 u8 epnum;
1489
1490 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1491
1492 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1493 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1494 if (!dep) {
1495 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1496 epnum);
1497 return -ENOMEM;
1498 }
1499
1500 dep->dwc = dwc;
1501 dep->number = epnum;
1502 dwc->eps[epnum] = dep;
1503
1504 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1505 (epnum & 1) ? "in" : "out");
1506 dep->endpoint.name = dep->name;
1507 dep->direction = (epnum & 1);
1508
1509 if (epnum == 0 || epnum == 1) {
1510 dep->endpoint.maxpacket = 512;
1511 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1512 if (!epnum)
1513 dwc->gadget.ep0 = &dep->endpoint;
1514 } else {
1515 int ret;
1516
1517 dep->endpoint.maxpacket = 1024;
1518 dep->endpoint.max_streams = 15;
1519 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1520 list_add_tail(&dep->endpoint.ep_list,
1521 &dwc->gadget.ep_list);
1522
1523 ret = dwc3_alloc_trb_pool(dep);
1524 if (ret)
1525 return ret;
1526 }
1527
1528 INIT_LIST_HEAD(&dep->request_list);
1529 INIT_LIST_HEAD(&dep->req_queued);
1530 }
1531
1532 return 0;
1533}
1534
1535static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1536{
1537 struct dwc3_ep *dep;
1538 u8 epnum;
1539
1540 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1541 dep = dwc->eps[epnum];
1542 dwc3_free_trb_pool(dep);
1543
1544 if (epnum != 0 && epnum != 1)
1545 list_del(&dep->endpoint.ep_list);
1546
1547 kfree(dep);
1548 }
1549}
1550
1551static void dwc3_gadget_release(struct device *dev)
1552{
1553 dev_dbg(dev, "%s\n", __func__);
1554}
1555
1556/* -------------------------------------------------------------------------- */
1557static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1558 const struct dwc3_event_depevt *event, int status)
1559{
1560 struct dwc3_request *req;
1561 struct dwc3_trb *trb;
1562 unsigned int count;
1563 unsigned int s_pkt = 0;
1564
1565 do {
1566 req = next_request(&dep->req_queued);
1567 if (!req) {
1568 WARN_ON_ONCE(1);
1569 return 1;
1570 }
1571
1572 trb = req->trb;
1573
1574 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1575 /*
1576 * We continue despite the error. There is not much we
1577 * can do. If we don't clean it up we loop forever. If
1578 * we skip the TRB then it gets overwritten after a
1579 * while since we use them in a ring buffer. A BUG()
1580 * would help. Lets hope that if this occurs, someone
1581 * fixes the root cause instead of looking away :)
1582 */
1583 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1584 dep->name, req->trb);
1585 count = trb->size & DWC3_TRB_SIZE_MASK;
1586
1587 if (dep->direction) {
1588 if (count) {
1589 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1590 dep->name);
1591 status = -ECONNRESET;
1592 }
1593 } else {
1594 if (count && (event->status & DEPEVT_STATUS_SHORT))
1595 s_pkt = 1;
1596 }
1597
1598 /*
1599 * We assume here we will always receive the entire data block
1600 * which we should receive. Meaning, if we program RX to
1601 * receive 4K but we receive only 2K, we assume that's all we
1602 * should receive and we simply bounce the request back to the
1603 * gadget driver for further processing.
1604 */
1605 req->request.actual += req->request.length - count;
1606 dwc3_gadget_giveback(dep, req, status);
1607 if (s_pkt)
1608 break;
1609 if ((event->status & DEPEVT_STATUS_LST) &&
1610 (trb->ctrl & DWC3_TRB_CTRL_LST))
1611 break;
1612 if ((event->status & DEPEVT_STATUS_IOC) &&
1613 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1614 break;
1615 } while (1);
1616
1617 if ((event->status & DEPEVT_STATUS_IOC) &&
1618 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1619 return 0;
1620 return 1;
1621}
1622
1623static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1624 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1625 int start_new)
1626{
1627 unsigned status = 0;
1628 int clean_busy;
1629
1630 if (event->status & DEPEVT_STATUS_BUSERR)
1631 status = -ECONNRESET;
1632
1633 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1634 if (clean_busy)
1635 dep->flags &= ~DWC3_EP_BUSY;
1636
1637 /*
1638 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1639 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1640 */
1641 if (dwc->revision < DWC3_REVISION_183A) {
1642 u32 reg;
1643 int i;
1644
1645 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1646 struct dwc3_ep *dep = dwc->eps[i];
1647
1648 if (!(dep->flags & DWC3_EP_ENABLED))
1649 continue;
1650
1651 if (!list_empty(&dep->req_queued))
1652 return;
1653 }
1654
1655 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1656 reg |= dwc->u1u2;
1657 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1658
1659 dwc->u1u2 = 0;
1660 }
1661}
1662
1663static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1664 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1665{
1666 u32 uf, mask;
1667
1668 if (list_empty(&dep->request_list)) {
1669 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1670 dep->name);
1671 return;
1672 }
1673
1674 mask = ~(dep->interval - 1);
1675 uf = event->parameters & mask;
1676 /* 4 micro frames in the future */
1677 uf += dep->interval * 4;
1678
1679 __dwc3_gadget_kick_transfer(dep, uf, 1);
1680}
1681
1682static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1683 const struct dwc3_event_depevt *event)
1684{
1685 struct dwc3 *dwc = dep->dwc;
1686 struct dwc3_event_depevt mod_ev = *event;
1687
1688 /*
1689 * We were asked to remove one request. It is possible that this
1690 * request and a few others were started together and have the same
1691 * transfer index. Since we stopped the complete endpoint we don't
1692 * know how many requests were already completed (and not yet)
1693 * reported and how could be done (later). We purge them all until
1694 * the end of the list.
1695 */
1696 mod_ev.status = DEPEVT_STATUS_LST;
1697 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1698 dep->flags &= ~DWC3_EP_BUSY;
1699 /* pending requests are ignored and are queued on XferNotReady */
1700}
1701
1702static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1703 const struct dwc3_event_depevt *event)
1704{
1705 u32 param = event->parameters;
1706 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1707
1708 switch (cmd_type) {
1709 case DWC3_DEPCMD_ENDTRANSFER:
1710 dwc3_process_ep_cmd_complete(dep, event);
1711 break;
1712 case DWC3_DEPCMD_STARTTRANSFER:
1713 dep->res_trans_idx = param & 0x7f;
1714 break;
1715 default:
1716 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1717 __func__, cmd_type);
1718 break;
1719 };
1720}
1721
1722static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1723 const struct dwc3_event_depevt *event)
1724{
1725 struct dwc3_ep *dep;
1726 u8 epnum = event->endpoint_number;
1727
1728 dep = dwc->eps[epnum];
1729
1730 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1731 dwc3_ep_event_string(event->endpoint_event));
1732
1733 if (epnum == 0 || epnum == 1) {
1734 dwc3_ep0_interrupt(dwc, event);
1735 return;
1736 }
1737
1738 switch (event->endpoint_event) {
1739 case DWC3_DEPEVT_XFERCOMPLETE:
1740 dep->res_trans_idx = 0;
1741
1742 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1743 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1744 dep->name);
1745 return;
1746 }
1747
1748 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1749 break;
1750 case DWC3_DEPEVT_XFERINPROGRESS:
1751 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1752 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1753 dep->name);
1754 return;
1755 }
1756
1757 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1758 break;
1759 case DWC3_DEPEVT_XFERNOTREADY:
1760 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1761 dwc3_gadget_start_isoc(dwc, dep, event);
1762 } else {
1763 int ret;
1764
1765 dev_vdbg(dwc->dev, "%s: reason %s\n",
1766 dep->name, event->status &
1767 DEPEVT_STATUS_TRANSFER_ACTIVE
1768 ? "Transfer Active"
1769 : "Transfer Not Active");
1770
1771 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1772 if (!ret || ret == -EBUSY)
1773 return;
1774
1775 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1776 dep->name);
1777 }
1778
1779 break;
1780 case DWC3_DEPEVT_STREAMEVT:
1781 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1782 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1783 dep->name);
1784 return;
1785 }
1786
1787 switch (event->status) {
1788 case DEPEVT_STREAMEVT_FOUND:
1789 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1790 event->parameters);
1791
1792 break;
1793 case DEPEVT_STREAMEVT_NOTFOUND:
1794 /* FALLTHROUGH */
1795 default:
1796 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1797 }
1798 break;
1799 case DWC3_DEPEVT_RXTXFIFOEVT:
1800 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1801 break;
1802 case DWC3_DEPEVT_EPCMDCMPLT:
1803 dwc3_ep_cmd_compl(dep, event);
1804 break;
1805 }
1806}
1807
1808static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1809{
1810 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1811 spin_unlock(&dwc->lock);
1812 dwc->gadget_driver->disconnect(&dwc->gadget);
1813 spin_lock(&dwc->lock);
1814 }
1815}
1816
1817static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1818{
1819 struct dwc3_ep *dep;
1820 struct dwc3_gadget_ep_cmd_params params;
1821 u32 cmd;
1822 int ret;
1823
1824 dep = dwc->eps[epnum];
1825
1826 WARN_ON(!dep->res_trans_idx);
1827 if (dep->res_trans_idx) {
1828 cmd = DWC3_DEPCMD_ENDTRANSFER;
1829 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1830 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1831 memset(¶ms, 0, sizeof(params));
1832 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1833 WARN_ON_ONCE(ret);
1834 dep->res_trans_idx = 0;
1835 }
1836}
1837
1838static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1839{
1840 u32 epnum;
1841
1842 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1843 struct dwc3_ep *dep;
1844
1845 dep = dwc->eps[epnum];
1846 if (!(dep->flags & DWC3_EP_ENABLED))
1847 continue;
1848
1849 dwc3_remove_requests(dwc, dep);
1850 }
1851}
1852
1853static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1854{
1855 u32 epnum;
1856
1857 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1858 struct dwc3_ep *dep;
1859 struct dwc3_gadget_ep_cmd_params params;
1860 int ret;
1861
1862 dep = dwc->eps[epnum];
1863
1864 if (!(dep->flags & DWC3_EP_STALL))
1865 continue;
1866
1867 dep->flags &= ~DWC3_EP_STALL;
1868
1869 memset(¶ms, 0, sizeof(params));
1870 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1871 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1872 WARN_ON_ONCE(ret);
1873 }
1874}
1875
1876static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1877{
1878 dev_vdbg(dwc->dev, "%s\n", __func__);
1879#if 0
1880 XXX
1881 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1882 enable it before we can disable it.
1883
1884 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1885 reg &= ~DWC3_DCTL_INITU1ENA;
1886 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1887
1888 reg &= ~DWC3_DCTL_INITU2ENA;
1889 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1890#endif
1891
1892 dwc3_stop_active_transfers(dwc);
1893 dwc3_disconnect_gadget(dwc);
1894 dwc->start_config_issued = false;
1895
1896 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1897 dwc->setup_packet_pending = false;
1898}
1899
1900static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1901{
1902 u32 reg;
1903
1904 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1905
1906 if (on)
1907 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1908 else
1909 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1910
1911 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1912}
1913
1914static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1915{
1916 u32 reg;
1917
1918 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1919
1920 if (on)
1921 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1922 else
1923 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1924
1925 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1926}
1927
1928static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1929{
1930 u32 reg;
1931
1932 dev_vdbg(dwc->dev, "%s\n", __func__);
1933
1934 /*
1935 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1936 * would cause a missing Disconnect Event if there's a
1937 * pending Setup Packet in the FIFO.
1938 *
1939 * There's no suggested workaround on the official Bug
1940 * report, which states that "unless the driver/application
1941 * is doing any special handling of a disconnect event,
1942 * there is no functional issue".
1943 *
1944 * Unfortunately, it turns out that we _do_ some special
1945 * handling of a disconnect event, namely complete all
1946 * pending transfers, notify gadget driver of the
1947 * disconnection, and so on.
1948 *
1949 * Our suggested workaround is to follow the Disconnect
1950 * Event steps here, instead, based on a setup_packet_pending
1951 * flag. Such flag gets set whenever we have a XferNotReady
1952 * event on EP0 and gets cleared on XferComplete for the
1953 * same endpoint.
1954 *
1955 * Refers to:
1956 *
1957 * STAR#9000466709: RTL: Device : Disconnect event not
1958 * generated if setup packet pending in FIFO
1959 */
1960 if (dwc->revision < DWC3_REVISION_188A) {
1961 if (dwc->setup_packet_pending)
1962 dwc3_gadget_disconnect_interrupt(dwc);
1963 }
1964
1965 /* after reset -> Default State */
1966 dwc->dev_state = DWC3_DEFAULT_STATE;
1967
1968 /* Enable PHYs */
1969 dwc3_gadget_usb2_phy_power(dwc, true);
1970 dwc3_gadget_usb3_phy_power(dwc, true);
1971
1972 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1973 dwc3_disconnect_gadget(dwc);
1974
1975 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1976 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1977 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
1978 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1979 dwc->test_mode = false;
1980
1981 dwc3_stop_active_transfers(dwc);
1982 dwc3_clear_stall_all_ep(dwc);
1983 dwc->start_config_issued = false;
1984
1985 /* Reset device address to zero */
1986 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1987 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1988 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1989}
1990
1991static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1992{
1993 u32 reg;
1994 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1995
1996 /*
1997 * We change the clock only at SS but I dunno why I would want to do
1998 * this. Maybe it becomes part of the power saving plan.
1999 */
2000
2001 if (speed != DWC3_DSTS_SUPERSPEED)
2002 return;
2003
2004 /*
2005 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2006 * each time on Connect Done.
2007 */
2008 if (!usb30_clock)
2009 return;
2010
2011 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2012 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2013 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2014}
2015
2016static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
2017{
2018 switch (speed) {
2019 case USB_SPEED_SUPER:
2020 dwc3_gadget_usb2_phy_power(dwc, false);
2021 break;
2022 case USB_SPEED_HIGH:
2023 case USB_SPEED_FULL:
2024 case USB_SPEED_LOW:
2025 dwc3_gadget_usb3_phy_power(dwc, false);
2026 break;
2027 }
2028}
2029
2030static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2031{
2032 struct dwc3_gadget_ep_cmd_params params;
2033 struct dwc3_ep *dep;
2034 int ret;
2035 u32 reg;
2036 u8 speed;
2037
2038 dev_vdbg(dwc->dev, "%s\n", __func__);
2039
2040 memset(¶ms, 0x00, sizeof(params));
2041
2042 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2043 speed = reg & DWC3_DSTS_CONNECTSPD;
2044 dwc->speed = speed;
2045
2046 dwc3_update_ram_clk_sel(dwc, speed);
2047
2048 switch (speed) {
2049 case DWC3_DCFG_SUPERSPEED:
2050 /*
2051 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2052 * would cause a missing USB3 Reset event.
2053 *
2054 * In such situations, we should force a USB3 Reset
2055 * event by calling our dwc3_gadget_reset_interrupt()
2056 * routine.
2057 *
2058 * Refers to:
2059 *
2060 * STAR#9000483510: RTL: SS : USB3 reset event may
2061 * not be generated always when the link enters poll
2062 */
2063 if (dwc->revision < DWC3_REVISION_190A)
2064 dwc3_gadget_reset_interrupt(dwc);
2065
2066 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2067 dwc->gadget.ep0->maxpacket = 512;
2068 dwc->gadget.speed = USB_SPEED_SUPER;
2069 break;
2070 case DWC3_DCFG_HIGHSPEED:
2071 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2072 dwc->gadget.ep0->maxpacket = 64;
2073 dwc->gadget.speed = USB_SPEED_HIGH;
2074 break;
2075 case DWC3_DCFG_FULLSPEED2:
2076 case DWC3_DCFG_FULLSPEED1:
2077 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2078 dwc->gadget.ep0->maxpacket = 64;
2079 dwc->gadget.speed = USB_SPEED_FULL;
2080 break;
2081 case DWC3_DCFG_LOWSPEED:
2082 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2083 dwc->gadget.ep0->maxpacket = 8;
2084 dwc->gadget.speed = USB_SPEED_LOW;
2085 break;
2086 }
2087
2088 /* Disable unneded PHY */
2089 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
2090
2091 dep = dwc->eps[0];
2092 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2093 if (ret) {
2094 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2095 return;
2096 }
2097
2098 dep = dwc->eps[1];
2099 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2100 if (ret) {
2101 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2102 return;
2103 }
2104
2105 /*
2106 * Configure PHY via GUSB3PIPECTLn if required.
2107 *
2108 * Update GTXFIFOSIZn
2109 *
2110 * In both cases reset values should be sufficient.
2111 */
2112}
2113
2114static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2115{
2116 dev_vdbg(dwc->dev, "%s\n", __func__);
2117
2118 /*
2119 * TODO take core out of low power mode when that's
2120 * implemented.
2121 */
2122
2123 dwc->gadget_driver->resume(&dwc->gadget);
2124}
2125
2126static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2127 unsigned int evtinfo)
2128{
2129 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2130
2131 /*
2132 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2133 * on the link partner, the USB session might do multiple entry/exit
2134 * of low power states before a transfer takes place.
2135 *
2136 * Due to this problem, we might experience lower throughput. The
2137 * suggested workaround is to disable DCTL[12:9] bits if we're
2138 * transitioning from U1/U2 to U0 and enable those bits again
2139 * after a transfer completes and there are no pending transfers
2140 * on any of the enabled endpoints.
2141 *
2142 * This is the first half of that workaround.
2143 *
2144 * Refers to:
2145 *
2146 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2147 * core send LGO_Ux entering U0
2148 */
2149 if (dwc->revision < DWC3_REVISION_183A) {
2150 if (next == DWC3_LINK_STATE_U0) {
2151 u32 u1u2;
2152 u32 reg;
2153
2154 switch (dwc->link_state) {
2155 case DWC3_LINK_STATE_U1:
2156 case DWC3_LINK_STATE_U2:
2157 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2158 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2159 | DWC3_DCTL_ACCEPTU2ENA
2160 | DWC3_DCTL_INITU1ENA
2161 | DWC3_DCTL_ACCEPTU1ENA);
2162
2163 if (!dwc->u1u2)
2164 dwc->u1u2 = reg & u1u2;
2165
2166 reg &= ~u1u2;
2167
2168 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2169 break;
2170 default:
2171 /* do nothing */
2172 break;
2173 }
2174 }
2175 }
2176
2177 dwc->link_state = next;
2178
2179 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2180}
2181
2182static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2183 const struct dwc3_event_devt *event)
2184{
2185 switch (event->type) {
2186 case DWC3_DEVICE_EVENT_DISCONNECT:
2187 dwc3_gadget_disconnect_interrupt(dwc);
2188 break;
2189 case DWC3_DEVICE_EVENT_RESET:
2190 dwc3_gadget_reset_interrupt(dwc);
2191 break;
2192 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2193 dwc3_gadget_conndone_interrupt(dwc);
2194 break;
2195 case DWC3_DEVICE_EVENT_WAKEUP:
2196 dwc3_gadget_wakeup_interrupt(dwc);
2197 break;
2198 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2199 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2200 break;
2201 case DWC3_DEVICE_EVENT_EOPF:
2202 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2203 break;
2204 case DWC3_DEVICE_EVENT_SOF:
2205 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2206 break;
2207 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2208 dev_vdbg(dwc->dev, "Erratic Error\n");
2209 break;
2210 case DWC3_DEVICE_EVENT_CMD_CMPL:
2211 dev_vdbg(dwc->dev, "Command Complete\n");
2212 break;
2213 case DWC3_DEVICE_EVENT_OVERFLOW:
2214 dev_vdbg(dwc->dev, "Overflow\n");
2215 break;
2216 default:
2217 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2218 }
2219}
2220
2221static void dwc3_process_event_entry(struct dwc3 *dwc,
2222 const union dwc3_event *event)
2223{
2224 /* Endpoint IRQ, handle it and return early */
2225 if (event->type.is_devspec == 0) {
2226 /* depevt */
2227 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2228 }
2229
2230 switch (event->type.type) {
2231 case DWC3_EVENT_TYPE_DEV:
2232 dwc3_gadget_interrupt(dwc, &event->devt);
2233 break;
2234 /* REVISIT what to do with Carkit and I2C events ? */
2235 default:
2236 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2237 }
2238}
2239
2240static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2241{
2242 struct dwc3_event_buffer *evt;
2243 int left;
2244 u32 count;
2245
2246 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2247 count &= DWC3_GEVNTCOUNT_MASK;
2248 if (!count)
2249 return IRQ_NONE;
2250
2251 evt = dwc->ev_buffs[buf];
2252 left = count;
2253
2254 while (left > 0) {
2255 union dwc3_event event;
2256
2257 event.raw = *(u32 *) (evt->buf + evt->lpos);
2258
2259 dwc3_process_event_entry(dwc, &event);
2260 /*
2261 * XXX we wrap around correctly to the next entry as almost all
2262 * entries are 4 bytes in size. There is one entry which has 12
2263 * bytes which is a regular entry followed by 8 bytes data. ATM
2264 * I don't know how things are organized if were get next to the
2265 * a boundary so I worry about that once we try to handle that.
2266 */
2267 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2268 left -= 4;
2269
2270 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2271 }
2272
2273 return IRQ_HANDLED;
2274}
2275
2276static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2277{
2278 struct dwc3 *dwc = _dwc;
2279 int i;
2280 irqreturn_t ret = IRQ_NONE;
2281
2282 spin_lock(&dwc->lock);
2283
2284 for (i = 0; i < dwc->num_event_buffers; i++) {
2285 irqreturn_t status;
2286
2287 status = dwc3_process_event_buf(dwc, i);
2288 if (status == IRQ_HANDLED)
2289 ret = status;
2290 }
2291
2292 spin_unlock(&dwc->lock);
2293
2294 return ret;
2295}
2296
2297/**
2298 * dwc3_gadget_init - Initializes gadget related registers
2299 * @dwc: pointer to our controller context structure
2300 *
2301 * Returns 0 on success otherwise negative errno.
2302 */
2303int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2304{
2305 u32 reg;
2306 int ret;
2307 int irq;
2308
2309 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2310 &dwc->ctrl_req_addr, GFP_KERNEL);
2311 if (!dwc->ctrl_req) {
2312 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2313 ret = -ENOMEM;
2314 goto err0;
2315 }
2316
2317 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2318 &dwc->ep0_trb_addr, GFP_KERNEL);
2319 if (!dwc->ep0_trb) {
2320 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2321 ret = -ENOMEM;
2322 goto err1;
2323 }
2324
2325 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2326 if (!dwc->setup_buf) {
2327 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2328 ret = -ENOMEM;
2329 goto err2;
2330 }
2331
2332 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2333 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2334 GFP_KERNEL);
2335 if (!dwc->ep0_bounce) {
2336 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2337 ret = -ENOMEM;
2338 goto err3;
2339 }
2340
2341 dev_set_name(&dwc->gadget.dev, "gadget");
2342
2343 dwc->gadget.ops = &dwc3_gadget_ops;
2344 dwc->gadget.max_speed = USB_SPEED_SUPER;
2345 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2346 dwc->gadget.dev.parent = dwc->dev;
2347 dwc->gadget.sg_supported = true;
2348
2349 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2350
2351 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2352 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2353 dwc->gadget.dev.release = dwc3_gadget_release;
2354 dwc->gadget.name = "dwc3-gadget";
2355
2356 /*
2357 * REVISIT: Here we should clear all pending IRQs to be
2358 * sure we're starting from a well known location.
2359 */
2360
2361 ret = dwc3_gadget_init_endpoints(dwc);
2362 if (ret)
2363 goto err4;
2364
2365 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2366
2367 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2368 "dwc3", dwc);
2369 if (ret) {
2370 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2371 irq, ret);
2372 goto err5;
2373 }
2374
2375 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2376 reg |= DWC3_DCFG_LPM_CAP;
2377 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2378
2379 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2380 reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA;
2381 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2382
2383 /* Enable all but Start and End of Frame IRQs */
2384 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2385 DWC3_DEVTEN_EVNTOVERFLOWEN |
2386 DWC3_DEVTEN_CMDCMPLTEN |
2387 DWC3_DEVTEN_ERRTICERREN |
2388 DWC3_DEVTEN_WKUPEVTEN |
2389 DWC3_DEVTEN_ULSTCNGEN |
2390 DWC3_DEVTEN_CONNECTDONEEN |
2391 DWC3_DEVTEN_USBRSTEN |
2392 DWC3_DEVTEN_DISCONNEVTEN);
2393 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2394
2395 ret = device_register(&dwc->gadget.dev);
2396 if (ret) {
2397 dev_err(dwc->dev, "failed to register gadget device\n");
2398 put_device(&dwc->gadget.dev);
2399 goto err6;
2400 }
2401
2402 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2403 if (ret) {
2404 dev_err(dwc->dev, "failed to register udc\n");
2405 goto err7;
2406 }
2407
2408 return 0;
2409
2410err7:
2411 device_unregister(&dwc->gadget.dev);
2412
2413err6:
2414 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2415 free_irq(irq, dwc);
2416
2417err5:
2418 dwc3_gadget_free_endpoints(dwc);
2419
2420err4:
2421 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2422 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2423
2424err3:
2425 kfree(dwc->setup_buf);
2426
2427err2:
2428 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2429 dwc->ep0_trb, dwc->ep0_trb_addr);
2430
2431err1:
2432 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2433 dwc->ctrl_req, dwc->ctrl_req_addr);
2434
2435err0:
2436 return ret;
2437}
2438
2439void dwc3_gadget_exit(struct dwc3 *dwc)
2440{
2441 int irq;
2442
2443 usb_del_gadget_udc(&dwc->gadget);
2444 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2445
2446 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2447 free_irq(irq, dwc);
2448
2449 dwc3_gadget_free_endpoints(dwc);
2450
2451 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2452 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2453
2454 kfree(dwc->setup_buf);
2455
2456 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2457 dwc->ep0_trb, dwc->ep0_trb_addr);
2458
2459 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2460 dwc->ctrl_req, dwc->ctrl_req_addr);
2461
2462 device_unregister(&dwc->gadget.dev);
2463}