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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "nouveau_drv.h"
26#include "nouveau_dma.h"
27#include "nouveau_fence.h"
28#include "nouveau_vmm.h"
29
30#include "nv50_display.h"
31
32static int
33nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
34{
35 int ret = RING_SPACE(chan, 8);
36 if (ret == 0) {
37 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
38 OUT_RING (chan, chan->vram.handle);
39 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5);
40 OUT_RING (chan, upper_32_bits(virtual));
41 OUT_RING (chan, lower_32_bits(virtual));
42 OUT_RING (chan, sequence);
43 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
44 OUT_RING (chan, 0x00000000);
45 FIRE_RING (chan);
46 }
47 return ret;
48}
49
50static int
51nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
52{
53 int ret = RING_SPACE(chan, 7);
54 if (ret == 0) {
55 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
56 OUT_RING (chan, chan->vram.handle);
57 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
58 OUT_RING (chan, upper_32_bits(virtual));
59 OUT_RING (chan, lower_32_bits(virtual));
60 OUT_RING (chan, sequence);
61 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
62 FIRE_RING (chan);
63 }
64 return ret;
65}
66
67static int
68nv84_fence_emit(struct nouveau_fence *fence)
69{
70 struct nouveau_channel *chan = fence->channel;
71 struct nv84_fence_chan *fctx = chan->fence;
72 u64 addr = fctx->vma->addr + chan->chid * 16;
73
74 return fctx->base.emit32(chan, addr, fence->base.seqno);
75}
76
77static int
78nv84_fence_sync(struct nouveau_fence *fence,
79 struct nouveau_channel *prev, struct nouveau_channel *chan)
80{
81 struct nv84_fence_chan *fctx = chan->fence;
82 u64 addr = fctx->vma->addr + prev->chid * 16;
83
84 return fctx->base.sync32(chan, addr, fence->base.seqno);
85}
86
87static u32
88nv84_fence_read(struct nouveau_channel *chan)
89{
90 struct nv84_fence_priv *priv = chan->drm->fence;
91 return nouveau_bo_rd32(priv->bo, chan->chid * 16/4);
92}
93
94static void
95nv84_fence_context_del(struct nouveau_channel *chan)
96{
97 struct nv84_fence_priv *priv = chan->drm->fence;
98 struct nv84_fence_chan *fctx = chan->fence;
99
100 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence);
101 mutex_lock(&priv->mutex);
102 nouveau_vma_del(&fctx->vma);
103 mutex_unlock(&priv->mutex);
104 nouveau_fence_context_del(&fctx->base);
105 chan->fence = NULL;
106 nouveau_fence_context_free(&fctx->base);
107}
108
109int
110nv84_fence_context_new(struct nouveau_channel *chan)
111{
112 struct nv84_fence_priv *priv = chan->drm->fence;
113 struct nv84_fence_chan *fctx;
114 int ret;
115
116 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
117 if (!fctx)
118 return -ENOMEM;
119
120 nouveau_fence_context_new(chan, &fctx->base);
121 fctx->base.emit = nv84_fence_emit;
122 fctx->base.sync = nv84_fence_sync;
123 fctx->base.read = nv84_fence_read;
124 fctx->base.emit32 = nv84_fence_emit32;
125 fctx->base.sync32 = nv84_fence_sync32;
126 fctx->base.sequence = nv84_fence_read(chan);
127
128 mutex_lock(&priv->mutex);
129 ret = nouveau_vma_new(priv->bo, chan->vmm, &fctx->vma);
130 mutex_unlock(&priv->mutex);
131
132 if (ret)
133 nv84_fence_context_del(chan);
134 return ret;
135}
136
137static bool
138nv84_fence_suspend(struct nouveau_drm *drm)
139{
140 struct nv84_fence_priv *priv = drm->fence;
141 int i;
142
143 priv->suspend = vmalloc(array_size(sizeof(u32), drm->chan.nr));
144 if (priv->suspend) {
145 for (i = 0; i < drm->chan.nr; i++)
146 priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4);
147 }
148
149 return priv->suspend != NULL;
150}
151
152static void
153nv84_fence_resume(struct nouveau_drm *drm)
154{
155 struct nv84_fence_priv *priv = drm->fence;
156 int i;
157
158 if (priv->suspend) {
159 for (i = 0; i < drm->chan.nr; i++)
160 nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]);
161 vfree(priv->suspend);
162 priv->suspend = NULL;
163 }
164}
165
166static void
167nv84_fence_destroy(struct nouveau_drm *drm)
168{
169 struct nv84_fence_priv *priv = drm->fence;
170 nouveau_bo_unmap(priv->bo);
171 if (priv->bo)
172 nouveau_bo_unpin(priv->bo);
173 nouveau_bo_ref(NULL, &priv->bo);
174 drm->fence = NULL;
175 kfree(priv);
176}
177
178int
179nv84_fence_create(struct nouveau_drm *drm)
180{
181 struct nv84_fence_priv *priv;
182 u32 domain;
183 int ret;
184
185 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
186 if (!priv)
187 return -ENOMEM;
188
189 priv->base.dtor = nv84_fence_destroy;
190 priv->base.suspend = nv84_fence_suspend;
191 priv->base.resume = nv84_fence_resume;
192 priv->base.context_new = nv84_fence_context_new;
193 priv->base.context_del = nv84_fence_context_del;
194
195 priv->base.uevent = true;
196
197 mutex_init(&priv->mutex);
198
199 /* Use VRAM if there is any ; otherwise fallback to system memory */
200 domain = drm->client.device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
201 /*
202 * fences created in sysmem must be non-cached or we
203 * will lose CPU/GPU coherency!
204 */
205 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
206 ret = nouveau_bo_new(&drm->client, 16 * drm->chan.nr, 0,
207 domain, 0, 0, NULL, NULL, &priv->bo);
208 if (ret == 0) {
209 ret = nouveau_bo_pin(priv->bo, domain, false);
210 if (ret == 0) {
211 ret = nouveau_bo_map(priv->bo);
212 if (ret)
213 nouveau_bo_unpin(priv->bo);
214 }
215 if (ret)
216 nouveau_bo_ref(NULL, &priv->bo);
217 }
218
219 if (ret)
220 nv84_fence_destroy(drm);
221 return ret;
222}
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_dma.h"
28#include "nouveau_fifo.h"
29#include "nouveau_ramht.h"
30#include "nouveau_fence.h"
31
32struct nv84_fence_chan {
33 struct nouveau_fence_chan base;
34};
35
36struct nv84_fence_priv {
37 struct nouveau_fence_priv base;
38 struct nouveau_gpuobj *mem;
39};
40
41static int
42nv84_fence_emit(struct nouveau_fence *fence)
43{
44 struct nouveau_channel *chan = fence->channel;
45 int ret = RING_SPACE(chan, 7);
46 if (ret == 0) {
47 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
48 OUT_RING (chan, NvSema);
49 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
50 OUT_RING (chan, upper_32_bits(chan->id * 16));
51 OUT_RING (chan, lower_32_bits(chan->id * 16));
52 OUT_RING (chan, fence->sequence);
53 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
54 FIRE_RING (chan);
55 }
56 return ret;
57}
58
59
60static int
61nv84_fence_sync(struct nouveau_fence *fence,
62 struct nouveau_channel *prev, struct nouveau_channel *chan)
63{
64 int ret = RING_SPACE(chan, 7);
65 if (ret == 0) {
66 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
67 OUT_RING (chan, NvSema);
68 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
69 OUT_RING (chan, upper_32_bits(prev->id * 16));
70 OUT_RING (chan, lower_32_bits(prev->id * 16));
71 OUT_RING (chan, fence->sequence);
72 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
73 FIRE_RING (chan);
74 }
75 return ret;
76}
77
78static u32
79nv84_fence_read(struct nouveau_channel *chan)
80{
81 struct nv84_fence_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_FENCE);
82 return nv_ro32(priv->mem, chan->id * 16);
83}
84
85static void
86nv84_fence_context_del(struct nouveau_channel *chan, int engine)
87{
88 struct nv84_fence_chan *fctx = chan->engctx[engine];
89 nouveau_fence_context_del(&fctx->base);
90 chan->engctx[engine] = NULL;
91 kfree(fctx);
92}
93
94static int
95nv84_fence_context_new(struct nouveau_channel *chan, int engine)
96{
97 struct nv84_fence_priv *priv = nv_engine(chan->dev, engine);
98 struct nv84_fence_chan *fctx;
99 struct nouveau_gpuobj *obj;
100 int ret;
101
102 fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL);
103 if (!fctx)
104 return -ENOMEM;
105
106 nouveau_fence_context_new(&fctx->base);
107
108 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
109 priv->mem->vinst, priv->mem->size,
110 NV_MEM_ACCESS_RW,
111 NV_MEM_TARGET_VRAM, &obj);
112 if (ret == 0) {
113 ret = nouveau_ramht_insert(chan, NvSema, obj);
114 nouveau_gpuobj_ref(NULL, &obj);
115 nv_wo32(priv->mem, chan->id * 16, 0x00000000);
116 }
117
118 if (ret)
119 nv84_fence_context_del(chan, engine);
120 return ret;
121}
122
123static int
124nv84_fence_fini(struct drm_device *dev, int engine, bool suspend)
125{
126 return 0;
127}
128
129static int
130nv84_fence_init(struct drm_device *dev, int engine)
131{
132 return 0;
133}
134
135static void
136nv84_fence_destroy(struct drm_device *dev, int engine)
137{
138 struct drm_nouveau_private *dev_priv = dev->dev_private;
139 struct nv84_fence_priv *priv = nv_engine(dev, engine);
140
141 nouveau_gpuobj_ref(NULL, &priv->mem);
142 dev_priv->eng[engine] = NULL;
143 kfree(priv);
144}
145
146int
147nv84_fence_create(struct drm_device *dev)
148{
149 struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
150 struct drm_nouveau_private *dev_priv = dev->dev_private;
151 struct nv84_fence_priv *priv;
152 int ret;
153
154 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
155 if (!priv)
156 return -ENOMEM;
157
158 priv->base.engine.destroy = nv84_fence_destroy;
159 priv->base.engine.init = nv84_fence_init;
160 priv->base.engine.fini = nv84_fence_fini;
161 priv->base.engine.context_new = nv84_fence_context_new;
162 priv->base.engine.context_del = nv84_fence_context_del;
163 priv->base.emit = nv84_fence_emit;
164 priv->base.sync = nv84_fence_sync;
165 priv->base.read = nv84_fence_read;
166 dev_priv->eng[NVOBJ_ENGINE_FENCE] = &priv->base.engine;
167
168 ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels,
169 0x1000, 0, &priv->mem);
170 if (ret)
171 goto out;
172
173out:
174 if (ret)
175 nv84_fence_destroy(dev, NVOBJ_ENGINE_FENCE);
176 return ret;
177}