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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Freescale QUICC Engine UART device driver
4 *
5 * Author: Timur Tabi <timur@freescale.com>
6 *
7 * Copyright 2007 Freescale Semiconductor, Inc.
8 *
9 * This driver adds support for UART devices via Freescale's QUICC Engine
10 * found on some Freescale SOCs.
11 *
12 * If Soft-UART support is needed but not already present, then this driver
13 * will request and upload the "Soft-UART" microcode upon probe. The
14 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
15 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
16 * (e.g. "11" for 1.1).
17 */
18
19#include <linux/module.h>
20#include <linux/serial.h>
21#include <linux/serial_core.h>
22#include <linux/slab.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/io.h>
26#include <linux/of_address.h>
27#include <linux/of_irq.h>
28#include <linux/of_platform.h>
29#include <linux/dma-mapping.h>
30
31#include <linux/fs_uart_pd.h>
32#include <soc/fsl/qe/ucc_slow.h>
33
34#include <linux/firmware.h>
35#include <asm/reg.h>
36
37/*
38 * The GUMR flag for Soft UART. This would normally be defined in qe.h,
39 * but Soft-UART is a hack and we want to keep everything related to it in
40 * this file.
41 */
42#define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
43
44/*
45 * soft_uart is 1 if we need to use Soft-UART mode
46 */
47static int soft_uart;
48/*
49 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
50 */
51static int firmware_loaded;
52
53/* Enable this macro to configure all serial ports in internal loopback
54 mode */
55/* #define LOOPBACK */
56
57/* The major and minor device numbers are defined in
58 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
59 * UART, we have major number 204 and minor numbers 46 - 49, which are the
60 * same as for the CPM2. This decision was made because no Freescale part
61 * has both a CPM and a QE.
62 */
63#define SERIAL_QE_MAJOR 204
64#define SERIAL_QE_MINOR 46
65
66/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
67#define UCC_MAX_UART 4
68
69/* The number of buffer descriptors for receiving characters. */
70#define RX_NUM_FIFO 4
71
72/* The number of buffer descriptors for transmitting characters. */
73#define TX_NUM_FIFO 4
74
75/* The maximum size of the character buffer for a single RX BD. */
76#define RX_BUF_SIZE 32
77
78/* The maximum size of the character buffer for a single TX BD. */
79#define TX_BUF_SIZE 32
80
81/*
82 * The number of jiffies to wait after receiving a close command before the
83 * device is actually closed. This allows the last few characters to be
84 * sent over the wire.
85 */
86#define UCC_WAIT_CLOSING 100
87
88struct ucc_uart_pram {
89 struct ucc_slow_pram common;
90 u8 res1[8]; /* reserved */
91 __be16 maxidl; /* Maximum idle chars */
92 __be16 idlc; /* temp idle counter */
93 __be16 brkcr; /* Break count register */
94 __be16 parec; /* receive parity error counter */
95 __be16 frmec; /* receive framing error counter */
96 __be16 nosec; /* receive noise counter */
97 __be16 brkec; /* receive break condition counter */
98 __be16 brkln; /* last received break length */
99 __be16 uaddr[2]; /* UART address character 1 & 2 */
100 __be16 rtemp; /* Temp storage */
101 __be16 toseq; /* Transmit out of sequence char */
102 __be16 cchars[8]; /* control characters 1-8 */
103 __be16 rccm; /* receive control character mask */
104 __be16 rccr; /* receive control character register */
105 __be16 rlbc; /* receive last break character */
106 __be16 res2; /* reserved */
107 __be32 res3; /* reserved, should be cleared */
108 u8 res4; /* reserved, should be cleared */
109 u8 res5[3]; /* reserved, should be cleared */
110 __be32 res6; /* reserved, should be cleared */
111 __be32 res7; /* reserved, should be cleared */
112 __be32 res8; /* reserved, should be cleared */
113 __be32 res9; /* reserved, should be cleared */
114 __be32 res10; /* reserved, should be cleared */
115 __be32 res11; /* reserved, should be cleared */
116 __be32 res12; /* reserved, should be cleared */
117 __be32 res13; /* reserved, should be cleared */
118/* The rest is for Soft-UART only */
119 __be16 supsmr; /* 0x90, Shadow UPSMR */
120 __be16 res92; /* 0x92, reserved, initialize to 0 */
121 __be32 rx_state; /* 0x94, RX state, initialize to 0 */
122 __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
123 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
124 u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
125 u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
126 u8 res14[0xBC - 0x9F]; /* reserved */
127 __be32 dump_ptr; /* 0xBC, Dump pointer */
128 __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
129 u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
130 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
131 __be16 tx_state; /* 0xC6, TX state */
132 u8 res15[0xD0 - 0xC8]; /* reserved */
133 __be32 resD0; /* 0xD0, reserved, initialize to 0 */
134 u8 resD4; /* 0xD4, reserved, initialize to 0 */
135 __be16 resD5; /* 0xD5, reserved, initialize to 0 */
136} __attribute__ ((packed));
137
138/* SUPSMR definitions, for Soft-UART only */
139#define UCC_UART_SUPSMR_SL 0x8000
140#define UCC_UART_SUPSMR_RPM_MASK 0x6000
141#define UCC_UART_SUPSMR_RPM_ODD 0x0000
142#define UCC_UART_SUPSMR_RPM_LOW 0x2000
143#define UCC_UART_SUPSMR_RPM_EVEN 0x4000
144#define UCC_UART_SUPSMR_RPM_HIGH 0x6000
145#define UCC_UART_SUPSMR_PEN 0x1000
146#define UCC_UART_SUPSMR_TPM_MASK 0x0C00
147#define UCC_UART_SUPSMR_TPM_ODD 0x0000
148#define UCC_UART_SUPSMR_TPM_LOW 0x0400
149#define UCC_UART_SUPSMR_TPM_EVEN 0x0800
150#define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
151#define UCC_UART_SUPSMR_FRZ 0x0100
152#define UCC_UART_SUPSMR_UM_MASK 0x00c0
153#define UCC_UART_SUPSMR_UM_NORMAL 0x0000
154#define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
155#define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
156#define UCC_UART_SUPSMR_CL_MASK 0x0030
157#define UCC_UART_SUPSMR_CL_8 0x0030
158#define UCC_UART_SUPSMR_CL_7 0x0020
159#define UCC_UART_SUPSMR_CL_6 0x0010
160#define UCC_UART_SUPSMR_CL_5 0x0000
161
162#define UCC_UART_TX_STATE_AHDLC 0x00
163#define UCC_UART_TX_STATE_UART 0x01
164#define UCC_UART_TX_STATE_X1 0x00
165#define UCC_UART_TX_STATE_X16 0x80
166
167#define UCC_UART_PRAM_ALIGNMENT 0x100
168
169#define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
170#define NUM_CONTROL_CHARS 8
171
172/* Private per-port data structure */
173struct uart_qe_port {
174 struct uart_port port;
175 struct ucc_slow __iomem *uccp;
176 struct ucc_uart_pram __iomem *uccup;
177 struct ucc_slow_info us_info;
178 struct ucc_slow_private *us_private;
179 struct device_node *np;
180 unsigned int ucc_num; /* First ucc is 0, not 1 */
181
182 u16 rx_nrfifos;
183 u16 rx_fifosize;
184 u16 tx_nrfifos;
185 u16 tx_fifosize;
186 int wait_closing;
187 u32 flags;
188 struct qe_bd *rx_bd_base;
189 struct qe_bd *rx_cur;
190 struct qe_bd *tx_bd_base;
191 struct qe_bd *tx_cur;
192 unsigned char *tx_buf;
193 unsigned char *rx_buf;
194 void *bd_virt; /* virtual address of the BD buffers */
195 dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
196 unsigned int bd_size; /* size of BD buffer space */
197};
198
199static struct uart_driver ucc_uart_driver = {
200 .owner = THIS_MODULE,
201 .driver_name = "ucc_uart",
202 .dev_name = "ttyQE",
203 .major = SERIAL_QE_MAJOR,
204 .minor = SERIAL_QE_MINOR,
205 .nr = UCC_MAX_UART,
206};
207
208/*
209 * Virtual to physical address translation.
210 *
211 * Given the virtual address for a character buffer, this function returns
212 * the physical (DMA) equivalent.
213 */
214static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
215{
216 if (likely((addr >= qe_port->bd_virt)) &&
217 (addr < (qe_port->bd_virt + qe_port->bd_size)))
218 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
219
220 /* something nasty happened */
221 printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
222 BUG();
223 return 0;
224}
225
226/*
227 * Physical to virtual address translation.
228 *
229 * Given the physical (DMA) address for a character buffer, this function
230 * returns the virtual equivalent.
231 */
232static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
233{
234 /* sanity check */
235 if (likely((addr >= qe_port->bd_dma_addr) &&
236 (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
237 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
238
239 /* something nasty happened */
240 printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
241 BUG();
242 return NULL;
243}
244
245/*
246 * Return 1 if the QE is done transmitting all buffers for this port
247 *
248 * This function scans each BD in sequence. If we find a BD that is not
249 * ready (READY=1), then we return 0 indicating that the QE is still sending
250 * data. If we reach the last BD (WRAP=1), then we know we've scanned
251 * the entire list, and all BDs are done.
252 */
253static unsigned int qe_uart_tx_empty(struct uart_port *port)
254{
255 struct uart_qe_port *qe_port =
256 container_of(port, struct uart_qe_port, port);
257 struct qe_bd *bdp = qe_port->tx_bd_base;
258
259 while (1) {
260 if (in_be16(&bdp->status) & BD_SC_READY)
261 /* This BD is not done, so return "not done" */
262 return 0;
263
264 if (in_be16(&bdp->status) & BD_SC_WRAP)
265 /*
266 * This BD is done and it's the last one, so return
267 * "done"
268 */
269 return 1;
270
271 bdp++;
272 }
273}
274
275/*
276 * Set the modem control lines
277 *
278 * Although the QE can control the modem control lines (e.g. CTS), we
279 * don't need that support. This function must exist, however, otherwise
280 * the kernel will panic.
281 */
282void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
283{
284}
285
286/*
287 * Get the current modem control line status
288 *
289 * Although the QE can control the modem control lines (e.g. CTS), this
290 * driver currently doesn't support that, so we always return Carrier
291 * Detect, Data Set Ready, and Clear To Send.
292 */
293static unsigned int qe_uart_get_mctrl(struct uart_port *port)
294{
295 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
296}
297
298/*
299 * Disable the transmit interrupt.
300 *
301 * Although this function is called "stop_tx", it does not actually stop
302 * transmission of data. Instead, it tells the QE to not generate an
303 * interrupt when the UCC is finished sending characters.
304 */
305static void qe_uart_stop_tx(struct uart_port *port)
306{
307 struct uart_qe_port *qe_port =
308 container_of(port, struct uart_qe_port, port);
309
310 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
311}
312
313/*
314 * Transmit as many characters to the HW as possible.
315 *
316 * This function will attempt to stuff of all the characters from the
317 * kernel's transmit buffer into TX BDs.
318 *
319 * A return value of non-zero indicates that it successfully stuffed all
320 * characters from the kernel buffer.
321 *
322 * A return value of zero indicates that there are still characters in the
323 * kernel's buffer that have not been transmitted, but there are no more BDs
324 * available. This function should be called again after a BD has been made
325 * available.
326 */
327static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
328{
329 struct qe_bd *bdp;
330 unsigned char *p;
331 unsigned int count;
332 struct uart_port *port = &qe_port->port;
333 struct circ_buf *xmit = &port->state->xmit;
334
335 bdp = qe_port->rx_cur;
336
337 /* Handle xon/xoff */
338 if (port->x_char) {
339 /* Pick next descriptor and fill from buffer */
340 bdp = qe_port->tx_cur;
341
342 p = qe2cpu_addr(bdp->buf, qe_port);
343
344 *p++ = port->x_char;
345 out_be16(&bdp->length, 1);
346 setbits16(&bdp->status, BD_SC_READY);
347 /* Get next BD. */
348 if (in_be16(&bdp->status) & BD_SC_WRAP)
349 bdp = qe_port->tx_bd_base;
350 else
351 bdp++;
352 qe_port->tx_cur = bdp;
353
354 port->icount.tx++;
355 port->x_char = 0;
356 return 1;
357 }
358
359 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
360 qe_uart_stop_tx(port);
361 return 0;
362 }
363
364 /* Pick next descriptor and fill from buffer */
365 bdp = qe_port->tx_cur;
366
367 while (!(in_be16(&bdp->status) & BD_SC_READY) &&
368 (xmit->tail != xmit->head)) {
369 count = 0;
370 p = qe2cpu_addr(bdp->buf, qe_port);
371 while (count < qe_port->tx_fifosize) {
372 *p++ = xmit->buf[xmit->tail];
373 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
374 port->icount.tx++;
375 count++;
376 if (xmit->head == xmit->tail)
377 break;
378 }
379
380 out_be16(&bdp->length, count);
381 setbits16(&bdp->status, BD_SC_READY);
382
383 /* Get next BD. */
384 if (in_be16(&bdp->status) & BD_SC_WRAP)
385 bdp = qe_port->tx_bd_base;
386 else
387 bdp++;
388 }
389 qe_port->tx_cur = bdp;
390
391 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
392 uart_write_wakeup(port);
393
394 if (uart_circ_empty(xmit)) {
395 /* The kernel buffer is empty, so turn off TX interrupts. We
396 don't need to be told when the QE is finished transmitting
397 the data. */
398 qe_uart_stop_tx(port);
399 return 0;
400 }
401
402 return 1;
403}
404
405/*
406 * Start transmitting data
407 *
408 * This function will start transmitting any available data, if the port
409 * isn't already transmitting data.
410 */
411static void qe_uart_start_tx(struct uart_port *port)
412{
413 struct uart_qe_port *qe_port =
414 container_of(port, struct uart_qe_port, port);
415
416 /* If we currently are transmitting, then just return */
417 if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
418 return;
419
420 /* Otherwise, pump the port and start transmission */
421 if (qe_uart_tx_pump(qe_port))
422 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
423}
424
425/*
426 * Stop transmitting data
427 */
428static void qe_uart_stop_rx(struct uart_port *port)
429{
430 struct uart_qe_port *qe_port =
431 container_of(port, struct uart_qe_port, port);
432
433 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
434}
435
436/* Start or stop sending break signal
437 *
438 * This function controls the sending of a break signal. If break_state=1,
439 * then we start sending a break signal. If break_state=0, then we stop
440 * sending the break signal.
441 */
442static void qe_uart_break_ctl(struct uart_port *port, int break_state)
443{
444 struct uart_qe_port *qe_port =
445 container_of(port, struct uart_qe_port, port);
446
447 if (break_state)
448 ucc_slow_stop_tx(qe_port->us_private);
449 else
450 ucc_slow_restart_tx(qe_port->us_private);
451}
452
453/* ISR helper function for receiving character.
454 *
455 * This function is called by the ISR to handling receiving characters
456 */
457static void qe_uart_int_rx(struct uart_qe_port *qe_port)
458{
459 int i;
460 unsigned char ch, *cp;
461 struct uart_port *port = &qe_port->port;
462 struct tty_port *tport = &port->state->port;
463 struct qe_bd *bdp;
464 u16 status;
465 unsigned int flg;
466
467 /* Just loop through the closed BDs and copy the characters into
468 * the buffer.
469 */
470 bdp = qe_port->rx_cur;
471 while (1) {
472 status = in_be16(&bdp->status);
473
474 /* If this one is empty, then we assume we've read them all */
475 if (status & BD_SC_EMPTY)
476 break;
477
478 /* get number of characters, and check space in RX buffer */
479 i = in_be16(&bdp->length);
480
481 /* If we don't have enough room in RX buffer for the entire BD,
482 * then we try later, which will be the next RX interrupt.
483 */
484 if (tty_buffer_request_room(tport, i) < i) {
485 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
486 return;
487 }
488
489 /* get pointer */
490 cp = qe2cpu_addr(bdp->buf, qe_port);
491
492 /* loop through the buffer */
493 while (i-- > 0) {
494 ch = *cp++;
495 port->icount.rx++;
496 flg = TTY_NORMAL;
497
498 if (!i && status &
499 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
500 goto handle_error;
501 if (uart_handle_sysrq_char(port, ch))
502 continue;
503
504error_return:
505 tty_insert_flip_char(tport, ch, flg);
506
507 }
508
509 /* This BD is ready to be used again. Clear status. get next */
510 clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
511 BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
512 if (in_be16(&bdp->status) & BD_SC_WRAP)
513 bdp = qe_port->rx_bd_base;
514 else
515 bdp++;
516
517 }
518
519 /* Write back buffer pointer */
520 qe_port->rx_cur = bdp;
521
522 /* Activate BH processing */
523 tty_flip_buffer_push(tport);
524
525 return;
526
527 /* Error processing */
528
529handle_error:
530 /* Statistics */
531 if (status & BD_SC_BR)
532 port->icount.brk++;
533 if (status & BD_SC_PR)
534 port->icount.parity++;
535 if (status & BD_SC_FR)
536 port->icount.frame++;
537 if (status & BD_SC_OV)
538 port->icount.overrun++;
539
540 /* Mask out ignored conditions */
541 status &= port->read_status_mask;
542
543 /* Handle the remaining ones */
544 if (status & BD_SC_BR)
545 flg = TTY_BREAK;
546 else if (status & BD_SC_PR)
547 flg = TTY_PARITY;
548 else if (status & BD_SC_FR)
549 flg = TTY_FRAME;
550
551 /* Overrun does not affect the current character ! */
552 if (status & BD_SC_OV)
553 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
554#ifdef SUPPORT_SYSRQ
555 port->sysrq = 0;
556#endif
557 goto error_return;
558}
559
560/* Interrupt handler
561 *
562 * This interrupt handler is called after a BD is processed.
563 */
564static irqreturn_t qe_uart_int(int irq, void *data)
565{
566 struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
567 struct ucc_slow __iomem *uccp = qe_port->uccp;
568 u16 events;
569
570 /* Clear the interrupts */
571 events = in_be16(&uccp->ucce);
572 out_be16(&uccp->ucce, events);
573
574 if (events & UCC_UART_UCCE_BRKE)
575 uart_handle_break(&qe_port->port);
576
577 if (events & UCC_UART_UCCE_RX)
578 qe_uart_int_rx(qe_port);
579
580 if (events & UCC_UART_UCCE_TX)
581 qe_uart_tx_pump(qe_port);
582
583 return events ? IRQ_HANDLED : IRQ_NONE;
584}
585
586/* Initialize buffer descriptors
587 *
588 * This function initializes all of the RX and TX buffer descriptors.
589 */
590static void qe_uart_initbd(struct uart_qe_port *qe_port)
591{
592 int i;
593 void *bd_virt;
594 struct qe_bd *bdp;
595
596 /* Set the physical address of the host memory buffers in the buffer
597 * descriptors, and the virtual address for us to work with.
598 */
599 bd_virt = qe_port->bd_virt;
600 bdp = qe_port->rx_bd_base;
601 qe_port->rx_cur = qe_port->rx_bd_base;
602 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
603 out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
604 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
605 out_be16(&bdp->length, 0);
606 bd_virt += qe_port->rx_fifosize;
607 bdp++;
608 }
609
610 /* */
611 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
612 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
613 out_be16(&bdp->length, 0);
614
615 /* Set the physical address of the host memory
616 * buffers in the buffer descriptors, and the
617 * virtual address for us to work with.
618 */
619 bd_virt = qe_port->bd_virt +
620 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
621 qe_port->tx_cur = qe_port->tx_bd_base;
622 bdp = qe_port->tx_bd_base;
623 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
624 out_be16(&bdp->status, BD_SC_INTRPT);
625 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
626 out_be16(&bdp->length, 0);
627 bd_virt += qe_port->tx_fifosize;
628 bdp++;
629 }
630
631 /* Loopback requires the preamble bit to be set on the first TX BD */
632#ifdef LOOPBACK
633 setbits16(&qe_port->tx_cur->status, BD_SC_P);
634#endif
635
636 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
637 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
638 out_be16(&bdp->length, 0);
639}
640
641/*
642 * Initialize a UCC for UART.
643 *
644 * This function configures a given UCC to be used as a UART device. Basic
645 * UCC initialization is handled in qe_uart_request_port(). This function
646 * does all the UART-specific stuff.
647 */
648static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
649{
650 u32 cecr_subblock;
651 struct ucc_slow __iomem *uccp = qe_port->uccp;
652 struct ucc_uart_pram *uccup = qe_port->uccup;
653
654 unsigned int i;
655
656 /* First, disable TX and RX in the UCC */
657 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
658
659 /* Program the UCC UART parameter RAM */
660 out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
661 out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
662 out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
663 out_be16(&uccup->maxidl, 0x10);
664 out_be16(&uccup->brkcr, 1);
665 out_be16(&uccup->parec, 0);
666 out_be16(&uccup->frmec, 0);
667 out_be16(&uccup->nosec, 0);
668 out_be16(&uccup->brkec, 0);
669 out_be16(&uccup->uaddr[0], 0);
670 out_be16(&uccup->uaddr[1], 0);
671 out_be16(&uccup->toseq, 0);
672 for (i = 0; i < 8; i++)
673 out_be16(&uccup->cchars[i], 0xC000);
674 out_be16(&uccup->rccm, 0xc0ff);
675
676 /* Configure the GUMR registers for UART */
677 if (soft_uart) {
678 /* Soft-UART requires a 1X multiplier for TX */
679 clrsetbits_be32(&uccp->gumr_l,
680 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
681 UCC_SLOW_GUMR_L_RDCR_MASK,
682 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
683 UCC_SLOW_GUMR_L_RDCR_16);
684
685 clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
686 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
687 } else {
688 clrsetbits_be32(&uccp->gumr_l,
689 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
690 UCC_SLOW_GUMR_L_RDCR_MASK,
691 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
692 UCC_SLOW_GUMR_L_RDCR_16);
693
694 clrsetbits_be32(&uccp->gumr_h,
695 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
696 UCC_SLOW_GUMR_H_RFW);
697 }
698
699#ifdef LOOPBACK
700 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
701 UCC_SLOW_GUMR_L_DIAG_LOOP);
702 clrsetbits_be32(&uccp->gumr_h,
703 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
704 UCC_SLOW_GUMR_H_CDS);
705#endif
706
707 /* Disable rx interrupts and clear all pending events. */
708 out_be16(&uccp->uccm, 0);
709 out_be16(&uccp->ucce, 0xffff);
710 out_be16(&uccp->udsr, 0x7e7e);
711
712 /* Initialize UPSMR */
713 out_be16(&uccp->upsmr, 0);
714
715 if (soft_uart) {
716 out_be16(&uccup->supsmr, 0x30);
717 out_be16(&uccup->res92, 0);
718 out_be32(&uccup->rx_state, 0);
719 out_be32(&uccup->rx_cnt, 0);
720 out_8(&uccup->rx_bitmark, 0);
721 out_8(&uccup->rx_length, 10);
722 out_be32(&uccup->dump_ptr, 0x4000);
723 out_8(&uccup->rx_temp_dlst_qe, 0);
724 out_be32(&uccup->rx_frame_rem, 0);
725 out_8(&uccup->rx_frame_rem_size, 0);
726 /* Soft-UART requires TX to be 1X */
727 out_8(&uccup->tx_mode,
728 UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
729 out_be16(&uccup->tx_state, 0);
730 out_8(&uccup->resD4, 0);
731 out_be16(&uccup->resD5, 0);
732
733 /* Set UART mode.
734 * Enable receive and transmit.
735 */
736
737 /* From the microcode errata:
738 * 1.GUMR_L register, set mode=0010 (QMC).
739 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
740 * 3.Set GUMR_H[19:20] (Transparent mode)
741 * 4.Clear GUMR_H[26] (RFW)
742 * ...
743 * 6.Receiver must use 16x over sampling
744 */
745 clrsetbits_be32(&uccp->gumr_l,
746 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
747 UCC_SLOW_GUMR_L_RDCR_MASK,
748 UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
749 UCC_SLOW_GUMR_L_RDCR_16);
750
751 clrsetbits_be32(&uccp->gumr_h,
752 UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
753 UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
754 UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
755
756#ifdef LOOPBACK
757 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
758 UCC_SLOW_GUMR_L_DIAG_LOOP);
759 clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
760 UCC_SLOW_GUMR_H_CDS);
761#endif
762
763 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
764 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
765 QE_CR_PROTOCOL_UNSPECIFIED, 0);
766 } else {
767 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
768 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
769 QE_CR_PROTOCOL_UART, 0);
770 }
771}
772
773/*
774 * Initialize the port.
775 */
776static int qe_uart_startup(struct uart_port *port)
777{
778 struct uart_qe_port *qe_port =
779 container_of(port, struct uart_qe_port, port);
780 int ret;
781
782 /*
783 * If we're using Soft-UART mode, then we need to make sure the
784 * firmware has been uploaded first.
785 */
786 if (soft_uart && !firmware_loaded) {
787 dev_err(port->dev, "Soft-UART firmware not uploaded\n");
788 return -ENODEV;
789 }
790
791 qe_uart_initbd(qe_port);
792 qe_uart_init_ucc(qe_port);
793
794 /* Install interrupt handler. */
795 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
796 qe_port);
797 if (ret) {
798 dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
799 return ret;
800 }
801
802 /* Startup rx-int */
803 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
804 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
805
806 return 0;
807}
808
809/*
810 * Shutdown the port.
811 */
812static void qe_uart_shutdown(struct uart_port *port)
813{
814 struct uart_qe_port *qe_port =
815 container_of(port, struct uart_qe_port, port);
816 struct ucc_slow __iomem *uccp = qe_port->uccp;
817 unsigned int timeout = 20;
818
819 /* Disable RX and TX */
820
821 /* Wait for all the BDs marked sent */
822 while (!qe_uart_tx_empty(port)) {
823 if (!--timeout) {
824 dev_warn(port->dev, "shutdown timeout\n");
825 break;
826 }
827 set_current_state(TASK_UNINTERRUPTIBLE);
828 schedule_timeout(2);
829 }
830
831 if (qe_port->wait_closing) {
832 /* Wait a bit longer */
833 set_current_state(TASK_UNINTERRUPTIBLE);
834 schedule_timeout(qe_port->wait_closing);
835 }
836
837 /* Stop uarts */
838 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
839 clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
840
841 /* Shut them really down and reinit buffer descriptors */
842 ucc_slow_graceful_stop_tx(qe_port->us_private);
843 qe_uart_initbd(qe_port);
844
845 free_irq(port->irq, qe_port);
846}
847
848/*
849 * Set the serial port parameters.
850 */
851static void qe_uart_set_termios(struct uart_port *port,
852 struct ktermios *termios, struct ktermios *old)
853{
854 struct uart_qe_port *qe_port =
855 container_of(port, struct uart_qe_port, port);
856 struct ucc_slow __iomem *uccp = qe_port->uccp;
857 unsigned int baud;
858 unsigned long flags;
859 u16 upsmr = in_be16(&uccp->upsmr);
860 struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
861 u16 supsmr = in_be16(&uccup->supsmr);
862 u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
863
864 /* Character length programmed into the mode register is the
865 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
866 * 1 or 2 stop bits, minus 1.
867 * The value 'bits' counts this for us.
868 */
869
870 /* byte size */
871 upsmr &= UCC_UART_UPSMR_CL_MASK;
872 supsmr &= UCC_UART_SUPSMR_CL_MASK;
873
874 switch (termios->c_cflag & CSIZE) {
875 case CS5:
876 upsmr |= UCC_UART_UPSMR_CL_5;
877 supsmr |= UCC_UART_SUPSMR_CL_5;
878 char_length += 5;
879 break;
880 case CS6:
881 upsmr |= UCC_UART_UPSMR_CL_6;
882 supsmr |= UCC_UART_SUPSMR_CL_6;
883 char_length += 6;
884 break;
885 case CS7:
886 upsmr |= UCC_UART_UPSMR_CL_7;
887 supsmr |= UCC_UART_SUPSMR_CL_7;
888 char_length += 7;
889 break;
890 default: /* case CS8 */
891 upsmr |= UCC_UART_UPSMR_CL_8;
892 supsmr |= UCC_UART_SUPSMR_CL_8;
893 char_length += 8;
894 break;
895 }
896
897 /* If CSTOPB is set, we want two stop bits */
898 if (termios->c_cflag & CSTOPB) {
899 upsmr |= UCC_UART_UPSMR_SL;
900 supsmr |= UCC_UART_SUPSMR_SL;
901 char_length++; /* + SL */
902 }
903
904 if (termios->c_cflag & PARENB) {
905 upsmr |= UCC_UART_UPSMR_PEN;
906 supsmr |= UCC_UART_SUPSMR_PEN;
907 char_length++; /* + PEN */
908
909 if (!(termios->c_cflag & PARODD)) {
910 upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
911 UCC_UART_UPSMR_TPM_MASK);
912 upsmr |= UCC_UART_UPSMR_RPM_EVEN |
913 UCC_UART_UPSMR_TPM_EVEN;
914 supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
915 UCC_UART_SUPSMR_TPM_MASK);
916 supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
917 UCC_UART_SUPSMR_TPM_EVEN;
918 }
919 }
920
921 /*
922 * Set up parity check flag
923 */
924 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
925 if (termios->c_iflag & INPCK)
926 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
927 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
928 port->read_status_mask |= BD_SC_BR;
929
930 /*
931 * Characters to ignore
932 */
933 port->ignore_status_mask = 0;
934 if (termios->c_iflag & IGNPAR)
935 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
936 if (termios->c_iflag & IGNBRK) {
937 port->ignore_status_mask |= BD_SC_BR;
938 /*
939 * If we're ignore parity and break indicators, ignore
940 * overruns too. (For real raw support).
941 */
942 if (termios->c_iflag & IGNPAR)
943 port->ignore_status_mask |= BD_SC_OV;
944 }
945 /*
946 * !!! ignore all characters if CREAD is not set
947 */
948 if ((termios->c_cflag & CREAD) == 0)
949 port->read_status_mask &= ~BD_SC_EMPTY;
950
951 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
952
953 /* Do we really need a spinlock here? */
954 spin_lock_irqsave(&port->lock, flags);
955
956 /* Update the per-port timeout. */
957 uart_update_timeout(port, termios->c_cflag, baud);
958
959 out_be16(&uccp->upsmr, upsmr);
960 if (soft_uart) {
961 out_be16(&uccup->supsmr, supsmr);
962 out_8(&uccup->rx_length, char_length);
963
964 /* Soft-UART requires a 1X multiplier for TX */
965 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
966 qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
967 } else {
968 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
969 qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
970 }
971
972 spin_unlock_irqrestore(&port->lock, flags);
973}
974
975/*
976 * Return a pointer to a string that describes what kind of port this is.
977 */
978static const char *qe_uart_type(struct uart_port *port)
979{
980 return "QE";
981}
982
983/*
984 * Allocate any memory and I/O resources required by the port.
985 */
986static int qe_uart_request_port(struct uart_port *port)
987{
988 int ret;
989 struct uart_qe_port *qe_port =
990 container_of(port, struct uart_qe_port, port);
991 struct ucc_slow_info *us_info = &qe_port->us_info;
992 struct ucc_slow_private *uccs;
993 unsigned int rx_size, tx_size;
994 void *bd_virt;
995 dma_addr_t bd_dma_addr = 0;
996
997 ret = ucc_slow_init(us_info, &uccs);
998 if (ret) {
999 dev_err(port->dev, "could not initialize UCC%u\n",
1000 qe_port->ucc_num);
1001 return ret;
1002 }
1003
1004 qe_port->us_private = uccs;
1005 qe_port->uccp = uccs->us_regs;
1006 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
1007 qe_port->rx_bd_base = uccs->rx_bd;
1008 qe_port->tx_bd_base = uccs->tx_bd;
1009
1010 /*
1011 * Allocate the transmit and receive data buffers.
1012 */
1013
1014 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
1015 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
1016
1017 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
1018 GFP_KERNEL);
1019 if (!bd_virt) {
1020 dev_err(port->dev, "could not allocate buffer descriptors\n");
1021 return -ENOMEM;
1022 }
1023
1024 qe_port->bd_virt = bd_virt;
1025 qe_port->bd_dma_addr = bd_dma_addr;
1026 qe_port->bd_size = rx_size + tx_size;
1027
1028 qe_port->rx_buf = bd_virt;
1029 qe_port->tx_buf = qe_port->rx_buf + rx_size;
1030
1031 return 0;
1032}
1033
1034/*
1035 * Configure the port.
1036 *
1037 * We say we're a CPM-type port because that's mostly true. Once the device
1038 * is configured, this driver operates almost identically to the CPM serial
1039 * driver.
1040 */
1041static void qe_uart_config_port(struct uart_port *port, int flags)
1042{
1043 if (flags & UART_CONFIG_TYPE) {
1044 port->type = PORT_CPM;
1045 qe_uart_request_port(port);
1046 }
1047}
1048
1049/*
1050 * Release any memory and I/O resources that were allocated in
1051 * qe_uart_request_port().
1052 */
1053static void qe_uart_release_port(struct uart_port *port)
1054{
1055 struct uart_qe_port *qe_port =
1056 container_of(port, struct uart_qe_port, port);
1057 struct ucc_slow_private *uccs = qe_port->us_private;
1058
1059 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1060 qe_port->bd_dma_addr);
1061
1062 ucc_slow_free(uccs);
1063}
1064
1065/*
1066 * Verify that the data in serial_struct is suitable for this device.
1067 */
1068static int qe_uart_verify_port(struct uart_port *port,
1069 struct serial_struct *ser)
1070{
1071 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1072 return -EINVAL;
1073
1074 if (ser->irq < 0 || ser->irq >= nr_irqs)
1075 return -EINVAL;
1076
1077 if (ser->baud_base < 9600)
1078 return -EINVAL;
1079
1080 return 0;
1081}
1082/* UART operations
1083 *
1084 * Details on these functions can be found in Documentation/driver-api/serial/driver.rst
1085 */
1086static const struct uart_ops qe_uart_pops = {
1087 .tx_empty = qe_uart_tx_empty,
1088 .set_mctrl = qe_uart_set_mctrl,
1089 .get_mctrl = qe_uart_get_mctrl,
1090 .stop_tx = qe_uart_stop_tx,
1091 .start_tx = qe_uart_start_tx,
1092 .stop_rx = qe_uart_stop_rx,
1093 .break_ctl = qe_uart_break_ctl,
1094 .startup = qe_uart_startup,
1095 .shutdown = qe_uart_shutdown,
1096 .set_termios = qe_uart_set_termios,
1097 .type = qe_uart_type,
1098 .release_port = qe_uart_release_port,
1099 .request_port = qe_uart_request_port,
1100 .config_port = qe_uart_config_port,
1101 .verify_port = qe_uart_verify_port,
1102};
1103
1104/*
1105 * Obtain the SOC model number and revision level
1106 *
1107 * This function parses the device tree to obtain the SOC model. It then
1108 * reads the SVR register to the revision.
1109 *
1110 * The device tree stores the SOC model two different ways.
1111 *
1112 * The new way is:
1113 *
1114 * cpu@0 {
1115 * compatible = "PowerPC,8323";
1116 * device_type = "cpu";
1117 * ...
1118 *
1119 *
1120 * The old way is:
1121 * PowerPC,8323@0 {
1122 * device_type = "cpu";
1123 * ...
1124 *
1125 * This code first checks the new way, and then the old way.
1126 */
1127static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1128{
1129 struct device_node *np;
1130 const char *soc_string;
1131 unsigned int svr;
1132 unsigned int soc;
1133
1134 /* Find the CPU node */
1135 np = of_find_node_by_type(NULL, "cpu");
1136 if (!np)
1137 return 0;
1138 /* Find the compatible property */
1139 soc_string = of_get_property(np, "compatible", NULL);
1140 if (!soc_string)
1141 /* No compatible property, so try the name. */
1142 soc_string = np->name;
1143
1144 /* Extract the SOC number from the "PowerPC," string */
1145 if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1146 return 0;
1147
1148 /* Get the revision from the SVR */
1149 svr = mfspr(SPRN_SVR);
1150 *rev_h = (svr >> 4) & 0xf;
1151 *rev_l = svr & 0xf;
1152
1153 return soc;
1154}
1155
1156/*
1157 * requst_firmware_nowait() callback function
1158 *
1159 * This function is called by the kernel when a firmware is made available,
1160 * or if it times out waiting for the firmware.
1161 */
1162static void uart_firmware_cont(const struct firmware *fw, void *context)
1163{
1164 struct qe_firmware *firmware;
1165 struct device *dev = context;
1166 int ret;
1167
1168 if (!fw) {
1169 dev_err(dev, "firmware not found\n");
1170 return;
1171 }
1172
1173 firmware = (struct qe_firmware *) fw->data;
1174
1175 if (firmware->header.length != fw->size) {
1176 dev_err(dev, "invalid firmware\n");
1177 goto out;
1178 }
1179
1180 ret = qe_upload_firmware(firmware);
1181 if (ret) {
1182 dev_err(dev, "could not load firmware\n");
1183 goto out;
1184 }
1185
1186 firmware_loaded = 1;
1187 out:
1188 release_firmware(fw);
1189}
1190
1191static int ucc_uart_probe(struct platform_device *ofdev)
1192{
1193 struct device_node *np = ofdev->dev.of_node;
1194 const unsigned int *iprop; /* Integer OF properties */
1195 const char *sprop; /* String OF properties */
1196 struct uart_qe_port *qe_port = NULL;
1197 struct resource res;
1198 int ret;
1199
1200 /*
1201 * Determine if we need Soft-UART mode
1202 */
1203 if (of_find_property(np, "soft-uart", NULL)) {
1204 dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1205 soft_uart = 1;
1206 }
1207
1208 /*
1209 * If we are using Soft-UART, determine if we need to upload the
1210 * firmware, too.
1211 */
1212 if (soft_uart) {
1213 struct qe_firmware_info *qe_fw_info;
1214
1215 qe_fw_info = qe_get_firmware_info();
1216
1217 /* Check if the firmware has been uploaded. */
1218 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1219 firmware_loaded = 1;
1220 } else {
1221 char filename[32];
1222 unsigned int soc;
1223 unsigned int rev_h;
1224 unsigned int rev_l;
1225
1226 soc = soc_info(&rev_h, &rev_l);
1227 if (!soc) {
1228 dev_err(&ofdev->dev, "unknown CPU model\n");
1229 return -ENXIO;
1230 }
1231 sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1232 soc, rev_h, rev_l);
1233
1234 dev_info(&ofdev->dev, "waiting for firmware %s\n",
1235 filename);
1236
1237 /*
1238 * We call request_firmware_nowait instead of
1239 * request_firmware so that the driver can load and
1240 * initialize the ports without holding up the rest of
1241 * the kernel. If hotplug support is enabled in the
1242 * kernel, then we use it.
1243 */
1244 ret = request_firmware_nowait(THIS_MODULE,
1245 FW_ACTION_HOTPLUG, filename, &ofdev->dev,
1246 GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1247 if (ret) {
1248 dev_err(&ofdev->dev,
1249 "could not load firmware %s\n",
1250 filename);
1251 return ret;
1252 }
1253 }
1254 }
1255
1256 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1257 if (!qe_port) {
1258 dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1259 return -ENOMEM;
1260 }
1261
1262 /* Search for IRQ and mapbase */
1263 ret = of_address_to_resource(np, 0, &res);
1264 if (ret) {
1265 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1266 goto out_free;
1267 }
1268 if (!res.start) {
1269 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1270 ret = -EINVAL;
1271 goto out_free;
1272 }
1273 qe_port->port.mapbase = res.start;
1274
1275 /* Get the UCC number (device ID) */
1276 /* UCCs are numbered 1-7 */
1277 iprop = of_get_property(np, "cell-index", NULL);
1278 if (!iprop) {
1279 iprop = of_get_property(np, "device-id", NULL);
1280 if (!iprop) {
1281 dev_err(&ofdev->dev, "UCC is unspecified in "
1282 "device tree\n");
1283 ret = -EINVAL;
1284 goto out_free;
1285 }
1286 }
1287
1288 if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
1289 dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
1290 ret = -ENODEV;
1291 goto out_free;
1292 }
1293 qe_port->ucc_num = *iprop - 1;
1294
1295 /*
1296 * In the future, we should not require the BRG to be specified in the
1297 * device tree. If no clock-source is specified, then just pick a BRG
1298 * to use. This requires a new QE library function that manages BRG
1299 * assignments.
1300 */
1301
1302 sprop = of_get_property(np, "rx-clock-name", NULL);
1303 if (!sprop) {
1304 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1305 ret = -ENODEV;
1306 goto out_free;
1307 }
1308
1309 qe_port->us_info.rx_clock = qe_clock_source(sprop);
1310 if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1311 (qe_port->us_info.rx_clock > QE_BRG16)) {
1312 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1313 ret = -ENODEV;
1314 goto out_free;
1315 }
1316
1317#ifdef LOOPBACK
1318 /* In internal loopback mode, TX and RX must use the same clock */
1319 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1320#else
1321 sprop = of_get_property(np, "tx-clock-name", NULL);
1322 if (!sprop) {
1323 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1324 ret = -ENODEV;
1325 goto out_free;
1326 }
1327 qe_port->us_info.tx_clock = qe_clock_source(sprop);
1328#endif
1329 if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1330 (qe_port->us_info.tx_clock > QE_BRG16)) {
1331 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1332 ret = -ENODEV;
1333 goto out_free;
1334 }
1335
1336 /* Get the port number, numbered 0-3 */
1337 iprop = of_get_property(np, "port-number", NULL);
1338 if (!iprop) {
1339 dev_err(&ofdev->dev, "missing port-number in device tree\n");
1340 ret = -EINVAL;
1341 goto out_free;
1342 }
1343 qe_port->port.line = *iprop;
1344 if (qe_port->port.line >= UCC_MAX_UART) {
1345 dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1346 UCC_MAX_UART - 1);
1347 ret = -EINVAL;
1348 goto out_free;
1349 }
1350
1351 qe_port->port.irq = irq_of_parse_and_map(np, 0);
1352 if (qe_port->port.irq == 0) {
1353 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1354 qe_port->ucc_num + 1);
1355 ret = -EINVAL;
1356 goto out_free;
1357 }
1358
1359 /*
1360 * Newer device trees have an "fsl,qe" compatible property for the QE
1361 * node, but we still need to support older device trees.
1362 */
1363 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1364 if (!np) {
1365 np = of_find_node_by_type(NULL, "qe");
1366 if (!np) {
1367 dev_err(&ofdev->dev, "could not find 'qe' node\n");
1368 ret = -EINVAL;
1369 goto out_free;
1370 }
1371 }
1372
1373 iprop = of_get_property(np, "brg-frequency", NULL);
1374 if (!iprop) {
1375 dev_err(&ofdev->dev,
1376 "missing brg-frequency in device tree\n");
1377 ret = -EINVAL;
1378 goto out_np;
1379 }
1380
1381 if (*iprop)
1382 qe_port->port.uartclk = *iprop;
1383 else {
1384 /*
1385 * Older versions of U-Boot do not initialize the brg-frequency
1386 * property, so in this case we assume the BRG frequency is
1387 * half the QE bus frequency.
1388 */
1389 iprop = of_get_property(np, "bus-frequency", NULL);
1390 if (!iprop) {
1391 dev_err(&ofdev->dev,
1392 "missing QE bus-frequency in device tree\n");
1393 ret = -EINVAL;
1394 goto out_np;
1395 }
1396 if (*iprop)
1397 qe_port->port.uartclk = *iprop / 2;
1398 else {
1399 dev_err(&ofdev->dev,
1400 "invalid QE bus-frequency in device tree\n");
1401 ret = -EINVAL;
1402 goto out_np;
1403 }
1404 }
1405
1406 spin_lock_init(&qe_port->port.lock);
1407 qe_port->np = np;
1408 qe_port->port.dev = &ofdev->dev;
1409 qe_port->port.ops = &qe_uart_pops;
1410 qe_port->port.iotype = UPIO_MEM;
1411
1412 qe_port->tx_nrfifos = TX_NUM_FIFO;
1413 qe_port->tx_fifosize = TX_BUF_SIZE;
1414 qe_port->rx_nrfifos = RX_NUM_FIFO;
1415 qe_port->rx_fifosize = RX_BUF_SIZE;
1416
1417 qe_port->wait_closing = UCC_WAIT_CLOSING;
1418 qe_port->port.fifosize = 512;
1419 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1420
1421 qe_port->us_info.ucc_num = qe_port->ucc_num;
1422 qe_port->us_info.regs = (phys_addr_t) res.start;
1423 qe_port->us_info.irq = qe_port->port.irq;
1424
1425 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1426 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1427
1428 /* Make sure ucc_slow_init() initializes both TX and RX */
1429 qe_port->us_info.init_tx = 1;
1430 qe_port->us_info.init_rx = 1;
1431
1432 /* Add the port to the uart sub-system. This will cause
1433 * qe_uart_config_port() to be called, so the us_info structure must
1434 * be initialized.
1435 */
1436 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1437 if (ret) {
1438 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1439 qe_port->port.line);
1440 goto out_np;
1441 }
1442
1443 platform_set_drvdata(ofdev, qe_port);
1444
1445 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1446 qe_port->ucc_num + 1, qe_port->port.line);
1447
1448 /* Display the mknod command for this device */
1449 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1450 qe_port->port.line, SERIAL_QE_MAJOR,
1451 SERIAL_QE_MINOR + qe_port->port.line);
1452
1453 return 0;
1454out_np:
1455 of_node_put(np);
1456out_free:
1457 kfree(qe_port);
1458 return ret;
1459}
1460
1461static int ucc_uart_remove(struct platform_device *ofdev)
1462{
1463 struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
1464
1465 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1466
1467 uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1468
1469 kfree(qe_port);
1470
1471 return 0;
1472}
1473
1474static const struct of_device_id ucc_uart_match[] = {
1475 {
1476 .type = "serial",
1477 .compatible = "ucc_uart",
1478 },
1479 {
1480 .compatible = "fsl,t1040-ucc-uart",
1481 },
1482 {},
1483};
1484MODULE_DEVICE_TABLE(of, ucc_uart_match);
1485
1486static struct platform_driver ucc_uart_of_driver = {
1487 .driver = {
1488 .name = "ucc_uart",
1489 .of_match_table = ucc_uart_match,
1490 },
1491 .probe = ucc_uart_probe,
1492 .remove = ucc_uart_remove,
1493};
1494
1495static int __init ucc_uart_init(void)
1496{
1497 int ret;
1498
1499 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1500#ifdef LOOPBACK
1501 printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1502#endif
1503
1504 ret = uart_register_driver(&ucc_uart_driver);
1505 if (ret) {
1506 printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1507 return ret;
1508 }
1509
1510 ret = platform_driver_register(&ucc_uart_of_driver);
1511 if (ret) {
1512 printk(KERN_ERR
1513 "ucc-uart: could not register platform driver\n");
1514 uart_unregister_driver(&ucc_uart_driver);
1515 }
1516
1517 return ret;
1518}
1519
1520static void __exit ucc_uart_exit(void)
1521{
1522 printk(KERN_INFO
1523 "Freescale QUICC Engine UART device driver unloading\n");
1524
1525 platform_driver_unregister(&ucc_uart_of_driver);
1526 uart_unregister_driver(&ucc_uart_driver);
1527}
1528
1529module_init(ucc_uart_init);
1530module_exit(ucc_uart_exit);
1531
1532MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1533MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1534MODULE_LICENSE("GPL v2");
1535MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1536
1/*
2 * Freescale QUICC Engine UART device driver
3 *
4 * Author: Timur Tabi <timur@freescale.com>
5 *
6 * Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * This driver adds support for UART devices via Freescale's QUICC Engine
12 * found on some Freescale SOCs.
13 *
14 * If Soft-UART support is needed but not already present, then this driver
15 * will request and upload the "Soft-UART" microcode upon probe. The
16 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
17 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
18 * (e.g. "11" for 1.1).
19 */
20
21#include <linux/module.h>
22#include <linux/serial.h>
23#include <linux/serial_core.h>
24#include <linux/slab.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/io.h>
28#include <linux/of_platform.h>
29#include <linux/dma-mapping.h>
30
31#include <linux/fs_uart_pd.h>
32#include <asm/ucc_slow.h>
33
34#include <linux/firmware.h>
35#include <asm/reg.h>
36
37/*
38 * The GUMR flag for Soft UART. This would normally be defined in qe.h,
39 * but Soft-UART is a hack and we want to keep everything related to it in
40 * this file.
41 */
42#define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */
43
44/*
45 * soft_uart is 1 if we need to use Soft-UART mode
46 */
47static int soft_uart;
48/*
49 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
50 */
51static int firmware_loaded;
52
53/* Enable this macro to configure all serial ports in internal loopback
54 mode */
55/* #define LOOPBACK */
56
57/* The major and minor device numbers are defined in
58 * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE
59 * UART, we have major number 204 and minor numbers 46 - 49, which are the
60 * same as for the CPM2. This decision was made because no Freescale part
61 * has both a CPM and a QE.
62 */
63#define SERIAL_QE_MAJOR 204
64#define SERIAL_QE_MINOR 46
65
66/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
67#define UCC_MAX_UART 4
68
69/* The number of buffer descriptors for receiving characters. */
70#define RX_NUM_FIFO 4
71
72/* The number of buffer descriptors for transmitting characters. */
73#define TX_NUM_FIFO 4
74
75/* The maximum size of the character buffer for a single RX BD. */
76#define RX_BUF_SIZE 32
77
78/* The maximum size of the character buffer for a single TX BD. */
79#define TX_BUF_SIZE 32
80
81/*
82 * The number of jiffies to wait after receiving a close command before the
83 * device is actually closed. This allows the last few characters to be
84 * sent over the wire.
85 */
86#define UCC_WAIT_CLOSING 100
87
88struct ucc_uart_pram {
89 struct ucc_slow_pram common;
90 u8 res1[8]; /* reserved */
91 __be16 maxidl; /* Maximum idle chars */
92 __be16 idlc; /* temp idle counter */
93 __be16 brkcr; /* Break count register */
94 __be16 parec; /* receive parity error counter */
95 __be16 frmec; /* receive framing error counter */
96 __be16 nosec; /* receive noise counter */
97 __be16 brkec; /* receive break condition counter */
98 __be16 brkln; /* last received break length */
99 __be16 uaddr[2]; /* UART address character 1 & 2 */
100 __be16 rtemp; /* Temp storage */
101 __be16 toseq; /* Transmit out of sequence char */
102 __be16 cchars[8]; /* control characters 1-8 */
103 __be16 rccm; /* receive control character mask */
104 __be16 rccr; /* receive control character register */
105 __be16 rlbc; /* receive last break character */
106 __be16 res2; /* reserved */
107 __be32 res3; /* reserved, should be cleared */
108 u8 res4; /* reserved, should be cleared */
109 u8 res5[3]; /* reserved, should be cleared */
110 __be32 res6; /* reserved, should be cleared */
111 __be32 res7; /* reserved, should be cleared */
112 __be32 res8; /* reserved, should be cleared */
113 __be32 res9; /* reserved, should be cleared */
114 __be32 res10; /* reserved, should be cleared */
115 __be32 res11; /* reserved, should be cleared */
116 __be32 res12; /* reserved, should be cleared */
117 __be32 res13; /* reserved, should be cleared */
118/* The rest is for Soft-UART only */
119 __be16 supsmr; /* 0x90, Shadow UPSMR */
120 __be16 res92; /* 0x92, reserved, initialize to 0 */
121 __be32 rx_state; /* 0x94, RX state, initialize to 0 */
122 __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */
123 u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */
124 u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */
125 u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */
126 u8 res14[0xBC - 0x9F]; /* reserved */
127 __be32 dump_ptr; /* 0xBC, Dump pointer */
128 __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */
129 u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */
130 u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */
131 __be16 tx_state; /* 0xC6, TX state */
132 u8 res15[0xD0 - 0xC8]; /* reserved */
133 __be32 resD0; /* 0xD0, reserved, initialize to 0 */
134 u8 resD4; /* 0xD4, reserved, initialize to 0 */
135 __be16 resD5; /* 0xD5, reserved, initialize to 0 */
136} __attribute__ ((packed));
137
138/* SUPSMR definitions, for Soft-UART only */
139#define UCC_UART_SUPSMR_SL 0x8000
140#define UCC_UART_SUPSMR_RPM_MASK 0x6000
141#define UCC_UART_SUPSMR_RPM_ODD 0x0000
142#define UCC_UART_SUPSMR_RPM_LOW 0x2000
143#define UCC_UART_SUPSMR_RPM_EVEN 0x4000
144#define UCC_UART_SUPSMR_RPM_HIGH 0x6000
145#define UCC_UART_SUPSMR_PEN 0x1000
146#define UCC_UART_SUPSMR_TPM_MASK 0x0C00
147#define UCC_UART_SUPSMR_TPM_ODD 0x0000
148#define UCC_UART_SUPSMR_TPM_LOW 0x0400
149#define UCC_UART_SUPSMR_TPM_EVEN 0x0800
150#define UCC_UART_SUPSMR_TPM_HIGH 0x0C00
151#define UCC_UART_SUPSMR_FRZ 0x0100
152#define UCC_UART_SUPSMR_UM_MASK 0x00c0
153#define UCC_UART_SUPSMR_UM_NORMAL 0x0000
154#define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040
155#define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0
156#define UCC_UART_SUPSMR_CL_MASK 0x0030
157#define UCC_UART_SUPSMR_CL_8 0x0030
158#define UCC_UART_SUPSMR_CL_7 0x0020
159#define UCC_UART_SUPSMR_CL_6 0x0010
160#define UCC_UART_SUPSMR_CL_5 0x0000
161
162#define UCC_UART_TX_STATE_AHDLC 0x00
163#define UCC_UART_TX_STATE_UART 0x01
164#define UCC_UART_TX_STATE_X1 0x00
165#define UCC_UART_TX_STATE_X16 0x80
166
167#define UCC_UART_PRAM_ALIGNMENT 0x100
168
169#define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD
170#define NUM_CONTROL_CHARS 8
171
172/* Private per-port data structure */
173struct uart_qe_port {
174 struct uart_port port;
175 struct ucc_slow __iomem *uccp;
176 struct ucc_uart_pram __iomem *uccup;
177 struct ucc_slow_info us_info;
178 struct ucc_slow_private *us_private;
179 struct device_node *np;
180 unsigned int ucc_num; /* First ucc is 0, not 1 */
181
182 u16 rx_nrfifos;
183 u16 rx_fifosize;
184 u16 tx_nrfifos;
185 u16 tx_fifosize;
186 int wait_closing;
187 u32 flags;
188 struct qe_bd *rx_bd_base;
189 struct qe_bd *rx_cur;
190 struct qe_bd *tx_bd_base;
191 struct qe_bd *tx_cur;
192 unsigned char *tx_buf;
193 unsigned char *rx_buf;
194 void *bd_virt; /* virtual address of the BD buffers */
195 dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
196 unsigned int bd_size; /* size of BD buffer space */
197};
198
199static struct uart_driver ucc_uart_driver = {
200 .owner = THIS_MODULE,
201 .driver_name = "ucc_uart",
202 .dev_name = "ttyQE",
203 .major = SERIAL_QE_MAJOR,
204 .minor = SERIAL_QE_MINOR,
205 .nr = UCC_MAX_UART,
206};
207
208/*
209 * Virtual to physical address translation.
210 *
211 * Given the virtual address for a character buffer, this function returns
212 * the physical (DMA) equivalent.
213 */
214static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
215{
216 if (likely((addr >= qe_port->bd_virt)) &&
217 (addr < (qe_port->bd_virt + qe_port->bd_size)))
218 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
219
220 /* something nasty happened */
221 printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
222 BUG();
223 return 0;
224}
225
226/*
227 * Physical to virtual address translation.
228 *
229 * Given the physical (DMA) address for a character buffer, this function
230 * returns the virtual equivalent.
231 */
232static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
233{
234 /* sanity check */
235 if (likely((addr >= qe_port->bd_dma_addr) &&
236 (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
237 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
238
239 /* something nasty happened */
240 printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
241 BUG();
242 return NULL;
243}
244
245/*
246 * Return 1 if the QE is done transmitting all buffers for this port
247 *
248 * This function scans each BD in sequence. If we find a BD that is not
249 * ready (READY=1), then we return 0 indicating that the QE is still sending
250 * data. If we reach the last BD (WRAP=1), then we know we've scanned
251 * the entire list, and all BDs are done.
252 */
253static unsigned int qe_uart_tx_empty(struct uart_port *port)
254{
255 struct uart_qe_port *qe_port =
256 container_of(port, struct uart_qe_port, port);
257 struct qe_bd *bdp = qe_port->tx_bd_base;
258
259 while (1) {
260 if (in_be16(&bdp->status) & BD_SC_READY)
261 /* This BD is not done, so return "not done" */
262 return 0;
263
264 if (in_be16(&bdp->status) & BD_SC_WRAP)
265 /*
266 * This BD is done and it's the last one, so return
267 * "done"
268 */
269 return 1;
270
271 bdp++;
272 };
273}
274
275/*
276 * Set the modem control lines
277 *
278 * Although the QE can control the modem control lines (e.g. CTS), we
279 * don't need that support. This function must exist, however, otherwise
280 * the kernel will panic.
281 */
282void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
283{
284}
285
286/*
287 * Get the current modem control line status
288 *
289 * Although the QE can control the modem control lines (e.g. CTS), this
290 * driver currently doesn't support that, so we always return Carrier
291 * Detect, Data Set Ready, and Clear To Send.
292 */
293static unsigned int qe_uart_get_mctrl(struct uart_port *port)
294{
295 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
296}
297
298/*
299 * Disable the transmit interrupt.
300 *
301 * Although this function is called "stop_tx", it does not actually stop
302 * transmission of data. Instead, it tells the QE to not generate an
303 * interrupt when the UCC is finished sending characters.
304 */
305static void qe_uart_stop_tx(struct uart_port *port)
306{
307 struct uart_qe_port *qe_port =
308 container_of(port, struct uart_qe_port, port);
309
310 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
311}
312
313/*
314 * Transmit as many characters to the HW as possible.
315 *
316 * This function will attempt to stuff of all the characters from the
317 * kernel's transmit buffer into TX BDs.
318 *
319 * A return value of non-zero indicates that it successfully stuffed all
320 * characters from the kernel buffer.
321 *
322 * A return value of zero indicates that there are still characters in the
323 * kernel's buffer that have not been transmitted, but there are no more BDs
324 * available. This function should be called again after a BD has been made
325 * available.
326 */
327static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
328{
329 struct qe_bd *bdp;
330 unsigned char *p;
331 unsigned int count;
332 struct uart_port *port = &qe_port->port;
333 struct circ_buf *xmit = &port->state->xmit;
334
335 bdp = qe_port->rx_cur;
336
337 /* Handle xon/xoff */
338 if (port->x_char) {
339 /* Pick next descriptor and fill from buffer */
340 bdp = qe_port->tx_cur;
341
342 p = qe2cpu_addr(bdp->buf, qe_port);
343
344 *p++ = port->x_char;
345 out_be16(&bdp->length, 1);
346 setbits16(&bdp->status, BD_SC_READY);
347 /* Get next BD. */
348 if (in_be16(&bdp->status) & BD_SC_WRAP)
349 bdp = qe_port->tx_bd_base;
350 else
351 bdp++;
352 qe_port->tx_cur = bdp;
353
354 port->icount.tx++;
355 port->x_char = 0;
356 return 1;
357 }
358
359 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
360 qe_uart_stop_tx(port);
361 return 0;
362 }
363
364 /* Pick next descriptor and fill from buffer */
365 bdp = qe_port->tx_cur;
366
367 while (!(in_be16(&bdp->status) & BD_SC_READY) &&
368 (xmit->tail != xmit->head)) {
369 count = 0;
370 p = qe2cpu_addr(bdp->buf, qe_port);
371 while (count < qe_port->tx_fifosize) {
372 *p++ = xmit->buf[xmit->tail];
373 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
374 port->icount.tx++;
375 count++;
376 if (xmit->head == xmit->tail)
377 break;
378 }
379
380 out_be16(&bdp->length, count);
381 setbits16(&bdp->status, BD_SC_READY);
382
383 /* Get next BD. */
384 if (in_be16(&bdp->status) & BD_SC_WRAP)
385 bdp = qe_port->tx_bd_base;
386 else
387 bdp++;
388 }
389 qe_port->tx_cur = bdp;
390
391 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
392 uart_write_wakeup(port);
393
394 if (uart_circ_empty(xmit)) {
395 /* The kernel buffer is empty, so turn off TX interrupts. We
396 don't need to be told when the QE is finished transmitting
397 the data. */
398 qe_uart_stop_tx(port);
399 return 0;
400 }
401
402 return 1;
403}
404
405/*
406 * Start transmitting data
407 *
408 * This function will start transmitting any available data, if the port
409 * isn't already transmitting data.
410 */
411static void qe_uart_start_tx(struct uart_port *port)
412{
413 struct uart_qe_port *qe_port =
414 container_of(port, struct uart_qe_port, port);
415
416 /* If we currently are transmitting, then just return */
417 if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
418 return;
419
420 /* Otherwise, pump the port and start transmission */
421 if (qe_uart_tx_pump(qe_port))
422 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
423}
424
425/*
426 * Stop transmitting data
427 */
428static void qe_uart_stop_rx(struct uart_port *port)
429{
430 struct uart_qe_port *qe_port =
431 container_of(port, struct uart_qe_port, port);
432
433 clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
434}
435
436/*
437 * Enable status change interrupts
438 *
439 * We don't support status change interrupts, but we need to define this
440 * function otherwise the kernel will panic.
441 */
442static void qe_uart_enable_ms(struct uart_port *port)
443{
444}
445
446/* Start or stop sending break signal
447 *
448 * This function controls the sending of a break signal. If break_state=1,
449 * then we start sending a break signal. If break_state=0, then we stop
450 * sending the break signal.
451 */
452static void qe_uart_break_ctl(struct uart_port *port, int break_state)
453{
454 struct uart_qe_port *qe_port =
455 container_of(port, struct uart_qe_port, port);
456
457 if (break_state)
458 ucc_slow_stop_tx(qe_port->us_private);
459 else
460 ucc_slow_restart_tx(qe_port->us_private);
461}
462
463/* ISR helper function for receiving character.
464 *
465 * This function is called by the ISR to handling receiving characters
466 */
467static void qe_uart_int_rx(struct uart_qe_port *qe_port)
468{
469 int i;
470 unsigned char ch, *cp;
471 struct uart_port *port = &qe_port->port;
472 struct tty_struct *tty = port->state->port.tty;
473 struct qe_bd *bdp;
474 u16 status;
475 unsigned int flg;
476
477 /* Just loop through the closed BDs and copy the characters into
478 * the buffer.
479 */
480 bdp = qe_port->rx_cur;
481 while (1) {
482 status = in_be16(&bdp->status);
483
484 /* If this one is empty, then we assume we've read them all */
485 if (status & BD_SC_EMPTY)
486 break;
487
488 /* get number of characters, and check space in RX buffer */
489 i = in_be16(&bdp->length);
490
491 /* If we don't have enough room in RX buffer for the entire BD,
492 * then we try later, which will be the next RX interrupt.
493 */
494 if (tty_buffer_request_room(tty, i) < i) {
495 dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
496 return;
497 }
498
499 /* get pointer */
500 cp = qe2cpu_addr(bdp->buf, qe_port);
501
502 /* loop through the buffer */
503 while (i-- > 0) {
504 ch = *cp++;
505 port->icount.rx++;
506 flg = TTY_NORMAL;
507
508 if (!i && status &
509 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
510 goto handle_error;
511 if (uart_handle_sysrq_char(port, ch))
512 continue;
513
514error_return:
515 tty_insert_flip_char(tty, ch, flg);
516
517 }
518
519 /* This BD is ready to be used again. Clear status. get next */
520 clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
521 BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
522 if (in_be16(&bdp->status) & BD_SC_WRAP)
523 bdp = qe_port->rx_bd_base;
524 else
525 bdp++;
526
527 }
528
529 /* Write back buffer pointer */
530 qe_port->rx_cur = bdp;
531
532 /* Activate BH processing */
533 tty_flip_buffer_push(tty);
534
535 return;
536
537 /* Error processing */
538
539handle_error:
540 /* Statistics */
541 if (status & BD_SC_BR)
542 port->icount.brk++;
543 if (status & BD_SC_PR)
544 port->icount.parity++;
545 if (status & BD_SC_FR)
546 port->icount.frame++;
547 if (status & BD_SC_OV)
548 port->icount.overrun++;
549
550 /* Mask out ignored conditions */
551 status &= port->read_status_mask;
552
553 /* Handle the remaining ones */
554 if (status & BD_SC_BR)
555 flg = TTY_BREAK;
556 else if (status & BD_SC_PR)
557 flg = TTY_PARITY;
558 else if (status & BD_SC_FR)
559 flg = TTY_FRAME;
560
561 /* Overrun does not affect the current character ! */
562 if (status & BD_SC_OV)
563 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
564#ifdef SUPPORT_SYSRQ
565 port->sysrq = 0;
566#endif
567 goto error_return;
568}
569
570/* Interrupt handler
571 *
572 * This interrupt handler is called after a BD is processed.
573 */
574static irqreturn_t qe_uart_int(int irq, void *data)
575{
576 struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
577 struct ucc_slow __iomem *uccp = qe_port->uccp;
578 u16 events;
579
580 /* Clear the interrupts */
581 events = in_be16(&uccp->ucce);
582 out_be16(&uccp->ucce, events);
583
584 if (events & UCC_UART_UCCE_BRKE)
585 uart_handle_break(&qe_port->port);
586
587 if (events & UCC_UART_UCCE_RX)
588 qe_uart_int_rx(qe_port);
589
590 if (events & UCC_UART_UCCE_TX)
591 qe_uart_tx_pump(qe_port);
592
593 return events ? IRQ_HANDLED : IRQ_NONE;
594}
595
596/* Initialize buffer descriptors
597 *
598 * This function initializes all of the RX and TX buffer descriptors.
599 */
600static void qe_uart_initbd(struct uart_qe_port *qe_port)
601{
602 int i;
603 void *bd_virt;
604 struct qe_bd *bdp;
605
606 /* Set the physical address of the host memory buffers in the buffer
607 * descriptors, and the virtual address for us to work with.
608 */
609 bd_virt = qe_port->bd_virt;
610 bdp = qe_port->rx_bd_base;
611 qe_port->rx_cur = qe_port->rx_bd_base;
612 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
613 out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
614 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
615 out_be16(&bdp->length, 0);
616 bd_virt += qe_port->rx_fifosize;
617 bdp++;
618 }
619
620 /* */
621 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
622 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
623 out_be16(&bdp->length, 0);
624
625 /* Set the physical address of the host memory
626 * buffers in the buffer descriptors, and the
627 * virtual address for us to work with.
628 */
629 bd_virt = qe_port->bd_virt +
630 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
631 qe_port->tx_cur = qe_port->tx_bd_base;
632 bdp = qe_port->tx_bd_base;
633 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
634 out_be16(&bdp->status, BD_SC_INTRPT);
635 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
636 out_be16(&bdp->length, 0);
637 bd_virt += qe_port->tx_fifosize;
638 bdp++;
639 }
640
641 /* Loopback requires the preamble bit to be set on the first TX BD */
642#ifdef LOOPBACK
643 setbits16(&qe_port->tx_cur->status, BD_SC_P);
644#endif
645
646 out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
647 out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
648 out_be16(&bdp->length, 0);
649}
650
651/*
652 * Initialize a UCC for UART.
653 *
654 * This function configures a given UCC to be used as a UART device. Basic
655 * UCC initialization is handled in qe_uart_request_port(). This function
656 * does all the UART-specific stuff.
657 */
658static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
659{
660 u32 cecr_subblock;
661 struct ucc_slow __iomem *uccp = qe_port->uccp;
662 struct ucc_uart_pram *uccup = qe_port->uccup;
663
664 unsigned int i;
665
666 /* First, disable TX and RX in the UCC */
667 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
668
669 /* Program the UCC UART parameter RAM */
670 out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
671 out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
672 out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
673 out_be16(&uccup->maxidl, 0x10);
674 out_be16(&uccup->brkcr, 1);
675 out_be16(&uccup->parec, 0);
676 out_be16(&uccup->frmec, 0);
677 out_be16(&uccup->nosec, 0);
678 out_be16(&uccup->brkec, 0);
679 out_be16(&uccup->uaddr[0], 0);
680 out_be16(&uccup->uaddr[1], 0);
681 out_be16(&uccup->toseq, 0);
682 for (i = 0; i < 8; i++)
683 out_be16(&uccup->cchars[i], 0xC000);
684 out_be16(&uccup->rccm, 0xc0ff);
685
686 /* Configure the GUMR registers for UART */
687 if (soft_uart) {
688 /* Soft-UART requires a 1X multiplier for TX */
689 clrsetbits_be32(&uccp->gumr_l,
690 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
691 UCC_SLOW_GUMR_L_RDCR_MASK,
692 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
693 UCC_SLOW_GUMR_L_RDCR_16);
694
695 clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
696 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
697 } else {
698 clrsetbits_be32(&uccp->gumr_l,
699 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
700 UCC_SLOW_GUMR_L_RDCR_MASK,
701 UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
702 UCC_SLOW_GUMR_L_RDCR_16);
703
704 clrsetbits_be32(&uccp->gumr_h,
705 UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
706 UCC_SLOW_GUMR_H_RFW);
707 }
708
709#ifdef LOOPBACK
710 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
711 UCC_SLOW_GUMR_L_DIAG_LOOP);
712 clrsetbits_be32(&uccp->gumr_h,
713 UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
714 UCC_SLOW_GUMR_H_CDS);
715#endif
716
717 /* Disable rx interrupts and clear all pending events. */
718 out_be16(&uccp->uccm, 0);
719 out_be16(&uccp->ucce, 0xffff);
720 out_be16(&uccp->udsr, 0x7e7e);
721
722 /* Initialize UPSMR */
723 out_be16(&uccp->upsmr, 0);
724
725 if (soft_uart) {
726 out_be16(&uccup->supsmr, 0x30);
727 out_be16(&uccup->res92, 0);
728 out_be32(&uccup->rx_state, 0);
729 out_be32(&uccup->rx_cnt, 0);
730 out_8(&uccup->rx_bitmark, 0);
731 out_8(&uccup->rx_length, 10);
732 out_be32(&uccup->dump_ptr, 0x4000);
733 out_8(&uccup->rx_temp_dlst_qe, 0);
734 out_be32(&uccup->rx_frame_rem, 0);
735 out_8(&uccup->rx_frame_rem_size, 0);
736 /* Soft-UART requires TX to be 1X */
737 out_8(&uccup->tx_mode,
738 UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
739 out_be16(&uccup->tx_state, 0);
740 out_8(&uccup->resD4, 0);
741 out_be16(&uccup->resD5, 0);
742
743 /* Set UART mode.
744 * Enable receive and transmit.
745 */
746
747 /* From the microcode errata:
748 * 1.GUMR_L register, set mode=0010 (QMC).
749 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
750 * 3.Set GUMR_H[19:20] (Transparent mode)
751 * 4.Clear GUMR_H[26] (RFW)
752 * ...
753 * 6.Receiver must use 16x over sampling
754 */
755 clrsetbits_be32(&uccp->gumr_l,
756 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
757 UCC_SLOW_GUMR_L_RDCR_MASK,
758 UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
759 UCC_SLOW_GUMR_L_RDCR_16);
760
761 clrsetbits_be32(&uccp->gumr_h,
762 UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
763 UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
764 UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
765
766#ifdef LOOPBACK
767 clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
768 UCC_SLOW_GUMR_L_DIAG_LOOP);
769 clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
770 UCC_SLOW_GUMR_H_CDS);
771#endif
772
773 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
774 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
775 QE_CR_PROTOCOL_UNSPECIFIED, 0);
776 } else {
777 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
778 qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
779 QE_CR_PROTOCOL_UART, 0);
780 }
781}
782
783/*
784 * Initialize the port.
785 */
786static int qe_uart_startup(struct uart_port *port)
787{
788 struct uart_qe_port *qe_port =
789 container_of(port, struct uart_qe_port, port);
790 int ret;
791
792 /*
793 * If we're using Soft-UART mode, then we need to make sure the
794 * firmware has been uploaded first.
795 */
796 if (soft_uart && !firmware_loaded) {
797 dev_err(port->dev, "Soft-UART firmware not uploaded\n");
798 return -ENODEV;
799 }
800
801 qe_uart_initbd(qe_port);
802 qe_uart_init_ucc(qe_port);
803
804 /* Install interrupt handler. */
805 ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
806 qe_port);
807 if (ret) {
808 dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
809 return ret;
810 }
811
812 /* Startup rx-int */
813 setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
814 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
815
816 return 0;
817}
818
819/*
820 * Shutdown the port.
821 */
822static void qe_uart_shutdown(struct uart_port *port)
823{
824 struct uart_qe_port *qe_port =
825 container_of(port, struct uart_qe_port, port);
826 struct ucc_slow __iomem *uccp = qe_port->uccp;
827 unsigned int timeout = 20;
828
829 /* Disable RX and TX */
830
831 /* Wait for all the BDs marked sent */
832 while (!qe_uart_tx_empty(port)) {
833 if (!--timeout) {
834 dev_warn(port->dev, "shutdown timeout\n");
835 break;
836 }
837 set_current_state(TASK_UNINTERRUPTIBLE);
838 schedule_timeout(2);
839 }
840
841 if (qe_port->wait_closing) {
842 /* Wait a bit longer */
843 set_current_state(TASK_UNINTERRUPTIBLE);
844 schedule_timeout(qe_port->wait_closing);
845 }
846
847 /* Stop uarts */
848 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
849 clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
850
851 /* Shut them really down and reinit buffer descriptors */
852 ucc_slow_graceful_stop_tx(qe_port->us_private);
853 qe_uart_initbd(qe_port);
854
855 free_irq(port->irq, qe_port);
856}
857
858/*
859 * Set the serial port parameters.
860 */
861static void qe_uart_set_termios(struct uart_port *port,
862 struct ktermios *termios, struct ktermios *old)
863{
864 struct uart_qe_port *qe_port =
865 container_of(port, struct uart_qe_port, port);
866 struct ucc_slow __iomem *uccp = qe_port->uccp;
867 unsigned int baud;
868 unsigned long flags;
869 u16 upsmr = in_be16(&uccp->upsmr);
870 struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
871 u16 supsmr = in_be16(&uccup->supsmr);
872 u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
873
874 /* Character length programmed into the mode register is the
875 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
876 * 1 or 2 stop bits, minus 1.
877 * The value 'bits' counts this for us.
878 */
879
880 /* byte size */
881 upsmr &= UCC_UART_UPSMR_CL_MASK;
882 supsmr &= UCC_UART_SUPSMR_CL_MASK;
883
884 switch (termios->c_cflag & CSIZE) {
885 case CS5:
886 upsmr |= UCC_UART_UPSMR_CL_5;
887 supsmr |= UCC_UART_SUPSMR_CL_5;
888 char_length += 5;
889 break;
890 case CS6:
891 upsmr |= UCC_UART_UPSMR_CL_6;
892 supsmr |= UCC_UART_SUPSMR_CL_6;
893 char_length += 6;
894 break;
895 case CS7:
896 upsmr |= UCC_UART_UPSMR_CL_7;
897 supsmr |= UCC_UART_SUPSMR_CL_7;
898 char_length += 7;
899 break;
900 default: /* case CS8 */
901 upsmr |= UCC_UART_UPSMR_CL_8;
902 supsmr |= UCC_UART_SUPSMR_CL_8;
903 char_length += 8;
904 break;
905 }
906
907 /* If CSTOPB is set, we want two stop bits */
908 if (termios->c_cflag & CSTOPB) {
909 upsmr |= UCC_UART_UPSMR_SL;
910 supsmr |= UCC_UART_SUPSMR_SL;
911 char_length++; /* + SL */
912 }
913
914 if (termios->c_cflag & PARENB) {
915 upsmr |= UCC_UART_UPSMR_PEN;
916 supsmr |= UCC_UART_SUPSMR_PEN;
917 char_length++; /* + PEN */
918
919 if (!(termios->c_cflag & PARODD)) {
920 upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
921 UCC_UART_UPSMR_TPM_MASK);
922 upsmr |= UCC_UART_UPSMR_RPM_EVEN |
923 UCC_UART_UPSMR_TPM_EVEN;
924 supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
925 UCC_UART_SUPSMR_TPM_MASK);
926 supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
927 UCC_UART_SUPSMR_TPM_EVEN;
928 }
929 }
930
931 /*
932 * Set up parity check flag
933 */
934 port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
935 if (termios->c_iflag & INPCK)
936 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
937 if (termios->c_iflag & (BRKINT | PARMRK))
938 port->read_status_mask |= BD_SC_BR;
939
940 /*
941 * Characters to ignore
942 */
943 port->ignore_status_mask = 0;
944 if (termios->c_iflag & IGNPAR)
945 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
946 if (termios->c_iflag & IGNBRK) {
947 port->ignore_status_mask |= BD_SC_BR;
948 /*
949 * If we're ignore parity and break indicators, ignore
950 * overruns too. (For real raw support).
951 */
952 if (termios->c_iflag & IGNPAR)
953 port->ignore_status_mask |= BD_SC_OV;
954 }
955 /*
956 * !!! ignore all characters if CREAD is not set
957 */
958 if ((termios->c_cflag & CREAD) == 0)
959 port->read_status_mask &= ~BD_SC_EMPTY;
960
961 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
962
963 /* Do we really need a spinlock here? */
964 spin_lock_irqsave(&port->lock, flags);
965
966 /* Update the per-port timeout. */
967 uart_update_timeout(port, termios->c_cflag, baud);
968
969 out_be16(&uccp->upsmr, upsmr);
970 if (soft_uart) {
971 out_be16(&uccup->supsmr, supsmr);
972 out_8(&uccup->rx_length, char_length);
973
974 /* Soft-UART requires a 1X multiplier for TX */
975 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
976 qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
977 } else {
978 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
979 qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
980 }
981
982 spin_unlock_irqrestore(&port->lock, flags);
983}
984
985/*
986 * Return a pointer to a string that describes what kind of port this is.
987 */
988static const char *qe_uart_type(struct uart_port *port)
989{
990 return "QE";
991}
992
993/*
994 * Allocate any memory and I/O resources required by the port.
995 */
996static int qe_uart_request_port(struct uart_port *port)
997{
998 int ret;
999 struct uart_qe_port *qe_port =
1000 container_of(port, struct uart_qe_port, port);
1001 struct ucc_slow_info *us_info = &qe_port->us_info;
1002 struct ucc_slow_private *uccs;
1003 unsigned int rx_size, tx_size;
1004 void *bd_virt;
1005 dma_addr_t bd_dma_addr = 0;
1006
1007 ret = ucc_slow_init(us_info, &uccs);
1008 if (ret) {
1009 dev_err(port->dev, "could not initialize UCC%u\n",
1010 qe_port->ucc_num);
1011 return ret;
1012 }
1013
1014 qe_port->us_private = uccs;
1015 qe_port->uccp = uccs->us_regs;
1016 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
1017 qe_port->rx_bd_base = uccs->rx_bd;
1018 qe_port->tx_bd_base = uccs->tx_bd;
1019
1020 /*
1021 * Allocate the transmit and receive data buffers.
1022 */
1023
1024 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
1025 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
1026
1027 bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
1028 GFP_KERNEL);
1029 if (!bd_virt) {
1030 dev_err(port->dev, "could not allocate buffer descriptors\n");
1031 return -ENOMEM;
1032 }
1033
1034 qe_port->bd_virt = bd_virt;
1035 qe_port->bd_dma_addr = bd_dma_addr;
1036 qe_port->bd_size = rx_size + tx_size;
1037
1038 qe_port->rx_buf = bd_virt;
1039 qe_port->tx_buf = qe_port->rx_buf + rx_size;
1040
1041 return 0;
1042}
1043
1044/*
1045 * Configure the port.
1046 *
1047 * We say we're a CPM-type port because that's mostly true. Once the device
1048 * is configured, this driver operates almost identically to the CPM serial
1049 * driver.
1050 */
1051static void qe_uart_config_port(struct uart_port *port, int flags)
1052{
1053 if (flags & UART_CONFIG_TYPE) {
1054 port->type = PORT_CPM;
1055 qe_uart_request_port(port);
1056 }
1057}
1058
1059/*
1060 * Release any memory and I/O resources that were allocated in
1061 * qe_uart_request_port().
1062 */
1063static void qe_uart_release_port(struct uart_port *port)
1064{
1065 struct uart_qe_port *qe_port =
1066 container_of(port, struct uart_qe_port, port);
1067 struct ucc_slow_private *uccs = qe_port->us_private;
1068
1069 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1070 qe_port->bd_dma_addr);
1071
1072 ucc_slow_free(uccs);
1073}
1074
1075/*
1076 * Verify that the data in serial_struct is suitable for this device.
1077 */
1078static int qe_uart_verify_port(struct uart_port *port,
1079 struct serial_struct *ser)
1080{
1081 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1082 return -EINVAL;
1083
1084 if (ser->irq < 0 || ser->irq >= nr_irqs)
1085 return -EINVAL;
1086
1087 if (ser->baud_base < 9600)
1088 return -EINVAL;
1089
1090 return 0;
1091}
1092/* UART operations
1093 *
1094 * Details on these functions can be found in Documentation/serial/driver
1095 */
1096static struct uart_ops qe_uart_pops = {
1097 .tx_empty = qe_uart_tx_empty,
1098 .set_mctrl = qe_uart_set_mctrl,
1099 .get_mctrl = qe_uart_get_mctrl,
1100 .stop_tx = qe_uart_stop_tx,
1101 .start_tx = qe_uart_start_tx,
1102 .stop_rx = qe_uart_stop_rx,
1103 .enable_ms = qe_uart_enable_ms,
1104 .break_ctl = qe_uart_break_ctl,
1105 .startup = qe_uart_startup,
1106 .shutdown = qe_uart_shutdown,
1107 .set_termios = qe_uart_set_termios,
1108 .type = qe_uart_type,
1109 .release_port = qe_uart_release_port,
1110 .request_port = qe_uart_request_port,
1111 .config_port = qe_uart_config_port,
1112 .verify_port = qe_uart_verify_port,
1113};
1114
1115/*
1116 * Obtain the SOC model number and revision level
1117 *
1118 * This function parses the device tree to obtain the SOC model. It then
1119 * reads the SVR register to the revision.
1120 *
1121 * The device tree stores the SOC model two different ways.
1122 *
1123 * The new way is:
1124 *
1125 * cpu@0 {
1126 * compatible = "PowerPC,8323";
1127 * device_type = "cpu";
1128 * ...
1129 *
1130 *
1131 * The old way is:
1132 * PowerPC,8323@0 {
1133 * device_type = "cpu";
1134 * ...
1135 *
1136 * This code first checks the new way, and then the old way.
1137 */
1138static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1139{
1140 struct device_node *np;
1141 const char *soc_string;
1142 unsigned int svr;
1143 unsigned int soc;
1144
1145 /* Find the CPU node */
1146 np = of_find_node_by_type(NULL, "cpu");
1147 if (!np)
1148 return 0;
1149 /* Find the compatible property */
1150 soc_string = of_get_property(np, "compatible", NULL);
1151 if (!soc_string)
1152 /* No compatible property, so try the name. */
1153 soc_string = np->name;
1154
1155 /* Extract the SOC number from the "PowerPC," string */
1156 if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1157 return 0;
1158
1159 /* Get the revision from the SVR */
1160 svr = mfspr(SPRN_SVR);
1161 *rev_h = (svr >> 4) & 0xf;
1162 *rev_l = svr & 0xf;
1163
1164 return soc;
1165}
1166
1167/*
1168 * requst_firmware_nowait() callback function
1169 *
1170 * This function is called by the kernel when a firmware is made available,
1171 * or if it times out waiting for the firmware.
1172 */
1173static void uart_firmware_cont(const struct firmware *fw, void *context)
1174{
1175 struct qe_firmware *firmware;
1176 struct device *dev = context;
1177 int ret;
1178
1179 if (!fw) {
1180 dev_err(dev, "firmware not found\n");
1181 return;
1182 }
1183
1184 firmware = (struct qe_firmware *) fw->data;
1185
1186 if (firmware->header.length != fw->size) {
1187 dev_err(dev, "invalid firmware\n");
1188 goto out;
1189 }
1190
1191 ret = qe_upload_firmware(firmware);
1192 if (ret) {
1193 dev_err(dev, "could not load firmware\n");
1194 goto out;
1195 }
1196
1197 firmware_loaded = 1;
1198 out:
1199 release_firmware(fw);
1200}
1201
1202static int ucc_uart_probe(struct platform_device *ofdev)
1203{
1204 struct device_node *np = ofdev->dev.of_node;
1205 const unsigned int *iprop; /* Integer OF properties */
1206 const char *sprop; /* String OF properties */
1207 struct uart_qe_port *qe_port = NULL;
1208 struct resource res;
1209 int ret;
1210
1211 /*
1212 * Determine if we need Soft-UART mode
1213 */
1214 if (of_find_property(np, "soft-uart", NULL)) {
1215 dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1216 soft_uart = 1;
1217 }
1218
1219 /*
1220 * If we are using Soft-UART, determine if we need to upload the
1221 * firmware, too.
1222 */
1223 if (soft_uart) {
1224 struct qe_firmware_info *qe_fw_info;
1225
1226 qe_fw_info = qe_get_firmware_info();
1227
1228 /* Check if the firmware has been uploaded. */
1229 if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1230 firmware_loaded = 1;
1231 } else {
1232 char filename[32];
1233 unsigned int soc;
1234 unsigned int rev_h;
1235 unsigned int rev_l;
1236
1237 soc = soc_info(&rev_h, &rev_l);
1238 if (!soc) {
1239 dev_err(&ofdev->dev, "unknown CPU model\n");
1240 return -ENXIO;
1241 }
1242 sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1243 soc, rev_h, rev_l);
1244
1245 dev_info(&ofdev->dev, "waiting for firmware %s\n",
1246 filename);
1247
1248 /*
1249 * We call request_firmware_nowait instead of
1250 * request_firmware so that the driver can load and
1251 * initialize the ports without holding up the rest of
1252 * the kernel. If hotplug support is enabled in the
1253 * kernel, then we use it.
1254 */
1255 ret = request_firmware_nowait(THIS_MODULE,
1256 FW_ACTION_HOTPLUG, filename, &ofdev->dev,
1257 GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1258 if (ret) {
1259 dev_err(&ofdev->dev,
1260 "could not load firmware %s\n",
1261 filename);
1262 return ret;
1263 }
1264 }
1265 }
1266
1267 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1268 if (!qe_port) {
1269 dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1270 return -ENOMEM;
1271 }
1272
1273 /* Search for IRQ and mapbase */
1274 ret = of_address_to_resource(np, 0, &res);
1275 if (ret) {
1276 dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1277 goto out_free;
1278 }
1279 if (!res.start) {
1280 dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1281 ret = -EINVAL;
1282 goto out_free;
1283 }
1284 qe_port->port.mapbase = res.start;
1285
1286 /* Get the UCC number (device ID) */
1287 /* UCCs are numbered 1-7 */
1288 iprop = of_get_property(np, "cell-index", NULL);
1289 if (!iprop) {
1290 iprop = of_get_property(np, "device-id", NULL);
1291 if (!iprop) {
1292 dev_err(&ofdev->dev, "UCC is unspecified in "
1293 "device tree\n");
1294 ret = -EINVAL;
1295 goto out_free;
1296 }
1297 }
1298
1299 if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
1300 dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
1301 ret = -ENODEV;
1302 goto out_free;
1303 }
1304 qe_port->ucc_num = *iprop - 1;
1305
1306 /*
1307 * In the future, we should not require the BRG to be specified in the
1308 * device tree. If no clock-source is specified, then just pick a BRG
1309 * to use. This requires a new QE library function that manages BRG
1310 * assignments.
1311 */
1312
1313 sprop = of_get_property(np, "rx-clock-name", NULL);
1314 if (!sprop) {
1315 dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1316 ret = -ENODEV;
1317 goto out_free;
1318 }
1319
1320 qe_port->us_info.rx_clock = qe_clock_source(sprop);
1321 if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1322 (qe_port->us_info.rx_clock > QE_BRG16)) {
1323 dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1324 ret = -ENODEV;
1325 goto out_free;
1326 }
1327
1328#ifdef LOOPBACK
1329 /* In internal loopback mode, TX and RX must use the same clock */
1330 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1331#else
1332 sprop = of_get_property(np, "tx-clock-name", NULL);
1333 if (!sprop) {
1334 dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1335 ret = -ENODEV;
1336 goto out_free;
1337 }
1338 qe_port->us_info.tx_clock = qe_clock_source(sprop);
1339#endif
1340 if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1341 (qe_port->us_info.tx_clock > QE_BRG16)) {
1342 dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1343 ret = -ENODEV;
1344 goto out_free;
1345 }
1346
1347 /* Get the port number, numbered 0-3 */
1348 iprop = of_get_property(np, "port-number", NULL);
1349 if (!iprop) {
1350 dev_err(&ofdev->dev, "missing port-number in device tree\n");
1351 ret = -EINVAL;
1352 goto out_free;
1353 }
1354 qe_port->port.line = *iprop;
1355 if (qe_port->port.line >= UCC_MAX_UART) {
1356 dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1357 UCC_MAX_UART - 1);
1358 ret = -EINVAL;
1359 goto out_free;
1360 }
1361
1362 qe_port->port.irq = irq_of_parse_and_map(np, 0);
1363 if (qe_port->port.irq == 0) {
1364 dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1365 qe_port->ucc_num + 1);
1366 ret = -EINVAL;
1367 goto out_free;
1368 }
1369
1370 /*
1371 * Newer device trees have an "fsl,qe" compatible property for the QE
1372 * node, but we still need to support older device trees.
1373 */
1374 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1375 if (!np) {
1376 np = of_find_node_by_type(NULL, "qe");
1377 if (!np) {
1378 dev_err(&ofdev->dev, "could not find 'qe' node\n");
1379 ret = -EINVAL;
1380 goto out_free;
1381 }
1382 }
1383
1384 iprop = of_get_property(np, "brg-frequency", NULL);
1385 if (!iprop) {
1386 dev_err(&ofdev->dev,
1387 "missing brg-frequency in device tree\n");
1388 ret = -EINVAL;
1389 goto out_np;
1390 }
1391
1392 if (*iprop)
1393 qe_port->port.uartclk = *iprop;
1394 else {
1395 /*
1396 * Older versions of U-Boot do not initialize the brg-frequency
1397 * property, so in this case we assume the BRG frequency is
1398 * half the QE bus frequency.
1399 */
1400 iprop = of_get_property(np, "bus-frequency", NULL);
1401 if (!iprop) {
1402 dev_err(&ofdev->dev,
1403 "missing QE bus-frequency in device tree\n");
1404 ret = -EINVAL;
1405 goto out_np;
1406 }
1407 if (*iprop)
1408 qe_port->port.uartclk = *iprop / 2;
1409 else {
1410 dev_err(&ofdev->dev,
1411 "invalid QE bus-frequency in device tree\n");
1412 ret = -EINVAL;
1413 goto out_np;
1414 }
1415 }
1416
1417 spin_lock_init(&qe_port->port.lock);
1418 qe_port->np = np;
1419 qe_port->port.dev = &ofdev->dev;
1420 qe_port->port.ops = &qe_uart_pops;
1421 qe_port->port.iotype = UPIO_MEM;
1422
1423 qe_port->tx_nrfifos = TX_NUM_FIFO;
1424 qe_port->tx_fifosize = TX_BUF_SIZE;
1425 qe_port->rx_nrfifos = RX_NUM_FIFO;
1426 qe_port->rx_fifosize = RX_BUF_SIZE;
1427
1428 qe_port->wait_closing = UCC_WAIT_CLOSING;
1429 qe_port->port.fifosize = 512;
1430 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1431
1432 qe_port->us_info.ucc_num = qe_port->ucc_num;
1433 qe_port->us_info.regs = (phys_addr_t) res.start;
1434 qe_port->us_info.irq = qe_port->port.irq;
1435
1436 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1437 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1438
1439 /* Make sure ucc_slow_init() initializes both TX and RX */
1440 qe_port->us_info.init_tx = 1;
1441 qe_port->us_info.init_rx = 1;
1442
1443 /* Add the port to the uart sub-system. This will cause
1444 * qe_uart_config_port() to be called, so the us_info structure must
1445 * be initialized.
1446 */
1447 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1448 if (ret) {
1449 dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1450 qe_port->port.line);
1451 goto out_np;
1452 }
1453
1454 dev_set_drvdata(&ofdev->dev, qe_port);
1455
1456 dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1457 qe_port->ucc_num + 1, qe_port->port.line);
1458
1459 /* Display the mknod command for this device */
1460 dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1461 qe_port->port.line, SERIAL_QE_MAJOR,
1462 SERIAL_QE_MINOR + qe_port->port.line);
1463
1464 return 0;
1465out_np:
1466 of_node_put(np);
1467out_free:
1468 kfree(qe_port);
1469 return ret;
1470}
1471
1472static int ucc_uart_remove(struct platform_device *ofdev)
1473{
1474 struct uart_qe_port *qe_port = dev_get_drvdata(&ofdev->dev);
1475
1476 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1477
1478 uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1479
1480 dev_set_drvdata(&ofdev->dev, NULL);
1481 kfree(qe_port);
1482
1483 return 0;
1484}
1485
1486static struct of_device_id ucc_uart_match[] = {
1487 {
1488 .type = "serial",
1489 .compatible = "ucc_uart",
1490 },
1491 {},
1492};
1493MODULE_DEVICE_TABLE(of, ucc_uart_match);
1494
1495static struct platform_driver ucc_uart_of_driver = {
1496 .driver = {
1497 .name = "ucc_uart",
1498 .owner = THIS_MODULE,
1499 .of_match_table = ucc_uart_match,
1500 },
1501 .probe = ucc_uart_probe,
1502 .remove = ucc_uart_remove,
1503};
1504
1505static int __init ucc_uart_init(void)
1506{
1507 int ret;
1508
1509 printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1510#ifdef LOOPBACK
1511 printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1512#endif
1513
1514 ret = uart_register_driver(&ucc_uart_driver);
1515 if (ret) {
1516 printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1517 return ret;
1518 }
1519
1520 ret = platform_driver_register(&ucc_uart_of_driver);
1521 if (ret)
1522 printk(KERN_ERR
1523 "ucc-uart: could not register platform driver\n");
1524
1525 return ret;
1526}
1527
1528static void __exit ucc_uart_exit(void)
1529{
1530 printk(KERN_INFO
1531 "Freescale QUICC Engine UART device driver unloading\n");
1532
1533 platform_driver_unregister(&ucc_uart_of_driver);
1534 uart_unregister_driver(&ucc_uart_driver);
1535}
1536
1537module_init(ucc_uart_init);
1538module_exit(ucc_uart_exit);
1539
1540MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1541MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1542MODULE_LICENSE("GPL v2");
1543MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1544