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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8
9#include <drm/drm_atomic_helper.h>
10#include <drm/drm_panel.h>
11
12#include "drm.h"
13#include "dc.h"
14
15struct tegra_rgb {
16 struct tegra_output output;
17 struct tegra_dc *dc;
18
19 struct clk *clk_parent;
20 struct clk *clk;
21};
22
23static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
24{
25 return container_of(output, struct tegra_rgb, output);
26}
27
28struct reg_entry {
29 unsigned long offset;
30 unsigned long value;
31};
32
33static const struct reg_entry rgb_enable[] = {
34 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
35 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
36 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
37 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
40 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
43 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
51 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
52 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
53};
54
55static const struct reg_entry rgb_disable[] = {
56 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
57 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
58 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
59 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
64 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
65 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
66 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
68 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
69 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
70 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
72 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
73 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
74 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
75};
76
77static void tegra_dc_write_regs(struct tegra_dc *dc,
78 const struct reg_entry *table,
79 unsigned int num)
80{
81 unsigned int i;
82
83 for (i = 0; i < num; i++)
84 tegra_dc_writel(dc, table[i].value, table[i].offset);
85}
86
87static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
88 .reset = drm_atomic_helper_connector_reset,
89 .detect = tegra_output_connector_detect,
90 .fill_modes = drm_helper_probe_single_connector_modes,
91 .destroy = tegra_output_connector_destroy,
92 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
93 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
94};
95
96static enum drm_mode_status
97tegra_rgb_connector_mode_valid(struct drm_connector *connector,
98 struct drm_display_mode *mode)
99{
100 /*
101 * FIXME: For now, always assume that the mode is okay. There are
102 * unresolved issues with clk_round_rate(), which doesn't always
103 * reliably report whether a frequency can be set or not.
104 */
105 return MODE_OK;
106}
107
108static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
109 .get_modes = tegra_output_connector_get_modes,
110 .mode_valid = tegra_rgb_connector_mode_valid,
111};
112
113static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
114 .destroy = tegra_output_encoder_destroy,
115};
116
117static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
118{
119 struct tegra_output *output = encoder_to_output(encoder);
120 struct tegra_rgb *rgb = to_rgb(output);
121
122 if (output->panel)
123 drm_panel_disable(output->panel);
124
125 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
126 tegra_dc_commit(rgb->dc);
127
128 if (output->panel)
129 drm_panel_unprepare(output->panel);
130}
131
132static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
133{
134 struct tegra_output *output = encoder_to_output(encoder);
135 struct tegra_rgb *rgb = to_rgb(output);
136 u32 value;
137
138 if (output->panel)
139 drm_panel_prepare(output->panel);
140
141 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
142
143 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
144 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
145
146 /* XXX: parameterize? */
147 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
148 value &= ~LVS_OUTPUT_POLARITY_LOW;
149 value &= ~LHS_OUTPUT_POLARITY_LOW;
150 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
151
152 /* XXX: parameterize? */
153 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
154 DISP_ORDER_RED_BLUE;
155 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
156
157 /* XXX: parameterize? */
158 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
159 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
160
161 tegra_dc_commit(rgb->dc);
162
163 if (output->panel)
164 drm_panel_enable(output->panel);
165}
166
167static int
168tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
169 struct drm_crtc_state *crtc_state,
170 struct drm_connector_state *conn_state)
171{
172 struct tegra_output *output = encoder_to_output(encoder);
173 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
174 unsigned long pclk = crtc_state->mode.clock * 1000;
175 struct tegra_rgb *rgb = to_rgb(output);
176 unsigned int div;
177 int err;
178
179 /*
180 * We may not want to change the frequency of the parent clock, since
181 * it may be a parent for other peripherals. This is due to the fact
182 * that on Tegra20 there's only a single clock dedicated to display
183 * (pll_d_out0), whereas later generations have a second one that can
184 * be used to independently drive a second output (pll_d2_out0).
185 *
186 * As a way to support multiple outputs on Tegra20 as well, pll_p is
187 * typically used as the parent clock for the display controllers.
188 * But this comes at a cost: pll_p is the parent of several other
189 * peripherals, so its frequency shouldn't change out of the blue.
190 *
191 * The best we can do at this point is to use the shift clock divider
192 * and hope that the desired frequency can be matched (or at least
193 * matched sufficiently close that the panel will still work).
194 */
195 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
196 pclk = 0;
197
198 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
199 pclk, div);
200 if (err < 0) {
201 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
202 return err;
203 }
204
205 return err;
206}
207
208static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
209 .disable = tegra_rgb_encoder_disable,
210 .enable = tegra_rgb_encoder_enable,
211 .atomic_check = tegra_rgb_encoder_atomic_check,
212};
213
214int tegra_dc_rgb_probe(struct tegra_dc *dc)
215{
216 struct device_node *np;
217 struct tegra_rgb *rgb;
218 int err;
219
220 np = of_get_child_by_name(dc->dev->of_node, "rgb");
221 if (!np || !of_device_is_available(np))
222 return -ENODEV;
223
224 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
225 if (!rgb)
226 return -ENOMEM;
227
228 rgb->output.dev = dc->dev;
229 rgb->output.of_node = np;
230 rgb->dc = dc;
231
232 err = tegra_output_probe(&rgb->output);
233 if (err < 0)
234 return err;
235
236 rgb->clk = devm_clk_get(dc->dev, NULL);
237 if (IS_ERR(rgb->clk)) {
238 dev_err(dc->dev, "failed to get clock\n");
239 return PTR_ERR(rgb->clk);
240 }
241
242 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
243 if (IS_ERR(rgb->clk_parent)) {
244 dev_err(dc->dev, "failed to get parent clock\n");
245 return PTR_ERR(rgb->clk_parent);
246 }
247
248 err = clk_set_parent(rgb->clk, rgb->clk_parent);
249 if (err < 0) {
250 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
251 return err;
252 }
253
254 dc->rgb = &rgb->output;
255
256 return 0;
257}
258
259int tegra_dc_rgb_remove(struct tegra_dc *dc)
260{
261 if (!dc->rgb)
262 return 0;
263
264 tegra_output_remove(dc->rgb);
265 dc->rgb = NULL;
266
267 return 0;
268}
269
270int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
271{
272 struct tegra_output *output = dc->rgb;
273 int err;
274
275 if (!dc->rgb)
276 return -ENODEV;
277
278 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
279 DRM_MODE_CONNECTOR_LVDS);
280 drm_connector_helper_add(&output->connector,
281 &tegra_rgb_connector_helper_funcs);
282 output->connector.dpms = DRM_MODE_DPMS_OFF;
283
284 drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs,
285 DRM_MODE_ENCODER_LVDS, NULL);
286 drm_encoder_helper_add(&output->encoder,
287 &tegra_rgb_encoder_helper_funcs);
288
289 drm_connector_attach_encoder(&output->connector,
290 &output->encoder);
291 drm_connector_register(&output->connector);
292
293 err = tegra_output_init(drm, output);
294 if (err < 0) {
295 dev_err(output->dev, "failed to initialize output: %d\n", err);
296 return err;
297 }
298
299 /*
300 * Other outputs can be attached to either display controller. The RGB
301 * outputs are an exception and work only with their parent display
302 * controller.
303 */
304 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
305
306 return 0;
307}
308
309int tegra_dc_rgb_exit(struct tegra_dc *dc)
310{
311 if (dc->rgb)
312 tegra_output_exit(dc->rgb);
313
314 return 0;
315}
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11
12#include "drm.h"
13#include "dc.h"
14
15struct tegra_rgb {
16 struct tegra_output output;
17 struct tegra_dc *dc;
18 bool enabled;
19
20 struct clk *clk_parent;
21 struct clk *clk;
22};
23
24static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
25{
26 return container_of(output, struct tegra_rgb, output);
27}
28
29struct reg_entry {
30 unsigned long offset;
31 unsigned long value;
32};
33
34static const struct reg_entry rgb_enable[] = {
35 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
36 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
37 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
43 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
52 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
53 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
54};
55
56static const struct reg_entry rgb_disable[] = {
57 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
58 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
59 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
65 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
66 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
69 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
70 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
73 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
74 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
75 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
76};
77
78static void tegra_dc_write_regs(struct tegra_dc *dc,
79 const struct reg_entry *table,
80 unsigned int num)
81{
82 unsigned int i;
83
84 for (i = 0; i < num; i++)
85 tegra_dc_writel(dc, table[i].value, table[i].offset);
86}
87
88static int tegra_output_rgb_enable(struct tegra_output *output)
89{
90 struct tegra_rgb *rgb = to_rgb(output);
91 unsigned long value;
92
93 if (rgb->enabled)
94 return 0;
95
96 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
97
98 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
99 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
100
101 /* XXX: parameterize? */
102 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
103 value &= ~LVS_OUTPUT_POLARITY_LOW;
104 value &= ~LHS_OUTPUT_POLARITY_LOW;
105 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
106
107 /* XXX: parameterize? */
108 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
109 DISP_ORDER_RED_BLUE;
110 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
111
112 /* XXX: parameterize? */
113 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
114 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
115
116 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
117 value &= ~DISP_CTRL_MODE_MASK;
118 value |= DISP_CTRL_MODE_C_DISPLAY;
119 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
120
121 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
122 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
123 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
124 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
125
126 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
127 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
128
129 rgb->enabled = true;
130
131 return 0;
132}
133
134static int tegra_output_rgb_disable(struct tegra_output *output)
135{
136 struct tegra_rgb *rgb = to_rgb(output);
137 unsigned long value;
138
139 if (!rgb->enabled)
140 return 0;
141
142 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
143 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
144 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
145 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
146
147 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
148 value &= ~DISP_CTRL_MODE_MASK;
149 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
150
151 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
152 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
153
154 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
155
156 rgb->enabled = false;
157
158 return 0;
159}
160
161static int tegra_output_rgb_setup_clock(struct tegra_output *output,
162 struct clk *clk, unsigned long pclk)
163{
164 struct tegra_rgb *rgb = to_rgb(output);
165
166 return clk_set_parent(clk, rgb->clk_parent);
167}
168
169static int tegra_output_rgb_check_mode(struct tegra_output *output,
170 struct drm_display_mode *mode,
171 enum drm_mode_status *status)
172{
173 /*
174 * FIXME: For now, always assume that the mode is okay. There are
175 * unresolved issues with clk_round_rate(), which doesn't always
176 * reliably report whether a frequency can be set or not.
177 */
178
179 *status = MODE_OK;
180
181 return 0;
182}
183
184static const struct tegra_output_ops rgb_ops = {
185 .enable = tegra_output_rgb_enable,
186 .disable = tegra_output_rgb_disable,
187 .setup_clock = tegra_output_rgb_setup_clock,
188 .check_mode = tegra_output_rgb_check_mode,
189};
190
191int tegra_dc_rgb_probe(struct tegra_dc *dc)
192{
193 struct device_node *np;
194 struct tegra_rgb *rgb;
195 int err;
196
197 np = of_get_child_by_name(dc->dev->of_node, "rgb");
198 if (!np || !of_device_is_available(np))
199 return -ENODEV;
200
201 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
202 if (!rgb)
203 return -ENOMEM;
204
205 rgb->output.dev = dc->dev;
206 rgb->output.of_node = np;
207 rgb->dc = dc;
208
209 err = tegra_output_probe(&rgb->output);
210 if (err < 0)
211 return err;
212
213 rgb->clk = devm_clk_get(dc->dev, NULL);
214 if (IS_ERR(rgb->clk)) {
215 dev_err(dc->dev, "failed to get clock\n");
216 return PTR_ERR(rgb->clk);
217 }
218
219 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
220 if (IS_ERR(rgb->clk_parent)) {
221 dev_err(dc->dev, "failed to get parent clock\n");
222 return PTR_ERR(rgb->clk_parent);
223 }
224
225 err = clk_set_parent(rgb->clk, rgb->clk_parent);
226 if (err < 0) {
227 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
228 return err;
229 }
230
231 dc->rgb = &rgb->output;
232
233 return 0;
234}
235
236int tegra_dc_rgb_remove(struct tegra_dc *dc)
237{
238 int err;
239
240 if (!dc->rgb)
241 return 0;
242
243 err = tegra_output_remove(dc->rgb);
244 if (err < 0)
245 return err;
246
247 return 0;
248}
249
250int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
251{
252 struct tegra_rgb *rgb = to_rgb(dc->rgb);
253 int err;
254
255 if (!dc->rgb)
256 return -ENODEV;
257
258 rgb->output.type = TEGRA_OUTPUT_RGB;
259 rgb->output.ops = &rgb_ops;
260
261 err = tegra_output_init(dc->base.dev, &rgb->output);
262 if (err < 0) {
263 dev_err(dc->dev, "output setup failed: %d\n", err);
264 return err;
265 }
266
267 /*
268 * By default, outputs can be associated with each display controller.
269 * RGB outputs are an exception, so we make sure they can be attached
270 * to only their parent display controller.
271 */
272 rgb->output.encoder.possible_crtcs = drm_crtc_mask(&dc->base);
273
274 return 0;
275}
276
277int tegra_dc_rgb_exit(struct tegra_dc *dc)
278{
279 if (dc->rgb) {
280 int err;
281
282 err = tegra_output_disable(dc->rgb);
283 if (err < 0) {
284 dev_err(dc->dev, "output failed to disable: %d\n", err);
285 return err;
286 }
287
288 err = tegra_output_exit(dc->rgb);
289 if (err < 0) {
290 dev_err(dc->dev, "output cleanup failed: %d\n", err);
291 return err;
292 }
293
294 dc->rgb = NULL;
295 }
296
297 return 0;
298}