Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
5 * Copyright (C) 2011 Wind River Systems,
6 * written by Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/bug.h>
9#include <linux/kernel.h>
10#include <linux/mm.h>
11#include <linux/memblock.h>
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/pci.h>
16#include <linux/of_address.h>
17
18#include <asm/cpu-info.h>
19
20unsigned long PCIBIOS_MIN_IO;
21EXPORT_SYMBOL(PCIBIOS_MIN_IO);
22
23unsigned long PCIBIOS_MIN_MEM;
24EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
25
26static int __init pcibios_set_cache_line_size(void)
27{
28 unsigned int lsize;
29
30 /*
31 * Set PCI cacheline size to that of the highest level in the
32 * cache hierarchy.
33 */
34 lsize = cpu_dcache_line_size();
35 lsize = cpu_scache_line_size() ? : lsize;
36 lsize = cpu_tcache_line_size() ? : lsize;
37
38 BUG_ON(!lsize);
39
40 pci_dfl_cache_line_size = lsize >> 2;
41
42 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
43 return 0;
44}
45arch_initcall(pcibios_set_cache_line_size);
46
47void pci_resource_to_user(const struct pci_dev *dev, int bar,
48 const struct resource *rsrc, resource_size_t *start,
49 resource_size_t *end)
50{
51 phys_addr_t size = resource_size(rsrc);
52
53 *start = fixup_bigphys_addr(rsrc->start, size);
54 *end = rsrc->start + size - 1;
55}
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
8 * Copyright (C) 2011 Wind River Systems,
9 * written by Ralf Baechle (ralf@linux-mips.org)
10 */
11#include <linux/bug.h>
12#include <linux/kernel.h>
13#include <linux/mm.h>
14#include <linux/bootmem.h>
15#include <linux/export.h>
16#include <linux/init.h>
17#include <linux/types.h>
18#include <linux/pci.h>
19#include <linux/of_address.h>
20
21#include <asm/cpu-info.h>
22
23/*
24 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
25 * assignments.
26 */
27
28/*
29 * The PCI controller list.
30 */
31
32static struct pci_controller *hose_head, **hose_tail = &hose_head;
33
34unsigned long PCIBIOS_MIN_IO;
35unsigned long PCIBIOS_MIN_MEM;
36
37static int pci_initialized;
38
39/*
40 * We need to avoid collisions with `mirrored' VGA ports
41 * and other strange ISA hardware, so we always want the
42 * addresses to be allocated in the 0x000-0x0ff region
43 * modulo 0x400.
44 *
45 * Why? Because some silly external IO cards only decode
46 * the low 10 bits of the IO address. The 0x00-0xff region
47 * is reserved for motherboard devices that decode all 16
48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
49 * but we want to try to avoid allocating at 0x2900-0x2bff
50 * which might have be mirrored at 0x0100-0x03ff..
51 */
52resource_size_t
53pcibios_align_resource(void *data, const struct resource *res,
54 resource_size_t size, resource_size_t align)
55{
56 struct pci_dev *dev = data;
57 struct pci_controller *hose = dev->sysdata;
58 resource_size_t start = res->start;
59
60 if (res->flags & IORESOURCE_IO) {
61 /* Make sure we start at our min on all hoses */
62 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
63 start = PCIBIOS_MIN_IO + hose->io_resource->start;
64
65 /*
66 * Put everything into 0x00-0xff region modulo 0x400
67 */
68 if (start & 0x300)
69 start = (start + 0x3ff) & ~0x3ff;
70 } else if (res->flags & IORESOURCE_MEM) {
71 /* Make sure we start at our min on all hoses */
72 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
74 }
75
76 return start;
77}
78
79static void pcibios_scanbus(struct pci_controller *hose)
80{
81 static int next_busno;
82 static int need_domain_info;
83 LIST_HEAD(resources);
84 struct pci_bus *bus;
85
86 if (!hose->iommu)
87 PCI_DMA_BUS_IS_PHYS = 1;
88
89 if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
90 next_busno = (*hose->get_busno)();
91
92 pci_add_resource_offset(&resources,
93 hose->mem_resource, hose->mem_offset);
94 pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset);
95 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
96 &resources);
97 if (!bus)
98 pci_free_resource_list(&resources);
99
100 hose->bus = bus;
101
102 need_domain_info = need_domain_info || hose->index;
103 hose->need_domain_info = need_domain_info;
104 if (bus) {
105 next_busno = bus->busn_res.end + 1;
106 /* Don't allow 8-bit bus number overflow inside the hose -
107 reserve some space for bridges. */
108 if (next_busno > 224) {
109 next_busno = 0;
110 need_domain_info = 1;
111 }
112
113 if (!pci_has_flag(PCI_PROBE_ONLY)) {
114 pci_bus_size_bridges(bus);
115 pci_bus_assign_resources(bus);
116 }
117 }
118}
119
120#ifdef CONFIG_OF
121void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
122{
123 struct of_pci_range range;
124 struct of_pci_range_parser parser;
125
126 pr_info("PCI host bridge %s ranges:\n", node->full_name);
127 hose->of_node = node;
128
129 if (of_pci_range_parser_init(&parser, node))
130 return;
131
132 for_each_of_pci_range(&parser, &range) {
133 struct resource *res = NULL;
134
135 switch (range.flags & IORESOURCE_TYPE_BITS) {
136 case IORESOURCE_IO:
137 pr_info(" IO 0x%016llx..0x%016llx\n",
138 range.cpu_addr,
139 range.cpu_addr + range.size - 1);
140 hose->io_map_base =
141 (unsigned long)ioremap(range.cpu_addr,
142 range.size);
143 res = hose->io_resource;
144 break;
145 case IORESOURCE_MEM:
146 pr_info(" MEM 0x%016llx..0x%016llx\n",
147 range.cpu_addr,
148 range.cpu_addr + range.size - 1);
149 res = hose->mem_resource;
150 break;
151 }
152 if (res != NULL)
153 of_pci_range_to_resource(&range, node, res);
154 }
155}
156
157struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
158{
159 struct pci_controller *hose = bus->sysdata;
160
161 return of_node_get(hose->of_node);
162}
163#endif
164
165static DEFINE_MUTEX(pci_scan_mutex);
166
167void register_pci_controller(struct pci_controller *hose)
168{
169 struct resource *parent;
170
171 parent = hose->mem_resource->parent;
172 if (!parent)
173 parent = &iomem_resource;
174
175 if (request_resource(parent, hose->mem_resource) < 0)
176 goto out;
177
178 parent = hose->io_resource->parent;
179 if (!parent)
180 parent = &ioport_resource;
181
182 if (request_resource(parent, hose->io_resource) < 0) {
183 release_resource(hose->mem_resource);
184 goto out;
185 }
186
187 *hose_tail = hose;
188 hose_tail = &hose->next;
189
190 /*
191 * Do not panic here but later - this might happen before console init.
192 */
193 if (!hose->io_map_base) {
194 printk(KERN_WARNING
195 "registering PCI controller with io_map_base unset\n");
196 }
197
198 /*
199 * Scan the bus if it is register after the PCI subsystem
200 * initialization.
201 */
202 if (pci_initialized) {
203 mutex_lock(&pci_scan_mutex);
204 pcibios_scanbus(hose);
205 mutex_unlock(&pci_scan_mutex);
206 }
207
208 return;
209
210out:
211 printk(KERN_WARNING
212 "Skipping PCI bus scan due to resource conflict\n");
213}
214
215static void __init pcibios_set_cache_line_size(void)
216{
217 struct cpuinfo_mips *c = ¤t_cpu_data;
218 unsigned int lsize;
219
220 /*
221 * Set PCI cacheline size to that of the highest level in the
222 * cache hierarchy.
223 */
224 lsize = c->dcache.linesz;
225 lsize = c->scache.linesz ? : lsize;
226 lsize = c->tcache.linesz ? : lsize;
227
228 BUG_ON(!lsize);
229
230 pci_dfl_cache_line_size = lsize >> 2;
231
232 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
233}
234
235static int __init pcibios_init(void)
236{
237 struct pci_controller *hose;
238
239 pcibios_set_cache_line_size();
240
241 /* Scan all of the recorded PCI controllers. */
242 for (hose = hose_head; hose; hose = hose->next)
243 pcibios_scanbus(hose);
244
245 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
246
247 pci_initialized = 1;
248
249 return 0;
250}
251
252subsys_initcall(pcibios_init);
253
254static int pcibios_enable_resources(struct pci_dev *dev, int mask)
255{
256 u16 cmd, old_cmd;
257 int idx;
258 struct resource *r;
259
260 pci_read_config_word(dev, PCI_COMMAND, &cmd);
261 old_cmd = cmd;
262 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
263 /* Only set up the requested stuff */
264 if (!(mask & (1<<idx)))
265 continue;
266
267 r = &dev->resource[idx];
268 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
269 continue;
270 if ((idx == PCI_ROM_RESOURCE) &&
271 (!(r->flags & IORESOURCE_ROM_ENABLE)))
272 continue;
273 if (!r->start && r->end) {
274 printk(KERN_ERR "PCI: Device %s not available "
275 "because of resource collisions\n",
276 pci_name(dev));
277 return -EINVAL;
278 }
279 if (r->flags & IORESOURCE_IO)
280 cmd |= PCI_COMMAND_IO;
281 if (r->flags & IORESOURCE_MEM)
282 cmd |= PCI_COMMAND_MEMORY;
283 }
284 if (cmd != old_cmd) {
285 printk("PCI: Enabling device %s (%04x -> %04x)\n",
286 pci_name(dev), old_cmd, cmd);
287 pci_write_config_word(dev, PCI_COMMAND, cmd);
288 }
289 return 0;
290}
291
292unsigned int pcibios_assign_all_busses(void)
293{
294 return 1;
295}
296
297int pcibios_enable_device(struct pci_dev *dev, int mask)
298{
299 int err;
300
301 if ((err = pcibios_enable_resources(dev, mask)) < 0)
302 return err;
303
304 return pcibios_plat_dev_init(dev);
305}
306
307void pcibios_fixup_bus(struct pci_bus *bus)
308{
309 struct pci_dev *dev = bus->self;
310
311 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
312 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
313 pci_read_bridge_bases(bus);
314 }
315}
316
317EXPORT_SYMBOL(PCIBIOS_MIN_IO);
318EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
319
320int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
321 enum pci_mmap_state mmap_state, int write_combine)
322{
323 unsigned long prot;
324
325 /*
326 * I/O space can be accessed via normal processor loads and stores on
327 * this platform but for now we elect not to do this and portable
328 * drivers should not do this anyway.
329 */
330 if (mmap_state == pci_mmap_io)
331 return -EINVAL;
332
333 /*
334 * Ignore write-combine; for now only return uncached mappings.
335 */
336 prot = pgprot_val(vma->vm_page_prot);
337 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
338 vma->vm_page_prot = __pgprot(prot);
339
340 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
341 vma->vm_end - vma->vm_start, vma->vm_page_prot);
342}
343
344char * (*pcibios_plat_setup)(char *str) __initdata;
345
346char *__init pcibios_setup(char *str)
347{
348 if (pcibios_plat_setup)
349 return pcibios_plat_setup(str);
350 return str;
351}