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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
5 * Copyright (C) 2011 Wind River Systems,
6 * written by Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/bug.h>
9#include <linux/kernel.h>
10#include <linux/mm.h>
11#include <linux/memblock.h>
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/pci.h>
16#include <linux/of_address.h>
17
18#include <asm/cpu-info.h>
19
20unsigned long PCIBIOS_MIN_IO;
21EXPORT_SYMBOL(PCIBIOS_MIN_IO);
22
23unsigned long PCIBIOS_MIN_MEM;
24EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
25
26static int __init pcibios_set_cache_line_size(void)
27{
28 unsigned int lsize;
29
30 /*
31 * Set PCI cacheline size to that of the highest level in the
32 * cache hierarchy.
33 */
34 lsize = cpu_dcache_line_size();
35 lsize = cpu_scache_line_size() ? : lsize;
36 lsize = cpu_tcache_line_size() ? : lsize;
37
38 BUG_ON(!lsize);
39
40 pci_dfl_cache_line_size = lsize >> 2;
41
42 pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
43 return 0;
44}
45arch_initcall(pcibios_set_cache_line_size);
46
47void pci_resource_to_user(const struct pci_dev *dev, int bar,
48 const struct resource *rsrc, resource_size_t *start,
49 resource_size_t *end)
50{
51 phys_addr_t size = resource_size(rsrc);
52
53 *start = fixup_bigphys_addr(rsrc->start, size);
54 *end = rsrc->start + size - 1;
55}
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
8 */
9#include <linux/kernel.h>
10#include <linux/mm.h>
11#include <linux/bootmem.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/pci.h>
15
16/*
17 * Indicate whether we respect the PCI setup left by the firmware.
18 *
19 * Make this long-lived so that we know when shutting down
20 * whether we probed only or not.
21 */
22int pci_probe_only;
23
24#define PCI_ASSIGN_ALL_BUSSES 1
25
26unsigned int pci_probe = PCI_ASSIGN_ALL_BUSSES;
27
28/*
29 * The PCI controller list.
30 */
31
32static struct pci_controller *hose_head, **hose_tail = &hose_head;
33
34unsigned long PCIBIOS_MIN_IO;
35unsigned long PCIBIOS_MIN_MEM;
36
37static int pci_initialized;
38
39/*
40 * We need to avoid collisions with `mirrored' VGA ports
41 * and other strange ISA hardware, so we always want the
42 * addresses to be allocated in the 0x000-0x0ff region
43 * modulo 0x400.
44 *
45 * Why? Because some silly external IO cards only decode
46 * the low 10 bits of the IO address. The 0x00-0xff region
47 * is reserved for motherboard devices that decode all 16
48 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
49 * but we want to try to avoid allocating at 0x2900-0x2bff
50 * which might have be mirrored at 0x0100-0x03ff..
51 */
52resource_size_t
53pcibios_align_resource(void *data, const struct resource *res,
54 resource_size_t size, resource_size_t align)
55{
56 struct pci_dev *dev = data;
57 struct pci_controller *hose = dev->sysdata;
58 resource_size_t start = res->start;
59
60 if (res->flags & IORESOURCE_IO) {
61 /* Make sure we start at our min on all hoses */
62 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
63 start = PCIBIOS_MIN_IO + hose->io_resource->start;
64
65 /*
66 * Put everything into 0x00-0xff region modulo 0x400
67 */
68 if (start & 0x300)
69 start = (start + 0x3ff) & ~0x3ff;
70 } else if (res->flags & IORESOURCE_MEM) {
71 /* Make sure we start at our min on all hoses */
72 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
73 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
74 }
75
76 return start;
77}
78
79static void __devinit pcibios_scanbus(struct pci_controller *hose)
80{
81 static int next_busno;
82 static int need_domain_info;
83 struct pci_bus *bus;
84
85 if (!hose->iommu)
86 PCI_DMA_BUS_IS_PHYS = 1;
87
88 if (hose->get_busno && pci_probe_only)
89 next_busno = (*hose->get_busno)();
90
91 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
92 hose->bus = bus;
93
94 need_domain_info = need_domain_info || hose->index;
95 hose->need_domain_info = need_domain_info;
96 if (bus) {
97 next_busno = bus->subordinate + 1;
98 /* Don't allow 8-bit bus number overflow inside the hose -
99 reserve some space for bridges. */
100 if (next_busno > 224) {
101 next_busno = 0;
102 need_domain_info = 1;
103 }
104
105 if (!pci_probe_only) {
106 pci_bus_size_bridges(bus);
107 pci_bus_assign_resources(bus);
108 pci_enable_bridges(bus);
109 }
110 }
111}
112
113static DEFINE_MUTEX(pci_scan_mutex);
114
115void __devinit register_pci_controller(struct pci_controller *hose)
116{
117 if (request_resource(&iomem_resource, hose->mem_resource) < 0)
118 goto out;
119 if (request_resource(&ioport_resource, hose->io_resource) < 0) {
120 release_resource(hose->mem_resource);
121 goto out;
122 }
123
124 *hose_tail = hose;
125 hose_tail = &hose->next;
126
127 /*
128 * Do not panic here but later - this might happen before console init.
129 */
130 if (!hose->io_map_base) {
131 printk(KERN_WARNING
132 "registering PCI controller with io_map_base unset\n");
133 }
134
135 /*
136 * Scan the bus if it is register after the PCI subsystem
137 * initialization.
138 */
139 if (pci_initialized) {
140 mutex_lock(&pci_scan_mutex);
141 pcibios_scanbus(hose);
142 mutex_unlock(&pci_scan_mutex);
143 }
144
145 return;
146
147out:
148 printk(KERN_WARNING
149 "Skipping PCI bus scan due to resource conflict\n");
150}
151
152static int __init pcibios_init(void)
153{
154 struct pci_controller *hose;
155
156 /* Scan all of the recorded PCI controllers. */
157 for (hose = hose_head; hose; hose = hose->next)
158 pcibios_scanbus(hose);
159
160 pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
161
162 pci_initialized = 1;
163
164 return 0;
165}
166
167subsys_initcall(pcibios_init);
168
169static int pcibios_enable_resources(struct pci_dev *dev, int mask)
170{
171 u16 cmd, old_cmd;
172 int idx;
173 struct resource *r;
174
175 pci_read_config_word(dev, PCI_COMMAND, &cmd);
176 old_cmd = cmd;
177 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
178 /* Only set up the requested stuff */
179 if (!(mask & (1<<idx)))
180 continue;
181
182 r = &dev->resource[idx];
183 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
184 continue;
185 if ((idx == PCI_ROM_RESOURCE) &&
186 (!(r->flags & IORESOURCE_ROM_ENABLE)))
187 continue;
188 if (!r->start && r->end) {
189 printk(KERN_ERR "PCI: Device %s not available "
190 "because of resource collisions\n",
191 pci_name(dev));
192 return -EINVAL;
193 }
194 if (r->flags & IORESOURCE_IO)
195 cmd |= PCI_COMMAND_IO;
196 if (r->flags & IORESOURCE_MEM)
197 cmd |= PCI_COMMAND_MEMORY;
198 }
199 if (cmd != old_cmd) {
200 printk("PCI: Enabling device %s (%04x -> %04x)\n",
201 pci_name(dev), old_cmd, cmd);
202 pci_write_config_word(dev, PCI_COMMAND, cmd);
203 }
204 return 0;
205}
206
207/*
208 * If we set up a device for bus mastering, we need to check the latency
209 * timer as certain crappy BIOSes forget to set it properly.
210 */
211static unsigned int pcibios_max_latency = 255;
212
213void pcibios_set_master(struct pci_dev *dev)
214{
215 u8 lat;
216 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
217 if (lat < 16)
218 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
219 else if (lat > pcibios_max_latency)
220 lat = pcibios_max_latency;
221 else
222 return;
223 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
224 pci_name(dev), lat);
225 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
226}
227
228unsigned int pcibios_assign_all_busses(void)
229{
230 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
231}
232
233int pcibios_enable_device(struct pci_dev *dev, int mask)
234{
235 int err;
236
237 if ((err = pcibios_enable_resources(dev, mask)) < 0)
238 return err;
239
240 return pcibios_plat_dev_init(dev);
241}
242
243static void pcibios_fixup_device_resources(struct pci_dev *dev,
244 struct pci_bus *bus)
245{
246 /* Update device resources. */
247 struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
248 unsigned long offset = 0;
249 int i;
250
251 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
252 if (!dev->resource[i].start)
253 continue;
254 if (dev->resource[i].flags & IORESOURCE_IO)
255 offset = hose->io_offset;
256 else if (dev->resource[i].flags & IORESOURCE_MEM)
257 offset = hose->mem_offset;
258
259 dev->resource[i].start += offset;
260 dev->resource[i].end += offset;
261 }
262}
263
264void __devinit pcibios_fixup_bus(struct pci_bus *bus)
265{
266 /* Propagate hose info into the subordinate devices. */
267
268 struct pci_controller *hose = bus->sysdata;
269 struct list_head *ln;
270 struct pci_dev *dev = bus->self;
271
272 if (!dev) {
273 bus->resource[0] = hose->io_resource;
274 bus->resource[1] = hose->mem_resource;
275 } else if (pci_probe_only &&
276 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
277 pci_read_bridge_bases(bus);
278 pcibios_fixup_device_resources(dev, bus);
279 }
280
281 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
282 dev = pci_dev_b(ln);
283
284 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
285 pcibios_fixup_device_resources(dev, bus);
286 }
287}
288
289void __init
290pcibios_update_irq(struct pci_dev *dev, int irq)
291{
292 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
293}
294
295void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
296 struct resource *res)
297{
298 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
299 unsigned long offset = 0;
300
301 if (res->flags & IORESOURCE_IO)
302 offset = hose->io_offset;
303 else if (res->flags & IORESOURCE_MEM)
304 offset = hose->mem_offset;
305
306 region->start = res->start - offset;
307 region->end = res->end - offset;
308}
309
310void __devinit
311pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
312 struct pci_bus_region *region)
313{
314 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
315 unsigned long offset = 0;
316
317 if (res->flags & IORESOURCE_IO)
318 offset = hose->io_offset;
319 else if (res->flags & IORESOURCE_MEM)
320 offset = hose->mem_offset;
321
322 res->start = region->start + offset;
323 res->end = region->end + offset;
324}
325
326#ifdef CONFIG_HOTPLUG
327EXPORT_SYMBOL(pcibios_resource_to_bus);
328EXPORT_SYMBOL(pcibios_bus_to_resource);
329EXPORT_SYMBOL(PCIBIOS_MIN_IO);
330EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
331#endif
332
333int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
334 enum pci_mmap_state mmap_state, int write_combine)
335{
336 unsigned long prot;
337
338 /*
339 * I/O space can be accessed via normal processor loads and stores on
340 * this platform but for now we elect not to do this and portable
341 * drivers should not do this anyway.
342 */
343 if (mmap_state == pci_mmap_io)
344 return -EINVAL;
345
346 /*
347 * Ignore write-combine; for now only return uncached mappings.
348 */
349 prot = pgprot_val(vma->vm_page_prot);
350 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
351 vma->vm_page_prot = __pgprot(prot);
352
353 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
354 vma->vm_end - vma->vm_start, vma->vm_page_prot);
355}
356
357char * (*pcibios_plat_setup)(char *str) __devinitdata;
358
359char *__devinit pcibios_setup(char *str)
360{
361 if (pcibios_plat_setup)
362 return pcibios_plat_setup(str);
363 return str;
364}