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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5# define SUPPORT_SYSRQ
6#endif
7
8#include <linux/clk.h>
9#include <linux/console.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/qcom-geni-se.h>
17#include <linux/serial.h>
18#include <linux/serial_core.h>
19#include <linux/slab.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22
23/* UART specific GENI registers */
24#define SE_UART_LOOPBACK_CFG 0x22c
25#define SE_UART_TX_TRANS_CFG 0x25c
26#define SE_UART_TX_WORD_LEN 0x268
27#define SE_UART_TX_STOP_BIT_LEN 0x26c
28#define SE_UART_TX_TRANS_LEN 0x270
29#define SE_UART_RX_TRANS_CFG 0x280
30#define SE_UART_RX_WORD_LEN 0x28c
31#define SE_UART_RX_STALE_CNT 0x294
32#define SE_UART_TX_PARITY_CFG 0x2a4
33#define SE_UART_RX_PARITY_CFG 0x2a8
34#define SE_UART_MANUAL_RFR 0x2ac
35
36/* SE_UART_TRANS_CFG */
37#define UART_TX_PAR_EN BIT(0)
38#define UART_CTS_MASK BIT(1)
39
40/* SE_UART_TX_WORD_LEN */
41#define TX_WORD_LEN_MSK GENMASK(9, 0)
42
43/* SE_UART_TX_STOP_BIT_LEN */
44#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
45#define TX_STOP_BIT_LEN_1 0
46#define TX_STOP_BIT_LEN_1_5 1
47#define TX_STOP_BIT_LEN_2 2
48
49/* SE_UART_TX_TRANS_LEN */
50#define TX_TRANS_LEN_MSK GENMASK(23, 0)
51
52/* SE_UART_RX_TRANS_CFG */
53#define UART_RX_INS_STATUS_BIT BIT(2)
54#define UART_RX_PAR_EN BIT(3)
55
56/* SE_UART_RX_WORD_LEN */
57#define RX_WORD_LEN_MASK GENMASK(9, 0)
58
59/* SE_UART_RX_STALE_CNT */
60#define RX_STALE_CNT GENMASK(23, 0)
61
62/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
63#define PAR_CALC_EN BIT(0)
64#define PAR_MODE_MSK GENMASK(2, 1)
65#define PAR_MODE_SHFT 1
66#define PAR_EVEN 0x00
67#define PAR_ODD 0x01
68#define PAR_SPACE 0x10
69#define PAR_MARK 0x11
70
71/* SE_UART_MANUAL_RFR register fields */
72#define UART_MANUAL_RFR_EN BIT(31)
73#define UART_RFR_NOT_READY BIT(1)
74#define UART_RFR_READY BIT(0)
75
76/* UART M_CMD OP codes */
77#define UART_START_TX 0x1
78#define UART_START_BREAK 0x4
79#define UART_STOP_BREAK 0x5
80/* UART S_CMD OP codes */
81#define UART_START_READ 0x1
82#define UART_PARAM 0x1
83
84#define UART_OVERSAMPLING 32
85#define STALE_TIMEOUT 16
86#define DEFAULT_BITS_PER_CHAR 10
87#define GENI_UART_CONS_PORTS 1
88#define GENI_UART_PORTS 3
89#define DEF_FIFO_DEPTH_WORDS 16
90#define DEF_TX_WM 2
91#define DEF_FIFO_WIDTH_BITS 32
92#define UART_RX_WM 2
93#define MAX_LOOPBACK_CFG 3
94
95#ifdef CONFIG_CONSOLE_POLL
96#define CONSOLE_RX_BYTES_PW 1
97#else
98#define CONSOLE_RX_BYTES_PW 4
99#endif
100
101struct qcom_geni_serial_port {
102 struct uart_port uport;
103 struct geni_se se;
104 char name[20];
105 u32 tx_fifo_depth;
106 u32 tx_fifo_width;
107 u32 rx_fifo_depth;
108 bool setup;
109 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
110 unsigned int baud;
111 unsigned int tx_bytes_pw;
112 unsigned int rx_bytes_pw;
113 u32 *rx_fifo;
114 u32 loopback;
115 bool brk;
116
117 unsigned int tx_remaining;
118};
119
120static const struct uart_ops qcom_geni_console_pops;
121static const struct uart_ops qcom_geni_uart_pops;
122static struct uart_driver qcom_geni_console_driver;
123static struct uart_driver qcom_geni_uart_driver;
124static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
125static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
126static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
127static void qcom_geni_serial_stop_rx(struct uart_port *uport);
128
129static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
130 32000000, 48000000, 64000000, 80000000,
131 96000000, 100000000, 102400000,
132 112000000, 120000000, 128000000};
133
134#define to_dev_port(ptr, member) \
135 container_of(ptr, struct qcom_geni_serial_port, member)
136
137static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
138 [0] = {
139 .uport = {
140 .iotype = UPIO_MEM,
141 .ops = &qcom_geni_uart_pops,
142 .flags = UPF_BOOT_AUTOCONF,
143 .line = 0,
144 },
145 },
146 [1] = {
147 .uport = {
148 .iotype = UPIO_MEM,
149 .ops = &qcom_geni_uart_pops,
150 .flags = UPF_BOOT_AUTOCONF,
151 .line = 1,
152 },
153 },
154 [2] = {
155 .uport = {
156 .iotype = UPIO_MEM,
157 .ops = &qcom_geni_uart_pops,
158 .flags = UPF_BOOT_AUTOCONF,
159 .line = 2,
160 },
161 },
162};
163
164static ssize_t loopback_show(struct device *dev,
165 struct device_attribute *attr, char *buf)
166{
167 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
168
169 return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
170}
171
172static ssize_t loopback_store(struct device *dev,
173 struct device_attribute *attr, const char *buf,
174 size_t size)
175{
176 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
177 u32 loopback;
178
179 if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
180 dev_err(dev, "Invalid input\n");
181 return -EINVAL;
182 }
183 port->loopback = loopback;
184 return size;
185}
186static DEVICE_ATTR_RW(loopback);
187
188static struct qcom_geni_serial_port qcom_geni_console_port = {
189 .uport = {
190 .iotype = UPIO_MEM,
191 .ops = &qcom_geni_console_pops,
192 .flags = UPF_BOOT_AUTOCONF,
193 .line = 0,
194 },
195};
196
197static int qcom_geni_serial_request_port(struct uart_port *uport)
198{
199 struct platform_device *pdev = to_platform_device(uport->dev);
200 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
201
202 uport->membase = devm_platform_ioremap_resource(pdev, 0);
203 if (IS_ERR(uport->membase))
204 return PTR_ERR(uport->membase);
205 port->se.base = uport->membase;
206 return 0;
207}
208
209static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
210{
211 if (cfg_flags & UART_CONFIG_TYPE) {
212 uport->type = PORT_MSM;
213 qcom_geni_serial_request_port(uport);
214 }
215}
216
217static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
218{
219 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
220 u32 geni_ios;
221
222 if (uart_console(uport)) {
223 mctrl |= TIOCM_CTS;
224 } else {
225 geni_ios = readl(uport->membase + SE_GENI_IOS);
226 if (!(geni_ios & IO2_DATA_IN))
227 mctrl |= TIOCM_CTS;
228 }
229
230 return mctrl;
231}
232
233static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
234 unsigned int mctrl)
235{
236 u32 uart_manual_rfr = 0;
237
238 if (uart_console(uport))
239 return;
240
241 if (!(mctrl & TIOCM_RTS))
242 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
243 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
244}
245
246static const char *qcom_geni_serial_get_type(struct uart_port *uport)
247{
248 return "MSM";
249}
250
251static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
252{
253 struct qcom_geni_serial_port *port;
254 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
255
256 if (line < 0 || line >= nr_ports)
257 return ERR_PTR(-ENXIO);
258
259 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
260 return port;
261}
262
263static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
264 int offset, int field, bool set)
265{
266 u32 reg;
267 struct qcom_geni_serial_port *port;
268 unsigned int baud;
269 unsigned int fifo_bits;
270 unsigned long timeout_us = 20000;
271
272 if (uport->private_data) {
273 port = to_dev_port(uport, uport);
274 baud = port->baud;
275 if (!baud)
276 baud = 115200;
277 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
278 /*
279 * Total polling iterations based on FIFO worth of bytes to be
280 * sent at current baud. Add a little fluff to the wait.
281 */
282 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
283 }
284
285 /*
286 * Use custom implementation instead of readl_poll_atomic since ktimer
287 * is not ready at the time of early console.
288 */
289 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
290 while (timeout_us) {
291 reg = readl(uport->membase + offset);
292 if ((bool)(reg & field) == set)
293 return true;
294 udelay(10);
295 timeout_us -= 10;
296 }
297 return false;
298}
299
300static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
301{
302 u32 m_cmd;
303
304 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
305 m_cmd = UART_START_TX << M_OPCODE_SHFT;
306 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
307}
308
309static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
310{
311 int done;
312 u32 irq_clear = M_CMD_DONE_EN;
313
314 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
315 M_CMD_DONE_EN, true);
316 if (!done) {
317 writel(M_GENI_CMD_ABORT, uport->membase +
318 SE_GENI_M_CMD_CTRL_REG);
319 irq_clear |= M_CMD_ABORT_EN;
320 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
321 M_CMD_ABORT_EN, true);
322 }
323 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
324}
325
326static void qcom_geni_serial_abort_rx(struct uart_port *uport)
327{
328 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
329
330 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
331 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
332 S_GENI_CMD_ABORT, false);
333 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
334 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
335}
336
337#ifdef CONFIG_CONSOLE_POLL
338static int qcom_geni_serial_get_char(struct uart_port *uport)
339{
340 u32 rx_fifo;
341 u32 status;
342
343 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
344 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
345
346 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
347 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
348
349 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
350 if (!(status & RX_FIFO_WC_MSK))
351 return NO_POLL_CHAR;
352
353 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
354 return rx_fifo & 0xff;
355}
356
357static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
358 unsigned char c)
359{
360 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
361 qcom_geni_serial_setup_tx(uport, 1);
362 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
363 M_TX_FIFO_WATERMARK_EN, true));
364 writel(c, uport->membase + SE_GENI_TX_FIFOn);
365 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
366 qcom_geni_serial_poll_tx_done(uport);
367}
368#endif
369
370#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
371static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
372{
373 writel(ch, uport->membase + SE_GENI_TX_FIFOn);
374}
375
376static void
377__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
378 unsigned int count)
379{
380 int i;
381 u32 bytes_to_send = count;
382
383 for (i = 0; i < count; i++) {
384 /*
385 * uart_console_write() adds a carriage return for each newline.
386 * Account for additional bytes to be written.
387 */
388 if (s[i] == '\n')
389 bytes_to_send++;
390 }
391
392 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
393 qcom_geni_serial_setup_tx(uport, bytes_to_send);
394 for (i = 0; i < count; ) {
395 size_t chars_to_write = 0;
396 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
397
398 /*
399 * If the WM bit never set, then the Tx state machine is not
400 * in a valid state, so break, cancel/abort any existing
401 * command. Unfortunately the current data being written is
402 * lost.
403 */
404 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
405 M_TX_FIFO_WATERMARK_EN, true))
406 break;
407 chars_to_write = min_t(size_t, count - i, avail / 2);
408 uart_console_write(uport, s + i, chars_to_write,
409 qcom_geni_serial_wr_char);
410 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
411 SE_GENI_M_IRQ_CLEAR);
412 i += chars_to_write;
413 }
414 qcom_geni_serial_poll_tx_done(uport);
415}
416
417static void qcom_geni_serial_console_write(struct console *co, const char *s,
418 unsigned int count)
419{
420 struct uart_port *uport;
421 struct qcom_geni_serial_port *port;
422 bool locked = true;
423 unsigned long flags;
424 u32 geni_status;
425 u32 irq_en;
426
427 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
428
429 port = get_port_from_line(co->index, true);
430 if (IS_ERR(port))
431 return;
432
433 uport = &port->uport;
434 if (oops_in_progress)
435 locked = spin_trylock_irqsave(&uport->lock, flags);
436 else
437 spin_lock_irqsave(&uport->lock, flags);
438
439 geni_status = readl(uport->membase + SE_GENI_STATUS);
440
441 /* Cancel the current write to log the fault */
442 if (!locked) {
443 geni_se_cancel_m_cmd(&port->se);
444 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
445 M_CMD_CANCEL_EN, true)) {
446 geni_se_abort_m_cmd(&port->se);
447 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
448 M_CMD_ABORT_EN, true);
449 writel(M_CMD_ABORT_EN, uport->membase +
450 SE_GENI_M_IRQ_CLEAR);
451 }
452 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
453 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
454 /*
455 * It seems we can't interrupt existing transfers if all data
456 * has been sent, in which case we need to look for done first.
457 */
458 qcom_geni_serial_poll_tx_done(uport);
459
460 if (uart_circ_chars_pending(&uport->state->xmit)) {
461 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
462 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
463 uport->membase + SE_GENI_M_IRQ_EN);
464 }
465 }
466
467 __qcom_geni_serial_console_write(uport, s, count);
468
469 if (port->tx_remaining)
470 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
471
472 if (locked)
473 spin_unlock_irqrestore(&uport->lock, flags);
474}
475
476static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
477{
478 u32 i;
479 unsigned char buf[sizeof(u32)];
480 struct tty_port *tport;
481 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
482
483 tport = &uport->state->port;
484 for (i = 0; i < bytes; ) {
485 int c;
486 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
487
488 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
489 i += chunk;
490 if (drop)
491 continue;
492
493 for (c = 0; c < chunk; c++) {
494 int sysrq;
495
496 uport->icount.rx++;
497 if (port->brk && buf[c] == 0) {
498 port->brk = false;
499 if (uart_handle_break(uport))
500 continue;
501 }
502
503 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
504
505 if (!sysrq)
506 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
507 }
508 }
509 if (!drop)
510 tty_flip_buffer_push(tport);
511 return 0;
512}
513#else
514static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
515{
516 return -EPERM;
517}
518
519#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
520
521static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
522{
523 unsigned char *buf;
524 struct tty_port *tport;
525 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
526 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
527 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
528 int ret;
529
530 tport = &uport->state->port;
531 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
532 if (drop)
533 return 0;
534
535 buf = (unsigned char *)port->rx_fifo;
536 ret = tty_insert_flip_string(tport, buf, bytes);
537 if (ret != bytes) {
538 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
539 __func__, ret, bytes);
540 WARN_ON_ONCE(1);
541 }
542 uport->icount.rx += ret;
543 tty_flip_buffer_push(tport);
544 return ret;
545}
546
547static void qcom_geni_serial_start_tx(struct uart_port *uport)
548{
549 u32 irq_en;
550 u32 status;
551
552 status = readl(uport->membase + SE_GENI_STATUS);
553 if (status & M_GENI_CMD_ACTIVE)
554 return;
555
556 if (!qcom_geni_serial_tx_empty(uport))
557 return;
558
559 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
560 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
561
562 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
563 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
564}
565
566static void qcom_geni_serial_stop_tx(struct uart_port *uport)
567{
568 u32 irq_en;
569 u32 status;
570 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
571
572 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
573 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
574 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
575 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
576 status = readl(uport->membase + SE_GENI_STATUS);
577 /* Possible stop tx is called multiple times. */
578 if (!(status & M_GENI_CMD_ACTIVE))
579 return;
580
581 geni_se_cancel_m_cmd(&port->se);
582 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
583 M_CMD_CANCEL_EN, true)) {
584 geni_se_abort_m_cmd(&port->se);
585 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
586 M_CMD_ABORT_EN, true);
587 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
588 }
589 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
590}
591
592static void qcom_geni_serial_start_rx(struct uart_port *uport)
593{
594 u32 irq_en;
595 u32 status;
596 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
597
598 status = readl(uport->membase + SE_GENI_STATUS);
599 if (status & S_GENI_CMD_ACTIVE)
600 qcom_geni_serial_stop_rx(uport);
601
602 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
603
604 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
605 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
606 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
607
608 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
609 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
610 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
611}
612
613static void qcom_geni_serial_stop_rx(struct uart_port *uport)
614{
615 u32 irq_en;
616 u32 status;
617 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
618 u32 irq_clear = S_CMD_DONE_EN;
619
620 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
621 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
622 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
623
624 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
625 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
626 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
627
628 status = readl(uport->membase + SE_GENI_STATUS);
629 /* Possible stop rx is called multiple times. */
630 if (!(status & S_GENI_CMD_ACTIVE))
631 return;
632
633 geni_se_cancel_s_cmd(&port->se);
634 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
635 S_GENI_CMD_CANCEL, false);
636 status = readl(uport->membase + SE_GENI_STATUS);
637 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
638 if (status & S_GENI_CMD_ACTIVE)
639 qcom_geni_serial_abort_rx(uport);
640}
641
642static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
643{
644 u32 status;
645 u32 word_cnt;
646 u32 last_word_byte_cnt;
647 u32 last_word_partial;
648 u32 total_bytes;
649 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
650
651 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
652 word_cnt = status & RX_FIFO_WC_MSK;
653 last_word_partial = status & RX_LAST;
654 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
655 RX_LAST_BYTE_VALID_SHFT;
656
657 if (!word_cnt)
658 return;
659 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
660 if (last_word_partial && last_word_byte_cnt)
661 total_bytes += last_word_byte_cnt;
662 else
663 total_bytes += port->rx_bytes_pw;
664 port->handle_rx(uport, total_bytes, drop);
665}
666
667static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
668 bool active)
669{
670 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
671 struct circ_buf *xmit = &uport->state->xmit;
672 size_t avail;
673 size_t remaining;
674 size_t pending;
675 int i;
676 u32 status;
677 u32 irq_en;
678 unsigned int chunk;
679 int tail;
680
681 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
682
683 /* Complete the current tx command before taking newly added data */
684 if (active)
685 pending = port->tx_remaining;
686 else
687 pending = uart_circ_chars_pending(xmit);
688
689 /* All data has been transmitted and acknowledged as received */
690 if (!pending && !status && done) {
691 qcom_geni_serial_stop_tx(uport);
692 goto out_write_wakeup;
693 }
694
695 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
696 avail *= port->tx_bytes_pw;
697
698 tail = xmit->tail;
699 chunk = min(avail, pending);
700 if (!chunk)
701 goto out_write_wakeup;
702
703 if (!port->tx_remaining) {
704 qcom_geni_serial_setup_tx(uport, pending);
705 port->tx_remaining = pending;
706
707 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
708 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
709 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
710 uport->membase + SE_GENI_M_IRQ_EN);
711 }
712
713 remaining = chunk;
714 for (i = 0; i < chunk; ) {
715 unsigned int tx_bytes;
716 u8 buf[sizeof(u32)];
717 int c;
718
719 memset(buf, 0, ARRAY_SIZE(buf));
720 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
721
722 for (c = 0; c < tx_bytes ; c++) {
723 buf[c] = xmit->buf[tail++];
724 tail &= UART_XMIT_SIZE - 1;
725 }
726
727 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
728
729 i += tx_bytes;
730 uport->icount.tx += tx_bytes;
731 remaining -= tx_bytes;
732 port->tx_remaining -= tx_bytes;
733 }
734
735 xmit->tail = tail;
736
737 /*
738 * The tx fifo watermark is level triggered and latched. Though we had
739 * cleared it in qcom_geni_serial_isr it will have already reasserted
740 * so we must clear it again here after our writes.
741 */
742 writel(M_TX_FIFO_WATERMARK_EN,
743 uport->membase + SE_GENI_M_IRQ_CLEAR);
744
745out_write_wakeup:
746 if (!port->tx_remaining) {
747 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
748 if (irq_en & M_TX_FIFO_WATERMARK_EN)
749 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
750 uport->membase + SE_GENI_M_IRQ_EN);
751 }
752
753 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
754 uart_write_wakeup(uport);
755}
756
757static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
758{
759 u32 m_irq_en;
760 u32 m_irq_status;
761 u32 s_irq_status;
762 u32 geni_status;
763 struct uart_port *uport = dev;
764 unsigned long flags;
765 bool drop_rx = false;
766 struct tty_port *tport = &uport->state->port;
767 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
768
769 if (uport->suspended)
770 return IRQ_NONE;
771
772 spin_lock_irqsave(&uport->lock, flags);
773 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
774 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
775 geni_status = readl(uport->membase + SE_GENI_STATUS);
776 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
777 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
778 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
779
780 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
781 goto out_unlock;
782
783 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
784 uport->icount.overrun++;
785 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
786 }
787
788 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
789 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
790 geni_status & M_GENI_CMD_ACTIVE);
791
792 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
793 if (s_irq_status & S_GP_IRQ_0_EN)
794 uport->icount.parity++;
795 drop_rx = true;
796 } else if (s_irq_status & S_GP_IRQ_2_EN ||
797 s_irq_status & S_GP_IRQ_3_EN) {
798 uport->icount.brk++;
799 port->brk = true;
800 }
801
802 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
803 s_irq_status & S_RX_FIFO_LAST_EN)
804 qcom_geni_serial_handle_rx(uport, drop_rx);
805
806out_unlock:
807 uart_unlock_and_check_sysrq(uport, flags);
808
809 return IRQ_HANDLED;
810}
811
812static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
813{
814 struct uart_port *uport;
815
816 uport = &port->uport;
817 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
818 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
819 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
820 uport->fifosize =
821 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
822}
823
824
825static void qcom_geni_serial_shutdown(struct uart_port *uport)
826{
827 unsigned long flags;
828
829 /* Stop the console before stopping the current tx */
830 if (uart_console(uport))
831 console_stop(uport->cons);
832
833 free_irq(uport->irq, uport);
834 spin_lock_irqsave(&uport->lock, flags);
835 qcom_geni_serial_stop_tx(uport);
836 qcom_geni_serial_stop_rx(uport);
837 spin_unlock_irqrestore(&uport->lock, flags);
838}
839
840static int qcom_geni_serial_port_setup(struct uart_port *uport)
841{
842 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
843 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
844 u32 proto;
845
846 if (uart_console(uport)) {
847 port->tx_bytes_pw = 1;
848 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
849 } else {
850 port->tx_bytes_pw = 4;
851 port->rx_bytes_pw = 4;
852 }
853
854 proto = geni_se_read_proto(&port->se);
855 if (proto != GENI_SE_UART) {
856 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
857 return -ENXIO;
858 }
859
860 qcom_geni_serial_stop_rx(uport);
861
862 get_tx_fifo_size(port);
863
864 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
865 /*
866 * Make an unconditional cancel on the main sequencer to reset
867 * it else we could end up in data loss scenarios.
868 */
869 if (uart_console(uport))
870 qcom_geni_serial_poll_tx_done(uport);
871 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
872 false, true, false);
873 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
874 false, false, true);
875 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
876 geni_se_select_mode(&port->se, GENI_SE_FIFO);
877 if (!uart_console(uport)) {
878 port->rx_fifo = devm_kcalloc(uport->dev,
879 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
880 if (!port->rx_fifo)
881 return -ENOMEM;
882 }
883 port->setup = true;
884
885 return 0;
886}
887
888static int qcom_geni_serial_startup(struct uart_port *uport)
889{
890 int ret;
891 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
892
893 scnprintf(port->name, sizeof(port->name),
894 "qcom_serial_%s%d",
895 (uart_console(uport) ? "console" : "uart"), uport->line);
896
897 if (!port->setup) {
898 ret = qcom_geni_serial_port_setup(uport);
899 if (ret)
900 return ret;
901 }
902
903 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
904 port->name, uport);
905 if (ret)
906 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
907 return ret;
908}
909
910static unsigned long get_clk_cfg(unsigned long clk_freq)
911{
912 int i;
913
914 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
915 if (!(root_freq[i] % clk_freq))
916 return root_freq[i];
917 }
918 return 0;
919}
920
921static unsigned long get_clk_div_rate(unsigned int baud,
922 unsigned int sampling_rate, unsigned int *clk_div)
923{
924 unsigned long ser_clk;
925 unsigned long desired_clk;
926
927 desired_clk = baud * sampling_rate;
928 ser_clk = get_clk_cfg(desired_clk);
929 if (!ser_clk) {
930 pr_err("%s: Can't find matching DFS entry for baud %d\n",
931 __func__, baud);
932 return ser_clk;
933 }
934
935 *clk_div = ser_clk / desired_clk;
936 return ser_clk;
937}
938
939static void qcom_geni_serial_set_termios(struct uart_port *uport,
940 struct ktermios *termios, struct ktermios *old)
941{
942 unsigned int baud;
943 u32 bits_per_char;
944 u32 tx_trans_cfg;
945 u32 tx_parity_cfg;
946 u32 rx_trans_cfg;
947 u32 rx_parity_cfg;
948 u32 stop_bit_len;
949 unsigned int clk_div;
950 u32 ser_clk_cfg;
951 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
952 unsigned long clk_rate;
953 u32 ver, sampling_rate;
954
955 qcom_geni_serial_stop_rx(uport);
956 /* baud rate */
957 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
958 port->baud = baud;
959
960 sampling_rate = UART_OVERSAMPLING;
961 /* Sampling rate is halved for IP versions >= 2.5 */
962 ver = geni_se_get_qup_hw_version(&port->se);
963 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
964 sampling_rate /= 2;
965
966 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
967 if (!clk_rate)
968 goto out_restart_rx;
969
970 uport->uartclk = clk_rate;
971 clk_set_rate(port->se.clk, clk_rate);
972 ser_clk_cfg = SER_CLK_EN;
973 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
974
975 /* parity */
976 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
977 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
978 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
979 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
980 if (termios->c_cflag & PARENB) {
981 tx_trans_cfg |= UART_TX_PAR_EN;
982 rx_trans_cfg |= UART_RX_PAR_EN;
983 tx_parity_cfg |= PAR_CALC_EN;
984 rx_parity_cfg |= PAR_CALC_EN;
985 if (termios->c_cflag & PARODD) {
986 tx_parity_cfg |= PAR_ODD;
987 rx_parity_cfg |= PAR_ODD;
988 } else if (termios->c_cflag & CMSPAR) {
989 tx_parity_cfg |= PAR_SPACE;
990 rx_parity_cfg |= PAR_SPACE;
991 } else {
992 tx_parity_cfg |= PAR_EVEN;
993 rx_parity_cfg |= PAR_EVEN;
994 }
995 } else {
996 tx_trans_cfg &= ~UART_TX_PAR_EN;
997 rx_trans_cfg &= ~UART_RX_PAR_EN;
998 tx_parity_cfg &= ~PAR_CALC_EN;
999 rx_parity_cfg &= ~PAR_CALC_EN;
1000 }
1001
1002 /* bits per char */
1003 switch (termios->c_cflag & CSIZE) {
1004 case CS5:
1005 bits_per_char = 5;
1006 break;
1007 case CS6:
1008 bits_per_char = 6;
1009 break;
1010 case CS7:
1011 bits_per_char = 7;
1012 break;
1013 case CS8:
1014 default:
1015 bits_per_char = 8;
1016 break;
1017 }
1018
1019 /* stop bits */
1020 if (termios->c_cflag & CSTOPB)
1021 stop_bit_len = TX_STOP_BIT_LEN_2;
1022 else
1023 stop_bit_len = TX_STOP_BIT_LEN_1;
1024
1025 /* flow control, clear the CTS_MASK bit if using flow control. */
1026 if (termios->c_cflag & CRTSCTS)
1027 tx_trans_cfg &= ~UART_CTS_MASK;
1028 else
1029 tx_trans_cfg |= UART_CTS_MASK;
1030
1031 if (baud)
1032 uart_update_timeout(uport, termios->c_cflag, baud);
1033
1034 if (!uart_console(uport))
1035 writel(port->loopback,
1036 uport->membase + SE_UART_LOOPBACK_CFG);
1037 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1038 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1039 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1040 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1041 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1042 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1043 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1044 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1045 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1046out_restart_rx:
1047 qcom_geni_serial_start_rx(uport);
1048}
1049
1050static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1051{
1052 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1053}
1054
1055#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1056static int __init qcom_geni_console_setup(struct console *co, char *options)
1057{
1058 struct uart_port *uport;
1059 struct qcom_geni_serial_port *port;
1060 int baud = 9600;
1061 int bits = 8;
1062 int parity = 'n';
1063 int flow = 'n';
1064 int ret;
1065
1066 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1067 return -ENXIO;
1068
1069 port = get_port_from_line(co->index, true);
1070 if (IS_ERR(port)) {
1071 pr_err("Invalid line %d\n", co->index);
1072 return PTR_ERR(port);
1073 }
1074
1075 uport = &port->uport;
1076
1077 if (unlikely(!uport->membase))
1078 return -ENXIO;
1079
1080 if (!port->setup) {
1081 ret = qcom_geni_serial_port_setup(uport);
1082 if (ret)
1083 return ret;
1084 }
1085
1086 if (options)
1087 uart_parse_options(options, &baud, &parity, &bits, &flow);
1088
1089 return uart_set_options(uport, co, baud, parity, bits, flow);
1090}
1091
1092static void qcom_geni_serial_earlycon_write(struct console *con,
1093 const char *s, unsigned int n)
1094{
1095 struct earlycon_device *dev = con->data;
1096
1097 __qcom_geni_serial_console_write(&dev->port, s, n);
1098}
1099
1100static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1101 const char *opt)
1102{
1103 struct uart_port *uport = &dev->port;
1104 u32 tx_trans_cfg;
1105 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1106 u32 rx_trans_cfg = 0;
1107 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1108 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1109 u32 bits_per_char;
1110 struct geni_se se;
1111
1112 if (!uport->membase)
1113 return -EINVAL;
1114
1115 memset(&se, 0, sizeof(se));
1116 se.base = uport->membase;
1117 if (geni_se_read_proto(&se) != GENI_SE_UART)
1118 return -ENXIO;
1119 /*
1120 * Ignore Flow control.
1121 * n = 8.
1122 */
1123 tx_trans_cfg = UART_CTS_MASK;
1124 bits_per_char = BITS_PER_BYTE;
1125
1126 /*
1127 * Make an unconditional cancel on the main sequencer to reset
1128 * it else we could end up in data loss scenarios.
1129 */
1130 qcom_geni_serial_poll_tx_done(uport);
1131 qcom_geni_serial_abort_rx(uport);
1132 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1133 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1134 geni_se_select_mode(&se, GENI_SE_FIFO);
1135
1136 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1137 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1138 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1139 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1140 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1141 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1142 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1143
1144 dev->con->write = qcom_geni_serial_earlycon_write;
1145 dev->con->setup = NULL;
1146 return 0;
1147}
1148OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1149 qcom_geni_serial_earlycon_setup);
1150
1151static int __init console_register(struct uart_driver *drv)
1152{
1153 return uart_register_driver(drv);
1154}
1155
1156static void console_unregister(struct uart_driver *drv)
1157{
1158 uart_unregister_driver(drv);
1159}
1160
1161static struct console cons_ops = {
1162 .name = "ttyMSM",
1163 .write = qcom_geni_serial_console_write,
1164 .device = uart_console_device,
1165 .setup = qcom_geni_console_setup,
1166 .flags = CON_PRINTBUFFER,
1167 .index = -1,
1168 .data = &qcom_geni_console_driver,
1169};
1170
1171static struct uart_driver qcom_geni_console_driver = {
1172 .owner = THIS_MODULE,
1173 .driver_name = "qcom_geni_console",
1174 .dev_name = "ttyMSM",
1175 .nr = GENI_UART_CONS_PORTS,
1176 .cons = &cons_ops,
1177};
1178#else
1179static int console_register(struct uart_driver *drv)
1180{
1181 return 0;
1182}
1183
1184static void console_unregister(struct uart_driver *drv)
1185{
1186}
1187#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1188
1189static struct uart_driver qcom_geni_uart_driver = {
1190 .owner = THIS_MODULE,
1191 .driver_name = "qcom_geni_uart",
1192 .dev_name = "ttyHS",
1193 .nr = GENI_UART_PORTS,
1194};
1195
1196static void qcom_geni_serial_pm(struct uart_port *uport,
1197 unsigned int new_state, unsigned int old_state)
1198{
1199 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1200
1201 /* If we've never been called, treat it as off */
1202 if (old_state == UART_PM_STATE_UNDEFINED)
1203 old_state = UART_PM_STATE_OFF;
1204
1205 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1206 geni_se_resources_on(&port->se);
1207 else if (new_state == UART_PM_STATE_OFF &&
1208 old_state == UART_PM_STATE_ON)
1209 geni_se_resources_off(&port->se);
1210}
1211
1212static const struct uart_ops qcom_geni_console_pops = {
1213 .tx_empty = qcom_geni_serial_tx_empty,
1214 .stop_tx = qcom_geni_serial_stop_tx,
1215 .start_tx = qcom_geni_serial_start_tx,
1216 .stop_rx = qcom_geni_serial_stop_rx,
1217 .set_termios = qcom_geni_serial_set_termios,
1218 .startup = qcom_geni_serial_startup,
1219 .request_port = qcom_geni_serial_request_port,
1220 .config_port = qcom_geni_serial_config_port,
1221 .shutdown = qcom_geni_serial_shutdown,
1222 .type = qcom_geni_serial_get_type,
1223 .set_mctrl = qcom_geni_serial_set_mctrl,
1224 .get_mctrl = qcom_geni_serial_get_mctrl,
1225#ifdef CONFIG_CONSOLE_POLL
1226 .poll_get_char = qcom_geni_serial_get_char,
1227 .poll_put_char = qcom_geni_serial_poll_put_char,
1228#endif
1229 .pm = qcom_geni_serial_pm,
1230};
1231
1232static const struct uart_ops qcom_geni_uart_pops = {
1233 .tx_empty = qcom_geni_serial_tx_empty,
1234 .stop_tx = qcom_geni_serial_stop_tx,
1235 .start_tx = qcom_geni_serial_start_tx,
1236 .stop_rx = qcom_geni_serial_stop_rx,
1237 .set_termios = qcom_geni_serial_set_termios,
1238 .startup = qcom_geni_serial_startup,
1239 .request_port = qcom_geni_serial_request_port,
1240 .config_port = qcom_geni_serial_config_port,
1241 .shutdown = qcom_geni_serial_shutdown,
1242 .type = qcom_geni_serial_get_type,
1243 .set_mctrl = qcom_geni_serial_set_mctrl,
1244 .get_mctrl = qcom_geni_serial_get_mctrl,
1245 .pm = qcom_geni_serial_pm,
1246};
1247
1248static int qcom_geni_serial_probe(struct platform_device *pdev)
1249{
1250 int ret = 0;
1251 int line = -1;
1252 struct qcom_geni_serial_port *port;
1253 struct uart_port *uport;
1254 struct resource *res;
1255 int irq;
1256 bool console = false;
1257 struct uart_driver *drv;
1258
1259 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1260 console = true;
1261
1262 if (console) {
1263 drv = &qcom_geni_console_driver;
1264 line = of_alias_get_id(pdev->dev.of_node, "serial");
1265 } else {
1266 drv = &qcom_geni_uart_driver;
1267 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1268 }
1269
1270 port = get_port_from_line(line, console);
1271 if (IS_ERR(port)) {
1272 dev_err(&pdev->dev, "Invalid line %d\n", line);
1273 return PTR_ERR(port);
1274 }
1275
1276 uport = &port->uport;
1277 /* Don't allow 2 drivers to access the same port */
1278 if (uport->private_data)
1279 return -ENODEV;
1280
1281 uport->dev = &pdev->dev;
1282 port->se.dev = &pdev->dev;
1283 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1284 port->se.clk = devm_clk_get(&pdev->dev, "se");
1285 if (IS_ERR(port->se.clk)) {
1286 ret = PTR_ERR(port->se.clk);
1287 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1288 return ret;
1289 }
1290
1291 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292 if (!res)
1293 return -EINVAL;
1294 uport->mapbase = res->start;
1295
1296 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1297 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1298 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1299
1300 irq = platform_get_irq(pdev, 0);
1301 if (irq < 0)
1302 return irq;
1303 uport->irq = irq;
1304
1305 uport->private_data = drv;
1306 platform_set_drvdata(pdev, port);
1307 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1308 if (!console)
1309 device_create_file(uport->dev, &dev_attr_loopback);
1310 return uart_add_one_port(drv, uport);
1311}
1312
1313static int qcom_geni_serial_remove(struct platform_device *pdev)
1314{
1315 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1316 struct uart_driver *drv = port->uport.private_data;
1317
1318 uart_remove_one_port(drv, &port->uport);
1319 return 0;
1320}
1321
1322static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1323{
1324 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1325 struct uart_port *uport = &port->uport;
1326
1327 return uart_suspend_port(uport->private_data, uport);
1328}
1329
1330static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1331{
1332 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1333 struct uart_port *uport = &port->uport;
1334
1335 return uart_resume_port(uport->private_data, uport);
1336}
1337
1338static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1339 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1340 qcom_geni_serial_sys_resume)
1341};
1342
1343static const struct of_device_id qcom_geni_serial_match_table[] = {
1344 { .compatible = "qcom,geni-debug-uart", },
1345 { .compatible = "qcom,geni-uart", },
1346 {}
1347};
1348MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1349
1350static struct platform_driver qcom_geni_serial_platform_driver = {
1351 .remove = qcom_geni_serial_remove,
1352 .probe = qcom_geni_serial_probe,
1353 .driver = {
1354 .name = "qcom_geni_serial",
1355 .of_match_table = qcom_geni_serial_match_table,
1356 .pm = &qcom_geni_serial_pm_ops,
1357 },
1358};
1359
1360static int __init qcom_geni_serial_init(void)
1361{
1362 int ret;
1363
1364 ret = console_register(&qcom_geni_console_driver);
1365 if (ret)
1366 return ret;
1367
1368 ret = uart_register_driver(&qcom_geni_uart_driver);
1369 if (ret) {
1370 console_unregister(&qcom_geni_console_driver);
1371 return ret;
1372 }
1373
1374 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1375 if (ret) {
1376 console_unregister(&qcom_geni_console_driver);
1377 uart_unregister_driver(&qcom_geni_uart_driver);
1378 }
1379 return ret;
1380}
1381module_init(qcom_geni_serial_init);
1382
1383static void __exit qcom_geni_serial_exit(void)
1384{
1385 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1386 console_unregister(&qcom_geni_console_driver);
1387 uart_unregister_driver(&qcom_geni_uart_driver);
1388}
1389module_exit(qcom_geni_serial_exit);
1390
1391MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1392MODULE_LICENSE("GPL v2");