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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#if defined(CONFIG_SERIAL_QCOM_GENI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
5# define SUPPORT_SYSRQ
6#endif
7
8#include <linux/clk.h>
9#include <linux/console.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/qcom-geni-se.h>
17#include <linux/serial.h>
18#include <linux/serial_core.h>
19#include <linux/slab.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22
23/* UART specific GENI registers */
24#define SE_UART_LOOPBACK_CFG 0x22c
25#define SE_UART_TX_TRANS_CFG 0x25c
26#define SE_UART_TX_WORD_LEN 0x268
27#define SE_UART_TX_STOP_BIT_LEN 0x26c
28#define SE_UART_TX_TRANS_LEN 0x270
29#define SE_UART_RX_TRANS_CFG 0x280
30#define SE_UART_RX_WORD_LEN 0x28c
31#define SE_UART_RX_STALE_CNT 0x294
32#define SE_UART_TX_PARITY_CFG 0x2a4
33#define SE_UART_RX_PARITY_CFG 0x2a8
34#define SE_UART_MANUAL_RFR 0x2ac
35
36/* SE_UART_TRANS_CFG */
37#define UART_TX_PAR_EN BIT(0)
38#define UART_CTS_MASK BIT(1)
39
40/* SE_UART_TX_WORD_LEN */
41#define TX_WORD_LEN_MSK GENMASK(9, 0)
42
43/* SE_UART_TX_STOP_BIT_LEN */
44#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
45#define TX_STOP_BIT_LEN_1 0
46#define TX_STOP_BIT_LEN_1_5 1
47#define TX_STOP_BIT_LEN_2 2
48
49/* SE_UART_TX_TRANS_LEN */
50#define TX_TRANS_LEN_MSK GENMASK(23, 0)
51
52/* SE_UART_RX_TRANS_CFG */
53#define UART_RX_INS_STATUS_BIT BIT(2)
54#define UART_RX_PAR_EN BIT(3)
55
56/* SE_UART_RX_WORD_LEN */
57#define RX_WORD_LEN_MASK GENMASK(9, 0)
58
59/* SE_UART_RX_STALE_CNT */
60#define RX_STALE_CNT GENMASK(23, 0)
61
62/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
63#define PAR_CALC_EN BIT(0)
64#define PAR_MODE_MSK GENMASK(2, 1)
65#define PAR_MODE_SHFT 1
66#define PAR_EVEN 0x00
67#define PAR_ODD 0x01
68#define PAR_SPACE 0x10
69#define PAR_MARK 0x11
70
71/* SE_UART_MANUAL_RFR register fields */
72#define UART_MANUAL_RFR_EN BIT(31)
73#define UART_RFR_NOT_READY BIT(1)
74#define UART_RFR_READY BIT(0)
75
76/* UART M_CMD OP codes */
77#define UART_START_TX 0x1
78#define UART_START_BREAK 0x4
79#define UART_STOP_BREAK 0x5
80/* UART S_CMD OP codes */
81#define UART_START_READ 0x1
82#define UART_PARAM 0x1
83
84#define UART_OVERSAMPLING 32
85#define STALE_TIMEOUT 16
86#define DEFAULT_BITS_PER_CHAR 10
87#define GENI_UART_CONS_PORTS 1
88#define GENI_UART_PORTS 3
89#define DEF_FIFO_DEPTH_WORDS 16
90#define DEF_TX_WM 2
91#define DEF_FIFO_WIDTH_BITS 32
92#define UART_RX_WM 2
93#define MAX_LOOPBACK_CFG 3
94
95#ifdef CONFIG_CONSOLE_POLL
96#define CONSOLE_RX_BYTES_PW 1
97#else
98#define CONSOLE_RX_BYTES_PW 4
99#endif
100
101struct qcom_geni_serial_port {
102 struct uart_port uport;
103 struct geni_se se;
104 char name[20];
105 u32 tx_fifo_depth;
106 u32 tx_fifo_width;
107 u32 rx_fifo_depth;
108 bool setup;
109 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
110 unsigned int baud;
111 unsigned int tx_bytes_pw;
112 unsigned int rx_bytes_pw;
113 u32 *rx_fifo;
114 u32 loopback;
115 bool brk;
116
117 unsigned int tx_remaining;
118};
119
120static const struct uart_ops qcom_geni_console_pops;
121static const struct uart_ops qcom_geni_uart_pops;
122static struct uart_driver qcom_geni_console_driver;
123static struct uart_driver qcom_geni_uart_driver;
124static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
125static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
126static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
127static void qcom_geni_serial_stop_rx(struct uart_port *uport);
128
129static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
130 32000000, 48000000, 64000000, 80000000,
131 96000000, 100000000, 102400000,
132 112000000, 120000000, 128000000};
133
134#define to_dev_port(ptr, member) \
135 container_of(ptr, struct qcom_geni_serial_port, member)
136
137static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
138 [0] = {
139 .uport = {
140 .iotype = UPIO_MEM,
141 .ops = &qcom_geni_uart_pops,
142 .flags = UPF_BOOT_AUTOCONF,
143 .line = 0,
144 },
145 },
146 [1] = {
147 .uport = {
148 .iotype = UPIO_MEM,
149 .ops = &qcom_geni_uart_pops,
150 .flags = UPF_BOOT_AUTOCONF,
151 .line = 1,
152 },
153 },
154 [2] = {
155 .uport = {
156 .iotype = UPIO_MEM,
157 .ops = &qcom_geni_uart_pops,
158 .flags = UPF_BOOT_AUTOCONF,
159 .line = 2,
160 },
161 },
162};
163
164static ssize_t loopback_show(struct device *dev,
165 struct device_attribute *attr, char *buf)
166{
167 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
168
169 return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
170}
171
172static ssize_t loopback_store(struct device *dev,
173 struct device_attribute *attr, const char *buf,
174 size_t size)
175{
176 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
177 u32 loopback;
178
179 if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
180 dev_err(dev, "Invalid input\n");
181 return -EINVAL;
182 }
183 port->loopback = loopback;
184 return size;
185}
186static DEVICE_ATTR_RW(loopback);
187
188static struct qcom_geni_serial_port qcom_geni_console_port = {
189 .uport = {
190 .iotype = UPIO_MEM,
191 .ops = &qcom_geni_console_pops,
192 .flags = UPF_BOOT_AUTOCONF,
193 .line = 0,
194 },
195};
196
197static int qcom_geni_serial_request_port(struct uart_port *uport)
198{
199 struct platform_device *pdev = to_platform_device(uport->dev);
200 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
201
202 uport->membase = devm_platform_ioremap_resource(pdev, 0);
203 if (IS_ERR(uport->membase))
204 return PTR_ERR(uport->membase);
205 port->se.base = uport->membase;
206 return 0;
207}
208
209static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
210{
211 if (cfg_flags & UART_CONFIG_TYPE) {
212 uport->type = PORT_MSM;
213 qcom_geni_serial_request_port(uport);
214 }
215}
216
217static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
218{
219 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
220 u32 geni_ios;
221
222 if (uart_console(uport)) {
223 mctrl |= TIOCM_CTS;
224 } else {
225 geni_ios = readl(uport->membase + SE_GENI_IOS);
226 if (!(geni_ios & IO2_DATA_IN))
227 mctrl |= TIOCM_CTS;
228 }
229
230 return mctrl;
231}
232
233static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
234 unsigned int mctrl)
235{
236 u32 uart_manual_rfr = 0;
237
238 if (uart_console(uport))
239 return;
240
241 if (!(mctrl & TIOCM_RTS))
242 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
243 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
244}
245
246static const char *qcom_geni_serial_get_type(struct uart_port *uport)
247{
248 return "MSM";
249}
250
251static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
252{
253 struct qcom_geni_serial_port *port;
254 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
255
256 if (line < 0 || line >= nr_ports)
257 return ERR_PTR(-ENXIO);
258
259 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
260 return port;
261}
262
263static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
264 int offset, int field, bool set)
265{
266 u32 reg;
267 struct qcom_geni_serial_port *port;
268 unsigned int baud;
269 unsigned int fifo_bits;
270 unsigned long timeout_us = 20000;
271
272 if (uport->private_data) {
273 port = to_dev_port(uport, uport);
274 baud = port->baud;
275 if (!baud)
276 baud = 115200;
277 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
278 /*
279 * Total polling iterations based on FIFO worth of bytes to be
280 * sent at current baud. Add a little fluff to the wait.
281 */
282 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
283 }
284
285 /*
286 * Use custom implementation instead of readl_poll_atomic since ktimer
287 * is not ready at the time of early console.
288 */
289 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
290 while (timeout_us) {
291 reg = readl(uport->membase + offset);
292 if ((bool)(reg & field) == set)
293 return true;
294 udelay(10);
295 timeout_us -= 10;
296 }
297 return false;
298}
299
300static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
301{
302 u32 m_cmd;
303
304 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
305 m_cmd = UART_START_TX << M_OPCODE_SHFT;
306 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
307}
308
309static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
310{
311 int done;
312 u32 irq_clear = M_CMD_DONE_EN;
313
314 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
315 M_CMD_DONE_EN, true);
316 if (!done) {
317 writel(M_GENI_CMD_ABORT, uport->membase +
318 SE_GENI_M_CMD_CTRL_REG);
319 irq_clear |= M_CMD_ABORT_EN;
320 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
321 M_CMD_ABORT_EN, true);
322 }
323 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
324}
325
326static void qcom_geni_serial_abort_rx(struct uart_port *uport)
327{
328 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
329
330 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
331 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
332 S_GENI_CMD_ABORT, false);
333 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
334 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
335}
336
337#ifdef CONFIG_CONSOLE_POLL
338static int qcom_geni_serial_get_char(struct uart_port *uport)
339{
340 u32 rx_fifo;
341 u32 status;
342
343 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
344 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
345
346 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
347 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
348
349 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
350 if (!(status & RX_FIFO_WC_MSK))
351 return NO_POLL_CHAR;
352
353 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
354 return rx_fifo & 0xff;
355}
356
357static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
358 unsigned char c)
359{
360 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
361 qcom_geni_serial_setup_tx(uport, 1);
362 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
363 M_TX_FIFO_WATERMARK_EN, true));
364 writel(c, uport->membase + SE_GENI_TX_FIFOn);
365 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
366 qcom_geni_serial_poll_tx_done(uport);
367}
368#endif
369
370#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
371static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
372{
373 writel(ch, uport->membase + SE_GENI_TX_FIFOn);
374}
375
376static void
377__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
378 unsigned int count)
379{
380 int i;
381 u32 bytes_to_send = count;
382
383 for (i = 0; i < count; i++) {
384 /*
385 * uart_console_write() adds a carriage return for each newline.
386 * Account for additional bytes to be written.
387 */
388 if (s[i] == '\n')
389 bytes_to_send++;
390 }
391
392 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
393 qcom_geni_serial_setup_tx(uport, bytes_to_send);
394 for (i = 0; i < count; ) {
395 size_t chars_to_write = 0;
396 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
397
398 /*
399 * If the WM bit never set, then the Tx state machine is not
400 * in a valid state, so break, cancel/abort any existing
401 * command. Unfortunately the current data being written is
402 * lost.
403 */
404 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
405 M_TX_FIFO_WATERMARK_EN, true))
406 break;
407 chars_to_write = min_t(size_t, count - i, avail / 2);
408 uart_console_write(uport, s + i, chars_to_write,
409 qcom_geni_serial_wr_char);
410 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
411 SE_GENI_M_IRQ_CLEAR);
412 i += chars_to_write;
413 }
414 qcom_geni_serial_poll_tx_done(uport);
415}
416
417static void qcom_geni_serial_console_write(struct console *co, const char *s,
418 unsigned int count)
419{
420 struct uart_port *uport;
421 struct qcom_geni_serial_port *port;
422 bool locked = true;
423 unsigned long flags;
424 u32 geni_status;
425 u32 irq_en;
426
427 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
428
429 port = get_port_from_line(co->index, true);
430 if (IS_ERR(port))
431 return;
432
433 uport = &port->uport;
434 if (oops_in_progress)
435 locked = spin_trylock_irqsave(&uport->lock, flags);
436 else
437 spin_lock_irqsave(&uport->lock, flags);
438
439 geni_status = readl(uport->membase + SE_GENI_STATUS);
440
441 /* Cancel the current write to log the fault */
442 if (!locked) {
443 geni_se_cancel_m_cmd(&port->se);
444 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
445 M_CMD_CANCEL_EN, true)) {
446 geni_se_abort_m_cmd(&port->se);
447 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
448 M_CMD_ABORT_EN, true);
449 writel(M_CMD_ABORT_EN, uport->membase +
450 SE_GENI_M_IRQ_CLEAR);
451 }
452 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
453 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
454 /*
455 * It seems we can't interrupt existing transfers if all data
456 * has been sent, in which case we need to look for done first.
457 */
458 qcom_geni_serial_poll_tx_done(uport);
459
460 if (uart_circ_chars_pending(&uport->state->xmit)) {
461 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
462 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
463 uport->membase + SE_GENI_M_IRQ_EN);
464 }
465 }
466
467 __qcom_geni_serial_console_write(uport, s, count);
468
469 if (port->tx_remaining)
470 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
471
472 if (locked)
473 spin_unlock_irqrestore(&uport->lock, flags);
474}
475
476static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
477{
478 u32 i;
479 unsigned char buf[sizeof(u32)];
480 struct tty_port *tport;
481 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
482
483 tport = &uport->state->port;
484 for (i = 0; i < bytes; ) {
485 int c;
486 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
487
488 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
489 i += chunk;
490 if (drop)
491 continue;
492
493 for (c = 0; c < chunk; c++) {
494 int sysrq;
495
496 uport->icount.rx++;
497 if (port->brk && buf[c] == 0) {
498 port->brk = false;
499 if (uart_handle_break(uport))
500 continue;
501 }
502
503 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
504
505 if (!sysrq)
506 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
507 }
508 }
509 if (!drop)
510 tty_flip_buffer_push(tport);
511 return 0;
512}
513#else
514static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
515{
516 return -EPERM;
517}
518
519#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
520
521static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
522{
523 unsigned char *buf;
524 struct tty_port *tport;
525 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
526 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
527 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
528 int ret;
529
530 tport = &uport->state->port;
531 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
532 if (drop)
533 return 0;
534
535 buf = (unsigned char *)port->rx_fifo;
536 ret = tty_insert_flip_string(tport, buf, bytes);
537 if (ret != bytes) {
538 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
539 __func__, ret, bytes);
540 WARN_ON_ONCE(1);
541 }
542 uport->icount.rx += ret;
543 tty_flip_buffer_push(tport);
544 return ret;
545}
546
547static void qcom_geni_serial_start_tx(struct uart_port *uport)
548{
549 u32 irq_en;
550 u32 status;
551
552 status = readl(uport->membase + SE_GENI_STATUS);
553 if (status & M_GENI_CMD_ACTIVE)
554 return;
555
556 if (!qcom_geni_serial_tx_empty(uport))
557 return;
558
559 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
560 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
561
562 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
563 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
564}
565
566static void qcom_geni_serial_stop_tx(struct uart_port *uport)
567{
568 u32 irq_en;
569 u32 status;
570 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
571
572 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
573 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
574 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
575 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
576 status = readl(uport->membase + SE_GENI_STATUS);
577 /* Possible stop tx is called multiple times. */
578 if (!(status & M_GENI_CMD_ACTIVE))
579 return;
580
581 geni_se_cancel_m_cmd(&port->se);
582 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
583 M_CMD_CANCEL_EN, true)) {
584 geni_se_abort_m_cmd(&port->se);
585 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
586 M_CMD_ABORT_EN, true);
587 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
588 }
589 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
590}
591
592static void qcom_geni_serial_start_rx(struct uart_port *uport)
593{
594 u32 irq_en;
595 u32 status;
596 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
597
598 status = readl(uport->membase + SE_GENI_STATUS);
599 if (status & S_GENI_CMD_ACTIVE)
600 qcom_geni_serial_stop_rx(uport);
601
602 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
603
604 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
605 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
606 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
607
608 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
609 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
610 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
611}
612
613static void qcom_geni_serial_stop_rx(struct uart_port *uport)
614{
615 u32 irq_en;
616 u32 status;
617 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
618 u32 irq_clear = S_CMD_DONE_EN;
619
620 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
621 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
622 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
623
624 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
625 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
626 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
627
628 status = readl(uport->membase + SE_GENI_STATUS);
629 /* Possible stop rx is called multiple times. */
630 if (!(status & S_GENI_CMD_ACTIVE))
631 return;
632
633 geni_se_cancel_s_cmd(&port->se);
634 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
635 S_GENI_CMD_CANCEL, false);
636 status = readl(uport->membase + SE_GENI_STATUS);
637 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
638 if (status & S_GENI_CMD_ACTIVE)
639 qcom_geni_serial_abort_rx(uport);
640}
641
642static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
643{
644 u32 status;
645 u32 word_cnt;
646 u32 last_word_byte_cnt;
647 u32 last_word_partial;
648 u32 total_bytes;
649 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
650
651 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
652 word_cnt = status & RX_FIFO_WC_MSK;
653 last_word_partial = status & RX_LAST;
654 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
655 RX_LAST_BYTE_VALID_SHFT;
656
657 if (!word_cnt)
658 return;
659 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
660 if (last_word_partial && last_word_byte_cnt)
661 total_bytes += last_word_byte_cnt;
662 else
663 total_bytes += port->rx_bytes_pw;
664 port->handle_rx(uport, total_bytes, drop);
665}
666
667static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
668 bool active)
669{
670 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
671 struct circ_buf *xmit = &uport->state->xmit;
672 size_t avail;
673 size_t remaining;
674 size_t pending;
675 int i;
676 u32 status;
677 u32 irq_en;
678 unsigned int chunk;
679 int tail;
680
681 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
682
683 /* Complete the current tx command before taking newly added data */
684 if (active)
685 pending = port->tx_remaining;
686 else
687 pending = uart_circ_chars_pending(xmit);
688
689 /* All data has been transmitted and acknowledged as received */
690 if (!pending && !status && done) {
691 qcom_geni_serial_stop_tx(uport);
692 goto out_write_wakeup;
693 }
694
695 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
696 avail *= port->tx_bytes_pw;
697
698 tail = xmit->tail;
699 chunk = min(avail, pending);
700 if (!chunk)
701 goto out_write_wakeup;
702
703 if (!port->tx_remaining) {
704 qcom_geni_serial_setup_tx(uport, pending);
705 port->tx_remaining = pending;
706
707 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
708 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
709 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
710 uport->membase + SE_GENI_M_IRQ_EN);
711 }
712
713 remaining = chunk;
714 for (i = 0; i < chunk; ) {
715 unsigned int tx_bytes;
716 u8 buf[sizeof(u32)];
717 int c;
718
719 memset(buf, 0, ARRAY_SIZE(buf));
720 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
721
722 for (c = 0; c < tx_bytes ; c++) {
723 buf[c] = xmit->buf[tail++];
724 tail &= UART_XMIT_SIZE - 1;
725 }
726
727 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
728
729 i += tx_bytes;
730 uport->icount.tx += tx_bytes;
731 remaining -= tx_bytes;
732 port->tx_remaining -= tx_bytes;
733 }
734
735 xmit->tail = tail;
736
737 /*
738 * The tx fifo watermark is level triggered and latched. Though we had
739 * cleared it in qcom_geni_serial_isr it will have already reasserted
740 * so we must clear it again here after our writes.
741 */
742 writel(M_TX_FIFO_WATERMARK_EN,
743 uport->membase + SE_GENI_M_IRQ_CLEAR);
744
745out_write_wakeup:
746 if (!port->tx_remaining) {
747 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
748 if (irq_en & M_TX_FIFO_WATERMARK_EN)
749 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
750 uport->membase + SE_GENI_M_IRQ_EN);
751 }
752
753 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
754 uart_write_wakeup(uport);
755}
756
757static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
758{
759 u32 m_irq_en;
760 u32 m_irq_status;
761 u32 s_irq_status;
762 u32 geni_status;
763 struct uart_port *uport = dev;
764 unsigned long flags;
765 bool drop_rx = false;
766 struct tty_port *tport = &uport->state->port;
767 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
768
769 if (uport->suspended)
770 return IRQ_NONE;
771
772 spin_lock_irqsave(&uport->lock, flags);
773 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
774 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
775 geni_status = readl(uport->membase + SE_GENI_STATUS);
776 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
777 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
778 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
779
780 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
781 goto out_unlock;
782
783 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
784 uport->icount.overrun++;
785 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
786 }
787
788 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
789 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
790 geni_status & M_GENI_CMD_ACTIVE);
791
792 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
793 if (s_irq_status & S_GP_IRQ_0_EN)
794 uport->icount.parity++;
795 drop_rx = true;
796 } else if (s_irq_status & S_GP_IRQ_2_EN ||
797 s_irq_status & S_GP_IRQ_3_EN) {
798 uport->icount.brk++;
799 port->brk = true;
800 }
801
802 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
803 s_irq_status & S_RX_FIFO_LAST_EN)
804 qcom_geni_serial_handle_rx(uport, drop_rx);
805
806out_unlock:
807 uart_unlock_and_check_sysrq(uport, flags);
808
809 return IRQ_HANDLED;
810}
811
812static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
813{
814 struct uart_port *uport;
815
816 uport = &port->uport;
817 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
818 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
819 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
820 uport->fifosize =
821 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
822}
823
824
825static void qcom_geni_serial_shutdown(struct uart_port *uport)
826{
827 unsigned long flags;
828
829 /* Stop the console before stopping the current tx */
830 if (uart_console(uport))
831 console_stop(uport->cons);
832
833 free_irq(uport->irq, uport);
834 spin_lock_irqsave(&uport->lock, flags);
835 qcom_geni_serial_stop_tx(uport);
836 qcom_geni_serial_stop_rx(uport);
837 spin_unlock_irqrestore(&uport->lock, flags);
838}
839
840static int qcom_geni_serial_port_setup(struct uart_port *uport)
841{
842 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
843 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
844 u32 proto;
845
846 if (uart_console(uport)) {
847 port->tx_bytes_pw = 1;
848 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
849 } else {
850 port->tx_bytes_pw = 4;
851 port->rx_bytes_pw = 4;
852 }
853
854 proto = geni_se_read_proto(&port->se);
855 if (proto != GENI_SE_UART) {
856 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
857 return -ENXIO;
858 }
859
860 qcom_geni_serial_stop_rx(uport);
861
862 get_tx_fifo_size(port);
863
864 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
865 /*
866 * Make an unconditional cancel on the main sequencer to reset
867 * it else we could end up in data loss scenarios.
868 */
869 if (uart_console(uport))
870 qcom_geni_serial_poll_tx_done(uport);
871 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
872 false, true, false);
873 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
874 false, false, true);
875 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
876 geni_se_select_mode(&port->se, GENI_SE_FIFO);
877 if (!uart_console(uport)) {
878 port->rx_fifo = devm_kcalloc(uport->dev,
879 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
880 if (!port->rx_fifo)
881 return -ENOMEM;
882 }
883 port->setup = true;
884
885 return 0;
886}
887
888static int qcom_geni_serial_startup(struct uart_port *uport)
889{
890 int ret;
891 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
892
893 scnprintf(port->name, sizeof(port->name),
894 "qcom_serial_%s%d",
895 (uart_console(uport) ? "console" : "uart"), uport->line);
896
897 if (!port->setup) {
898 ret = qcom_geni_serial_port_setup(uport);
899 if (ret)
900 return ret;
901 }
902
903 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
904 port->name, uport);
905 if (ret)
906 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
907 return ret;
908}
909
910static unsigned long get_clk_cfg(unsigned long clk_freq)
911{
912 int i;
913
914 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
915 if (!(root_freq[i] % clk_freq))
916 return root_freq[i];
917 }
918 return 0;
919}
920
921static unsigned long get_clk_div_rate(unsigned int baud,
922 unsigned int sampling_rate, unsigned int *clk_div)
923{
924 unsigned long ser_clk;
925 unsigned long desired_clk;
926
927 desired_clk = baud * sampling_rate;
928 ser_clk = get_clk_cfg(desired_clk);
929 if (!ser_clk) {
930 pr_err("%s: Can't find matching DFS entry for baud %d\n",
931 __func__, baud);
932 return ser_clk;
933 }
934
935 *clk_div = ser_clk / desired_clk;
936 return ser_clk;
937}
938
939static void qcom_geni_serial_set_termios(struct uart_port *uport,
940 struct ktermios *termios, struct ktermios *old)
941{
942 unsigned int baud;
943 u32 bits_per_char;
944 u32 tx_trans_cfg;
945 u32 tx_parity_cfg;
946 u32 rx_trans_cfg;
947 u32 rx_parity_cfg;
948 u32 stop_bit_len;
949 unsigned int clk_div;
950 u32 ser_clk_cfg;
951 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
952 unsigned long clk_rate;
953 u32 ver, sampling_rate;
954
955 qcom_geni_serial_stop_rx(uport);
956 /* baud rate */
957 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
958 port->baud = baud;
959
960 sampling_rate = UART_OVERSAMPLING;
961 /* Sampling rate is halved for IP versions >= 2.5 */
962 ver = geni_se_get_qup_hw_version(&port->se);
963 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
964 sampling_rate /= 2;
965
966 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
967 if (!clk_rate)
968 goto out_restart_rx;
969
970 uport->uartclk = clk_rate;
971 clk_set_rate(port->se.clk, clk_rate);
972 ser_clk_cfg = SER_CLK_EN;
973 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
974
975 /* parity */
976 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
977 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
978 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
979 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
980 if (termios->c_cflag & PARENB) {
981 tx_trans_cfg |= UART_TX_PAR_EN;
982 rx_trans_cfg |= UART_RX_PAR_EN;
983 tx_parity_cfg |= PAR_CALC_EN;
984 rx_parity_cfg |= PAR_CALC_EN;
985 if (termios->c_cflag & PARODD) {
986 tx_parity_cfg |= PAR_ODD;
987 rx_parity_cfg |= PAR_ODD;
988 } else if (termios->c_cflag & CMSPAR) {
989 tx_parity_cfg |= PAR_SPACE;
990 rx_parity_cfg |= PAR_SPACE;
991 } else {
992 tx_parity_cfg |= PAR_EVEN;
993 rx_parity_cfg |= PAR_EVEN;
994 }
995 } else {
996 tx_trans_cfg &= ~UART_TX_PAR_EN;
997 rx_trans_cfg &= ~UART_RX_PAR_EN;
998 tx_parity_cfg &= ~PAR_CALC_EN;
999 rx_parity_cfg &= ~PAR_CALC_EN;
1000 }
1001
1002 /* bits per char */
1003 switch (termios->c_cflag & CSIZE) {
1004 case CS5:
1005 bits_per_char = 5;
1006 break;
1007 case CS6:
1008 bits_per_char = 6;
1009 break;
1010 case CS7:
1011 bits_per_char = 7;
1012 break;
1013 case CS8:
1014 default:
1015 bits_per_char = 8;
1016 break;
1017 }
1018
1019 /* stop bits */
1020 if (termios->c_cflag & CSTOPB)
1021 stop_bit_len = TX_STOP_BIT_LEN_2;
1022 else
1023 stop_bit_len = TX_STOP_BIT_LEN_1;
1024
1025 /* flow control, clear the CTS_MASK bit if using flow control. */
1026 if (termios->c_cflag & CRTSCTS)
1027 tx_trans_cfg &= ~UART_CTS_MASK;
1028 else
1029 tx_trans_cfg |= UART_CTS_MASK;
1030
1031 if (baud)
1032 uart_update_timeout(uport, termios->c_cflag, baud);
1033
1034 if (!uart_console(uport))
1035 writel(port->loopback,
1036 uport->membase + SE_UART_LOOPBACK_CFG);
1037 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1038 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1039 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1040 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1041 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1042 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1043 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1044 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1045 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1046out_restart_rx:
1047 qcom_geni_serial_start_rx(uport);
1048}
1049
1050static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1051{
1052 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1053}
1054
1055#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1056static int __init qcom_geni_console_setup(struct console *co, char *options)
1057{
1058 struct uart_port *uport;
1059 struct qcom_geni_serial_port *port;
1060 int baud = 9600;
1061 int bits = 8;
1062 int parity = 'n';
1063 int flow = 'n';
1064 int ret;
1065
1066 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1067 return -ENXIO;
1068
1069 port = get_port_from_line(co->index, true);
1070 if (IS_ERR(port)) {
1071 pr_err("Invalid line %d\n", co->index);
1072 return PTR_ERR(port);
1073 }
1074
1075 uport = &port->uport;
1076
1077 if (unlikely(!uport->membase))
1078 return -ENXIO;
1079
1080 if (!port->setup) {
1081 ret = qcom_geni_serial_port_setup(uport);
1082 if (ret)
1083 return ret;
1084 }
1085
1086 if (options)
1087 uart_parse_options(options, &baud, &parity, &bits, &flow);
1088
1089 return uart_set_options(uport, co, baud, parity, bits, flow);
1090}
1091
1092static void qcom_geni_serial_earlycon_write(struct console *con,
1093 const char *s, unsigned int n)
1094{
1095 struct earlycon_device *dev = con->data;
1096
1097 __qcom_geni_serial_console_write(&dev->port, s, n);
1098}
1099
1100static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1101 const char *opt)
1102{
1103 struct uart_port *uport = &dev->port;
1104 u32 tx_trans_cfg;
1105 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1106 u32 rx_trans_cfg = 0;
1107 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1108 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1109 u32 bits_per_char;
1110 struct geni_se se;
1111
1112 if (!uport->membase)
1113 return -EINVAL;
1114
1115 memset(&se, 0, sizeof(se));
1116 se.base = uport->membase;
1117 if (geni_se_read_proto(&se) != GENI_SE_UART)
1118 return -ENXIO;
1119 /*
1120 * Ignore Flow control.
1121 * n = 8.
1122 */
1123 tx_trans_cfg = UART_CTS_MASK;
1124 bits_per_char = BITS_PER_BYTE;
1125
1126 /*
1127 * Make an unconditional cancel on the main sequencer to reset
1128 * it else we could end up in data loss scenarios.
1129 */
1130 qcom_geni_serial_poll_tx_done(uport);
1131 qcom_geni_serial_abort_rx(uport);
1132 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1133 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1134 geni_se_select_mode(&se, GENI_SE_FIFO);
1135
1136 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1137 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1138 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1139 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1140 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1141 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1142 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1143
1144 dev->con->write = qcom_geni_serial_earlycon_write;
1145 dev->con->setup = NULL;
1146 return 0;
1147}
1148OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1149 qcom_geni_serial_earlycon_setup);
1150
1151static int __init console_register(struct uart_driver *drv)
1152{
1153 return uart_register_driver(drv);
1154}
1155
1156static void console_unregister(struct uart_driver *drv)
1157{
1158 uart_unregister_driver(drv);
1159}
1160
1161static struct console cons_ops = {
1162 .name = "ttyMSM",
1163 .write = qcom_geni_serial_console_write,
1164 .device = uart_console_device,
1165 .setup = qcom_geni_console_setup,
1166 .flags = CON_PRINTBUFFER,
1167 .index = -1,
1168 .data = &qcom_geni_console_driver,
1169};
1170
1171static struct uart_driver qcom_geni_console_driver = {
1172 .owner = THIS_MODULE,
1173 .driver_name = "qcom_geni_console",
1174 .dev_name = "ttyMSM",
1175 .nr = GENI_UART_CONS_PORTS,
1176 .cons = &cons_ops,
1177};
1178#else
1179static int console_register(struct uart_driver *drv)
1180{
1181 return 0;
1182}
1183
1184static void console_unregister(struct uart_driver *drv)
1185{
1186}
1187#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1188
1189static struct uart_driver qcom_geni_uart_driver = {
1190 .owner = THIS_MODULE,
1191 .driver_name = "qcom_geni_uart",
1192 .dev_name = "ttyHS",
1193 .nr = GENI_UART_PORTS,
1194};
1195
1196static void qcom_geni_serial_pm(struct uart_port *uport,
1197 unsigned int new_state, unsigned int old_state)
1198{
1199 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1200
1201 /* If we've never been called, treat it as off */
1202 if (old_state == UART_PM_STATE_UNDEFINED)
1203 old_state = UART_PM_STATE_OFF;
1204
1205 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1206 geni_se_resources_on(&port->se);
1207 else if (new_state == UART_PM_STATE_OFF &&
1208 old_state == UART_PM_STATE_ON)
1209 geni_se_resources_off(&port->se);
1210}
1211
1212static const struct uart_ops qcom_geni_console_pops = {
1213 .tx_empty = qcom_geni_serial_tx_empty,
1214 .stop_tx = qcom_geni_serial_stop_tx,
1215 .start_tx = qcom_geni_serial_start_tx,
1216 .stop_rx = qcom_geni_serial_stop_rx,
1217 .set_termios = qcom_geni_serial_set_termios,
1218 .startup = qcom_geni_serial_startup,
1219 .request_port = qcom_geni_serial_request_port,
1220 .config_port = qcom_geni_serial_config_port,
1221 .shutdown = qcom_geni_serial_shutdown,
1222 .type = qcom_geni_serial_get_type,
1223 .set_mctrl = qcom_geni_serial_set_mctrl,
1224 .get_mctrl = qcom_geni_serial_get_mctrl,
1225#ifdef CONFIG_CONSOLE_POLL
1226 .poll_get_char = qcom_geni_serial_get_char,
1227 .poll_put_char = qcom_geni_serial_poll_put_char,
1228#endif
1229 .pm = qcom_geni_serial_pm,
1230};
1231
1232static const struct uart_ops qcom_geni_uart_pops = {
1233 .tx_empty = qcom_geni_serial_tx_empty,
1234 .stop_tx = qcom_geni_serial_stop_tx,
1235 .start_tx = qcom_geni_serial_start_tx,
1236 .stop_rx = qcom_geni_serial_stop_rx,
1237 .set_termios = qcom_geni_serial_set_termios,
1238 .startup = qcom_geni_serial_startup,
1239 .request_port = qcom_geni_serial_request_port,
1240 .config_port = qcom_geni_serial_config_port,
1241 .shutdown = qcom_geni_serial_shutdown,
1242 .type = qcom_geni_serial_get_type,
1243 .set_mctrl = qcom_geni_serial_set_mctrl,
1244 .get_mctrl = qcom_geni_serial_get_mctrl,
1245 .pm = qcom_geni_serial_pm,
1246};
1247
1248static int qcom_geni_serial_probe(struct platform_device *pdev)
1249{
1250 int ret = 0;
1251 int line = -1;
1252 struct qcom_geni_serial_port *port;
1253 struct uart_port *uport;
1254 struct resource *res;
1255 int irq;
1256 bool console = false;
1257 struct uart_driver *drv;
1258
1259 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1260 console = true;
1261
1262 if (console) {
1263 drv = &qcom_geni_console_driver;
1264 line = of_alias_get_id(pdev->dev.of_node, "serial");
1265 } else {
1266 drv = &qcom_geni_uart_driver;
1267 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1268 }
1269
1270 port = get_port_from_line(line, console);
1271 if (IS_ERR(port)) {
1272 dev_err(&pdev->dev, "Invalid line %d\n", line);
1273 return PTR_ERR(port);
1274 }
1275
1276 uport = &port->uport;
1277 /* Don't allow 2 drivers to access the same port */
1278 if (uport->private_data)
1279 return -ENODEV;
1280
1281 uport->dev = &pdev->dev;
1282 port->se.dev = &pdev->dev;
1283 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1284 port->se.clk = devm_clk_get(&pdev->dev, "se");
1285 if (IS_ERR(port->se.clk)) {
1286 ret = PTR_ERR(port->se.clk);
1287 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1288 return ret;
1289 }
1290
1291 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1292 if (!res)
1293 return -EINVAL;
1294 uport->mapbase = res->start;
1295
1296 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1297 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1298 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1299
1300 irq = platform_get_irq(pdev, 0);
1301 if (irq < 0)
1302 return irq;
1303 uport->irq = irq;
1304
1305 uport->private_data = drv;
1306 platform_set_drvdata(pdev, port);
1307 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1308 if (!console)
1309 device_create_file(uport->dev, &dev_attr_loopback);
1310 return uart_add_one_port(drv, uport);
1311}
1312
1313static int qcom_geni_serial_remove(struct platform_device *pdev)
1314{
1315 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1316 struct uart_driver *drv = port->uport.private_data;
1317
1318 uart_remove_one_port(drv, &port->uport);
1319 return 0;
1320}
1321
1322static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1323{
1324 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1325 struct uart_port *uport = &port->uport;
1326
1327 return uart_suspend_port(uport->private_data, uport);
1328}
1329
1330static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1331{
1332 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1333 struct uart_port *uport = &port->uport;
1334
1335 return uart_resume_port(uport->private_data, uport);
1336}
1337
1338static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1339 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1340 qcom_geni_serial_sys_resume)
1341};
1342
1343static const struct of_device_id qcom_geni_serial_match_table[] = {
1344 { .compatible = "qcom,geni-debug-uart", },
1345 { .compatible = "qcom,geni-uart", },
1346 {}
1347};
1348MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1349
1350static struct platform_driver qcom_geni_serial_platform_driver = {
1351 .remove = qcom_geni_serial_remove,
1352 .probe = qcom_geni_serial_probe,
1353 .driver = {
1354 .name = "qcom_geni_serial",
1355 .of_match_table = qcom_geni_serial_match_table,
1356 .pm = &qcom_geni_serial_pm_ops,
1357 },
1358};
1359
1360static int __init qcom_geni_serial_init(void)
1361{
1362 int ret;
1363
1364 ret = console_register(&qcom_geni_console_driver);
1365 if (ret)
1366 return ret;
1367
1368 ret = uart_register_driver(&qcom_geni_uart_driver);
1369 if (ret) {
1370 console_unregister(&qcom_geni_console_driver);
1371 return ret;
1372 }
1373
1374 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1375 if (ret) {
1376 console_unregister(&qcom_geni_console_driver);
1377 uart_unregister_driver(&qcom_geni_uart_driver);
1378 }
1379 return ret;
1380}
1381module_init(qcom_geni_serial_init);
1382
1383static void __exit qcom_geni_serial_exit(void)
1384{
1385 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1386 console_unregister(&qcom_geni_console_driver);
1387 uart_unregister_driver(&qcom_geni_uart_driver);
1388}
1389module_exit(qcom_geni_serial_exit);
1390
1391MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1392MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#include <linux/clk.h>
5#include <linux/console.h>
6#include <linux/io.h>
7#include <linux/iopoll.h>
8#include <linux/irq.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_device.h>
12#include <linux/pm_opp.h>
13#include <linux/platform_device.h>
14#include <linux/pm_runtime.h>
15#include <linux/pm_wakeirq.h>
16#include <linux/qcom-geni-se.h>
17#include <linux/serial.h>
18#include <linux/serial_core.h>
19#include <linux/slab.h>
20#include <linux/tty.h>
21#include <linux/tty_flip.h>
22
23/* UART specific GENI registers */
24#define SE_UART_LOOPBACK_CFG 0x22c
25#define SE_UART_IO_MACRO_CTRL 0x240
26#define SE_UART_TX_TRANS_CFG 0x25c
27#define SE_UART_TX_WORD_LEN 0x268
28#define SE_UART_TX_STOP_BIT_LEN 0x26c
29#define SE_UART_TX_TRANS_LEN 0x270
30#define SE_UART_RX_TRANS_CFG 0x280
31#define SE_UART_RX_WORD_LEN 0x28c
32#define SE_UART_RX_STALE_CNT 0x294
33#define SE_UART_TX_PARITY_CFG 0x2a4
34#define SE_UART_RX_PARITY_CFG 0x2a8
35#define SE_UART_MANUAL_RFR 0x2ac
36
37/* SE_UART_TRANS_CFG */
38#define UART_TX_PAR_EN BIT(0)
39#define UART_CTS_MASK BIT(1)
40
41/* SE_UART_TX_WORD_LEN */
42#define TX_WORD_LEN_MSK GENMASK(9, 0)
43
44/* SE_UART_TX_STOP_BIT_LEN */
45#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
46#define TX_STOP_BIT_LEN_1 0
47#define TX_STOP_BIT_LEN_1_5 1
48#define TX_STOP_BIT_LEN_2 2
49
50/* SE_UART_TX_TRANS_LEN */
51#define TX_TRANS_LEN_MSK GENMASK(23, 0)
52
53/* SE_UART_RX_TRANS_CFG */
54#define UART_RX_INS_STATUS_BIT BIT(2)
55#define UART_RX_PAR_EN BIT(3)
56
57/* SE_UART_RX_WORD_LEN */
58#define RX_WORD_LEN_MASK GENMASK(9, 0)
59
60/* SE_UART_RX_STALE_CNT */
61#define RX_STALE_CNT GENMASK(23, 0)
62
63/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
64#define PAR_CALC_EN BIT(0)
65#define PAR_MODE_MSK GENMASK(2, 1)
66#define PAR_MODE_SHFT 1
67#define PAR_EVEN 0x00
68#define PAR_ODD 0x01
69#define PAR_SPACE 0x10
70#define PAR_MARK 0x11
71
72/* SE_UART_MANUAL_RFR register fields */
73#define UART_MANUAL_RFR_EN BIT(31)
74#define UART_RFR_NOT_READY BIT(1)
75#define UART_RFR_READY BIT(0)
76
77/* UART M_CMD OP codes */
78#define UART_START_TX 0x1
79#define UART_START_BREAK 0x4
80#define UART_STOP_BREAK 0x5
81/* UART S_CMD OP codes */
82#define UART_START_READ 0x1
83#define UART_PARAM 0x1
84
85#define UART_OVERSAMPLING 32
86#define STALE_TIMEOUT 16
87#define DEFAULT_BITS_PER_CHAR 10
88#define GENI_UART_CONS_PORTS 1
89#define GENI_UART_PORTS 3
90#define DEF_FIFO_DEPTH_WORDS 16
91#define DEF_TX_WM 2
92#define DEF_FIFO_WIDTH_BITS 32
93#define UART_RX_WM 2
94
95/* SE_UART_LOOPBACK_CFG */
96#define RX_TX_SORTED BIT(0)
97#define CTS_RTS_SORTED BIT(1)
98#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
99
100/* UART pin swap value */
101#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
102#define IO_MACRO_IO0_SEL 0x3
103#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
104#define IO_MACRO_IO2_IO3_SWAP 0x4640
105
106/* We always configure 4 bytes per FIFO word */
107#define BYTES_PER_FIFO_WORD 4
108
109struct qcom_geni_private_data {
110 /* NOTE: earlycon port will have NULL here */
111 struct uart_driver *drv;
112
113 u32 poll_cached_bytes;
114 unsigned int poll_cached_bytes_cnt;
115
116 u32 write_cached_bytes;
117 unsigned int write_cached_bytes_cnt;
118};
119
120struct qcom_geni_serial_port {
121 struct uart_port uport;
122 struct geni_se se;
123 const char *name;
124 u32 tx_fifo_depth;
125 u32 tx_fifo_width;
126 u32 rx_fifo_depth;
127 bool setup;
128 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
129 unsigned int baud;
130 void *rx_fifo;
131 u32 loopback;
132 bool brk;
133
134 unsigned int tx_remaining;
135 int wakeup_irq;
136 bool rx_tx_swap;
137 bool cts_rts_swap;
138
139 struct qcom_geni_private_data private_data;
140};
141
142static const struct uart_ops qcom_geni_console_pops;
143static const struct uart_ops qcom_geni_uart_pops;
144static struct uart_driver qcom_geni_console_driver;
145static struct uart_driver qcom_geni_uart_driver;
146static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
147static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
148static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
149static void qcom_geni_serial_stop_rx(struct uart_port *uport);
150static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
151
152static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
153 32000000, 48000000, 51200000, 64000000,
154 80000000, 96000000, 100000000,
155 102400000, 112000000, 120000000,
156 128000000};
157
158#define to_dev_port(ptr, member) \
159 container_of(ptr, struct qcom_geni_serial_port, member)
160
161static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
162 [0] = {
163 .uport = {
164 .iotype = UPIO_MEM,
165 .ops = &qcom_geni_uart_pops,
166 .flags = UPF_BOOT_AUTOCONF,
167 .line = 0,
168 },
169 },
170 [1] = {
171 .uport = {
172 .iotype = UPIO_MEM,
173 .ops = &qcom_geni_uart_pops,
174 .flags = UPF_BOOT_AUTOCONF,
175 .line = 1,
176 },
177 },
178 [2] = {
179 .uport = {
180 .iotype = UPIO_MEM,
181 .ops = &qcom_geni_uart_pops,
182 .flags = UPF_BOOT_AUTOCONF,
183 .line = 2,
184 },
185 },
186};
187
188static struct qcom_geni_serial_port qcom_geni_console_port = {
189 .uport = {
190 .iotype = UPIO_MEM,
191 .ops = &qcom_geni_console_pops,
192 .flags = UPF_BOOT_AUTOCONF,
193 .line = 0,
194 },
195};
196
197static int qcom_geni_serial_request_port(struct uart_port *uport)
198{
199 struct platform_device *pdev = to_platform_device(uport->dev);
200 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
201
202 uport->membase = devm_platform_ioremap_resource(pdev, 0);
203 if (IS_ERR(uport->membase))
204 return PTR_ERR(uport->membase);
205 port->se.base = uport->membase;
206 return 0;
207}
208
209static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
210{
211 if (cfg_flags & UART_CONFIG_TYPE) {
212 uport->type = PORT_MSM;
213 qcom_geni_serial_request_port(uport);
214 }
215}
216
217static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
218{
219 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
220 u32 geni_ios;
221
222 if (uart_console(uport)) {
223 mctrl |= TIOCM_CTS;
224 } else {
225 geni_ios = readl(uport->membase + SE_GENI_IOS);
226 if (!(geni_ios & IO2_DATA_IN))
227 mctrl |= TIOCM_CTS;
228 }
229
230 return mctrl;
231}
232
233static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
234 unsigned int mctrl)
235{
236 u32 uart_manual_rfr = 0;
237 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
238
239 if (uart_console(uport))
240 return;
241
242 if (mctrl & TIOCM_LOOP)
243 port->loopback = RX_TX_CTS_RTS_SORTED;
244
245 if (!(mctrl & TIOCM_RTS))
246 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
247 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
248}
249
250static const char *qcom_geni_serial_get_type(struct uart_port *uport)
251{
252 return "MSM";
253}
254
255static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
256{
257 struct qcom_geni_serial_port *port;
258 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
259
260 if (line < 0 || line >= nr_ports)
261 return ERR_PTR(-ENXIO);
262
263 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
264 return port;
265}
266
267static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
268 int offset, int field, bool set)
269{
270 u32 reg;
271 struct qcom_geni_serial_port *port;
272 unsigned int baud;
273 unsigned int fifo_bits;
274 unsigned long timeout_us = 20000;
275 struct qcom_geni_private_data *private_data = uport->private_data;
276
277 if (private_data->drv) {
278 port = to_dev_port(uport, uport);
279 baud = port->baud;
280 if (!baud)
281 baud = 115200;
282 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
283 /*
284 * Total polling iterations based on FIFO worth of bytes to be
285 * sent at current baud. Add a little fluff to the wait.
286 */
287 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
288 }
289
290 /*
291 * Use custom implementation instead of readl_poll_atomic since ktimer
292 * is not ready at the time of early console.
293 */
294 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
295 while (timeout_us) {
296 reg = readl(uport->membase + offset);
297 if ((bool)(reg & field) == set)
298 return true;
299 udelay(10);
300 timeout_us -= 10;
301 }
302 return false;
303}
304
305static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
306{
307 u32 m_cmd;
308
309 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
310 m_cmd = UART_START_TX << M_OPCODE_SHFT;
311 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
312}
313
314static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
315{
316 int done;
317 u32 irq_clear = M_CMD_DONE_EN;
318
319 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
320 M_CMD_DONE_EN, true);
321 if (!done) {
322 writel(M_GENI_CMD_ABORT, uport->membase +
323 SE_GENI_M_CMD_CTRL_REG);
324 irq_clear |= M_CMD_ABORT_EN;
325 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
326 M_CMD_ABORT_EN, true);
327 }
328 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
329}
330
331static void qcom_geni_serial_abort_rx(struct uart_port *uport)
332{
333 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
334
335 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
336 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
337 S_GENI_CMD_ABORT, false);
338 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
339 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
340}
341
342#ifdef CONFIG_CONSOLE_POLL
343
344static int qcom_geni_serial_get_char(struct uart_port *uport)
345{
346 struct qcom_geni_private_data *private_data = uport->private_data;
347 u32 status;
348 u32 word_cnt;
349 int ret;
350
351 if (!private_data->poll_cached_bytes_cnt) {
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
354
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
357
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
359 word_cnt = status & RX_FIFO_WC_MSK;
360 if (!word_cnt)
361 return NO_POLL_CHAR;
362
363 if (word_cnt == 1 && (status & RX_LAST))
364 /*
365 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
366 * treated as if it was BYTES_PER_FIFO_WORD.
367 */
368 private_data->poll_cached_bytes_cnt =
369 (status & RX_LAST_BYTE_VALID_MSK) >>
370 RX_LAST_BYTE_VALID_SHFT;
371
372 if (private_data->poll_cached_bytes_cnt == 0)
373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
374
375 private_data->poll_cached_bytes =
376 readl(uport->membase + SE_GENI_RX_FIFOn);
377 }
378
379 private_data->poll_cached_bytes_cnt--;
380 ret = private_data->poll_cached_bytes & 0xff;
381 private_data->poll_cached_bytes >>= 8;
382
383 return ret;
384}
385
386static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
387 unsigned char c)
388{
389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
390 qcom_geni_serial_setup_tx(uport, 1);
391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
392 M_TX_FIFO_WATERMARK_EN, true));
393 writel(c, uport->membase + SE_GENI_TX_FIFOn);
394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
395 qcom_geni_serial_poll_tx_done(uport);
396}
397#endif
398
399#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
400static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
401{
402 struct qcom_geni_private_data *private_data = uport->private_data;
403
404 private_data->write_cached_bytes =
405 (private_data->write_cached_bytes >> 8) | (ch << 24);
406 private_data->write_cached_bytes_cnt++;
407
408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
409 writel(private_data->write_cached_bytes,
410 uport->membase + SE_GENI_TX_FIFOn);
411 private_data->write_cached_bytes_cnt = 0;
412 }
413}
414
415static void
416__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
417 unsigned int count)
418{
419 struct qcom_geni_private_data *private_data = uport->private_data;
420
421 int i;
422 u32 bytes_to_send = count;
423
424 for (i = 0; i < count; i++) {
425 /*
426 * uart_console_write() adds a carriage return for each newline.
427 * Account for additional bytes to be written.
428 */
429 if (s[i] == '\n')
430 bytes_to_send++;
431 }
432
433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
434 qcom_geni_serial_setup_tx(uport, bytes_to_send);
435 for (i = 0; i < count; ) {
436 size_t chars_to_write = 0;
437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
438
439 /*
440 * If the WM bit never set, then the Tx state machine is not
441 * in a valid state, so break, cancel/abort any existing
442 * command. Unfortunately the current data being written is
443 * lost.
444 */
445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
446 M_TX_FIFO_WATERMARK_EN, true))
447 break;
448 chars_to_write = min_t(size_t, count - i, avail / 2);
449 uart_console_write(uport, s + i, chars_to_write,
450 qcom_geni_serial_wr_char);
451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
452 SE_GENI_M_IRQ_CLEAR);
453 i += chars_to_write;
454 }
455
456 if (private_data->write_cached_bytes_cnt) {
457 private_data->write_cached_bytes >>= BITS_PER_BYTE *
458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
459 writel(private_data->write_cached_bytes,
460 uport->membase + SE_GENI_TX_FIFOn);
461 private_data->write_cached_bytes_cnt = 0;
462 }
463
464 qcom_geni_serial_poll_tx_done(uport);
465}
466
467static void qcom_geni_serial_console_write(struct console *co, const char *s,
468 unsigned int count)
469{
470 struct uart_port *uport;
471 struct qcom_geni_serial_port *port;
472 bool locked = true;
473 unsigned long flags;
474 u32 geni_status;
475 u32 irq_en;
476
477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
478
479 port = get_port_from_line(co->index, true);
480 if (IS_ERR(port))
481 return;
482
483 uport = &port->uport;
484 if (oops_in_progress)
485 locked = spin_trylock_irqsave(&uport->lock, flags);
486 else
487 spin_lock_irqsave(&uport->lock, flags);
488
489 geni_status = readl(uport->membase + SE_GENI_STATUS);
490
491 /* Cancel the current write to log the fault */
492 if (!locked) {
493 geni_se_cancel_m_cmd(&port->se);
494 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
495 M_CMD_CANCEL_EN, true)) {
496 geni_se_abort_m_cmd(&port->se);
497 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
498 M_CMD_ABORT_EN, true);
499 writel(M_CMD_ABORT_EN, uport->membase +
500 SE_GENI_M_IRQ_CLEAR);
501 }
502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
503 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
504 /*
505 * It seems we can't interrupt existing transfers if all data
506 * has been sent, in which case we need to look for done first.
507 */
508 qcom_geni_serial_poll_tx_done(uport);
509
510 if (uart_circ_chars_pending(&uport->state->xmit)) {
511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
512 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
513 uport->membase + SE_GENI_M_IRQ_EN);
514 }
515 }
516
517 __qcom_geni_serial_console_write(uport, s, count);
518
519 if (port->tx_remaining)
520 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
521
522 if (locked)
523 spin_unlock_irqrestore(&uport->lock, flags);
524}
525
526static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
527{
528 u32 i;
529 unsigned char buf[sizeof(u32)];
530 struct tty_port *tport;
531 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
532
533 tport = &uport->state->port;
534 for (i = 0; i < bytes; ) {
535 int c;
536 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
537
538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
539 i += chunk;
540 if (drop)
541 continue;
542
543 for (c = 0; c < chunk; c++) {
544 int sysrq;
545
546 uport->icount.rx++;
547 if (port->brk && buf[c] == 0) {
548 port->brk = false;
549 if (uart_handle_break(uport))
550 continue;
551 }
552
553 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
554
555 if (!sysrq)
556 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
557 }
558 }
559 if (!drop)
560 tty_flip_buffer_push(tport);
561 return 0;
562}
563#else
564static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
565{
566 return -EPERM;
567}
568
569#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
570
571static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
572{
573 struct tty_port *tport;
574 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
575 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
576 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
577 int ret;
578
579 tport = &uport->state->port;
580 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
581 if (drop)
582 return 0;
583
584 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
585 if (ret != bytes) {
586 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
587 __func__, ret, bytes);
588 WARN_ON_ONCE(1);
589 }
590 uport->icount.rx += ret;
591 tty_flip_buffer_push(tport);
592 return ret;
593}
594
595static void qcom_geni_serial_start_tx(struct uart_port *uport)
596{
597 u32 irq_en;
598 u32 status;
599
600 status = readl(uport->membase + SE_GENI_STATUS);
601 if (status & M_GENI_CMD_ACTIVE)
602 return;
603
604 if (!qcom_geni_serial_tx_empty(uport))
605 return;
606
607 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
608 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
609
610 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
611 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
612}
613
614static void qcom_geni_serial_stop_tx(struct uart_port *uport)
615{
616 u32 irq_en;
617 u32 status;
618 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
619
620 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
621 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
622 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
623 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
624 status = readl(uport->membase + SE_GENI_STATUS);
625 /* Possible stop tx is called multiple times. */
626 if (!(status & M_GENI_CMD_ACTIVE))
627 return;
628
629 geni_se_cancel_m_cmd(&port->se);
630 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
631 M_CMD_CANCEL_EN, true)) {
632 geni_se_abort_m_cmd(&port->se);
633 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
634 M_CMD_ABORT_EN, true);
635 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
636 }
637 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
638}
639
640static void qcom_geni_serial_start_rx(struct uart_port *uport)
641{
642 u32 irq_en;
643 u32 status;
644 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
645
646 status = readl(uport->membase + SE_GENI_STATUS);
647 if (status & S_GENI_CMD_ACTIVE)
648 qcom_geni_serial_stop_rx(uport);
649
650 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
651
652 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
653 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
654 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
655
656 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
657 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
658 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
659}
660
661static void qcom_geni_serial_stop_rx(struct uart_port *uport)
662{
663 u32 irq_en;
664 u32 status;
665 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
666 u32 s_irq_status;
667
668 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
669 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
670 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
671
672 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
673 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
674 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
675
676 status = readl(uport->membase + SE_GENI_STATUS);
677 /* Possible stop rx is called multiple times. */
678 if (!(status & S_GENI_CMD_ACTIVE))
679 return;
680
681 geni_se_cancel_s_cmd(&port->se);
682 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
683 S_CMD_CANCEL_EN, true);
684 /*
685 * If timeout occurs secondary engine remains active
686 * and Abort sequence is executed.
687 */
688 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
689 /* Flush the Rx buffer */
690 if (s_irq_status & S_RX_FIFO_LAST_EN)
691 qcom_geni_serial_handle_rx(uport, true);
692 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
693
694 status = readl(uport->membase + SE_GENI_STATUS);
695 if (status & S_GENI_CMD_ACTIVE)
696 qcom_geni_serial_abort_rx(uport);
697}
698
699static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
700{
701 u32 status;
702 u32 word_cnt;
703 u32 last_word_byte_cnt;
704 u32 last_word_partial;
705 u32 total_bytes;
706 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
707
708 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
709 word_cnt = status & RX_FIFO_WC_MSK;
710 last_word_partial = status & RX_LAST;
711 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
712 RX_LAST_BYTE_VALID_SHFT;
713
714 if (!word_cnt)
715 return;
716 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
717 if (last_word_partial && last_word_byte_cnt)
718 total_bytes += last_word_byte_cnt;
719 else
720 total_bytes += BYTES_PER_FIFO_WORD;
721 port->handle_rx(uport, total_bytes, drop);
722}
723
724static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
725 bool active)
726{
727 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
728 struct circ_buf *xmit = &uport->state->xmit;
729 size_t avail;
730 size_t remaining;
731 size_t pending;
732 int i;
733 u32 status;
734 u32 irq_en;
735 unsigned int chunk;
736 int tail;
737
738 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
739
740 /* Complete the current tx command before taking newly added data */
741 if (active)
742 pending = port->tx_remaining;
743 else
744 pending = uart_circ_chars_pending(xmit);
745
746 /* All data has been transmitted and acknowledged as received */
747 if (!pending && !status && done) {
748 qcom_geni_serial_stop_tx(uport);
749 goto out_write_wakeup;
750 }
751
752 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
753 avail *= BYTES_PER_FIFO_WORD;
754
755 tail = xmit->tail;
756 chunk = min(avail, pending);
757 if (!chunk)
758 goto out_write_wakeup;
759
760 if (!port->tx_remaining) {
761 qcom_geni_serial_setup_tx(uport, pending);
762 port->tx_remaining = pending;
763
764 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
765 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
766 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
767 uport->membase + SE_GENI_M_IRQ_EN);
768 }
769
770 remaining = chunk;
771 for (i = 0; i < chunk; ) {
772 unsigned int tx_bytes;
773 u8 buf[sizeof(u32)];
774 int c;
775
776 memset(buf, 0, sizeof(buf));
777 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
778
779 for (c = 0; c < tx_bytes ; c++) {
780 buf[c] = xmit->buf[tail++];
781 tail &= UART_XMIT_SIZE - 1;
782 }
783
784 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
785
786 i += tx_bytes;
787 uport->icount.tx += tx_bytes;
788 remaining -= tx_bytes;
789 port->tx_remaining -= tx_bytes;
790 }
791
792 xmit->tail = tail;
793
794 /*
795 * The tx fifo watermark is level triggered and latched. Though we had
796 * cleared it in qcom_geni_serial_isr it will have already reasserted
797 * so we must clear it again here after our writes.
798 */
799 writel(M_TX_FIFO_WATERMARK_EN,
800 uport->membase + SE_GENI_M_IRQ_CLEAR);
801
802out_write_wakeup:
803 if (!port->tx_remaining) {
804 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
805 if (irq_en & M_TX_FIFO_WATERMARK_EN)
806 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
807 uport->membase + SE_GENI_M_IRQ_EN);
808 }
809
810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
811 uart_write_wakeup(uport);
812}
813
814static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
815{
816 u32 m_irq_en;
817 u32 m_irq_status;
818 u32 s_irq_status;
819 u32 geni_status;
820 struct uart_port *uport = dev;
821 unsigned long flags;
822 bool drop_rx = false;
823 struct tty_port *tport = &uport->state->port;
824 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
825
826 if (uport->suspended)
827 return IRQ_NONE;
828
829 spin_lock_irqsave(&uport->lock, flags);
830 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
831 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
832 geni_status = readl(uport->membase + SE_GENI_STATUS);
833 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
834 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
835 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
836
837 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
838 goto out_unlock;
839
840 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
841 uport->icount.overrun++;
842 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
843 }
844
845 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
846 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
847 geni_status & M_GENI_CMD_ACTIVE);
848
849 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
850 if (s_irq_status & S_GP_IRQ_0_EN)
851 uport->icount.parity++;
852 drop_rx = true;
853 } else if (s_irq_status & S_GP_IRQ_2_EN ||
854 s_irq_status & S_GP_IRQ_3_EN) {
855 uport->icount.brk++;
856 port->brk = true;
857 }
858
859 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
860 s_irq_status & S_RX_FIFO_LAST_EN)
861 qcom_geni_serial_handle_rx(uport, drop_rx);
862
863out_unlock:
864 uart_unlock_and_check_sysrq(uport, flags);
865
866 return IRQ_HANDLED;
867}
868
869static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
870{
871 struct uart_port *uport;
872
873 uport = &port->uport;
874 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
875 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
876 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
877 uport->fifosize =
878 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
879}
880
881
882static void qcom_geni_serial_shutdown(struct uart_port *uport)
883{
884 disable_irq(uport->irq);
885}
886
887static int qcom_geni_serial_port_setup(struct uart_port *uport)
888{
889 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
890 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
891 u32 proto;
892 u32 pin_swap;
893
894 proto = geni_se_read_proto(&port->se);
895 if (proto != GENI_SE_UART) {
896 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
897 return -ENXIO;
898 }
899
900 qcom_geni_serial_stop_rx(uport);
901
902 get_tx_fifo_size(port);
903
904 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
905
906 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
907 if (port->rx_tx_swap) {
908 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
909 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
910 }
911 if (port->cts_rts_swap) {
912 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
913 pin_swap |= IO_MACRO_IO0_SEL;
914 }
915 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
916 if (port->rx_tx_swap || port->cts_rts_swap)
917 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
918
919 /*
920 * Make an unconditional cancel on the main sequencer to reset
921 * it else we could end up in data loss scenarios.
922 */
923 if (uart_console(uport))
924 qcom_geni_serial_poll_tx_done(uport);
925 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
926 false, true, true);
927 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
928 geni_se_select_mode(&port->se, GENI_SE_FIFO);
929 port->setup = true;
930
931 return 0;
932}
933
934static int qcom_geni_serial_startup(struct uart_port *uport)
935{
936 int ret;
937 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
938
939 if (!port->setup) {
940 ret = qcom_geni_serial_port_setup(uport);
941 if (ret)
942 return ret;
943 }
944 enable_irq(uport->irq);
945
946 return 0;
947}
948
949static unsigned long get_clk_cfg(unsigned long clk_freq)
950{
951 int i;
952
953 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
954 if (!(root_freq[i] % clk_freq))
955 return root_freq[i];
956 }
957 return 0;
958}
959
960static unsigned long get_clk_div_rate(unsigned int baud,
961 unsigned int sampling_rate, unsigned int *clk_div)
962{
963 unsigned long ser_clk;
964 unsigned long desired_clk;
965
966 desired_clk = baud * sampling_rate;
967 ser_clk = get_clk_cfg(desired_clk);
968 if (!ser_clk) {
969 pr_err("%s: Can't find matching DFS entry for baud %d\n",
970 __func__, baud);
971 return ser_clk;
972 }
973
974 *clk_div = ser_clk / desired_clk;
975 return ser_clk;
976}
977
978static void qcom_geni_serial_set_termios(struct uart_port *uport,
979 struct ktermios *termios, struct ktermios *old)
980{
981 unsigned int baud;
982 u32 bits_per_char;
983 u32 tx_trans_cfg;
984 u32 tx_parity_cfg;
985 u32 rx_trans_cfg;
986 u32 rx_parity_cfg;
987 u32 stop_bit_len;
988 unsigned int clk_div;
989 u32 ser_clk_cfg;
990 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
991 unsigned long clk_rate;
992 u32 ver, sampling_rate;
993 unsigned int avg_bw_core;
994
995 qcom_geni_serial_stop_rx(uport);
996 /* baud rate */
997 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
998 port->baud = baud;
999
1000 sampling_rate = UART_OVERSAMPLING;
1001 /* Sampling rate is halved for IP versions >= 2.5 */
1002 ver = geni_se_get_qup_hw_version(&port->se);
1003 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
1004 sampling_rate /= 2;
1005
1006 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
1007 if (!clk_rate)
1008 goto out_restart_rx;
1009
1010 uport->uartclk = clk_rate;
1011 dev_pm_opp_set_rate(uport->dev, clk_rate);
1012 ser_clk_cfg = SER_CLK_EN;
1013 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1014
1015 /*
1016 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1017 * only.
1018 */
1019 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1020 : GENI_DEFAULT_BW;
1021 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1022 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1023 geni_icc_set_bw(&port->se);
1024
1025 /* parity */
1026 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1027 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1028 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1029 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1030 if (termios->c_cflag & PARENB) {
1031 tx_trans_cfg |= UART_TX_PAR_EN;
1032 rx_trans_cfg |= UART_RX_PAR_EN;
1033 tx_parity_cfg |= PAR_CALC_EN;
1034 rx_parity_cfg |= PAR_CALC_EN;
1035 if (termios->c_cflag & PARODD) {
1036 tx_parity_cfg |= PAR_ODD;
1037 rx_parity_cfg |= PAR_ODD;
1038 } else if (termios->c_cflag & CMSPAR) {
1039 tx_parity_cfg |= PAR_SPACE;
1040 rx_parity_cfg |= PAR_SPACE;
1041 } else {
1042 tx_parity_cfg |= PAR_EVEN;
1043 rx_parity_cfg |= PAR_EVEN;
1044 }
1045 } else {
1046 tx_trans_cfg &= ~UART_TX_PAR_EN;
1047 rx_trans_cfg &= ~UART_RX_PAR_EN;
1048 tx_parity_cfg &= ~PAR_CALC_EN;
1049 rx_parity_cfg &= ~PAR_CALC_EN;
1050 }
1051
1052 /* bits per char */
1053 switch (termios->c_cflag & CSIZE) {
1054 case CS5:
1055 bits_per_char = 5;
1056 break;
1057 case CS6:
1058 bits_per_char = 6;
1059 break;
1060 case CS7:
1061 bits_per_char = 7;
1062 break;
1063 case CS8:
1064 default:
1065 bits_per_char = 8;
1066 break;
1067 }
1068
1069 /* stop bits */
1070 if (termios->c_cflag & CSTOPB)
1071 stop_bit_len = TX_STOP_BIT_LEN_2;
1072 else
1073 stop_bit_len = TX_STOP_BIT_LEN_1;
1074
1075 /* flow control, clear the CTS_MASK bit if using flow control. */
1076 if (termios->c_cflag & CRTSCTS)
1077 tx_trans_cfg &= ~UART_CTS_MASK;
1078 else
1079 tx_trans_cfg |= UART_CTS_MASK;
1080
1081 if (baud)
1082 uart_update_timeout(uport, termios->c_cflag, baud);
1083
1084 if (!uart_console(uport))
1085 writel(port->loopback,
1086 uport->membase + SE_UART_LOOPBACK_CFG);
1087 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1088 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1089 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1090 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1091 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1092 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1093 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1094 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1095 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1096out_restart_rx:
1097 qcom_geni_serial_start_rx(uport);
1098}
1099
1100static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1101{
1102 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1103}
1104
1105#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1106static int qcom_geni_console_setup(struct console *co, char *options)
1107{
1108 struct uart_port *uport;
1109 struct qcom_geni_serial_port *port;
1110 int baud = 9600;
1111 int bits = 8;
1112 int parity = 'n';
1113 int flow = 'n';
1114 int ret;
1115
1116 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1117 return -ENXIO;
1118
1119 port = get_port_from_line(co->index, true);
1120 if (IS_ERR(port)) {
1121 pr_err("Invalid line %d\n", co->index);
1122 return PTR_ERR(port);
1123 }
1124
1125 uport = &port->uport;
1126
1127 if (unlikely(!uport->membase))
1128 return -ENXIO;
1129
1130 if (!port->setup) {
1131 ret = qcom_geni_serial_port_setup(uport);
1132 if (ret)
1133 return ret;
1134 }
1135
1136 if (options)
1137 uart_parse_options(options, &baud, &parity, &bits, &flow);
1138
1139 return uart_set_options(uport, co, baud, parity, bits, flow);
1140}
1141
1142static void qcom_geni_serial_earlycon_write(struct console *con,
1143 const char *s, unsigned int n)
1144{
1145 struct earlycon_device *dev = con->data;
1146
1147 __qcom_geni_serial_console_write(&dev->port, s, n);
1148}
1149
1150#ifdef CONFIG_CONSOLE_POLL
1151static int qcom_geni_serial_earlycon_read(struct console *con,
1152 char *s, unsigned int n)
1153{
1154 struct earlycon_device *dev = con->data;
1155 struct uart_port *uport = &dev->port;
1156 int num_read = 0;
1157 int ch;
1158
1159 while (num_read < n) {
1160 ch = qcom_geni_serial_get_char(uport);
1161 if (ch == NO_POLL_CHAR)
1162 break;
1163 s[num_read++] = ch;
1164 }
1165
1166 return num_read;
1167}
1168
1169static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1170 struct console *con)
1171{
1172 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1173 con->read = qcom_geni_serial_earlycon_read;
1174}
1175#else
1176static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1177 struct console *con) { }
1178#endif
1179
1180static int qcom_geni_serial_earlycon_exit(struct console *con)
1181{
1182 geni_remove_earlycon_icc_vote();
1183 return 0;
1184}
1185
1186static struct qcom_geni_private_data earlycon_private_data;
1187
1188static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1189 const char *opt)
1190{
1191 struct uart_port *uport = &dev->port;
1192 u32 tx_trans_cfg;
1193 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1194 u32 rx_trans_cfg = 0;
1195 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1196 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1197 u32 bits_per_char;
1198 struct geni_se se;
1199
1200 if (!uport->membase)
1201 return -EINVAL;
1202
1203 uport->private_data = &earlycon_private_data;
1204
1205 memset(&se, 0, sizeof(se));
1206 se.base = uport->membase;
1207 if (geni_se_read_proto(&se) != GENI_SE_UART)
1208 return -ENXIO;
1209 /*
1210 * Ignore Flow control.
1211 * n = 8.
1212 */
1213 tx_trans_cfg = UART_CTS_MASK;
1214 bits_per_char = BITS_PER_BYTE;
1215
1216 /*
1217 * Make an unconditional cancel on the main sequencer to reset
1218 * it else we could end up in data loss scenarios.
1219 */
1220 qcom_geni_serial_poll_tx_done(uport);
1221 qcom_geni_serial_abort_rx(uport);
1222 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1223 false, true, true);
1224 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1225 geni_se_select_mode(&se, GENI_SE_FIFO);
1226
1227 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1228 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1229 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1230 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1231 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1232 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1233 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1234
1235 dev->con->write = qcom_geni_serial_earlycon_write;
1236 dev->con->exit = qcom_geni_serial_earlycon_exit;
1237 dev->con->setup = NULL;
1238 qcom_geni_serial_enable_early_read(&se, dev->con);
1239
1240 return 0;
1241}
1242OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1243 qcom_geni_serial_earlycon_setup);
1244
1245static int __init console_register(struct uart_driver *drv)
1246{
1247 return uart_register_driver(drv);
1248}
1249
1250static void console_unregister(struct uart_driver *drv)
1251{
1252 uart_unregister_driver(drv);
1253}
1254
1255static struct console cons_ops = {
1256 .name = "ttyMSM",
1257 .write = qcom_geni_serial_console_write,
1258 .device = uart_console_device,
1259 .setup = qcom_geni_console_setup,
1260 .flags = CON_PRINTBUFFER,
1261 .index = -1,
1262 .data = &qcom_geni_console_driver,
1263};
1264
1265static struct uart_driver qcom_geni_console_driver = {
1266 .owner = THIS_MODULE,
1267 .driver_name = "qcom_geni_console",
1268 .dev_name = "ttyMSM",
1269 .nr = GENI_UART_CONS_PORTS,
1270 .cons = &cons_ops,
1271};
1272#else
1273static int console_register(struct uart_driver *drv)
1274{
1275 return 0;
1276}
1277
1278static void console_unregister(struct uart_driver *drv)
1279{
1280}
1281#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1282
1283static struct uart_driver qcom_geni_uart_driver = {
1284 .owner = THIS_MODULE,
1285 .driver_name = "qcom_geni_uart",
1286 .dev_name = "ttyHS",
1287 .nr = GENI_UART_PORTS,
1288};
1289
1290static void qcom_geni_serial_pm(struct uart_port *uport,
1291 unsigned int new_state, unsigned int old_state)
1292{
1293 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1294
1295 /* If we've never been called, treat it as off */
1296 if (old_state == UART_PM_STATE_UNDEFINED)
1297 old_state = UART_PM_STATE_OFF;
1298
1299 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1300 geni_icc_enable(&port->se);
1301 geni_se_resources_on(&port->se);
1302 } else if (new_state == UART_PM_STATE_OFF &&
1303 old_state == UART_PM_STATE_ON) {
1304 geni_se_resources_off(&port->se);
1305 geni_icc_disable(&port->se);
1306 }
1307}
1308
1309static const struct uart_ops qcom_geni_console_pops = {
1310 .tx_empty = qcom_geni_serial_tx_empty,
1311 .stop_tx = qcom_geni_serial_stop_tx,
1312 .start_tx = qcom_geni_serial_start_tx,
1313 .stop_rx = qcom_geni_serial_stop_rx,
1314 .set_termios = qcom_geni_serial_set_termios,
1315 .startup = qcom_geni_serial_startup,
1316 .request_port = qcom_geni_serial_request_port,
1317 .config_port = qcom_geni_serial_config_port,
1318 .shutdown = qcom_geni_serial_shutdown,
1319 .type = qcom_geni_serial_get_type,
1320 .set_mctrl = qcom_geni_serial_set_mctrl,
1321 .get_mctrl = qcom_geni_serial_get_mctrl,
1322#ifdef CONFIG_CONSOLE_POLL
1323 .poll_get_char = qcom_geni_serial_get_char,
1324 .poll_put_char = qcom_geni_serial_poll_put_char,
1325#endif
1326 .pm = qcom_geni_serial_pm,
1327};
1328
1329static const struct uart_ops qcom_geni_uart_pops = {
1330 .tx_empty = qcom_geni_serial_tx_empty,
1331 .stop_tx = qcom_geni_serial_stop_tx,
1332 .start_tx = qcom_geni_serial_start_tx,
1333 .stop_rx = qcom_geni_serial_stop_rx,
1334 .set_termios = qcom_geni_serial_set_termios,
1335 .startup = qcom_geni_serial_startup,
1336 .request_port = qcom_geni_serial_request_port,
1337 .config_port = qcom_geni_serial_config_port,
1338 .shutdown = qcom_geni_serial_shutdown,
1339 .type = qcom_geni_serial_get_type,
1340 .set_mctrl = qcom_geni_serial_set_mctrl,
1341 .get_mctrl = qcom_geni_serial_get_mctrl,
1342 .pm = qcom_geni_serial_pm,
1343};
1344
1345static int qcom_geni_serial_probe(struct platform_device *pdev)
1346{
1347 int ret = 0;
1348 int line = -1;
1349 struct qcom_geni_serial_port *port;
1350 struct uart_port *uport;
1351 struct resource *res;
1352 int irq;
1353 bool console = false;
1354 struct uart_driver *drv;
1355
1356 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1357 console = true;
1358
1359 if (console) {
1360 drv = &qcom_geni_console_driver;
1361 line = of_alias_get_id(pdev->dev.of_node, "serial");
1362 } else {
1363 drv = &qcom_geni_uart_driver;
1364 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1365 }
1366
1367 port = get_port_from_line(line, console);
1368 if (IS_ERR(port)) {
1369 dev_err(&pdev->dev, "Invalid line %d\n", line);
1370 return PTR_ERR(port);
1371 }
1372
1373 uport = &port->uport;
1374 /* Don't allow 2 drivers to access the same port */
1375 if (uport->private_data)
1376 return -ENODEV;
1377
1378 uport->dev = &pdev->dev;
1379 port->se.dev = &pdev->dev;
1380 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1381 port->se.clk = devm_clk_get(&pdev->dev, "se");
1382 if (IS_ERR(port->se.clk)) {
1383 ret = PTR_ERR(port->se.clk);
1384 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1385 return ret;
1386 }
1387
1388 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1389 if (!res)
1390 return -EINVAL;
1391 uport->mapbase = res->start;
1392
1393 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1394 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1395 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1396
1397 if (!console) {
1398 port->rx_fifo = devm_kcalloc(uport->dev,
1399 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1400 if (!port->rx_fifo)
1401 return -ENOMEM;
1402 }
1403
1404 ret = geni_icc_get(&port->se, NULL);
1405 if (ret)
1406 return ret;
1407 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1408 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1409
1410 /* Set BW for register access */
1411 ret = geni_icc_set_bw(&port->se);
1412 if (ret)
1413 return ret;
1414
1415 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1416 "qcom_geni_serial_%s%d",
1417 uart_console(uport) ? "console" : "uart", uport->line);
1418 if (!port->name)
1419 return -ENOMEM;
1420
1421 irq = platform_get_irq(pdev, 0);
1422 if (irq < 0)
1423 return irq;
1424 uport->irq = irq;
1425 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1426
1427 if (!console)
1428 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1429
1430 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1431 port->rx_tx_swap = true;
1432
1433 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1434 port->cts_rts_swap = true;
1435
1436 port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
1437 if (IS_ERR(port->se.opp_table))
1438 return PTR_ERR(port->se.opp_table);
1439 /* OPP table is optional */
1440 ret = dev_pm_opp_of_add_table(&pdev->dev);
1441 if (!ret) {
1442 port->se.has_opp_table = true;
1443 } else if (ret != -ENODEV) {
1444 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1445 return ret;
1446 }
1447
1448 port->private_data.drv = drv;
1449 uport->private_data = &port->private_data;
1450 platform_set_drvdata(pdev, port);
1451 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1452
1453 ret = uart_add_one_port(drv, uport);
1454 if (ret)
1455 goto err;
1456
1457 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1458 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1459 IRQF_TRIGGER_HIGH, port->name, uport);
1460 if (ret) {
1461 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1462 uart_remove_one_port(drv, uport);
1463 goto err;
1464 }
1465
1466 /*
1467 * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1468 * enabled/disabled from dev_pm_arm_wake_irq during system
1469 * suspend/resume respectively.
1470 */
1471 pm_runtime_set_active(&pdev->dev);
1472
1473 if (port->wakeup_irq > 0) {
1474 device_init_wakeup(&pdev->dev, true);
1475 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1476 port->wakeup_irq);
1477 if (ret) {
1478 device_init_wakeup(&pdev->dev, false);
1479 uart_remove_one_port(drv, uport);
1480 goto err;
1481 }
1482 }
1483
1484 return 0;
1485err:
1486 if (port->se.has_opp_table)
1487 dev_pm_opp_of_remove_table(&pdev->dev);
1488 dev_pm_opp_put_clkname(port->se.opp_table);
1489 return ret;
1490}
1491
1492static int qcom_geni_serial_remove(struct platform_device *pdev)
1493{
1494 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1495 struct uart_driver *drv = port->private_data.drv;
1496
1497 if (port->se.has_opp_table)
1498 dev_pm_opp_of_remove_table(&pdev->dev);
1499 dev_pm_opp_put_clkname(port->se.opp_table);
1500 dev_pm_clear_wake_irq(&pdev->dev);
1501 device_init_wakeup(&pdev->dev, false);
1502 uart_remove_one_port(drv, &port->uport);
1503
1504 return 0;
1505}
1506
1507static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1508{
1509 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1510 struct uart_port *uport = &port->uport;
1511 struct qcom_geni_private_data *private_data = uport->private_data;
1512
1513 /*
1514 * This is done so we can hit the lowest possible state in suspend
1515 * even with no_console_suspend
1516 */
1517 if (uart_console(uport)) {
1518 geni_icc_set_tag(&port->se, 0x3);
1519 geni_icc_set_bw(&port->se);
1520 }
1521 return uart_suspend_port(private_data->drv, uport);
1522}
1523
1524static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1525{
1526 int ret;
1527 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1528 struct uart_port *uport = &port->uport;
1529 struct qcom_geni_private_data *private_data = uport->private_data;
1530
1531 ret = uart_resume_port(private_data->drv, uport);
1532 if (uart_console(uport)) {
1533 geni_icc_set_tag(&port->se, 0x7);
1534 geni_icc_set_bw(&port->se);
1535 }
1536 return ret;
1537}
1538
1539static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1540 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1541 qcom_geni_serial_sys_resume)
1542};
1543
1544static const struct of_device_id qcom_geni_serial_match_table[] = {
1545 { .compatible = "qcom,geni-debug-uart", },
1546 { .compatible = "qcom,geni-uart", },
1547 {}
1548};
1549MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1550
1551static struct platform_driver qcom_geni_serial_platform_driver = {
1552 .remove = qcom_geni_serial_remove,
1553 .probe = qcom_geni_serial_probe,
1554 .driver = {
1555 .name = "qcom_geni_serial",
1556 .of_match_table = qcom_geni_serial_match_table,
1557 .pm = &qcom_geni_serial_pm_ops,
1558 },
1559};
1560
1561static int __init qcom_geni_serial_init(void)
1562{
1563 int ret;
1564
1565 ret = console_register(&qcom_geni_console_driver);
1566 if (ret)
1567 return ret;
1568
1569 ret = uart_register_driver(&qcom_geni_uart_driver);
1570 if (ret) {
1571 console_unregister(&qcom_geni_console_driver);
1572 return ret;
1573 }
1574
1575 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1576 if (ret) {
1577 console_unregister(&qcom_geni_console_driver);
1578 uart_unregister_driver(&qcom_geni_uart_driver);
1579 }
1580 return ret;
1581}
1582module_init(qcom_geni_serial_init);
1583
1584static void __exit qcom_geni_serial_exit(void)
1585{
1586 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1587 console_unregister(&qcom_geni_console_driver);
1588 uart_unregister_driver(&qcom_geni_uart_driver);
1589}
1590module_exit(qcom_geni_serial_exit);
1591
1592MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1593MODULE_LICENSE("GPL v2");