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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5#include "intel_de.h"
6#include "intel_display_types.h"
7#include "skl_scaler.h"
8#include "skl_universal_plane.h"
9
10/*
11 * The hardware phase 0.0 refers to the center of the pixel.
12 * We want to start from the top/left edge which is phase
13 * -0.5. That matches how the hardware calculates the scaling
14 * factors (from top-left of the first pixel to bottom-right
15 * of the last pixel, as opposed to the pixel centers).
16 *
17 * For 4:2:0 subsampled chroma planes we obviously have to
18 * adjust that so that the chroma sample position lands in
19 * the right spot.
20 *
21 * Note that for packed YCbCr 4:2:2 formats there is no way to
22 * control chroma siting. The hardware simply replicates the
23 * chroma samples for both of the luma samples, and thus we don't
24 * actually get the expected MPEG2 chroma siting convention :(
25 * The same behaviour is observed on pre-SKL platforms as well.
26 *
27 * Theory behind the formula (note that we ignore sub-pixel
28 * source coordinates):
29 * s = source sample position
30 * d = destination sample position
31 *
32 * Downscaling 4:1:
33 * -0.5
34 * | 0.0
35 * | | 1.5 (initial phase)
36 * | | |
37 * v v v
38 * | s | s | s | s |
39 * | d |
40 *
41 * Upscaling 1:4:
42 * -0.5
43 * | -0.375 (initial phase)
44 * | | 0.0
45 * | | |
46 * v v v
47 * | s |
48 * | d | d | d | d |
49 */
50static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
51{
52 int phase = -0x8000;
53 u16 trip = 0;
54
55 if (chroma_cosited)
56 phase += (sub - 1) * 0x8000 / sub;
57
58 phase += scale / (2 * sub);
59
60 /*
61 * Hardware initial phase limited to [-0.5:1.5].
62 * Since the max hardware scale factor is 3.0, we
63 * should never actually excdeed 1.0 here.
64 */
65 WARN_ON(phase < -0x8000 || phase > 0x18000);
66
67 if (phase < 0)
68 phase = 0x10000 + phase;
69 else
70 trip = PS_PHASE_TRIP;
71
72 return ((phase >> 2) & PS_PHASE_MASK) | trip;
73}
74
75#define SKL_MIN_SRC_W 8
76#define SKL_MAX_SRC_W 4096
77#define SKL_MIN_SRC_H 8
78#define SKL_MAX_SRC_H 4096
79#define SKL_MIN_DST_W 8
80#define SKL_MAX_DST_W 4096
81#define SKL_MIN_DST_H 8
82#define SKL_MAX_DST_H 4096
83#define ICL_MAX_SRC_W 5120
84#define ICL_MAX_SRC_H 4096
85#define ICL_MAX_DST_W 5120
86#define ICL_MAX_DST_H 4096
87#define SKL_MIN_YUV_420_SRC_W 16
88#define SKL_MIN_YUV_420_SRC_H 16
89
90static int
91skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
92 unsigned int scaler_user, int *scaler_id,
93 int src_w, int src_h, int dst_w, int dst_h,
94 const struct drm_format_info *format,
95 u64 modifier, bool need_scaler)
96{
97 struct intel_crtc_scaler_state *scaler_state =
98 &crtc_state->scaler_state;
99 struct intel_crtc *intel_crtc =
100 to_intel_crtc(crtc_state->uapi.crtc);
101 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
102 const struct drm_display_mode *adjusted_mode =
103 &crtc_state->hw.adjusted_mode;
104
105 /*
106 * Src coordinates are already rotated by 270 degrees for
107 * the 90/270 degree plane rotation cases (to match the
108 * GTT mapping), hence no need to account for rotation here.
109 */
110 if (src_w != dst_w || src_h != dst_h)
111 need_scaler = true;
112
113 /*
114 * Scaling/fitting not supported in IF-ID mode in GEN9+
115 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
116 * Once NV12 is enabled, handle it here while allocating scaler
117 * for NV12.
118 */
119 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
120 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
121 drm_dbg_kms(&dev_priv->drm,
122 "Pipe/Plane scaling not supported with IF-ID mode\n");
123 return -EINVAL;
124 }
125
126 /*
127 * if plane is being disabled or scaler is no more required or force detach
128 * - free scaler binded to this plane/crtc
129 * - in order to do this, update crtc->scaler_usage
130 *
131 * Here scaler state in crtc_state is set free so that
132 * scaler can be assigned to other user. Actual register
133 * update to free the scaler is done in plane/panel-fit programming.
134 * For this purpose crtc/plane_state->scaler_id isn't reset here.
135 */
136 if (force_detach || !need_scaler) {
137 if (*scaler_id >= 0) {
138 scaler_state->scaler_users &= ~(1 << scaler_user);
139 scaler_state->scalers[*scaler_id].in_use = 0;
140
141 drm_dbg_kms(&dev_priv->drm,
142 "scaler_user index %u.%u: "
143 "Staged freeing scaler id %d scaler_users = 0x%x\n",
144 intel_crtc->pipe, scaler_user, *scaler_id,
145 scaler_state->scaler_users);
146 *scaler_id = -1;
147 }
148 return 0;
149 }
150
151 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
152 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
153 drm_dbg_kms(&dev_priv->drm,
154 "Planar YUV: src dimensions not met\n");
155 return -EINVAL;
156 }
157
158 /* range checks */
159 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
160 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
161 (DISPLAY_VER(dev_priv) >= 11 &&
162 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
163 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
164 (DISPLAY_VER(dev_priv) < 11 &&
165 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
166 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
167 drm_dbg_kms(&dev_priv->drm,
168 "scaler_user index %u.%u: src %ux%u dst %ux%u "
169 "size is out of scaler range\n",
170 intel_crtc->pipe, scaler_user, src_w, src_h,
171 dst_w, dst_h);
172 return -EINVAL;
173 }
174
175 /* mark this plane as a scaler user in crtc_state */
176 scaler_state->scaler_users |= (1 << scaler_user);
177 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
178 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
179 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
180 scaler_state->scaler_users);
181
182 return 0;
183}
184
185int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
186{
187 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
188 int width, height;
189
190 if (crtc_state->pch_pfit.enabled) {
191 width = drm_rect_width(&crtc_state->pch_pfit.dst);
192 height = drm_rect_height(&crtc_state->pch_pfit.dst);
193 } else {
194 width = pipe_mode->crtc_hdisplay;
195 height = pipe_mode->crtc_vdisplay;
196 }
197 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
198 SKL_CRTC_INDEX,
199 &crtc_state->scaler_state.scaler_id,
200 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
201 width, height, NULL, 0,
202 crtc_state->pch_pfit.enabled);
203}
204
205/**
206 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
207 * @crtc_state: crtc's scaler state
208 * @plane_state: atomic plane state to update
209 *
210 * Return
211 * 0 - scaler_usage updated successfully
212 * error - requested scaling cannot be supported or other error condition
213 */
214int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
215 struct intel_plane_state *plane_state)
216{
217 struct intel_plane *intel_plane =
218 to_intel_plane(plane_state->uapi.plane);
219 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
220 struct drm_framebuffer *fb = plane_state->hw.fb;
221 int ret;
222 bool force_detach = !fb || !plane_state->uapi.visible;
223 bool need_scaler = false;
224
225 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
226 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
227 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
228 need_scaler = true;
229
230 ret = skl_update_scaler(crtc_state, force_detach,
231 drm_plane_index(&intel_plane->base),
232 &plane_state->scaler_id,
233 drm_rect_width(&plane_state->uapi.src) >> 16,
234 drm_rect_height(&plane_state->uapi.src) >> 16,
235 drm_rect_width(&plane_state->uapi.dst),
236 drm_rect_height(&plane_state->uapi.dst),
237 fb ? fb->format : NULL,
238 fb ? fb->modifier : 0,
239 need_scaler);
240
241 if (ret || plane_state->scaler_id < 0)
242 return ret;
243
244 /* check colorkey */
245 if (plane_state->ckey.flags) {
246 drm_dbg_kms(&dev_priv->drm,
247 "[PLANE:%d:%s] scaling with color key not allowed",
248 intel_plane->base.base.id,
249 intel_plane->base.name);
250 return -EINVAL;
251 }
252
253 /* Check src format */
254 switch (fb->format->format) {
255 case DRM_FORMAT_RGB565:
256 case DRM_FORMAT_XBGR8888:
257 case DRM_FORMAT_XRGB8888:
258 case DRM_FORMAT_ABGR8888:
259 case DRM_FORMAT_ARGB8888:
260 case DRM_FORMAT_XRGB2101010:
261 case DRM_FORMAT_XBGR2101010:
262 case DRM_FORMAT_ARGB2101010:
263 case DRM_FORMAT_ABGR2101010:
264 case DRM_FORMAT_YUYV:
265 case DRM_FORMAT_YVYU:
266 case DRM_FORMAT_UYVY:
267 case DRM_FORMAT_VYUY:
268 case DRM_FORMAT_NV12:
269 case DRM_FORMAT_XYUV8888:
270 case DRM_FORMAT_P010:
271 case DRM_FORMAT_P012:
272 case DRM_FORMAT_P016:
273 case DRM_FORMAT_Y210:
274 case DRM_FORMAT_Y212:
275 case DRM_FORMAT_Y216:
276 case DRM_FORMAT_XVYU2101010:
277 case DRM_FORMAT_XVYU12_16161616:
278 case DRM_FORMAT_XVYU16161616:
279 break;
280 case DRM_FORMAT_XBGR16161616F:
281 case DRM_FORMAT_ABGR16161616F:
282 case DRM_FORMAT_XRGB16161616F:
283 case DRM_FORMAT_ARGB16161616F:
284 if (DISPLAY_VER(dev_priv) >= 11)
285 break;
286 fallthrough;
287 default:
288 drm_dbg_kms(&dev_priv->drm,
289 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
290 intel_plane->base.base.id, intel_plane->base.name,
291 fb->base.id, fb->format->format);
292 return -EINVAL;
293 }
294
295 return 0;
296}
297
298static int cnl_coef_tap(int i)
299{
300 return i % 7;
301}
302
303static u16 cnl_nearest_filter_coef(int t)
304{
305 return t == 3 ? 0x0800 : 0x3000;
306}
307
308/*
309 * Theory behind setting nearest-neighbor integer scaling:
310 *
311 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
312 * The letter represents the filter tap (D is the center tap) and the number
313 * represents the coefficient set for a phase (0-16).
314 *
315 * +------------+------------------------+------------------------+
316 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
317 * +------------+------------------------+------------------------+
318 * | 00h | B0 | A0 |
319 * +------------+------------------------+------------------------+
320 * | 01h | D0 | C0 |
321 * +------------+------------------------+------------------------+
322 * | 02h | F0 | E0 |
323 * +------------+------------------------+------------------------+
324 * | 03h | A1 | G0 |
325 * +------------+------------------------+------------------------+
326 * | 04h | C1 | B1 |
327 * +------------+------------------------+------------------------+
328 * | ... | ... | ... |
329 * +------------+------------------------+------------------------+
330 * | 38h | B16 | A16 |
331 * +------------+------------------------+------------------------+
332 * | 39h | D16 | C16 |
333 * +------------+------------------------+------------------------+
334 * | 3Ah | F16 | C16 |
335 * +------------+------------------------+------------------------+
336 * | 3Bh | Reserved | G16 |
337 * +------------+------------------------+------------------------+
338 *
339 * To enable nearest-neighbor scaling: program scaler coefficents with
340 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
341 * SCALER_COEFFICIENT_FORMAT
342 *
343 */
344
345static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
346 enum pipe pipe, int id, int set)
347{
348 int i;
349
350 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
351 PS_COEE_INDEX_AUTO_INC);
352
353 for (i = 0; i < 17 * 7; i += 2) {
354 u32 tmp;
355 int t;
356
357 t = cnl_coef_tap(i);
358 tmp = cnl_nearest_filter_coef(t);
359
360 t = cnl_coef_tap(i + 1);
361 tmp |= cnl_nearest_filter_coef(t) << 16;
362
363 intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
364 tmp);
365 }
366
367 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
368}
369
370static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
371{
372 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
373 return (PS_FILTER_PROGRAMMED |
374 PS_Y_VERT_FILTER_SELECT(set) |
375 PS_Y_HORZ_FILTER_SELECT(set) |
376 PS_UV_VERT_FILTER_SELECT(set) |
377 PS_UV_HORZ_FILTER_SELECT(set));
378 }
379
380 return PS_FILTER_MEDIUM;
381}
382
383static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
384 int id, int set, enum drm_scaling_filter filter)
385{
386 switch (filter) {
387 case DRM_SCALING_FILTER_DEFAULT:
388 break;
389 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
390 cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
391 break;
392 default:
393 MISSING_CASE(filter);
394 }
395}
396
397void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
398{
399 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
400 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
401 const struct intel_crtc_scaler_state *scaler_state =
402 &crtc_state->scaler_state;
403 struct drm_rect src = {
404 .x2 = crtc_state->pipe_src_w << 16,
405 .y2 = crtc_state->pipe_src_h << 16,
406 };
407 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
408 u16 uv_rgb_hphase, uv_rgb_vphase;
409 enum pipe pipe = crtc->pipe;
410 int width = drm_rect_width(dst);
411 int height = drm_rect_height(dst);
412 int x = dst->x1;
413 int y = dst->y1;
414 int hscale, vscale;
415 unsigned long irqflags;
416 int id;
417 u32 ps_ctrl;
418
419 if (!crtc_state->pch_pfit.enabled)
420 return;
421
422 if (drm_WARN_ON(&dev_priv->drm,
423 crtc_state->scaler_state.scaler_id < 0))
424 return;
425
426 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
427 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
428
429 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
430 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
431
432 id = scaler_state->scaler_id;
433
434 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
435 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
436
437 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
438
439 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
440 crtc_state->hw.scaling_filter);
441
442 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
443
444 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
445 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
446 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
447 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
448 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
449 x << 16 | y);
450 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
451 width << 16 | height);
452
453 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
454}
455
456void
457skl_program_plane_scaler(struct intel_plane *plane,
458 const struct intel_crtc_state *crtc_state,
459 const struct intel_plane_state *plane_state)
460{
461 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
462 const struct drm_framebuffer *fb = plane_state->hw.fb;
463 enum pipe pipe = plane->pipe;
464 int scaler_id = plane_state->scaler_id;
465 const struct intel_scaler *scaler =
466 &crtc_state->scaler_state.scalers[scaler_id];
467 int crtc_x = plane_state->uapi.dst.x1;
468 int crtc_y = plane_state->uapi.dst.y1;
469 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
470 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
471 u16 y_hphase, uv_rgb_hphase;
472 u16 y_vphase, uv_rgb_vphase;
473 int hscale, vscale;
474 u32 ps_ctrl;
475
476 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
477 &plane_state->uapi.dst,
478 0, INT_MAX);
479 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
480 &plane_state->uapi.dst,
481 0, INT_MAX);
482
483 /* TODO: handle sub-pixel coordinates */
484 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
485 !icl_is_hdr_plane(dev_priv, plane->id)) {
486 y_hphase = skl_scaler_calc_phase(1, hscale, false);
487 y_vphase = skl_scaler_calc_phase(1, vscale, false);
488
489 /* MPEG2 chroma siting convention */
490 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
491 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
492 } else {
493 /* not used */
494 y_hphase = 0;
495 y_vphase = 0;
496
497 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
498 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
499 }
500
501 ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
502 ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
503
504 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
505 plane_state->hw.scaling_filter);
506
507 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
508 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
509 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
510 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
511 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
512 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
513 (crtc_x << 16) | crtc_y);
514 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
515 (crtc_w << 16) | crtc_h);
516}
517
518static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
519{
520 struct drm_device *dev = intel_crtc->base.dev;
521 struct drm_i915_private *dev_priv = to_i915(dev);
522 unsigned long irqflags;
523
524 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
525
526 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
527 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
528 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
529
530 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
531}
532
533/*
534 * This function detaches (aka. unbinds) unused scalers in hardware
535 */
536void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
537{
538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
539 const struct intel_crtc_scaler_state *scaler_state =
540 &crtc_state->scaler_state;
541 int i;
542
543 /* loop through and disable scalers that aren't in use */
544 for (i = 0; i < intel_crtc->num_scalers; i++) {
545 if (!scaler_state->scalers[i].in_use)
546 skl_detach_scaler(intel_crtc, i);
547 }
548}
549
550void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
551{
552 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
553 int i;
554
555 for (i = 0; i < crtc->num_scalers; i++)
556 skl_detach_scaler(crtc, i);
557}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5
6#include "i915_reg.h"
7#include "intel_de.h"
8#include "intel_display_types.h"
9#include "intel_fb.h"
10#include "skl_scaler.h"
11#include "skl_universal_plane.h"
12
13/*
14 * The hardware phase 0.0 refers to the center of the pixel.
15 * We want to start from the top/left edge which is phase
16 * -0.5. That matches how the hardware calculates the scaling
17 * factors (from top-left of the first pixel to bottom-right
18 * of the last pixel, as opposed to the pixel centers).
19 *
20 * For 4:2:0 subsampled chroma planes we obviously have to
21 * adjust that so that the chroma sample position lands in
22 * the right spot.
23 *
24 * Note that for packed YCbCr 4:2:2 formats there is no way to
25 * control chroma siting. The hardware simply replicates the
26 * chroma samples for both of the luma samples, and thus we don't
27 * actually get the expected MPEG2 chroma siting convention :(
28 * The same behaviour is observed on pre-SKL platforms as well.
29 *
30 * Theory behind the formula (note that we ignore sub-pixel
31 * source coordinates):
32 * s = source sample position
33 * d = destination sample position
34 *
35 * Downscaling 4:1:
36 * -0.5
37 * | 0.0
38 * | | 1.5 (initial phase)
39 * | | |
40 * v v v
41 * | s | s | s | s |
42 * | d |
43 *
44 * Upscaling 1:4:
45 * -0.5
46 * | -0.375 (initial phase)
47 * | | 0.0
48 * | | |
49 * v v v
50 * | s |
51 * | d | d | d | d |
52 */
53static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
54{
55 int phase = -0x8000;
56 u16 trip = 0;
57
58 if (chroma_cosited)
59 phase += (sub - 1) * 0x8000 / sub;
60
61 phase += scale / (2 * sub);
62
63 /*
64 * Hardware initial phase limited to [-0.5:1.5].
65 * Since the max hardware scale factor is 3.0, we
66 * should never actually excdeed 1.0 here.
67 */
68 WARN_ON(phase < -0x8000 || phase > 0x18000);
69
70 if (phase < 0)
71 phase = 0x10000 + phase;
72 else
73 trip = PS_PHASE_TRIP;
74
75 return ((phase >> 2) & PS_PHASE_MASK) | trip;
76}
77
78#define SKL_MIN_SRC_W 8
79#define SKL_MAX_SRC_W 4096
80#define SKL_MIN_SRC_H 8
81#define SKL_MAX_SRC_H 4096
82#define SKL_MIN_DST_W 8
83#define SKL_MAX_DST_W 4096
84#define SKL_MIN_DST_H 8
85#define SKL_MAX_DST_H 4096
86#define ICL_MAX_SRC_W 5120
87#define ICL_MAX_SRC_H 4096
88#define ICL_MAX_DST_W 5120
89#define ICL_MAX_DST_H 4096
90#define TGL_MAX_SRC_W 5120
91#define TGL_MAX_SRC_H 8192
92#define TGL_MAX_DST_W 8192
93#define TGL_MAX_DST_H 8192
94#define MTL_MAX_SRC_W 4096
95#define MTL_MAX_SRC_H 8192
96#define MTL_MAX_DST_W 8192
97#define MTL_MAX_DST_H 8192
98#define SKL_MIN_YUV_420_SRC_W 16
99#define SKL_MIN_YUV_420_SRC_H 16
100
101static int
102skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
103 unsigned int scaler_user, int *scaler_id,
104 int src_w, int src_h, int dst_w, int dst_h,
105 const struct drm_format_info *format,
106 u64 modifier, bool need_scaler)
107{
108 struct intel_crtc_scaler_state *scaler_state =
109 &crtc_state->scaler_state;
110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
111 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
112 const struct drm_display_mode *adjusted_mode =
113 &crtc_state->hw.adjusted_mode;
114 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
115 int pipe_src_h = drm_rect_height(&crtc_state->pipe_src);
116 int min_src_w, min_src_h, min_dst_w, min_dst_h;
117 int max_src_w, max_src_h, max_dst_w, max_dst_h;
118
119 /*
120 * Src coordinates are already rotated by 270 degrees for
121 * the 90/270 degree plane rotation cases (to match the
122 * GTT mapping), hence no need to account for rotation here.
123 */
124 if (src_w != dst_w || src_h != dst_h)
125 need_scaler = true;
126
127 /*
128 * Scaling/fitting not supported in IF-ID mode in GEN9+
129 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
130 * Once NV12 is enabled, handle it here while allocating scaler
131 * for NV12.
132 */
133 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
134 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
135 drm_dbg_kms(&dev_priv->drm,
136 "Pipe/Plane scaling not supported with IF-ID mode\n");
137 return -EINVAL;
138 }
139
140 /*
141 * if plane is being disabled or scaler is no more required or force detach
142 * - free scaler binded to this plane/crtc
143 * - in order to do this, update crtc->scaler_usage
144 *
145 * Here scaler state in crtc_state is set free so that
146 * scaler can be assigned to other user. Actual register
147 * update to free the scaler is done in plane/panel-fit programming.
148 * For this purpose crtc/plane_state->scaler_id isn't reset here.
149 */
150 if (force_detach || !need_scaler) {
151 if (*scaler_id >= 0) {
152 scaler_state->scaler_users &= ~(1 << scaler_user);
153 scaler_state->scalers[*scaler_id].in_use = 0;
154
155 drm_dbg_kms(&dev_priv->drm,
156 "scaler_user index %u.%u: "
157 "Staged freeing scaler id %d scaler_users = 0x%x\n",
158 crtc->pipe, scaler_user, *scaler_id,
159 scaler_state->scaler_users);
160 *scaler_id = -1;
161 }
162 return 0;
163 }
164
165 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
166 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
167 drm_dbg_kms(&dev_priv->drm,
168 "Planar YUV: src dimensions not met\n");
169 return -EINVAL;
170 }
171
172 min_src_w = SKL_MIN_SRC_W;
173 min_src_h = SKL_MIN_SRC_H;
174 min_dst_w = SKL_MIN_DST_W;
175 min_dst_h = SKL_MIN_DST_H;
176
177 if (DISPLAY_VER(dev_priv) < 11) {
178 max_src_w = SKL_MAX_SRC_W;
179 max_src_h = SKL_MAX_SRC_H;
180 max_dst_w = SKL_MAX_DST_W;
181 max_dst_h = SKL_MAX_DST_H;
182 } else if (DISPLAY_VER(dev_priv) < 12) {
183 max_src_w = ICL_MAX_SRC_W;
184 max_src_h = ICL_MAX_SRC_H;
185 max_dst_w = ICL_MAX_DST_W;
186 max_dst_h = ICL_MAX_DST_H;
187 } else if (DISPLAY_VER(dev_priv) < 14) {
188 max_src_w = TGL_MAX_SRC_W;
189 max_src_h = TGL_MAX_SRC_H;
190 max_dst_w = TGL_MAX_DST_W;
191 max_dst_h = TGL_MAX_DST_H;
192 } else {
193 max_src_w = MTL_MAX_SRC_W;
194 max_src_h = MTL_MAX_SRC_H;
195 max_dst_w = MTL_MAX_DST_W;
196 max_dst_h = MTL_MAX_DST_H;
197 }
198
199 /* range checks */
200 if (src_w < min_src_w || src_h < min_src_h ||
201 dst_w < min_dst_w || dst_h < min_dst_h ||
202 src_w > max_src_w || src_h > max_src_h ||
203 dst_w > max_dst_w || dst_h > max_dst_h) {
204 drm_dbg_kms(&dev_priv->drm,
205 "scaler_user index %u.%u: src %ux%u dst %ux%u "
206 "size is out of scaler range\n",
207 crtc->pipe, scaler_user, src_w, src_h,
208 dst_w, dst_h);
209 return -EINVAL;
210 }
211
212 /*
213 * The pipe scaler does not use all the bits of PIPESRC, at least
214 * on the earlier platforms. So even when we're scaling a plane
215 * the *pipe* source size must not be too large. For simplicity
216 * we assume the limits match the scaler destination size limits.
217 * Might not be 100% accurate on all platforms, but good enough for
218 * now.
219 */
220 if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) {
221 drm_dbg_kms(&dev_priv->drm,
222 "scaler_user index %u.%u: pipe src size %ux%u "
223 "is out of scaler range\n",
224 crtc->pipe, scaler_user, pipe_src_w, pipe_src_h);
225 return -EINVAL;
226 }
227
228 /* mark this plane as a scaler user in crtc_state */
229 scaler_state->scaler_users |= (1 << scaler_user);
230 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
231 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
232 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
233 scaler_state->scaler_users);
234
235 return 0;
236}
237
238int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
239{
240 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
241 int width, height;
242
243 if (crtc_state->pch_pfit.enabled) {
244 width = drm_rect_width(&crtc_state->pch_pfit.dst);
245 height = drm_rect_height(&crtc_state->pch_pfit.dst);
246 } else {
247 width = pipe_mode->crtc_hdisplay;
248 height = pipe_mode->crtc_vdisplay;
249 }
250 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
251 SKL_CRTC_INDEX,
252 &crtc_state->scaler_state.scaler_id,
253 drm_rect_width(&crtc_state->pipe_src),
254 drm_rect_height(&crtc_state->pipe_src),
255 width, height, NULL, 0,
256 crtc_state->pch_pfit.enabled);
257}
258
259/**
260 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
261 * @crtc_state: crtc's scaler state
262 * @plane_state: atomic plane state to update
263 *
264 * Return
265 * 0 - scaler_usage updated successfully
266 * error - requested scaling cannot be supported or other error condition
267 */
268int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
269 struct intel_plane_state *plane_state)
270{
271 struct intel_plane *intel_plane =
272 to_intel_plane(plane_state->uapi.plane);
273 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
274 struct drm_framebuffer *fb = plane_state->hw.fb;
275 bool force_detach = !fb || !plane_state->uapi.visible;
276 bool need_scaler = false;
277
278 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
279 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
280 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
281 need_scaler = true;
282
283 return skl_update_scaler(crtc_state, force_detach,
284 drm_plane_index(&intel_plane->base),
285 &plane_state->scaler_id,
286 drm_rect_width(&plane_state->uapi.src) >> 16,
287 drm_rect_height(&plane_state->uapi.src) >> 16,
288 drm_rect_width(&plane_state->uapi.dst),
289 drm_rect_height(&plane_state->uapi.dst),
290 fb ? fb->format : NULL,
291 fb ? fb->modifier : 0,
292 need_scaler);
293}
294
295static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
296 int num_scalers_need, struct intel_crtc *intel_crtc,
297 const char *name, int idx,
298 struct intel_plane_state *plane_state,
299 int *scaler_id)
300{
301 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
302 int j;
303 u32 mode;
304
305 if (*scaler_id < 0) {
306 /* find a free scaler */
307 for (j = 0; j < intel_crtc->num_scalers; j++) {
308 if (scaler_state->scalers[j].in_use)
309 continue;
310
311 *scaler_id = j;
312 scaler_state->scalers[*scaler_id].in_use = 1;
313 break;
314 }
315 }
316
317 if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
318 "Cannot find scaler for %s:%d\n", name, idx))
319 return -EINVAL;
320
321 /* set scaler mode */
322 if (plane_state && plane_state->hw.fb &&
323 plane_state->hw.fb->format->is_yuv &&
324 plane_state->hw.fb->format->num_planes > 1) {
325 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
326
327 if (DISPLAY_VER(dev_priv) == 9) {
328 mode = SKL_PS_SCALER_MODE_NV12;
329 } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
330 /*
331 * On gen11+'s HDR planes we only use the scaler for
332 * scaling. They have a dedicated chroma upsampler, so
333 * we don't need the scaler to upsample the UV plane.
334 */
335 mode = PS_SCALER_MODE_NORMAL;
336 } else {
337 struct intel_plane *linked =
338 plane_state->planar_linked_plane;
339
340 mode = PS_SCALER_MODE_PLANAR;
341
342 if (linked)
343 mode |= PS_BINDING_Y_PLANE(linked->id);
344 }
345 } else if (DISPLAY_VER(dev_priv) >= 10) {
346 mode = PS_SCALER_MODE_NORMAL;
347 } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
348 /*
349 * when only 1 scaler is in use on a pipe with 2 scalers
350 * scaler 0 operates in high quality (HQ) mode.
351 * In this case use scaler 0 to take advantage of HQ mode
352 */
353 scaler_state->scalers[*scaler_id].in_use = 0;
354 *scaler_id = 0;
355 scaler_state->scalers[0].in_use = 1;
356 mode = SKL_PS_SCALER_MODE_HQ;
357 } else {
358 mode = SKL_PS_SCALER_MODE_DYN;
359 }
360
361 /*
362 * FIXME: we should also check the scaler factors for pfit, so
363 * this shouldn't be tied directly to planes.
364 */
365 if (plane_state && plane_state->hw.fb) {
366 const struct drm_framebuffer *fb = plane_state->hw.fb;
367 const struct drm_rect *src = &plane_state->uapi.src;
368 const struct drm_rect *dst = &plane_state->uapi.dst;
369 int hscale, vscale, max_vscale, max_hscale;
370
371 /*
372 * FIXME: When two scalers are needed, but only one of
373 * them needs to downscale, we should make sure that
374 * the one that needs downscaling support is assigned
375 * as the first scaler, so we don't reject downscaling
376 * unnecessarily.
377 */
378
379 if (DISPLAY_VER(dev_priv) >= 14) {
380 /*
381 * On versions 14 and up, only the first
382 * scaler supports a vertical scaling factor
383 * of more than 1.0, while a horizontal
384 * scaling factor of 3.0 is supported.
385 */
386 max_hscale = 0x30000 - 1;
387 if (*scaler_id == 0)
388 max_vscale = 0x30000 - 1;
389 else
390 max_vscale = 0x10000;
391
392 } else if (DISPLAY_VER(dev_priv) >= 10 ||
393 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
394 max_hscale = 0x30000 - 1;
395 max_vscale = 0x30000 - 1;
396 } else {
397 max_hscale = 0x20000 - 1;
398 max_vscale = 0x20000 - 1;
399 }
400
401 /*
402 * FIXME: We should change the if-else block above to
403 * support HQ vs dynamic scaler properly.
404 */
405
406 /* Check if required scaling is within limits */
407 hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
408 vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
409
410 if (hscale < 0 || vscale < 0) {
411 drm_dbg_kms(&dev_priv->drm,
412 "Scaler %d doesn't support required plane scaling\n",
413 *scaler_id);
414 drm_rect_debug_print("src: ", src, true);
415 drm_rect_debug_print("dst: ", dst, false);
416
417 return -EINVAL;
418 }
419 }
420
421 drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
422 intel_crtc->pipe, *scaler_id, name, idx);
423 scaler_state->scalers[*scaler_id].mode = mode;
424
425 return 0;
426}
427
428/**
429 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
430 * @dev_priv: i915 device
431 * @intel_crtc: intel crtc
432 * @crtc_state: incoming crtc_state to validate and setup scalers
433 *
434 * This function sets up scalers based on staged scaling requests for
435 * a @crtc and its planes. It is called from crtc level check path. If request
436 * is a supportable request, it attaches scalers to requested planes and crtc.
437 *
438 * This function takes into account the current scaler(s) in use by any planes
439 * not being part of this atomic state
440 *
441 * Returns:
442 * 0 - scalers were setup successfully
443 * error code - otherwise
444 */
445int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
446 struct intel_crtc *intel_crtc,
447 struct intel_crtc_state *crtc_state)
448{
449 struct drm_plane *plane = NULL;
450 struct intel_plane *intel_plane;
451 struct intel_crtc_scaler_state *scaler_state =
452 &crtc_state->scaler_state;
453 struct drm_atomic_state *drm_state = crtc_state->uapi.state;
454 struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
455 int num_scalers_need;
456 int i;
457
458 num_scalers_need = hweight32(scaler_state->scaler_users);
459
460 /*
461 * High level flow:
462 * - staged scaler requests are already in scaler_state->scaler_users
463 * - check whether staged scaling requests can be supported
464 * - add planes using scalers that aren't in current transaction
465 * - assign scalers to requested users
466 * - as part of plane commit, scalers will be committed
467 * (i.e., either attached or detached) to respective planes in hw
468 * - as part of crtc_commit, scaler will be either attached or detached
469 * to crtc in hw
470 */
471
472 /* fail if required scalers > available scalers */
473 if (num_scalers_need > intel_crtc->num_scalers) {
474 drm_dbg_kms(&dev_priv->drm,
475 "Too many scaling requests %d > %d\n",
476 num_scalers_need, intel_crtc->num_scalers);
477 return -EINVAL;
478 }
479
480 /* walkthrough scaler_users bits and start assigning scalers */
481 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
482 struct intel_plane_state *plane_state = NULL;
483 int *scaler_id;
484 const char *name;
485 int idx, ret;
486
487 /* skip if scaler not required */
488 if (!(scaler_state->scaler_users & (1 << i)))
489 continue;
490
491 if (i == SKL_CRTC_INDEX) {
492 name = "CRTC";
493 idx = intel_crtc->base.base.id;
494
495 /* panel fitter case: assign as a crtc scaler */
496 scaler_id = &scaler_state->scaler_id;
497 } else {
498 name = "PLANE";
499
500 /* plane scaler case: assign as a plane scaler */
501 /* find the plane that set the bit as scaler_user */
502 plane = drm_state->planes[i].ptr;
503
504 /*
505 * to enable/disable hq mode, add planes that are using scaler
506 * into this transaction
507 */
508 if (!plane) {
509 struct drm_plane_state *state;
510
511 /*
512 * GLK+ scalers don't have a HQ mode so it
513 * isn't necessary to change between HQ and dyn mode
514 * on those platforms.
515 */
516 if (DISPLAY_VER(dev_priv) >= 10)
517 continue;
518
519 plane = drm_plane_from_index(&dev_priv->drm, i);
520 state = drm_atomic_get_plane_state(drm_state, plane);
521 if (IS_ERR(state)) {
522 drm_dbg_kms(&dev_priv->drm,
523 "Failed to add [PLANE:%d] to drm_state\n",
524 plane->base.id);
525 return PTR_ERR(state);
526 }
527 }
528
529 intel_plane = to_intel_plane(plane);
530 idx = plane->base.id;
531
532 /* plane on different crtc cannot be a scaler user of this crtc */
533 if (drm_WARN_ON(&dev_priv->drm,
534 intel_plane->pipe != intel_crtc->pipe))
535 continue;
536
537 plane_state = intel_atomic_get_new_plane_state(intel_state,
538 intel_plane);
539 scaler_id = &plane_state->scaler_id;
540 }
541
542 ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
543 intel_crtc, name, idx,
544 plane_state, scaler_id);
545 if (ret < 0)
546 return ret;
547 }
548
549 return 0;
550}
551
552static int glk_coef_tap(int i)
553{
554 return i % 7;
555}
556
557static u16 glk_nearest_filter_coef(int t)
558{
559 return t == 3 ? 0x0800 : 0x3000;
560}
561
562/*
563 * Theory behind setting nearest-neighbor integer scaling:
564 *
565 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
566 * The letter represents the filter tap (D is the center tap) and the number
567 * represents the coefficient set for a phase (0-16).
568 *
569 * +------------+------------------------+------------------------+
570 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
571 * +------------+------------------------+------------------------+
572 * | 00h | B0 | A0 |
573 * +------------+------------------------+------------------------+
574 * | 01h | D0 | C0 |
575 * +------------+------------------------+------------------------+
576 * | 02h | F0 | E0 |
577 * +------------+------------------------+------------------------+
578 * | 03h | A1 | G0 |
579 * +------------+------------------------+------------------------+
580 * | 04h | C1 | B1 |
581 * +------------+------------------------+------------------------+
582 * | ... | ... | ... |
583 * +------------+------------------------+------------------------+
584 * | 38h | B16 | A16 |
585 * +------------+------------------------+------------------------+
586 * | 39h | D16 | C16 |
587 * +------------+------------------------+------------------------+
588 * | 3Ah | F16 | C16 |
589 * +------------+------------------------+------------------------+
590 * | 3Bh | Reserved | G16 |
591 * +------------+------------------------+------------------------+
592 *
593 * To enable nearest-neighbor scaling: program scaler coefficents with
594 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
595 * SCALER_COEFFICIENT_FORMAT
596 *
597 */
598
599static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
600 enum pipe pipe, int id, int set)
601{
602 int i;
603
604 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
605 PS_COEF_INDEX_AUTO_INC);
606
607 for (i = 0; i < 17 * 7; i += 2) {
608 u32 tmp;
609 int t;
610
611 t = glk_coef_tap(i);
612 tmp = glk_nearest_filter_coef(t);
613
614 t = glk_coef_tap(i + 1);
615 tmp |= glk_nearest_filter_coef(t) << 16;
616
617 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
618 tmp);
619 }
620
621 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
622}
623
624static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
625{
626 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
627 return (PS_FILTER_PROGRAMMED |
628 PS_Y_VERT_FILTER_SELECT(set) |
629 PS_Y_HORZ_FILTER_SELECT(set) |
630 PS_UV_VERT_FILTER_SELECT(set) |
631 PS_UV_HORZ_FILTER_SELECT(set));
632 }
633
634 return PS_FILTER_MEDIUM;
635}
636
637static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
638 int id, int set, enum drm_scaling_filter filter)
639{
640 switch (filter) {
641 case DRM_SCALING_FILTER_DEFAULT:
642 break;
643 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
644 glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
645 break;
646 default:
647 MISSING_CASE(filter);
648 }
649}
650
651void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
652{
653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
654 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
655 const struct intel_crtc_scaler_state *scaler_state =
656 &crtc_state->scaler_state;
657 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
658 u16 uv_rgb_hphase, uv_rgb_vphase;
659 enum pipe pipe = crtc->pipe;
660 int width = drm_rect_width(dst);
661 int height = drm_rect_height(dst);
662 int x = dst->x1;
663 int y = dst->y1;
664 int hscale, vscale;
665 struct drm_rect src;
666 int id;
667 u32 ps_ctrl;
668
669 if (!crtc_state->pch_pfit.enabled)
670 return;
671
672 if (drm_WARN_ON(&dev_priv->drm,
673 crtc_state->scaler_state.scaler_id < 0))
674 return;
675
676 drm_rect_init(&src, 0, 0,
677 drm_rect_width(&crtc_state->pipe_src) << 16,
678 drm_rect_height(&crtc_state->pipe_src) << 16);
679
680 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
681 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
682
683 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
684 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
685
686 id = scaler_state->scaler_id;
687
688 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
689 skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
690
691 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
692 crtc_state->hw.scaling_filter);
693
694 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
695
696 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
697 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
698 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
699 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
700 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
701 PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
702 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
703 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
704}
705
706void
707skl_program_plane_scaler(struct intel_plane *plane,
708 const struct intel_crtc_state *crtc_state,
709 const struct intel_plane_state *plane_state)
710{
711 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
712 const struct drm_framebuffer *fb = plane_state->hw.fb;
713 enum pipe pipe = plane->pipe;
714 int scaler_id = plane_state->scaler_id;
715 const struct intel_scaler *scaler =
716 &crtc_state->scaler_state.scalers[scaler_id];
717 int crtc_x = plane_state->uapi.dst.x1;
718 int crtc_y = plane_state->uapi.dst.y1;
719 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
720 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
721 u16 y_hphase, uv_rgb_hphase;
722 u16 y_vphase, uv_rgb_vphase;
723 int hscale, vscale;
724 u32 ps_ctrl;
725
726 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
727 &plane_state->uapi.dst,
728 0, INT_MAX);
729 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
730 &plane_state->uapi.dst,
731 0, INT_MAX);
732
733 /* TODO: handle sub-pixel coordinates */
734 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
735 !icl_is_hdr_plane(dev_priv, plane->id)) {
736 y_hphase = skl_scaler_calc_phase(1, hscale, false);
737 y_vphase = skl_scaler_calc_phase(1, vscale, false);
738
739 /* MPEG2 chroma siting convention */
740 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
741 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
742 } else {
743 /* not used */
744 y_hphase = 0;
745 y_vphase = 0;
746
747 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
748 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
749 }
750
751 ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
752 skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
753
754 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
755 plane_state->hw.scaling_filter);
756
757 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
758 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
759 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
760 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
761 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
762 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
763 PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
764 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
765 PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
766}
767
768static void skl_detach_scaler(struct intel_crtc *crtc, int id)
769{
770 struct drm_device *dev = crtc->base.dev;
771 struct drm_i915_private *dev_priv = to_i915(dev);
772
773 intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
774 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
775 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
776}
777
778/*
779 * This function detaches (aka. unbinds) unused scalers in hardware
780 */
781void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
782{
783 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
784 const struct intel_crtc_scaler_state *scaler_state =
785 &crtc_state->scaler_state;
786 int i;
787
788 /* loop through and disable scalers that aren't in use */
789 for (i = 0; i < crtc->num_scalers; i++) {
790 if (!scaler_state->scalers[i].in_use)
791 skl_detach_scaler(crtc, i);
792 }
793}
794
795void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
796{
797 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
798 int i;
799
800 for (i = 0; i < crtc->num_scalers; i++)
801 skl_detach_scaler(crtc, i);
802}
803
804void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
805{
806 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
807 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
808 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
809 int id = -1;
810 int i;
811
812 /* find scaler attached to this pipe */
813 for (i = 0; i < crtc->num_scalers; i++) {
814 u32 ctl, pos, size;
815
816 ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
817 if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
818 continue;
819
820 id = i;
821 crtc_state->pch_pfit.enabled = true;
822
823 pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i));
824 size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
825
826 drm_rect_init(&crtc_state->pch_pfit.dst,
827 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
828 REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
829 REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
830 REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
831
832 scaler_state->scalers[i].in_use = true;
833 break;
834 }
835
836 scaler_state->scaler_id = id;
837 if (id >= 0)
838 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
839 else
840 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
841}