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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5#include "intel_de.h"
6#include "intel_display_types.h"
7#include "skl_scaler.h"
8#include "skl_universal_plane.h"
9
10/*
11 * The hardware phase 0.0 refers to the center of the pixel.
12 * We want to start from the top/left edge which is phase
13 * -0.5. That matches how the hardware calculates the scaling
14 * factors (from top-left of the first pixel to bottom-right
15 * of the last pixel, as opposed to the pixel centers).
16 *
17 * For 4:2:0 subsampled chroma planes we obviously have to
18 * adjust that so that the chroma sample position lands in
19 * the right spot.
20 *
21 * Note that for packed YCbCr 4:2:2 formats there is no way to
22 * control chroma siting. The hardware simply replicates the
23 * chroma samples for both of the luma samples, and thus we don't
24 * actually get the expected MPEG2 chroma siting convention :(
25 * The same behaviour is observed on pre-SKL platforms as well.
26 *
27 * Theory behind the formula (note that we ignore sub-pixel
28 * source coordinates):
29 * s = source sample position
30 * d = destination sample position
31 *
32 * Downscaling 4:1:
33 * -0.5
34 * | 0.0
35 * | | 1.5 (initial phase)
36 * | | |
37 * v v v
38 * | s | s | s | s |
39 * | d |
40 *
41 * Upscaling 1:4:
42 * -0.5
43 * | -0.375 (initial phase)
44 * | | 0.0
45 * | | |
46 * v v v
47 * | s |
48 * | d | d | d | d |
49 */
50static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
51{
52 int phase = -0x8000;
53 u16 trip = 0;
54
55 if (chroma_cosited)
56 phase += (sub - 1) * 0x8000 / sub;
57
58 phase += scale / (2 * sub);
59
60 /*
61 * Hardware initial phase limited to [-0.5:1.5].
62 * Since the max hardware scale factor is 3.0, we
63 * should never actually excdeed 1.0 here.
64 */
65 WARN_ON(phase < -0x8000 || phase > 0x18000);
66
67 if (phase < 0)
68 phase = 0x10000 + phase;
69 else
70 trip = PS_PHASE_TRIP;
71
72 return ((phase >> 2) & PS_PHASE_MASK) | trip;
73}
74
75#define SKL_MIN_SRC_W 8
76#define SKL_MAX_SRC_W 4096
77#define SKL_MIN_SRC_H 8
78#define SKL_MAX_SRC_H 4096
79#define SKL_MIN_DST_W 8
80#define SKL_MAX_DST_W 4096
81#define SKL_MIN_DST_H 8
82#define SKL_MAX_DST_H 4096
83#define ICL_MAX_SRC_W 5120
84#define ICL_MAX_SRC_H 4096
85#define ICL_MAX_DST_W 5120
86#define ICL_MAX_DST_H 4096
87#define SKL_MIN_YUV_420_SRC_W 16
88#define SKL_MIN_YUV_420_SRC_H 16
89
90static int
91skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
92 unsigned int scaler_user, int *scaler_id,
93 int src_w, int src_h, int dst_w, int dst_h,
94 const struct drm_format_info *format,
95 u64 modifier, bool need_scaler)
96{
97 struct intel_crtc_scaler_state *scaler_state =
98 &crtc_state->scaler_state;
99 struct intel_crtc *intel_crtc =
100 to_intel_crtc(crtc_state->uapi.crtc);
101 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
102 const struct drm_display_mode *adjusted_mode =
103 &crtc_state->hw.adjusted_mode;
104
105 /*
106 * Src coordinates are already rotated by 270 degrees for
107 * the 90/270 degree plane rotation cases (to match the
108 * GTT mapping), hence no need to account for rotation here.
109 */
110 if (src_w != dst_w || src_h != dst_h)
111 need_scaler = true;
112
113 /*
114 * Scaling/fitting not supported in IF-ID mode in GEN9+
115 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
116 * Once NV12 is enabled, handle it here while allocating scaler
117 * for NV12.
118 */
119 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
120 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
121 drm_dbg_kms(&dev_priv->drm,
122 "Pipe/Plane scaling not supported with IF-ID mode\n");
123 return -EINVAL;
124 }
125
126 /*
127 * if plane is being disabled or scaler is no more required or force detach
128 * - free scaler binded to this plane/crtc
129 * - in order to do this, update crtc->scaler_usage
130 *
131 * Here scaler state in crtc_state is set free so that
132 * scaler can be assigned to other user. Actual register
133 * update to free the scaler is done in plane/panel-fit programming.
134 * For this purpose crtc/plane_state->scaler_id isn't reset here.
135 */
136 if (force_detach || !need_scaler) {
137 if (*scaler_id >= 0) {
138 scaler_state->scaler_users &= ~(1 << scaler_user);
139 scaler_state->scalers[*scaler_id].in_use = 0;
140
141 drm_dbg_kms(&dev_priv->drm,
142 "scaler_user index %u.%u: "
143 "Staged freeing scaler id %d scaler_users = 0x%x\n",
144 intel_crtc->pipe, scaler_user, *scaler_id,
145 scaler_state->scaler_users);
146 *scaler_id = -1;
147 }
148 return 0;
149 }
150
151 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
152 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
153 drm_dbg_kms(&dev_priv->drm,
154 "Planar YUV: src dimensions not met\n");
155 return -EINVAL;
156 }
157
158 /* range checks */
159 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
160 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
161 (DISPLAY_VER(dev_priv) >= 11 &&
162 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
163 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
164 (DISPLAY_VER(dev_priv) < 11 &&
165 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
166 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
167 drm_dbg_kms(&dev_priv->drm,
168 "scaler_user index %u.%u: src %ux%u dst %ux%u "
169 "size is out of scaler range\n",
170 intel_crtc->pipe, scaler_user, src_w, src_h,
171 dst_w, dst_h);
172 return -EINVAL;
173 }
174
175 /* mark this plane as a scaler user in crtc_state */
176 scaler_state->scaler_users |= (1 << scaler_user);
177 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
178 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
179 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
180 scaler_state->scaler_users);
181
182 return 0;
183}
184
185int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
186{
187 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
188 int width, height;
189
190 if (crtc_state->pch_pfit.enabled) {
191 width = drm_rect_width(&crtc_state->pch_pfit.dst);
192 height = drm_rect_height(&crtc_state->pch_pfit.dst);
193 } else {
194 width = pipe_mode->crtc_hdisplay;
195 height = pipe_mode->crtc_vdisplay;
196 }
197 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
198 SKL_CRTC_INDEX,
199 &crtc_state->scaler_state.scaler_id,
200 crtc_state->pipe_src_w, crtc_state->pipe_src_h,
201 width, height, NULL, 0,
202 crtc_state->pch_pfit.enabled);
203}
204
205/**
206 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
207 * @crtc_state: crtc's scaler state
208 * @plane_state: atomic plane state to update
209 *
210 * Return
211 * 0 - scaler_usage updated successfully
212 * error - requested scaling cannot be supported or other error condition
213 */
214int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
215 struct intel_plane_state *plane_state)
216{
217 struct intel_plane *intel_plane =
218 to_intel_plane(plane_state->uapi.plane);
219 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
220 struct drm_framebuffer *fb = plane_state->hw.fb;
221 int ret;
222 bool force_detach = !fb || !plane_state->uapi.visible;
223 bool need_scaler = false;
224
225 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
226 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
227 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
228 need_scaler = true;
229
230 ret = skl_update_scaler(crtc_state, force_detach,
231 drm_plane_index(&intel_plane->base),
232 &plane_state->scaler_id,
233 drm_rect_width(&plane_state->uapi.src) >> 16,
234 drm_rect_height(&plane_state->uapi.src) >> 16,
235 drm_rect_width(&plane_state->uapi.dst),
236 drm_rect_height(&plane_state->uapi.dst),
237 fb ? fb->format : NULL,
238 fb ? fb->modifier : 0,
239 need_scaler);
240
241 if (ret || plane_state->scaler_id < 0)
242 return ret;
243
244 /* check colorkey */
245 if (plane_state->ckey.flags) {
246 drm_dbg_kms(&dev_priv->drm,
247 "[PLANE:%d:%s] scaling with color key not allowed",
248 intel_plane->base.base.id,
249 intel_plane->base.name);
250 return -EINVAL;
251 }
252
253 /* Check src format */
254 switch (fb->format->format) {
255 case DRM_FORMAT_RGB565:
256 case DRM_FORMAT_XBGR8888:
257 case DRM_FORMAT_XRGB8888:
258 case DRM_FORMAT_ABGR8888:
259 case DRM_FORMAT_ARGB8888:
260 case DRM_FORMAT_XRGB2101010:
261 case DRM_FORMAT_XBGR2101010:
262 case DRM_FORMAT_ARGB2101010:
263 case DRM_FORMAT_ABGR2101010:
264 case DRM_FORMAT_YUYV:
265 case DRM_FORMAT_YVYU:
266 case DRM_FORMAT_UYVY:
267 case DRM_FORMAT_VYUY:
268 case DRM_FORMAT_NV12:
269 case DRM_FORMAT_XYUV8888:
270 case DRM_FORMAT_P010:
271 case DRM_FORMAT_P012:
272 case DRM_FORMAT_P016:
273 case DRM_FORMAT_Y210:
274 case DRM_FORMAT_Y212:
275 case DRM_FORMAT_Y216:
276 case DRM_FORMAT_XVYU2101010:
277 case DRM_FORMAT_XVYU12_16161616:
278 case DRM_FORMAT_XVYU16161616:
279 break;
280 case DRM_FORMAT_XBGR16161616F:
281 case DRM_FORMAT_ABGR16161616F:
282 case DRM_FORMAT_XRGB16161616F:
283 case DRM_FORMAT_ARGB16161616F:
284 if (DISPLAY_VER(dev_priv) >= 11)
285 break;
286 fallthrough;
287 default:
288 drm_dbg_kms(&dev_priv->drm,
289 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
290 intel_plane->base.base.id, intel_plane->base.name,
291 fb->base.id, fb->format->format);
292 return -EINVAL;
293 }
294
295 return 0;
296}
297
298static int cnl_coef_tap(int i)
299{
300 return i % 7;
301}
302
303static u16 cnl_nearest_filter_coef(int t)
304{
305 return t == 3 ? 0x0800 : 0x3000;
306}
307
308/*
309 * Theory behind setting nearest-neighbor integer scaling:
310 *
311 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
312 * The letter represents the filter tap (D is the center tap) and the number
313 * represents the coefficient set for a phase (0-16).
314 *
315 * +------------+------------------------+------------------------+
316 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
317 * +------------+------------------------+------------------------+
318 * | 00h | B0 | A0 |
319 * +------------+------------------------+------------------------+
320 * | 01h | D0 | C0 |
321 * +------------+------------------------+------------------------+
322 * | 02h | F0 | E0 |
323 * +------------+------------------------+------------------------+
324 * | 03h | A1 | G0 |
325 * +------------+------------------------+------------------------+
326 * | 04h | C1 | B1 |
327 * +------------+------------------------+------------------------+
328 * | ... | ... | ... |
329 * +------------+------------------------+------------------------+
330 * | 38h | B16 | A16 |
331 * +------------+------------------------+------------------------+
332 * | 39h | D16 | C16 |
333 * +------------+------------------------+------------------------+
334 * | 3Ah | F16 | C16 |
335 * +------------+------------------------+------------------------+
336 * | 3Bh | Reserved | G16 |
337 * +------------+------------------------+------------------------+
338 *
339 * To enable nearest-neighbor scaling: program scaler coefficents with
340 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
341 * SCALER_COEFFICIENT_FORMAT
342 *
343 */
344
345static void cnl_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
346 enum pipe pipe, int id, int set)
347{
348 int i;
349
350 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set),
351 PS_COEE_INDEX_AUTO_INC);
352
353 for (i = 0; i < 17 * 7; i += 2) {
354 u32 tmp;
355 int t;
356
357 t = cnl_coef_tap(i);
358 tmp = cnl_nearest_filter_coef(t);
359
360 t = cnl_coef_tap(i + 1);
361 tmp |= cnl_nearest_filter_coef(t) << 16;
362
363 intel_de_write_fw(dev_priv, CNL_PS_COEF_DATA_SET(pipe, id, set),
364 tmp);
365 }
366
367 intel_de_write_fw(dev_priv, CNL_PS_COEF_INDEX_SET(pipe, id, set), 0);
368}
369
370static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
371{
372 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
373 return (PS_FILTER_PROGRAMMED |
374 PS_Y_VERT_FILTER_SELECT(set) |
375 PS_Y_HORZ_FILTER_SELECT(set) |
376 PS_UV_VERT_FILTER_SELECT(set) |
377 PS_UV_HORZ_FILTER_SELECT(set));
378 }
379
380 return PS_FILTER_MEDIUM;
381}
382
383static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
384 int id, int set, enum drm_scaling_filter filter)
385{
386 switch (filter) {
387 case DRM_SCALING_FILTER_DEFAULT:
388 break;
389 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
390 cnl_program_nearest_filter_coefs(dev_priv, pipe, id, set);
391 break;
392 default:
393 MISSING_CASE(filter);
394 }
395}
396
397void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
398{
399 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
400 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
401 const struct intel_crtc_scaler_state *scaler_state =
402 &crtc_state->scaler_state;
403 struct drm_rect src = {
404 .x2 = crtc_state->pipe_src_w << 16,
405 .y2 = crtc_state->pipe_src_h << 16,
406 };
407 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
408 u16 uv_rgb_hphase, uv_rgb_vphase;
409 enum pipe pipe = crtc->pipe;
410 int width = drm_rect_width(dst);
411 int height = drm_rect_height(dst);
412 int x = dst->x1;
413 int y = dst->y1;
414 int hscale, vscale;
415 unsigned long irqflags;
416 int id;
417 u32 ps_ctrl;
418
419 if (!crtc_state->pch_pfit.enabled)
420 return;
421
422 if (drm_WARN_ON(&dev_priv->drm,
423 crtc_state->scaler_state.scaler_id < 0))
424 return;
425
426 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
427 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
428
429 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
430 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
431
432 id = scaler_state->scaler_id;
433
434 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
435 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
436
437 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
438
439 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
440 crtc_state->hw.scaling_filter);
441
442 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
443
444 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
445 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
446 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
447 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
448 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
449 x << 16 | y);
450 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
451 width << 16 | height);
452
453 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
454}
455
456void
457skl_program_plane_scaler(struct intel_plane *plane,
458 const struct intel_crtc_state *crtc_state,
459 const struct intel_plane_state *plane_state)
460{
461 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
462 const struct drm_framebuffer *fb = plane_state->hw.fb;
463 enum pipe pipe = plane->pipe;
464 int scaler_id = plane_state->scaler_id;
465 const struct intel_scaler *scaler =
466 &crtc_state->scaler_state.scalers[scaler_id];
467 int crtc_x = plane_state->uapi.dst.x1;
468 int crtc_y = plane_state->uapi.dst.y1;
469 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
470 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
471 u16 y_hphase, uv_rgb_hphase;
472 u16 y_vphase, uv_rgb_vphase;
473 int hscale, vscale;
474 u32 ps_ctrl;
475
476 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
477 &plane_state->uapi.dst,
478 0, INT_MAX);
479 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
480 &plane_state->uapi.dst,
481 0, INT_MAX);
482
483 /* TODO: handle sub-pixel coordinates */
484 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
485 !icl_is_hdr_plane(dev_priv, plane->id)) {
486 y_hphase = skl_scaler_calc_phase(1, hscale, false);
487 y_vphase = skl_scaler_calc_phase(1, vscale, false);
488
489 /* MPEG2 chroma siting convention */
490 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
491 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
492 } else {
493 /* not used */
494 y_hphase = 0;
495 y_vphase = 0;
496
497 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
498 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
499 }
500
501 ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
502 ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
503
504 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
505 plane_state->hw.scaling_filter);
506
507 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
508 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
509 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
510 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
511 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
512 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
513 (crtc_x << 16) | crtc_y);
514 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
515 (crtc_w << 16) | crtc_h);
516}
517
518static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
519{
520 struct drm_device *dev = intel_crtc->base.dev;
521 struct drm_i915_private *dev_priv = to_i915(dev);
522 unsigned long irqflags;
523
524 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
525
526 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0);
527 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
528 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
529
530 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
531}
532
533/*
534 * This function detaches (aka. unbinds) unused scalers in hardware
535 */
536void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
537{
538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
539 const struct intel_crtc_scaler_state *scaler_state =
540 &crtc_state->scaler_state;
541 int i;
542
543 /* loop through and disable scalers that aren't in use */
544 for (i = 0; i < intel_crtc->num_scalers; i++) {
545 if (!scaler_state->scalers[i].in_use)
546 skl_detach_scaler(intel_crtc, i);
547 }
548}
549
550void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
551{
552 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
553 int i;
554
555 for (i = 0; i < crtc->num_scalers; i++)
556 skl_detach_scaler(crtc, i);
557}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5
6#include "i915_reg.h"
7#include "intel_de.h"
8#include "intel_display_types.h"
9#include "intel_fb.h"
10#include "skl_scaler.h"
11#include "skl_universal_plane.h"
12
13/*
14 * The hardware phase 0.0 refers to the center of the pixel.
15 * We want to start from the top/left edge which is phase
16 * -0.5. That matches how the hardware calculates the scaling
17 * factors (from top-left of the first pixel to bottom-right
18 * of the last pixel, as opposed to the pixel centers).
19 *
20 * For 4:2:0 subsampled chroma planes we obviously have to
21 * adjust that so that the chroma sample position lands in
22 * the right spot.
23 *
24 * Note that for packed YCbCr 4:2:2 formats there is no way to
25 * control chroma siting. The hardware simply replicates the
26 * chroma samples for both of the luma samples, and thus we don't
27 * actually get the expected MPEG2 chroma siting convention :(
28 * The same behaviour is observed on pre-SKL platforms as well.
29 *
30 * Theory behind the formula (note that we ignore sub-pixel
31 * source coordinates):
32 * s = source sample position
33 * d = destination sample position
34 *
35 * Downscaling 4:1:
36 * -0.5
37 * | 0.0
38 * | | 1.5 (initial phase)
39 * | | |
40 * v v v
41 * | s | s | s | s |
42 * | d |
43 *
44 * Upscaling 1:4:
45 * -0.5
46 * | -0.375 (initial phase)
47 * | | 0.0
48 * | | |
49 * v v v
50 * | s |
51 * | d | d | d | d |
52 */
53static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
54{
55 int phase = -0x8000;
56 u16 trip = 0;
57
58 if (chroma_cosited)
59 phase += (sub - 1) * 0x8000 / sub;
60
61 phase += scale / (2 * sub);
62
63 /*
64 * Hardware initial phase limited to [-0.5:1.5].
65 * Since the max hardware scale factor is 3.0, we
66 * should never actually excdeed 1.0 here.
67 */
68 WARN_ON(phase < -0x8000 || phase > 0x18000);
69
70 if (phase < 0)
71 phase = 0x10000 + phase;
72 else
73 trip = PS_PHASE_TRIP;
74
75 return ((phase >> 2) & PS_PHASE_MASK) | trip;
76}
77
78#define SKL_MIN_SRC_W 8
79#define SKL_MAX_SRC_W 4096
80#define SKL_MIN_SRC_H 8
81#define SKL_MAX_SRC_H 4096
82#define SKL_MIN_DST_W 8
83#define SKL_MAX_DST_W 4096
84#define SKL_MIN_DST_H 8
85#define SKL_MAX_DST_H 4096
86#define ICL_MAX_SRC_W 5120
87#define ICL_MAX_SRC_H 4096
88#define ICL_MAX_DST_W 5120
89#define ICL_MAX_DST_H 4096
90#define SKL_MIN_YUV_420_SRC_W 16
91#define SKL_MIN_YUV_420_SRC_H 16
92
93static int
94skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
95 unsigned int scaler_user, int *scaler_id,
96 int src_w, int src_h, int dst_w, int dst_h,
97 const struct drm_format_info *format,
98 u64 modifier, bool need_scaler)
99{
100 struct intel_crtc_scaler_state *scaler_state =
101 &crtc_state->scaler_state;
102 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
103 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
104 const struct drm_display_mode *adjusted_mode =
105 &crtc_state->hw.adjusted_mode;
106
107 /*
108 * Src coordinates are already rotated by 270 degrees for
109 * the 90/270 degree plane rotation cases (to match the
110 * GTT mapping), hence no need to account for rotation here.
111 */
112 if (src_w != dst_w || src_h != dst_h)
113 need_scaler = true;
114
115 /*
116 * Scaling/fitting not supported in IF-ID mode in GEN9+
117 * TODO: Interlace fetch mode doesn't support YUV420 planar formats.
118 * Once NV12 is enabled, handle it here while allocating scaler
119 * for NV12.
120 */
121 if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
122 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
123 drm_dbg_kms(&dev_priv->drm,
124 "Pipe/Plane scaling not supported with IF-ID mode\n");
125 return -EINVAL;
126 }
127
128 /*
129 * if plane is being disabled or scaler is no more required or force detach
130 * - free scaler binded to this plane/crtc
131 * - in order to do this, update crtc->scaler_usage
132 *
133 * Here scaler state in crtc_state is set free so that
134 * scaler can be assigned to other user. Actual register
135 * update to free the scaler is done in plane/panel-fit programming.
136 * For this purpose crtc/plane_state->scaler_id isn't reset here.
137 */
138 if (force_detach || !need_scaler) {
139 if (*scaler_id >= 0) {
140 scaler_state->scaler_users &= ~(1 << scaler_user);
141 scaler_state->scalers[*scaler_id].in_use = 0;
142
143 drm_dbg_kms(&dev_priv->drm,
144 "scaler_user index %u.%u: "
145 "Staged freeing scaler id %d scaler_users = 0x%x\n",
146 crtc->pipe, scaler_user, *scaler_id,
147 scaler_state->scaler_users);
148 *scaler_id = -1;
149 }
150 return 0;
151 }
152
153 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
154 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
155 drm_dbg_kms(&dev_priv->drm,
156 "Planar YUV: src dimensions not met\n");
157 return -EINVAL;
158 }
159
160 /* range checks */
161 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
162 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
163 (DISPLAY_VER(dev_priv) >= 11 &&
164 (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
165 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
166 (DISPLAY_VER(dev_priv) < 11 &&
167 (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
168 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
169 drm_dbg_kms(&dev_priv->drm,
170 "scaler_user index %u.%u: src %ux%u dst %ux%u "
171 "size is out of scaler range\n",
172 crtc->pipe, scaler_user, src_w, src_h,
173 dst_w, dst_h);
174 return -EINVAL;
175 }
176
177 /* mark this plane as a scaler user in crtc_state */
178 scaler_state->scaler_users |= (1 << scaler_user);
179 drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
180 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
181 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
182 scaler_state->scaler_users);
183
184 return 0;
185}
186
187int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
188{
189 const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
190 int width, height;
191
192 if (crtc_state->pch_pfit.enabled) {
193 width = drm_rect_width(&crtc_state->pch_pfit.dst);
194 height = drm_rect_height(&crtc_state->pch_pfit.dst);
195 } else {
196 width = pipe_mode->crtc_hdisplay;
197 height = pipe_mode->crtc_vdisplay;
198 }
199 return skl_update_scaler(crtc_state, !crtc_state->hw.active,
200 SKL_CRTC_INDEX,
201 &crtc_state->scaler_state.scaler_id,
202 drm_rect_width(&crtc_state->pipe_src),
203 drm_rect_height(&crtc_state->pipe_src),
204 width, height, NULL, 0,
205 crtc_state->pch_pfit.enabled);
206}
207
208/**
209 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
210 * @crtc_state: crtc's scaler state
211 * @plane_state: atomic plane state to update
212 *
213 * Return
214 * 0 - scaler_usage updated successfully
215 * error - requested scaling cannot be supported or other error condition
216 */
217int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
218 struct intel_plane_state *plane_state)
219{
220 struct intel_plane *intel_plane =
221 to_intel_plane(plane_state->uapi.plane);
222 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
223 struct drm_framebuffer *fb = plane_state->hw.fb;
224 int ret;
225 bool force_detach = !fb || !plane_state->uapi.visible;
226 bool need_scaler = false;
227
228 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */
229 if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
230 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
231 need_scaler = true;
232
233 ret = skl_update_scaler(crtc_state, force_detach,
234 drm_plane_index(&intel_plane->base),
235 &plane_state->scaler_id,
236 drm_rect_width(&plane_state->uapi.src) >> 16,
237 drm_rect_height(&plane_state->uapi.src) >> 16,
238 drm_rect_width(&plane_state->uapi.dst),
239 drm_rect_height(&plane_state->uapi.dst),
240 fb ? fb->format : NULL,
241 fb ? fb->modifier : 0,
242 need_scaler);
243
244 if (ret || plane_state->scaler_id < 0)
245 return ret;
246
247 /* check colorkey */
248 if (plane_state->ckey.flags) {
249 drm_dbg_kms(&dev_priv->drm,
250 "[PLANE:%d:%s] scaling with color key not allowed",
251 intel_plane->base.base.id,
252 intel_plane->base.name);
253 return -EINVAL;
254 }
255
256 /* Check src format */
257 switch (fb->format->format) {
258 case DRM_FORMAT_RGB565:
259 case DRM_FORMAT_XBGR8888:
260 case DRM_FORMAT_XRGB8888:
261 case DRM_FORMAT_ABGR8888:
262 case DRM_FORMAT_ARGB8888:
263 case DRM_FORMAT_XRGB2101010:
264 case DRM_FORMAT_XBGR2101010:
265 case DRM_FORMAT_ARGB2101010:
266 case DRM_FORMAT_ABGR2101010:
267 case DRM_FORMAT_YUYV:
268 case DRM_FORMAT_YVYU:
269 case DRM_FORMAT_UYVY:
270 case DRM_FORMAT_VYUY:
271 case DRM_FORMAT_NV12:
272 case DRM_FORMAT_XYUV8888:
273 case DRM_FORMAT_P010:
274 case DRM_FORMAT_P012:
275 case DRM_FORMAT_P016:
276 case DRM_FORMAT_Y210:
277 case DRM_FORMAT_Y212:
278 case DRM_FORMAT_Y216:
279 case DRM_FORMAT_XVYU2101010:
280 case DRM_FORMAT_XVYU12_16161616:
281 case DRM_FORMAT_XVYU16161616:
282 break;
283 case DRM_FORMAT_XBGR16161616F:
284 case DRM_FORMAT_ABGR16161616F:
285 case DRM_FORMAT_XRGB16161616F:
286 case DRM_FORMAT_ARGB16161616F:
287 if (DISPLAY_VER(dev_priv) >= 11)
288 break;
289 fallthrough;
290 default:
291 drm_dbg_kms(&dev_priv->drm,
292 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
293 intel_plane->base.base.id, intel_plane->base.name,
294 fb->base.id, fb->format->format);
295 return -EINVAL;
296 }
297
298 return 0;
299}
300
301static int glk_coef_tap(int i)
302{
303 return i % 7;
304}
305
306static u16 glk_nearest_filter_coef(int t)
307{
308 return t == 3 ? 0x0800 : 0x3000;
309}
310
311/*
312 * Theory behind setting nearest-neighbor integer scaling:
313 *
314 * 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
315 * The letter represents the filter tap (D is the center tap) and the number
316 * represents the coefficient set for a phase (0-16).
317 *
318 * +------------+------------------------+------------------------+
319 * |Index value | Data value coeffient 1 | Data value coeffient 2 |
320 * +------------+------------------------+------------------------+
321 * | 00h | B0 | A0 |
322 * +------------+------------------------+------------------------+
323 * | 01h | D0 | C0 |
324 * +------------+------------------------+------------------------+
325 * | 02h | F0 | E0 |
326 * +------------+------------------------+------------------------+
327 * | 03h | A1 | G0 |
328 * +------------+------------------------+------------------------+
329 * | 04h | C1 | B1 |
330 * +------------+------------------------+------------------------+
331 * | ... | ... | ... |
332 * +------------+------------------------+------------------------+
333 * | 38h | B16 | A16 |
334 * +------------+------------------------+------------------------+
335 * | 39h | D16 | C16 |
336 * +------------+------------------------+------------------------+
337 * | 3Ah | F16 | C16 |
338 * +------------+------------------------+------------------------+
339 * | 3Bh | Reserved | G16 |
340 * +------------+------------------------+------------------------+
341 *
342 * To enable nearest-neighbor scaling: program scaler coefficents with
343 * the center tap (Dxx) values set to 1 and all other values set to 0 as per
344 * SCALER_COEFFICIENT_FORMAT
345 *
346 */
347
348static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
349 enum pipe pipe, int id, int set)
350{
351 int i;
352
353 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
354 PS_COEE_INDEX_AUTO_INC);
355
356 for (i = 0; i < 17 * 7; i += 2) {
357 u32 tmp;
358 int t;
359
360 t = glk_coef_tap(i);
361 tmp = glk_nearest_filter_coef(t);
362
363 t = glk_coef_tap(i + 1);
364 tmp |= glk_nearest_filter_coef(t) << 16;
365
366 intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
367 tmp);
368 }
369
370 intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
371}
372
373static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
374{
375 if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
376 return (PS_FILTER_PROGRAMMED |
377 PS_Y_VERT_FILTER_SELECT(set) |
378 PS_Y_HORZ_FILTER_SELECT(set) |
379 PS_UV_VERT_FILTER_SELECT(set) |
380 PS_UV_HORZ_FILTER_SELECT(set));
381 }
382
383 return PS_FILTER_MEDIUM;
384}
385
386static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
387 int id, int set, enum drm_scaling_filter filter)
388{
389 switch (filter) {
390 case DRM_SCALING_FILTER_DEFAULT:
391 break;
392 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
393 glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
394 break;
395 default:
396 MISSING_CASE(filter);
397 }
398}
399
400void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
401{
402 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
404 const struct intel_crtc_scaler_state *scaler_state =
405 &crtc_state->scaler_state;
406 const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
407 u16 uv_rgb_hphase, uv_rgb_vphase;
408 enum pipe pipe = crtc->pipe;
409 int width = drm_rect_width(dst);
410 int height = drm_rect_height(dst);
411 int x = dst->x1;
412 int y = dst->y1;
413 int hscale, vscale;
414 struct drm_rect src;
415 int id;
416 u32 ps_ctrl;
417
418 if (!crtc_state->pch_pfit.enabled)
419 return;
420
421 if (drm_WARN_ON(&dev_priv->drm,
422 crtc_state->scaler_state.scaler_id < 0))
423 return;
424
425 drm_rect_init(&src, 0, 0,
426 drm_rect_width(&crtc_state->pipe_src) << 16,
427 drm_rect_height(&crtc_state->pipe_src) << 16);
428
429 hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
430 vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
431
432 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
433 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
434
435 id = scaler_state->scaler_id;
436
437 ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
438 ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
439
440 skl_scaler_setup_filter(dev_priv, pipe, id, 0,
441 crtc_state->hw.scaling_filter);
442
443 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
444
445 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
446 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
447 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
448 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
449 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
450 x << 16 | y);
451 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
452 width << 16 | height);
453}
454
455void
456skl_program_plane_scaler(struct intel_plane *plane,
457 const struct intel_crtc_state *crtc_state,
458 const struct intel_plane_state *plane_state)
459{
460 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
461 const struct drm_framebuffer *fb = plane_state->hw.fb;
462 enum pipe pipe = plane->pipe;
463 int scaler_id = plane_state->scaler_id;
464 const struct intel_scaler *scaler =
465 &crtc_state->scaler_state.scalers[scaler_id];
466 int crtc_x = plane_state->uapi.dst.x1;
467 int crtc_y = plane_state->uapi.dst.y1;
468 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
469 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
470 u16 y_hphase, uv_rgb_hphase;
471 u16 y_vphase, uv_rgb_vphase;
472 int hscale, vscale;
473 u32 ps_ctrl;
474
475 hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
476 &plane_state->uapi.dst,
477 0, INT_MAX);
478 vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
479 &plane_state->uapi.dst,
480 0, INT_MAX);
481
482 /* TODO: handle sub-pixel coordinates */
483 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
484 !icl_is_hdr_plane(dev_priv, plane->id)) {
485 y_hphase = skl_scaler_calc_phase(1, hscale, false);
486 y_vphase = skl_scaler_calc_phase(1, vscale, false);
487
488 /* MPEG2 chroma siting convention */
489 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
490 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
491 } else {
492 /* not used */
493 y_hphase = 0;
494 y_vphase = 0;
495
496 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
497 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
498 }
499
500 ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
501 ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
502
503 skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
504 plane_state->hw.scaling_filter);
505
506 intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
507 intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
508 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
509 intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
510 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
511 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
512 (crtc_x << 16) | crtc_y);
513 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
514 (crtc_w << 16) | crtc_h);
515}
516
517static void skl_detach_scaler(struct intel_crtc *crtc, int id)
518{
519 struct drm_device *dev = crtc->base.dev;
520 struct drm_i915_private *dev_priv = to_i915(dev);
521
522 intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
523 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
524 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
525}
526
527/*
528 * This function detaches (aka. unbinds) unused scalers in hardware
529 */
530void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
531{
532 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
533 const struct intel_crtc_scaler_state *scaler_state =
534 &crtc_state->scaler_state;
535 int i;
536
537 /* loop through and disable scalers that aren't in use */
538 for (i = 0; i < crtc->num_scalers; i++) {
539 if (!scaler_state->scalers[i].in_use)
540 skl_detach_scaler(crtc, i);
541 }
542}
543
544void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
545{
546 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
547 int i;
548
549 for (i = 0; i < crtc->num_scalers; i++)
550 skl_detach_scaler(crtc, i);
551}