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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/isa-rev.h>
20#include <asm/war.h>
21
22/*
23 * The following macros are especially useful for __asm__
24 * inline assembler.
25 */
26#ifndef __STR
27#define __STR(x) #x
28#endif
29#ifndef STR
30#define STR(x) __STR(x)
31#endif
32
33/*
34 * Configure language
35 */
36#ifdef __ASSEMBLY__
37#define _ULCAST_
38#define _U64CAST_
39#else
40#define _ULCAST_ (unsigned long)
41#define _U64CAST_ (u64)
42#endif
43
44/*
45 * Coprocessor 0 register names
46 */
47#define CP0_INDEX $0
48#define CP0_RANDOM $1
49#define CP0_ENTRYLO0 $2
50#define CP0_ENTRYLO1 $3
51#define CP0_CONF $3
52#define CP0_GLOBALNUMBER $3, 1
53#define CP0_CONTEXT $4
54#define CP0_PAGEMASK $5
55#define CP0_PAGEGRAIN $5, 1
56#define CP0_SEGCTL0 $5, 2
57#define CP0_SEGCTL1 $5, 3
58#define CP0_SEGCTL2 $5, 4
59#define CP0_WIRED $6
60#define CP0_INFO $7
61#define CP0_HWRENA $7
62#define CP0_BADVADDR $8
63#define CP0_BADINSTR $8, 1
64#define CP0_COUNT $9
65#define CP0_ENTRYHI $10
66#define CP0_GUESTCTL1 $10, 4
67#define CP0_GUESTCTL2 $10, 5
68#define CP0_GUESTCTL3 $10, 6
69#define CP0_COMPARE $11
70#define CP0_GUESTCTL0EXT $11, 4
71#define CP0_STATUS $12
72#define CP0_GUESTCTL0 $12, 6
73#define CP0_GTOFFSET $12, 7
74#define CP0_CAUSE $13
75#define CP0_EPC $14
76#define CP0_PRID $15
77#define CP0_EBASE $15, 1
78#define CP0_CMGCRBASE $15, 3
79#define CP0_CONFIG $16
80#define CP0_CONFIG3 $16, 3
81#define CP0_CONFIG5 $16, 5
82#define CP0_CONFIG6 $16, 6
83#define CP0_LLADDR $17
84#define CP0_WATCHLO $18
85#define CP0_WATCHHI $19
86#define CP0_XCONTEXT $20
87#define CP0_FRAMEMASK $21
88#define CP0_DIAGNOSTIC $22
89#define CP0_DIAGNOSTIC1 $22, 1
90#define CP0_DEBUG $23
91#define CP0_DEPC $24
92#define CP0_PERFORMANCE $25
93#define CP0_ECC $26
94#define CP0_CACHEERR $27
95#define CP0_TAGLO $28
96#define CP0_TAGHI $29
97#define CP0_ERROREPC $30
98#define CP0_DESAVE $31
99
100/*
101 * R4640/R4650 cp0 register names. These registers are listed
102 * here only for completeness; without MMU these CPUs are not useable
103 * by Linux. A future ELKS port might take make Linux run on them
104 * though ...
105 */
106#define CP0_IBASE $0
107#define CP0_IBOUND $1
108#define CP0_DBASE $2
109#define CP0_DBOUND $3
110#define CP0_CALG $17
111#define CP0_IWATCH $18
112#define CP0_DWATCH $19
113
114/*
115 * Coprocessor 0 Set 1 register names
116 */
117#define CP0_S1_DERRADDR0 $26
118#define CP0_S1_DERRADDR1 $27
119#define CP0_S1_INTCONTROL $20
120
121/*
122 * Coprocessor 0 Set 2 register names
123 */
124#define CP0_S2_SRSCTL $12 /* MIPSR2 */
125
126/*
127 * Coprocessor 0 Set 3 register names
128 */
129#define CP0_S3_SRSMAP $12 /* MIPSR2 */
130
131/*
132 * TX39 Series
133 */
134#define CP0_TX39_CACHE $7
135
136
137/* Generic EntryLo bit definitions */
138#define ENTRYLO_G (_ULCAST_(1) << 0)
139#define ENTRYLO_V (_ULCAST_(1) << 1)
140#define ENTRYLO_D (_ULCAST_(1) << 2)
141#define ENTRYLO_C_SHIFT 3
142#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
143
144/* R3000 EntryLo bit definitions */
145#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
146#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
147#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
148#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
149
150/* MIPS32/64 EntryLo bit definitions */
151#define MIPS_ENTRYLO_PFN_SHIFT 6
152#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
153#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
154
155/*
156 * MIPSr6+ GlobalNumber register definitions
157 */
158#define MIPS_GLOBALNUMBER_VP_SHF 0
159#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
160#define MIPS_GLOBALNUMBER_CORE_SHF 8
161#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
162#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
163#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
164
165/*
166 * Values for PageMask register
167 */
168#ifdef CONFIG_CPU_VR41XX
169
170/* Why doesn't stupidity hurt ... */
171
172#define PM_1K 0x00000000
173#define PM_4K 0x00001800
174#define PM_16K 0x00007800
175#define PM_64K 0x0001f800
176#define PM_256K 0x0007f800
177
178#else
179
180#define PM_4K 0x00000000
181#define PM_8K 0x00002000
182#define PM_16K 0x00006000
183#define PM_32K 0x0000e000
184#define PM_64K 0x0001e000
185#define PM_128K 0x0003e000
186#define PM_256K 0x0007e000
187#define PM_512K 0x000fe000
188#define PM_1M 0x001fe000
189#define PM_2M 0x003fe000
190#define PM_4M 0x007fe000
191#define PM_8M 0x00ffe000
192#define PM_16M 0x01ffe000
193#define PM_32M 0x03ffe000
194#define PM_64M 0x07ffe000
195#define PM_256M 0x1fffe000
196#define PM_1G 0x7fffe000
197
198#endif
199
200/*
201 * Default page size for a given kernel configuration
202 */
203#ifdef CONFIG_PAGE_SIZE_4KB
204#define PM_DEFAULT_MASK PM_4K
205#elif defined(CONFIG_PAGE_SIZE_8KB)
206#define PM_DEFAULT_MASK PM_8K
207#elif defined(CONFIG_PAGE_SIZE_16KB)
208#define PM_DEFAULT_MASK PM_16K
209#elif defined(CONFIG_PAGE_SIZE_32KB)
210#define PM_DEFAULT_MASK PM_32K
211#elif defined(CONFIG_PAGE_SIZE_64KB)
212#define PM_DEFAULT_MASK PM_64K
213#else
214#error Bad page size configuration!
215#endif
216
217/*
218 * Default huge tlb size for a given kernel configuration
219 */
220#ifdef CONFIG_PAGE_SIZE_4KB
221#define PM_HUGE_MASK PM_1M
222#elif defined(CONFIG_PAGE_SIZE_8KB)
223#define PM_HUGE_MASK PM_4M
224#elif defined(CONFIG_PAGE_SIZE_16KB)
225#define PM_HUGE_MASK PM_16M
226#elif defined(CONFIG_PAGE_SIZE_32KB)
227#define PM_HUGE_MASK PM_64M
228#elif defined(CONFIG_PAGE_SIZE_64KB)
229#define PM_HUGE_MASK PM_256M
230#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
231#error Bad page size configuration for hugetlbfs!
232#endif
233
234/*
235 * Wired register bits
236 */
237#define MIPSR6_WIRED_LIMIT_SHIFT 16
238#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
239#define MIPSR6_WIRED_WIRED_SHIFT 0
240#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
241
242/*
243 * Values used for computation of new tlb entries
244 */
245#define PL_4K 12
246#define PL_16K 14
247#define PL_64K 16
248#define PL_256K 18
249#define PL_1M 20
250#define PL_4M 22
251#define PL_16M 24
252#define PL_64M 26
253#define PL_256M 28
254
255/*
256 * PageGrain bits
257 */
258#define PG_RIE (_ULCAST_(1) << 31)
259#define PG_XIE (_ULCAST_(1) << 30)
260#define PG_ELPA (_ULCAST_(1) << 29)
261#define PG_ESP (_ULCAST_(1) << 28)
262#define PG_IEC (_ULCAST_(1) << 27)
263
264/* MIPS32/64 EntryHI bit definitions */
265#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
266#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
267#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
268
269/*
270 * R4x00 interrupt enable / cause bits
271 */
272#define IE_SW0 (_ULCAST_(1) << 8)
273#define IE_SW1 (_ULCAST_(1) << 9)
274#define IE_IRQ0 (_ULCAST_(1) << 10)
275#define IE_IRQ1 (_ULCAST_(1) << 11)
276#define IE_IRQ2 (_ULCAST_(1) << 12)
277#define IE_IRQ3 (_ULCAST_(1) << 13)
278#define IE_IRQ4 (_ULCAST_(1) << 14)
279#define IE_IRQ5 (_ULCAST_(1) << 15)
280
281/*
282 * R4x00 interrupt cause bits
283 */
284#define C_SW0 (_ULCAST_(1) << 8)
285#define C_SW1 (_ULCAST_(1) << 9)
286#define C_IRQ0 (_ULCAST_(1) << 10)
287#define C_IRQ1 (_ULCAST_(1) << 11)
288#define C_IRQ2 (_ULCAST_(1) << 12)
289#define C_IRQ3 (_ULCAST_(1) << 13)
290#define C_IRQ4 (_ULCAST_(1) << 14)
291#define C_IRQ5 (_ULCAST_(1) << 15)
292
293/*
294 * Bitfields in the R4xx0 cp0 status register
295 */
296#define ST0_IE 0x00000001
297#define ST0_EXL 0x00000002
298#define ST0_ERL 0x00000004
299#define ST0_KSU 0x00000018
300# define KSU_USER 0x00000010
301# define KSU_SUPERVISOR 0x00000008
302# define KSU_KERNEL 0x00000000
303#define ST0_UX 0x00000020
304#define ST0_SX 0x00000040
305#define ST0_KX 0x00000080
306#define ST0_DE 0x00010000
307#define ST0_CE 0x00020000
308
309/*
310 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
311 * cacheops in userspace. This bit exists only on RM7000 and RM9000
312 * processors.
313 */
314#define ST0_CO 0x08000000
315
316/*
317 * Bitfields in the R[23]000 cp0 status register.
318 */
319#define ST0_IEC 0x00000001
320#define ST0_KUC 0x00000002
321#define ST0_IEP 0x00000004
322#define ST0_KUP 0x00000008
323#define ST0_IEO 0x00000010
324#define ST0_KUO 0x00000020
325/* bits 6 & 7 are reserved on R[23]000 */
326#define ST0_ISC 0x00010000
327#define ST0_SWC 0x00020000
328#define ST0_CM 0x00080000
329
330/*
331 * Bits specific to the R4640/R4650
332 */
333#define ST0_UM (_ULCAST_(1) << 4)
334#define ST0_IL (_ULCAST_(1) << 23)
335#define ST0_DL (_ULCAST_(1) << 24)
336
337/*
338 * Enable the MIPS MDMX and DSP ASEs
339 */
340#define ST0_MX 0x01000000
341
342/*
343 * Status register bits available in all MIPS CPUs.
344 */
345#define ST0_IM 0x0000ff00
346#define STATUSB_IP0 8
347#define STATUSF_IP0 (_ULCAST_(1) << 8)
348#define STATUSB_IP1 9
349#define STATUSF_IP1 (_ULCAST_(1) << 9)
350#define STATUSB_IP2 10
351#define STATUSF_IP2 (_ULCAST_(1) << 10)
352#define STATUSB_IP3 11
353#define STATUSF_IP3 (_ULCAST_(1) << 11)
354#define STATUSB_IP4 12
355#define STATUSF_IP4 (_ULCAST_(1) << 12)
356#define STATUSB_IP5 13
357#define STATUSF_IP5 (_ULCAST_(1) << 13)
358#define STATUSB_IP6 14
359#define STATUSF_IP6 (_ULCAST_(1) << 14)
360#define STATUSB_IP7 15
361#define STATUSF_IP7 (_ULCAST_(1) << 15)
362#define STATUSB_IP8 0
363#define STATUSF_IP8 (_ULCAST_(1) << 0)
364#define STATUSB_IP9 1
365#define STATUSF_IP9 (_ULCAST_(1) << 1)
366#define STATUSB_IP10 2
367#define STATUSF_IP10 (_ULCAST_(1) << 2)
368#define STATUSB_IP11 3
369#define STATUSF_IP11 (_ULCAST_(1) << 3)
370#define STATUSB_IP12 4
371#define STATUSF_IP12 (_ULCAST_(1) << 4)
372#define STATUSB_IP13 5
373#define STATUSF_IP13 (_ULCAST_(1) << 5)
374#define STATUSB_IP14 6
375#define STATUSF_IP14 (_ULCAST_(1) << 6)
376#define STATUSB_IP15 7
377#define STATUSF_IP15 (_ULCAST_(1) << 7)
378#define ST0_CH 0x00040000
379#define ST0_NMI 0x00080000
380#define ST0_SR 0x00100000
381#define ST0_TS 0x00200000
382#define ST0_BEV 0x00400000
383#define ST0_RE 0x02000000
384#define ST0_FR 0x04000000
385#define ST0_CU 0xf0000000
386#define ST0_CU0 0x10000000
387#define ST0_CU1 0x20000000
388#define ST0_CU2 0x40000000
389#define ST0_CU3 0x80000000
390#define ST0_XX 0x80000000 /* MIPS IV naming */
391
392/* in-kernel enabled CUs */
393#ifdef CONFIG_CPU_LOONGSON64
394#define ST0_KERNEL_CUMASK (ST0_CU0 | ST0_CU2)
395#else
396#define ST0_KERNEL_CUMASK ST0_CU0
397#endif
398
399/*
400 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
401 */
402#define INTCTLB_IPFDC 23
403#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
404#define INTCTLB_IPPCI 26
405#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
406#define INTCTLB_IPTI 29
407#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
408
409/*
410 * Bitfields and bit numbers in the coprocessor 0 cause register.
411 *
412 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
413 */
414#define CAUSEB_EXCCODE 2
415#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
416#define CAUSEB_IP 8
417#define CAUSEF_IP (_ULCAST_(255) << 8)
418#define CAUSEB_IP0 8
419#define CAUSEF_IP0 (_ULCAST_(1) << 8)
420#define CAUSEB_IP1 9
421#define CAUSEF_IP1 (_ULCAST_(1) << 9)
422#define CAUSEB_IP2 10
423#define CAUSEF_IP2 (_ULCAST_(1) << 10)
424#define CAUSEB_IP3 11
425#define CAUSEF_IP3 (_ULCAST_(1) << 11)
426#define CAUSEB_IP4 12
427#define CAUSEF_IP4 (_ULCAST_(1) << 12)
428#define CAUSEB_IP5 13
429#define CAUSEF_IP5 (_ULCAST_(1) << 13)
430#define CAUSEB_IP6 14
431#define CAUSEF_IP6 (_ULCAST_(1) << 14)
432#define CAUSEB_IP7 15
433#define CAUSEF_IP7 (_ULCAST_(1) << 15)
434#define CAUSEB_FDCI 21
435#define CAUSEF_FDCI (_ULCAST_(1) << 21)
436#define CAUSEB_WP 22
437#define CAUSEF_WP (_ULCAST_(1) << 22)
438#define CAUSEB_IV 23
439#define CAUSEF_IV (_ULCAST_(1) << 23)
440#define CAUSEB_PCI 26
441#define CAUSEF_PCI (_ULCAST_(1) << 26)
442#define CAUSEB_DC 27
443#define CAUSEF_DC (_ULCAST_(1) << 27)
444#define CAUSEB_CE 28
445#define CAUSEF_CE (_ULCAST_(3) << 28)
446#define CAUSEB_TI 30
447#define CAUSEF_TI (_ULCAST_(1) << 30)
448#define CAUSEB_BD 31
449#define CAUSEF_BD (_ULCAST_(1) << 31)
450
451/*
452 * Cause.ExcCode trap codes.
453 */
454#define EXCCODE_INT 0 /* Interrupt pending */
455#define EXCCODE_MOD 1 /* TLB modified fault */
456#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
457#define EXCCODE_TLBS 3 /* TLB miss on a store */
458#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
459#define EXCCODE_ADES 5 /* Address error on a store */
460#define EXCCODE_IBE 6 /* Bus error on an ifetch */
461#define EXCCODE_DBE 7 /* Bus error on a load or store */
462#define EXCCODE_SYS 8 /* System call */
463#define EXCCODE_BP 9 /* Breakpoint */
464#define EXCCODE_RI 10 /* Reserved instruction exception */
465#define EXCCODE_CPU 11 /* Coprocessor unusable */
466#define EXCCODE_OV 12 /* Arithmetic overflow */
467#define EXCCODE_TR 13 /* Trap instruction */
468#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
469#define EXCCODE_FPE 15 /* Floating point exception */
470#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
471#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
472#define EXCCODE_MSADIS 21 /* MSA disabled exception */
473#define EXCCODE_MDMX 22 /* MDMX unusable exception */
474#define EXCCODE_WATCH 23 /* Watch address reference */
475#define EXCCODE_MCHECK 24 /* Machine check */
476#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
477#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
478#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
479#define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
480
481/* Implementation specific trap codes used by MIPS cores */
482#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
483
484/* Implementation specific trap codes used by Loongson cores */
485#define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
486
487/*
488 * Bits in the coprocessor 0 config register.
489 */
490/* Generic bits. */
491#define CONF_CM_CACHABLE_NO_WA 0
492#define CONF_CM_CACHABLE_WA 1
493#define CONF_CM_UNCACHED 2
494#define CONF_CM_CACHABLE_NONCOHERENT 3
495#define CONF_CM_CACHABLE_CE 4
496#define CONF_CM_CACHABLE_COW 5
497#define CONF_CM_CACHABLE_CUW 6
498#define CONF_CM_CACHABLE_ACCELERATED 7
499#define CONF_CM_CMASK 7
500#define CONF_BE (_ULCAST_(1) << 15)
501
502/* Bits common to various processors. */
503#define CONF_CU (_ULCAST_(1) << 3)
504#define CONF_DB (_ULCAST_(1) << 4)
505#define CONF_IB (_ULCAST_(1) << 5)
506#define CONF_DC (_ULCAST_(7) << 6)
507#define CONF_IC (_ULCAST_(7) << 9)
508#define CONF_EB (_ULCAST_(1) << 13)
509#define CONF_EM (_ULCAST_(1) << 14)
510#define CONF_SM (_ULCAST_(1) << 16)
511#define CONF_SC (_ULCAST_(1) << 17)
512#define CONF_EW (_ULCAST_(3) << 18)
513#define CONF_EP (_ULCAST_(15)<< 24)
514#define CONF_EC (_ULCAST_(7) << 28)
515#define CONF_CM (_ULCAST_(1) << 31)
516
517/* Bits specific to the R4xx0. */
518#define R4K_CONF_SW (_ULCAST_(1) << 20)
519#define R4K_CONF_SS (_ULCAST_(1) << 21)
520#define R4K_CONF_SB (_ULCAST_(3) << 22)
521
522/* Bits specific to the R5000. */
523#define R5K_CONF_SE (_ULCAST_(1) << 12)
524#define R5K_CONF_SS (_ULCAST_(3) << 20)
525
526/* Bits specific to the RM7000. */
527#define RM7K_CONF_SE (_ULCAST_(1) << 3)
528#define RM7K_CONF_TE (_ULCAST_(1) << 12)
529#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
530#define RM7K_CONF_TC (_ULCAST_(1) << 17)
531#define RM7K_CONF_SI (_ULCAST_(3) << 20)
532#define RM7K_CONF_SC (_ULCAST_(1) << 31)
533
534/* Bits specific to the R10000. */
535#define R10K_CONF_DN (_ULCAST_(3) << 3)
536#define R10K_CONF_CT (_ULCAST_(1) << 5)
537#define R10K_CONF_PE (_ULCAST_(1) << 6)
538#define R10K_CONF_PM (_ULCAST_(3) << 7)
539#define R10K_CONF_EC (_ULCAST_(15)<< 9)
540#define R10K_CONF_SB (_ULCAST_(1) << 13)
541#define R10K_CONF_SK (_ULCAST_(1) << 14)
542#define R10K_CONF_SS (_ULCAST_(7) << 16)
543#define R10K_CONF_SC (_ULCAST_(7) << 19)
544#define R10K_CONF_DC (_ULCAST_(7) << 26)
545#define R10K_CONF_IC (_ULCAST_(7) << 29)
546
547/* Bits specific to the VR41xx. */
548#define VR41_CONF_CS (_ULCAST_(1) << 12)
549#define VR41_CONF_P4K (_ULCAST_(1) << 13)
550#define VR41_CONF_BP (_ULCAST_(1) << 16)
551#define VR41_CONF_M16 (_ULCAST_(1) << 20)
552#define VR41_CONF_AD (_ULCAST_(1) << 23)
553
554/* Bits specific to the R30xx. */
555#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
556#define R30XX_CONF_REV (_ULCAST_(1) << 22)
557#define R30XX_CONF_AC (_ULCAST_(1) << 23)
558#define R30XX_CONF_RF (_ULCAST_(1) << 24)
559#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
560#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
561#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
562#define R30XX_CONF_SB (_ULCAST_(1) << 30)
563#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
564
565/* Bits specific to the TX49. */
566#define TX49_CONF_DC (_ULCAST_(1) << 16)
567#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
568#define TX49_CONF_HALT (_ULCAST_(1) << 18)
569#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
570
571/* Bits specific to the MIPS32/64 PRA. */
572#define MIPS_CONF_VI (_ULCAST_(1) << 3)
573#define MIPS_CONF_MT (_ULCAST_(7) << 7)
574#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
575#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
576#define MIPS_CONF_AR (_ULCAST_(7) << 10)
577#define MIPS_CONF_AT (_ULCAST_(3) << 13)
578#define MIPS_CONF_BE (_ULCAST_(1) << 15)
579#define MIPS_CONF_BM (_ULCAST_(1) << 16)
580#define MIPS_CONF_MM (_ULCAST_(3) << 17)
581#define MIPS_CONF_MM_SYSAD (_ULCAST_(1) << 17)
582#define MIPS_CONF_MM_FULL (_ULCAST_(2) << 17)
583#define MIPS_CONF_SB (_ULCAST_(1) << 21)
584#define MIPS_CONF_UDI (_ULCAST_(1) << 22)
585#define MIPS_CONF_DSP (_ULCAST_(1) << 23)
586#define MIPS_CONF_ISP (_ULCAST_(1) << 24)
587#define MIPS_CONF_KU (_ULCAST_(3) << 25)
588#define MIPS_CONF_K23 (_ULCAST_(3) << 28)
589#define MIPS_CONF_M (_ULCAST_(1) << 31)
590
591/*
592 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
593 */
594#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
595#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
596#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
597#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
598#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
599#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
600#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
601#define MIPS_CONF1_DA_SHF 7
602#define MIPS_CONF1_DA_SZ 3
603#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
604#define MIPS_CONF1_DL_SHF 10
605#define MIPS_CONF1_DL_SZ 3
606#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
607#define MIPS_CONF1_DS_SHF 13
608#define MIPS_CONF1_DS_SZ 3
609#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
610#define MIPS_CONF1_IA_SHF 16
611#define MIPS_CONF1_IA_SZ 3
612#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
613#define MIPS_CONF1_IL_SHF 19
614#define MIPS_CONF1_IL_SZ 3
615#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
616#define MIPS_CONF1_IS_SHF 22
617#define MIPS_CONF1_IS_SZ 3
618#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
619#define MIPS_CONF1_TLBS_SHIFT (25)
620#define MIPS_CONF1_TLBS_SIZE (6)
621#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
622
623#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
624#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
625#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
626#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
627#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
628#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
629#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
630#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
631
632#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
633#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
634#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
635#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
636#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
637#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
638#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
639#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
640#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
641#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
642#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
643#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
644#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
645#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
646#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
647#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
648#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
649#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
650#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
651#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
652#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
653#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
654#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
655#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
656#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
657#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
658#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
659
660#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
661#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
662#define MIPS_CONF4_FTLBSETS_SHIFT (0)
663#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
664#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
665#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
666#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
667/* bits 10:8 in FTLB-only configurations */
668#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
669/* bits 12:8 in VTLB-FTLB only configurations */
670#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
671#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
672#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
673#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
674#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
675#define MIPS_CONF4_KSCREXIST_SHIFT (16)
676#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
677#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
678#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
679#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
680#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
681#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
682
683#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
684#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
685#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
686#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
687#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
688#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
689#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
690#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
691#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
692#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
693#define MIPS_CONF5_MI (_ULCAST_(1) << 17)
694#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
695#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
696#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
697#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
698#define MIPS_CONF5_K (_ULCAST_(1) << 30)
699
700/* Config6 feature bits for proAptiv/P5600 */
701
702/* Jump register cache prediction disable */
703#define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
704/* MIPSr6 extensions enable */
705#define MTI_CONF6_R6 (_ULCAST_(1) << 2)
706/* IFU Performance Control */
707#define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
708#define MTI_CONF6_SYND (_ULCAST_(1) << 13)
709/* Sleep state performance counter disable */
710#define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
711/* proAptiv FTLB on/off bit */
712#define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
713/* Disable load/store bonding */
714#define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
715/* FTLB probability bits */
716#define MTI_CONF6_FTLBP_SHIFT (16)
717
718/* Config6 feature bits for Loongson-3 */
719
720/* Loongson-3 internal timer bit */
721#define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
722/* Loongson-3 external timer bit */
723#define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
724/* Loongson-3 SFB on/off bit, STFill in manual */
725#define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
726/* Loongson-3's LL on exclusive cacheline */
727#define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
728/* Loongson-3's SC has a random delay */
729#define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
730/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
731#define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
732
733#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
734
735#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
736
737#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
738#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
739
740/* Ingenic HPTLB off bits */
741#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
742
743/* Ingenic Config7 bits */
744#define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
745
746/* Config7 Bits specific to MIPS Technologies. */
747
748/* Performance counters implemented Per TC */
749#define MTI_CONF7_PTC (_ULCAST_(1) << 19)
750
751/* WatchLo* register definitions */
752#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
753
754/* WatchHi* register definitions */
755#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
756#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
757#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
758#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
759#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
760#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
761#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
762#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
763#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
764#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
765#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
766#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
767#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
768
769/* PerfCnt control register definitions */
770#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
771#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
772#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
773#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
774#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
775#define MIPS_PERFCTRL_EVENT_S 5
776#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
777#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
778#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
779#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
780#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
781#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
782#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
783#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
784#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
785
786/* PerfCnt control register MT extensions used by MIPS cores */
787#define MIPS_PERFCTRL_VPEID_S 16
788#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
789#define MIPS_PERFCTRL_TCID_S 22
790#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
791#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
792#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
793#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
794#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
795
796/* PerfCnt control register MT extensions used by BMIPS5000 */
797#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
798
799/* PerfCnt control register MT extensions used by Netlogic XLR */
800#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
801
802/* MAAR bit definitions */
803#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
804#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
805#define MIPS_MAAR_ADDR_SHIFT 12
806#define MIPS_MAAR_S (_ULCAST_(1) << 1)
807#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
808#ifdef CONFIG_XPA
809#define MIPS_MAAR_V (MIPS_MAAR_VH | MIPS_MAAR_VL)
810#else
811#define MIPS_MAAR_V MIPS_MAAR_VL
812#endif
813#define MIPS_MAARX_VH (_ULCAST_(1) << 31)
814#define MIPS_MAARX_ADDR 0xF
815#define MIPS_MAARX_ADDR_SHIFT 32
816
817/* MAARI bit definitions */
818#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
819
820/* EBase bit definitions */
821#define MIPS_EBASE_CPUNUM_SHIFT 0
822#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
823#define MIPS_EBASE_WG_SHIFT 11
824#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
825#define MIPS_EBASE_BASE_SHIFT 12
826#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
827
828/* CMGCRBase bit definitions */
829#define MIPS_CMGCRB_BASE 11
830#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
831
832/* LLAddr bit definitions */
833#define MIPS_LLADDR_LLB_SHIFT 0
834#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
835
836/*
837 * Bits in the MIPS32 Memory Segmentation registers.
838 */
839#define MIPS_SEGCFG_PA_SHIFT 9
840#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
841#define MIPS_SEGCFG_AM_SHIFT 4
842#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
843#define MIPS_SEGCFG_EU_SHIFT 3
844#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
845#define MIPS_SEGCFG_C_SHIFT 0
846#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
847
848#define MIPS_SEGCFG_UUSK _ULCAST_(7)
849#define MIPS_SEGCFG_USK _ULCAST_(5)
850#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
851#define MIPS_SEGCFG_MUSK _ULCAST_(3)
852#define MIPS_SEGCFG_MSK _ULCAST_(2)
853#define MIPS_SEGCFG_MK _ULCAST_(1)
854#define MIPS_SEGCFG_UK _ULCAST_(0)
855
856#define MIPS_PWFIELD_GDI_SHIFT 24
857#define MIPS_PWFIELD_GDI_MASK 0x3f000000
858#define MIPS_PWFIELD_UDI_SHIFT 18
859#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
860#define MIPS_PWFIELD_MDI_SHIFT 12
861#define MIPS_PWFIELD_MDI_MASK 0x0003f000
862#define MIPS_PWFIELD_PTI_SHIFT 6
863#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
864#define MIPS_PWFIELD_PTEI_SHIFT 0
865#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
866
867#define MIPS_PWSIZE_PS_SHIFT 30
868#define MIPS_PWSIZE_PS_MASK 0x40000000
869#define MIPS_PWSIZE_GDW_SHIFT 24
870#define MIPS_PWSIZE_GDW_MASK 0x3f000000
871#define MIPS_PWSIZE_UDW_SHIFT 18
872#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
873#define MIPS_PWSIZE_MDW_SHIFT 12
874#define MIPS_PWSIZE_MDW_MASK 0x0003f000
875#define MIPS_PWSIZE_PTW_SHIFT 6
876#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
877#define MIPS_PWSIZE_PTEW_SHIFT 0
878#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
879
880#define MIPS_PWCTL_PWEN_SHIFT 31
881#define MIPS_PWCTL_PWEN_MASK 0x80000000
882#define MIPS_PWCTL_XK_SHIFT 28
883#define MIPS_PWCTL_XK_MASK 0x10000000
884#define MIPS_PWCTL_XS_SHIFT 27
885#define MIPS_PWCTL_XS_MASK 0x08000000
886#define MIPS_PWCTL_XU_SHIFT 26
887#define MIPS_PWCTL_XU_MASK 0x04000000
888#define MIPS_PWCTL_DPH_SHIFT 7
889#define MIPS_PWCTL_DPH_MASK 0x00000080
890#define MIPS_PWCTL_HUGEPG_SHIFT 6
891#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
892#define MIPS_PWCTL_PSN_SHIFT 0
893#define MIPS_PWCTL_PSN_MASK 0x0000003f
894
895/* GuestCtl0 fields */
896#define MIPS_GCTL0_GM_SHIFT 31
897#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
898#define MIPS_GCTL0_RI_SHIFT 30
899#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
900#define MIPS_GCTL0_MC_SHIFT 29
901#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
902#define MIPS_GCTL0_CP0_SHIFT 28
903#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
904#define MIPS_GCTL0_AT_SHIFT 26
905#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
906#define MIPS_GCTL0_GT_SHIFT 25
907#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
908#define MIPS_GCTL0_CG_SHIFT 24
909#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
910#define MIPS_GCTL0_CF_SHIFT 23
911#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
912#define MIPS_GCTL0_G1_SHIFT 22
913#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
914#define MIPS_GCTL0_G0E_SHIFT 19
915#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
916#define MIPS_GCTL0_PT_SHIFT 18
917#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
918#define MIPS_GCTL0_RAD_SHIFT 9
919#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
920#define MIPS_GCTL0_DRG_SHIFT 8
921#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
922#define MIPS_GCTL0_G2_SHIFT 7
923#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
924#define MIPS_GCTL0_GEXC_SHIFT 2
925#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
926#define MIPS_GCTL0_SFC2_SHIFT 1
927#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
928#define MIPS_GCTL0_SFC1_SHIFT 0
929#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
930
931/* GuestCtl0.AT Guest address translation control */
932#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
933#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
934
935/* GuestCtl0.GExcCode Hypervisor exception cause codes */
936#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
937#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
938#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
939#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
940#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
941#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
942#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
943
944/* GuestCtl0Ext fields */
945#define MIPS_GCTL0EXT_RPW_SHIFT 8
946#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
947#define MIPS_GCTL0EXT_NCC_SHIFT 6
948#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
949#define MIPS_GCTL0EXT_CGI_SHIFT 4
950#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
951#define MIPS_GCTL0EXT_FCD_SHIFT 3
952#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
953#define MIPS_GCTL0EXT_OG_SHIFT 2
954#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
955#define MIPS_GCTL0EXT_BG_SHIFT 1
956#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
957#define MIPS_GCTL0EXT_MG_SHIFT 0
958#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
959
960/* GuestCtl0Ext.RPW Root page walk configuration */
961#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
962#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
963#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
964
965/* GuestCtl0Ext.NCC Nested cache coherency attributes */
966#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
967#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
968
969/* GuestCtl1 fields */
970#define MIPS_GCTL1_ID_SHIFT 0
971#define MIPS_GCTL1_ID_WIDTH 8
972#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
973#define MIPS_GCTL1_RID_SHIFT 16
974#define MIPS_GCTL1_RID_WIDTH 8
975#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
976#define MIPS_GCTL1_EID_SHIFT 24
977#define MIPS_GCTL1_EID_WIDTH 8
978#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
979
980/* GuestID reserved for root context */
981#define MIPS_GCTL1_ROOT_GUESTID 0
982
983/* CDMMBase register bit definitions */
984#define MIPS_CDMMBASE_SIZE_SHIFT 0
985#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
986#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
987#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
988#define MIPS_CDMMBASE_ADDR_SHIFT 11
989#define MIPS_CDMMBASE_ADDR_START 15
990
991/* RDHWR register numbers */
992#define MIPS_HWR_CPUNUM 0 /* CPU number */
993#define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
994#define MIPS_HWR_CC 2 /* Cycle counter */
995#define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
996#define MIPS_HWR_ULR 29 /* UserLocal */
997#define MIPS_HWR_IMPL1 30 /* Implementation dependent */
998#define MIPS_HWR_IMPL2 31 /* Implementation dependent */
999
1000/* Bits in HWREna register */
1001#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
1002#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
1003#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
1004#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
1005#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
1006#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
1007#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
1008
1009/*
1010 * Bitfields in the TX39 family CP0 Configuration Register 3
1011 */
1012#define TX39_CONF_ICS_SHIFT 19
1013#define TX39_CONF_ICS_MASK 0x00380000
1014#define TX39_CONF_ICS_1KB 0x00000000
1015#define TX39_CONF_ICS_2KB 0x00080000
1016#define TX39_CONF_ICS_4KB 0x00100000
1017#define TX39_CONF_ICS_8KB 0x00180000
1018#define TX39_CONF_ICS_16KB 0x00200000
1019
1020#define TX39_CONF_DCS_SHIFT 16
1021#define TX39_CONF_DCS_MASK 0x00070000
1022#define TX39_CONF_DCS_1KB 0x00000000
1023#define TX39_CONF_DCS_2KB 0x00010000
1024#define TX39_CONF_DCS_4KB 0x00020000
1025#define TX39_CONF_DCS_8KB 0x00030000
1026#define TX39_CONF_DCS_16KB 0x00040000
1027
1028#define TX39_CONF_CWFON 0x00004000
1029#define TX39_CONF_WBON 0x00002000
1030#define TX39_CONF_RF_SHIFT 10
1031#define TX39_CONF_RF_MASK 0x00000c00
1032#define TX39_CONF_DOZE 0x00000200
1033#define TX39_CONF_HALT 0x00000100
1034#define TX39_CONF_LOCK 0x00000080
1035#define TX39_CONF_ICE 0x00000020
1036#define TX39_CONF_DCE 0x00000010
1037#define TX39_CONF_IRSIZE_SHIFT 2
1038#define TX39_CONF_IRSIZE_MASK 0x0000000c
1039#define TX39_CONF_DRSIZE_SHIFT 0
1040#define TX39_CONF_DRSIZE_MASK 0x00000003
1041
1042/*
1043 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
1044 */
1045/* Disable Branch Target Address Cache */
1046#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
1047/* Enable Branch Prediction Global History */
1048#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
1049/* Disable Branch Return Cache */
1050#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
1051
1052/* Flush BTB */
1053#define LOONGSON_DIAG_BTB (_ULCAST_(1) << 1)
1054/* Flush ITLB */
1055#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
1056/* Flush DTLB */
1057#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
1058/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1059#define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8)
1060/* Flush VTLB */
1061#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
1062/* Flush FTLB */
1063#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1064
1065/*
1066 * Diag1 (GSCause in Loongson-speak) fields
1067 */
1068/* Loongson-specific exception code (GSExcCode) */
1069#define LOONGSON_DIAG1_EXCCODE_SHIFT 2
1070#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
1071
1072/* CvmCtl register field definitions */
1073#define CVMCTL_IPPCI_SHIFT 7
1074#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1075#define CVMCTL_IPTI_SHIFT 4
1076#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1077
1078/* CvmMemCtl2 register field definitions */
1079#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1080
1081/* CvmVMConfig register field definitions */
1082#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1083#define CVMVMCONF_MMUSIZEM1_S 12
1084#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1085#define CVMVMCONF_RMMUSIZEM1_S 0
1086#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1087
1088/* Debug register field definitions */
1089#define MIPS_DEBUG_DBP_SHIFT 1
1090#define MIPS_DEBUG_DBP (_ULCAST_(1) << MIPS_DEBUG_DBP_SHIFT)
1091
1092/*
1093 * Coprocessor 1 (FPU) register names
1094 */
1095#define CP1_REVISION $0
1096#define CP1_UFR $1
1097#define CP1_UNFR $4
1098#define CP1_FCCR $25
1099#define CP1_FEXR $26
1100#define CP1_FENR $28
1101#define CP1_STATUS $31
1102
1103
1104/*
1105 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1106 */
1107#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1108#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1109#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1110#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1111#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1112#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1113#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1114#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1115#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1116#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1117
1118/*
1119 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1120 */
1121#define MIPS_FCCR_CONDX_S 0
1122#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1123#define MIPS_FCCR_COND0_S 0
1124#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1125#define MIPS_FCCR_COND1_S 1
1126#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1127#define MIPS_FCCR_COND2_S 2
1128#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1129#define MIPS_FCCR_COND3_S 3
1130#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1131#define MIPS_FCCR_COND4_S 4
1132#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1133#define MIPS_FCCR_COND5_S 5
1134#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1135#define MIPS_FCCR_COND6_S 6
1136#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1137#define MIPS_FCCR_COND7_S 7
1138#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1139
1140/*
1141 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1142 */
1143#define MIPS_FENR_FS_S 2
1144#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1145
1146/*
1147 * FPU Status Register Values
1148 */
1149#define FPU_CSR_COND_S 23 /* $fcc0 */
1150#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1151
1152#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1153#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1154
1155#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1156#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1157#define FPU_CSR_COND1_S 25 /* $fcc1 */
1158#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1159#define FPU_CSR_COND2_S 26 /* $fcc2 */
1160#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1161#define FPU_CSR_COND3_S 27 /* $fcc3 */
1162#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1163#define FPU_CSR_COND4_S 28 /* $fcc4 */
1164#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1165#define FPU_CSR_COND5_S 29 /* $fcc5 */
1166#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1167#define FPU_CSR_COND6_S 30 /* $fcc6 */
1168#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1169#define FPU_CSR_COND7_S 31 /* $fcc7 */
1170#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1171
1172/*
1173 * Bits 22:20 of the FPU Status Register will be read as 0,
1174 * and should be written as zero.
1175 * MAC2008 was removed in Release 5 so we still treat it as
1176 * reserved.
1177 */
1178#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1179
1180#define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1181#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1182#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1183
1184/*
1185 * X the exception cause indicator
1186 * E the exception enable
1187 * S the sticky/flag bit
1188*/
1189#define FPU_CSR_ALL_X 0x0003f000
1190#define FPU_CSR_UNI_X 0x00020000
1191#define FPU_CSR_INV_X 0x00010000
1192#define FPU_CSR_DIV_X 0x00008000
1193#define FPU_CSR_OVF_X 0x00004000
1194#define FPU_CSR_UDF_X 0x00002000
1195#define FPU_CSR_INE_X 0x00001000
1196
1197#define FPU_CSR_ALL_E 0x00000f80
1198#define FPU_CSR_INV_E 0x00000800
1199#define FPU_CSR_DIV_E 0x00000400
1200#define FPU_CSR_OVF_E 0x00000200
1201#define FPU_CSR_UDF_E 0x00000100
1202#define FPU_CSR_INE_E 0x00000080
1203
1204#define FPU_CSR_ALL_S 0x0000007c
1205#define FPU_CSR_INV_S 0x00000040
1206#define FPU_CSR_DIV_S 0x00000020
1207#define FPU_CSR_OVF_S 0x00000010
1208#define FPU_CSR_UDF_S 0x00000008
1209#define FPU_CSR_INE_S 0x00000004
1210
1211/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1212#define FPU_CSR_RM 0x00000003
1213#define FPU_CSR_RN 0x0 /* nearest */
1214#define FPU_CSR_RZ 0x1 /* towards zero */
1215#define FPU_CSR_RU 0x2 /* towards +Infinity */
1216#define FPU_CSR_RD 0x3 /* towards -Infinity */
1217
1218
1219#ifndef __ASSEMBLY__
1220
1221/*
1222 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1223 */
1224#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1225 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1226#define get_isa16_mode(x) ((x) & 0x1)
1227#define msk_isa16_mode(x) ((x) & ~0x1)
1228#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1229#else
1230#define get_isa16_mode(x) 0
1231#define msk_isa16_mode(x) (x)
1232#define set_isa16_mode(x) do { } while(0)
1233#endif
1234
1235/*
1236 * microMIPS instructions can be 16-bit or 32-bit in length. This
1237 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1238 */
1239static inline int mm_insn_16bit(u16 insn)
1240{
1241 u16 opcode = (insn >> 10) & 0x7;
1242
1243 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1244}
1245
1246/*
1247 * Helper macros for generating raw instruction encodings in inline asm.
1248 */
1249#ifdef CONFIG_CPU_MICROMIPS
1250#define _ASM_INSN16_IF_MM(_enc) \
1251 ".insn\n\t" \
1252 ".hword (" #_enc ")\n\t"
1253#define _ASM_INSN32_IF_MM(_enc) \
1254 ".insn\n\t" \
1255 ".hword ((" #_enc ") >> 16)\n\t" \
1256 ".hword ((" #_enc ") & 0xffff)\n\t"
1257#else
1258#define _ASM_INSN_IF_MIPS(_enc) \
1259 ".insn\n\t" \
1260 ".word (" #_enc ")\n\t"
1261#endif
1262
1263#ifndef _ASM_INSN16_IF_MM
1264#define _ASM_INSN16_IF_MM(_enc)
1265#endif
1266#ifndef _ASM_INSN32_IF_MM
1267#define _ASM_INSN32_IF_MM(_enc)
1268#endif
1269#ifndef _ASM_INSN_IF_MIPS
1270#define _ASM_INSN_IF_MIPS(_enc)
1271#endif
1272
1273/*
1274 * parse_r var, r - Helper assembler macro for parsing register names.
1275 *
1276 * This converts the register name in $n form provided in \r to the
1277 * corresponding register number, which is assigned to the variable \var. It is
1278 * needed to allow explicit encoding of instructions in inline assembly where
1279 * registers are chosen by the compiler in $n form, allowing us to avoid using
1280 * fixed register numbers.
1281 *
1282 * It also allows newer instructions (not implemented by the assembler) to be
1283 * transparently implemented using assembler macros, instead of needing separate
1284 * cases depending on toolchain support.
1285 *
1286 * Simple usage example:
1287 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1288 * ".insn\n\t"
1289 * "# di %0\n\t"
1290 * ".word (0x41606000 | (__rt << 16))"
1291 * : "=r" (status);
1292 */
1293
1294/* Match an individual register number and assign to \var */
1295#define _IFC_REG(n) \
1296 ".ifc \\r, $" #n "\n\t" \
1297 "\\var = " #n "\n\t" \
1298 ".endif\n\t"
1299
1300__asm__(".macro parse_r var r\n\t"
1301 "\\var = -1\n\t"
1302 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1303 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1304 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1305 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1306 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1307 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1308 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1309 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1310 ".iflt \\var\n\t"
1311 ".error \"Unable to parse register name \\r\"\n\t"
1312 ".endif\n\t"
1313 ".endm");
1314
1315#undef _IFC_REG
1316
1317/*
1318 * C macros for generating assembler macros for common instruction formats.
1319 *
1320 * The names of the operands can be chosen by the caller, and the encoding of
1321 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1322 * the ENC encodings.
1323 */
1324
1325/* Instructions with no operands */
1326#define _ASM_MACRO_0(OP, ENC) \
1327 __asm__(".macro " #OP "\n\t" \
1328 ENC \
1329 ".endm")
1330
1331/* Instructions with 1 register operand & 1 immediate operand */
1332#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
1333 __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
1334 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1335 ENC \
1336 ".endm")
1337
1338/* Instructions with 2 register operands */
1339#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1340 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1341 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1342 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1343 ENC \
1344 ".endm")
1345
1346/* Instructions with 3 register operands */
1347#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1348 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1349 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1350 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1351 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1352 ENC \
1353 ".endm")
1354
1355/* Instructions with 2 register operands and 1 optional select operand */
1356#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1357 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1358 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1359 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1360 ENC \
1361 ".endm")
1362
1363/*
1364 * TLB Invalidate Flush
1365 */
1366static inline void tlbinvf(void)
1367{
1368 __asm__ __volatile__(
1369 ".set push\n\t"
1370 ".set noreorder\n\t"
1371 "# tlbinvf\n\t"
1372 _ASM_INSN_IF_MIPS(0x42000004)
1373 _ASM_INSN32_IF_MM(0x0000537c)
1374 ".set pop");
1375}
1376
1377
1378/*
1379 * Functions to access the R10000 performance counters. These are basically
1380 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1381 * performance counter number encoded into bits 1 ... 5 of the instruction.
1382 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1383 * disassembler these will look like an access to sel 0 or 1.
1384 */
1385#define read_r10k_perf_cntr(counter) \
1386({ \
1387 unsigned int __res; \
1388 __asm__ __volatile__( \
1389 "mfpc\t%0, %1" \
1390 : "=r" (__res) \
1391 : "i" (counter)); \
1392 \
1393 __res; \
1394})
1395
1396#define write_r10k_perf_cntr(counter,val) \
1397do { \
1398 __asm__ __volatile__( \
1399 "mtpc\t%0, %1" \
1400 : \
1401 : "r" (val), "i" (counter)); \
1402} while (0)
1403
1404#define read_r10k_perf_event(counter) \
1405({ \
1406 unsigned int __res; \
1407 __asm__ __volatile__( \
1408 "mfps\t%0, %1" \
1409 : "=r" (__res) \
1410 : "i" (counter)); \
1411 \
1412 __res; \
1413})
1414
1415#define write_r10k_perf_cntl(counter,val) \
1416do { \
1417 __asm__ __volatile__( \
1418 "mtps\t%0, %1" \
1419 : \
1420 : "r" (val), "i" (counter)); \
1421} while (0)
1422
1423
1424/*
1425 * Macros to access the system control coprocessor
1426 */
1427
1428#define ___read_32bit_c0_register(source, sel, vol) \
1429({ unsigned int __res; \
1430 if (sel == 0) \
1431 __asm__ vol( \
1432 "mfc0\t%0, " #source "\n\t" \
1433 : "=r" (__res)); \
1434 else \
1435 __asm__ vol( \
1436 ".set\tpush\n\t" \
1437 ".set\tmips32\n\t" \
1438 "mfc0\t%0, " #source ", " #sel "\n\t" \
1439 ".set\tpop\n\t" \
1440 : "=r" (__res)); \
1441 __res; \
1442})
1443
1444#define ___read_64bit_c0_register(source, sel, vol) \
1445({ unsigned long long __res; \
1446 if (sizeof(unsigned long) == 4) \
1447 __res = __read_64bit_c0_split(source, sel, vol); \
1448 else if (sel == 0) \
1449 __asm__ vol( \
1450 ".set\tpush\n\t" \
1451 ".set\tmips3\n\t" \
1452 "dmfc0\t%0, " #source "\n\t" \
1453 ".set\tpop" \
1454 : "=r" (__res)); \
1455 else \
1456 __asm__ vol( \
1457 ".set\tpush\n\t" \
1458 ".set\tmips64\n\t" \
1459 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1460 ".set\tpop" \
1461 : "=r" (__res)); \
1462 __res; \
1463})
1464
1465#define __read_32bit_c0_register(source, sel) \
1466 ___read_32bit_c0_register(source, sel, __volatile__)
1467
1468#define __read_const_32bit_c0_register(source, sel) \
1469 ___read_32bit_c0_register(source, sel,)
1470
1471#define __read_64bit_c0_register(source, sel) \
1472 ___read_64bit_c0_register(source, sel, __volatile__)
1473
1474#define __read_const_64bit_c0_register(source, sel) \
1475 ___read_64bit_c0_register(source, sel,)
1476
1477#define __write_32bit_c0_register(register, sel, value) \
1478do { \
1479 if (sel == 0) \
1480 __asm__ __volatile__( \
1481 "mtc0\t%z0, " #register "\n\t" \
1482 : : "Jr" ((unsigned int)(value))); \
1483 else \
1484 __asm__ __volatile__( \
1485 ".set\tpush\n\t" \
1486 ".set\tmips32\n\t" \
1487 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1488 ".set\tpop" \
1489 : : "Jr" ((unsigned int)(value))); \
1490} while (0)
1491
1492#define __write_64bit_c0_register(register, sel, value) \
1493do { \
1494 if (sizeof(unsigned long) == 4) \
1495 __write_64bit_c0_split(register, sel, value); \
1496 else if (sel == 0) \
1497 __asm__ __volatile__( \
1498 ".set\tpush\n\t" \
1499 ".set\tmips3\n\t" \
1500 "dmtc0\t%z0, " #register "\n\t" \
1501 ".set\tpop" \
1502 : : "Jr" (value)); \
1503 else \
1504 __asm__ __volatile__( \
1505 ".set\tpush\n\t" \
1506 ".set\tmips64\n\t" \
1507 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1508 ".set\tpop" \
1509 : : "Jr" (value)); \
1510} while (0)
1511
1512#define __read_ulong_c0_register(reg, sel) \
1513 ((sizeof(unsigned long) == 4) ? \
1514 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1515 (unsigned long) __read_64bit_c0_register(reg, sel))
1516
1517#define __read_const_ulong_c0_register(reg, sel) \
1518 ((sizeof(unsigned long) == 4) ? \
1519 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1520 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1521
1522#define __write_ulong_c0_register(reg, sel, val) \
1523do { \
1524 if (sizeof(unsigned long) == 4) \
1525 __write_32bit_c0_register(reg, sel, val); \
1526 else \
1527 __write_64bit_c0_register(reg, sel, val); \
1528} while (0)
1529
1530/*
1531 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1532 */
1533#define __read_32bit_c0_ctrl_register(source) \
1534({ unsigned int __res; \
1535 __asm__ __volatile__( \
1536 "cfc0\t%0, " #source "\n\t" \
1537 : "=r" (__res)); \
1538 __res; \
1539})
1540
1541#define __write_32bit_c0_ctrl_register(register, value) \
1542do { \
1543 __asm__ __volatile__( \
1544 "ctc0\t%z0, " #register "\n\t" \
1545 : : "Jr" ((unsigned int)(value))); \
1546} while (0)
1547
1548/*
1549 * These versions are only needed for systems with more than 38 bits of
1550 * physical address space running the 32-bit kernel. That's none atm :-)
1551 */
1552#define __read_64bit_c0_split(source, sel, vol) \
1553({ \
1554 unsigned long long __val; \
1555 unsigned long __flags; \
1556 \
1557 local_irq_save(__flags); \
1558 if (sel == 0) \
1559 __asm__ vol( \
1560 ".set\tpush\n\t" \
1561 ".set\tmips64\n\t" \
1562 "dmfc0\t%L0, " #source "\n\t" \
1563 "dsra\t%M0, %L0, 32\n\t" \
1564 "sll\t%L0, %L0, 0\n\t" \
1565 ".set\tpop" \
1566 : "=r" (__val)); \
1567 else \
1568 __asm__ vol( \
1569 ".set\tpush\n\t" \
1570 ".set\tmips64\n\t" \
1571 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1572 "dsra\t%M0, %L0, 32\n\t" \
1573 "sll\t%L0, %L0, 0\n\t" \
1574 ".set\tpop" \
1575 : "=r" (__val)); \
1576 local_irq_restore(__flags); \
1577 \
1578 __val; \
1579})
1580
1581#define __write_64bit_c0_split(source, sel, val) \
1582do { \
1583 unsigned long long __tmp = (val); \
1584 unsigned long __flags; \
1585 \
1586 local_irq_save(__flags); \
1587 if (MIPS_ISA_REV >= 2) \
1588 __asm__ __volatile__( \
1589 ".set\tpush\n\t" \
1590 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1591 "dins\t%L0, %M0, 32, 32\n\t" \
1592 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1593 ".set\tpop" \
1594 : "+r" (__tmp)); \
1595 else if (sel == 0) \
1596 __asm__ __volatile__( \
1597 ".set\tpush\n\t" \
1598 ".set\tmips64\n\t" \
1599 "dsll\t%L0, %L0, 32\n\t" \
1600 "dsrl\t%L0, %L0, 32\n\t" \
1601 "dsll\t%M0, %M0, 32\n\t" \
1602 "or\t%L0, %L0, %M0\n\t" \
1603 "dmtc0\t%L0, " #source "\n\t" \
1604 ".set\tpop" \
1605 : "+r" (__tmp)); \
1606 else \
1607 __asm__ __volatile__( \
1608 ".set\tpush\n\t" \
1609 ".set\tmips64\n\t" \
1610 "dsll\t%L0, %L0, 32\n\t" \
1611 "dsrl\t%L0, %L0, 32\n\t" \
1612 "dsll\t%M0, %M0, 32\n\t" \
1613 "or\t%L0, %L0, %M0\n\t" \
1614 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1615 ".set\tpop" \
1616 : "+r" (__tmp)); \
1617 local_irq_restore(__flags); \
1618} while (0)
1619
1620#ifndef TOOLCHAIN_SUPPORTS_XPA
1621_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1622 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1623 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1624_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1625 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1626 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1627#define _ASM_SET_XPA ""
1628#else /* !TOOLCHAIN_SUPPORTS_XPA */
1629#define _ASM_SET_XPA ".set\txpa\n\t"
1630#endif
1631
1632#define __readx_32bit_c0_register(source, sel) \
1633({ \
1634 unsigned int __res; \
1635 \
1636 __asm__ __volatile__( \
1637 " .set push \n" \
1638 " .set mips32r2 \n" \
1639 _ASM_SET_XPA \
1640 " mfhc0 %0, " #source ", %1 \n" \
1641 " .set pop \n" \
1642 : "=r" (__res) \
1643 : "i" (sel)); \
1644 __res; \
1645})
1646
1647#define __writex_32bit_c0_register(register, sel, value) \
1648do { \
1649 __asm__ __volatile__( \
1650 " .set push \n" \
1651 " .set mips32r2 \n" \
1652 _ASM_SET_XPA \
1653 " mthc0 %z0, " #register ", %1 \n" \
1654 " .set pop \n" \
1655 : \
1656 : "Jr" (value), "i" (sel)); \
1657} while (0)
1658
1659#define read_c0_index() __read_32bit_c0_register($0, 0)
1660#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1661
1662#define read_c0_random() __read_32bit_c0_register($1, 0)
1663#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1664
1665#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1666#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1667
1668#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1669#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1670
1671#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1672#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1673
1674#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1675#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1676
1677#define read_c0_conf() __read_32bit_c0_register($3, 0)
1678#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1679
1680#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1681
1682#define read_c0_context() __read_ulong_c0_register($4, 0)
1683#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1684
1685#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1686#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1687
1688#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1689#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1690
1691#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1692#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1693
1694#define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
1695#define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
1696
1697#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1698#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1699
1700#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1701#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1702
1703#define read_c0_wired() __read_32bit_c0_register($6, 0)
1704#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1705
1706#define read_c0_info() __read_32bit_c0_register($7, 0)
1707
1708#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1709#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1710
1711#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1712#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1713
1714#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1715#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1716
1717#define read_c0_count() __read_32bit_c0_register($9, 0)
1718#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1719
1720#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1721#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1722
1723#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1724#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1725
1726#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1727#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1728
1729#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1730#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1731
1732#define read_c0_compare() __read_32bit_c0_register($11, 0)
1733#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1734
1735#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1736#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1737
1738#define read_c0_status() __read_32bit_c0_register($12, 0)
1739
1740#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1741
1742#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1743#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1744
1745#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1746#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1747
1748#define read_c0_cause() __read_32bit_c0_register($13, 0)
1749#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1750
1751#define read_c0_epc() __read_ulong_c0_register($14, 0)
1752#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1753
1754#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1755
1756#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1757
1758#define read_c0_config() __read_32bit_c0_register($16, 0)
1759#define read_c0_config1() __read_32bit_c0_register($16, 1)
1760#define read_c0_config2() __read_32bit_c0_register($16, 2)
1761#define read_c0_config3() __read_32bit_c0_register($16, 3)
1762#define read_c0_config4() __read_32bit_c0_register($16, 4)
1763#define read_c0_config5() __read_32bit_c0_register($16, 5)
1764#define read_c0_config6() __read_32bit_c0_register($16, 6)
1765#define read_c0_config7() __read_32bit_c0_register($16, 7)
1766#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1767#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1768#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1769#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1770#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1771#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1772#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1773#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1774
1775#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1776#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1777#define read_c0_maar() __read_ulong_c0_register($17, 1)
1778#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1779#define readx_c0_maar() __readx_32bit_c0_register($17, 1)
1780#define writex_c0_maar(val) __writex_32bit_c0_register($17, 1, val)
1781#define read_c0_maari() __read_32bit_c0_register($17, 2)
1782#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1783
1784/*
1785 * The WatchLo register. There may be up to 8 of them.
1786 */
1787#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1788#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1789#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1790#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1791#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1792#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1793#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1794#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1795#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1796#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1797#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1798#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1799#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1800#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1801#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1802#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1803
1804/*
1805 * The WatchHi register. There may be up to 8 of them.
1806 */
1807#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1808#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1809#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1810#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1811#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1812#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1813#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1814#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1815
1816#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1817#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1818#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1819#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1820#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1821#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1822#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1823#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1824
1825#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1826#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1827
1828#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1829#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1830
1831#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1832#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1833
1834#define read_c0_diag() __read_32bit_c0_register($22, 0)
1835#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1836
1837/* R10K CP0 Branch Diagnostic register is 64bits wide */
1838#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1839#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1840
1841#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1842#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1843
1844#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1845#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1846
1847#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1848#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1849
1850#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1851#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1852
1853#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1854#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1855
1856#define read_c0_debug() __read_32bit_c0_register($23, 0)
1857#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1858
1859#define read_c0_depc() __read_ulong_c0_register($24, 0)
1860#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1861
1862/*
1863 * MIPS32 / MIPS64 performance counters
1864 */
1865#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1866#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1867#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1868#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1869#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1870#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1871#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1872#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1873#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1874#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1875#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1876#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1877#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1878#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1879#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1880#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1881#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1882#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1883#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1884#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1885#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1886#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1887#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1888#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1889
1890#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1891#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1892
1893#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1894#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1895
1896#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1897
1898#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1899#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1900
1901#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1902#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1903
1904#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1905#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1906
1907#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1908#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1909
1910#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1911#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1912
1913#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1914#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1915
1916#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1917#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1918
1919/* MIPSR2 */
1920#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1921#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1922
1923#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1924#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1925
1926#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1927#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1928
1929#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1930#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1931
1932#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1933#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1934
1935#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1936#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1937
1938#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1939#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1940
1941/* MIPSR3 */
1942#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1943#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1944
1945#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1946#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1947
1948#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1949#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1950
1951/* Hardware Page Table Walker */
1952#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1953#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1954
1955#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1956#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1957
1958#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1959#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1960
1961#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1962#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1963
1964#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1965#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1966
1967#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1968#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1969
1970/* Cavium OCTEON (cnMIPS) */
1971#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1972#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1973
1974#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1975#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1976
1977#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1978#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1979
1980#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1981#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1982
1983#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1984#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1985
1986/*
1987 * The cacheerr registers are not standardized. On OCTEON, they are
1988 * 64 bits wide.
1989 */
1990#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1991#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1992
1993#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1994#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1995
1996/* BMIPS3300 */
1997#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1998#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1999
2000#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
2001#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
2002
2003#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
2004#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
2005
2006/* BMIPS43xx */
2007#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
2008#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
2009
2010#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
2011#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
2012
2013#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
2014#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
2015
2016#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
2017#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
2018
2019#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
2020#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
2021
2022/* BMIPS5000 */
2023#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
2024#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
2025
2026#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
2027#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
2028
2029#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
2030#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
2031
2032#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
2033#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
2034
2035#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
2036#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
2037
2038#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
2039#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
2040
2041/* Ingenic page ctrl register */
2042#define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
2043
2044/*
2045 * Macros to access the guest system control coprocessor
2046 */
2047
2048#ifndef TOOLCHAIN_SUPPORTS_VIRT
2049_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
2050 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
2051 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2052_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
2053 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
2054 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2055_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
2056 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
2057 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2058_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
2059 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
2060 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2061_ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
2062 _ASM_INSN32_IF_MM(0x0000017c));
2063_ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
2064 _ASM_INSN32_IF_MM(0x0000117c));
2065_ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
2066 _ASM_INSN32_IF_MM(0x0000217c));
2067_ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
2068 _ASM_INSN32_IF_MM(0x0000317c));
2069_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
2070 _ASM_INSN32_IF_MM(0x0000517c));
2071#define _ASM_SET_VIRT ""
2072#else /* !TOOLCHAIN_SUPPORTS_VIRT */
2073#define _ASM_SET_VIRT ".set\tvirt\n\t"
2074#endif
2075
2076#define __read_32bit_gc0_register(source, sel) \
2077({ int __res; \
2078 __asm__ __volatile__( \
2079 ".set\tpush\n\t" \
2080 ".set\tmips32r5\n\t" \
2081 _ASM_SET_VIRT \
2082 "mfgc0\t%0, " #source ", %1\n\t" \
2083 ".set\tpop" \
2084 : "=r" (__res) \
2085 : "i" (sel)); \
2086 __res; \
2087})
2088
2089#define __read_64bit_gc0_register(source, sel) \
2090({ unsigned long long __res; \
2091 __asm__ __volatile__( \
2092 ".set\tpush\n\t" \
2093 ".set\tmips64r5\n\t" \
2094 _ASM_SET_VIRT \
2095 "dmfgc0\t%0, " #source ", %1\n\t" \
2096 ".set\tpop" \
2097 : "=r" (__res) \
2098 : "i" (sel)); \
2099 __res; \
2100})
2101
2102#define __write_32bit_gc0_register(register, sel, value) \
2103do { \
2104 __asm__ __volatile__( \
2105 ".set\tpush\n\t" \
2106 ".set\tmips32r5\n\t" \
2107 _ASM_SET_VIRT \
2108 "mtgc0\t%z0, " #register ", %1\n\t" \
2109 ".set\tpop" \
2110 : : "Jr" ((unsigned int)(value)), \
2111 "i" (sel)); \
2112} while (0)
2113
2114#define __write_64bit_gc0_register(register, sel, value) \
2115do { \
2116 __asm__ __volatile__( \
2117 ".set\tpush\n\t" \
2118 ".set\tmips64r5\n\t" \
2119 _ASM_SET_VIRT \
2120 "dmtgc0\t%z0, " #register ", %1\n\t" \
2121 ".set\tpop" \
2122 : : "Jr" (value), \
2123 "i" (sel)); \
2124} while (0)
2125
2126#define __read_ulong_gc0_register(reg, sel) \
2127 ((sizeof(unsigned long) == 4) ? \
2128 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2129 (unsigned long) __read_64bit_gc0_register(reg, sel))
2130
2131#define __write_ulong_gc0_register(reg, sel, val) \
2132do { \
2133 if (sizeof(unsigned long) == 4) \
2134 __write_32bit_gc0_register(reg, sel, val); \
2135 else \
2136 __write_64bit_gc0_register(reg, sel, val); \
2137} while (0)
2138
2139#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2140#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2141
2142#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2143#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2144
2145#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2146#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2147
2148#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2149#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2150
2151#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2152#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2153
2154#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2155#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2156
2157#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2158#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2159
2160#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2161#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2162
2163#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2164#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2165
2166#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2167#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2168
2169#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2170#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2171
2172#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2173#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2174
2175#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2176#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2177
2178#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2179#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2180
2181#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2182#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2183
2184#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2185#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2186
2187#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2188#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2189
2190#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2191#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2192
2193#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2194#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2195
2196#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2197#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2198
2199#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2200#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2201
2202#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2203
2204#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2205#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2206
2207#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2208#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2209
2210#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2211#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2212
2213#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2214#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2215
2216#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2217#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2218
2219#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2220#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2221
2222#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2223
2224#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2225#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2226
2227#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2228#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2229
2230#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2231#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2232#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2233#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2234#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2235#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2236#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2237#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2238#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2239#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2240#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2241#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2242#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2243#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2244#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2245#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2246
2247#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2248#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2249
2250#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2251#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2252#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2253#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2254#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2255#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2256#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2257#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2258#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2259#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2260#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2261#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2262#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2263#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2264#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2265#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2266
2267#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2268#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2269#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2270#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2271#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2272#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2273#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2274#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2275#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2276#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2277#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2278#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2279#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2280#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2281#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2282#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2283
2284#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2285#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2286
2287#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2288#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2289#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2290#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2291#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2292#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2293#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2294#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2295#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2296#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2297#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2298#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2299#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2300#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2301#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2302#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2303#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2304#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2305#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2306#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2307#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2308#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2309#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2310#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2311
2312#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2313#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2314
2315#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2316#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2317#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2318#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2319#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2320#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2321#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2322#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2323#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2324#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2325#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2326#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2327
2328/* Cavium OCTEON (cnMIPS) */
2329#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2330#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2331
2332#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2333#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2334
2335#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2336#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2337
2338#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2339#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2340
2341/*
2342 * Macros to access the floating point coprocessor control registers
2343 */
2344#define _read_32bit_cp1_register(source, gas_hardfloat) \
2345({ \
2346 unsigned int __res; \
2347 \
2348 __asm__ __volatile__( \
2349 " .set push \n" \
2350 " .set reorder \n" \
2351 " # gas fails to assemble cfc1 for some archs, \n" \
2352 " # like Octeon. \n" \
2353 " .set mips1 \n" \
2354 " "STR(gas_hardfloat)" \n" \
2355 " cfc1 %0,"STR(source)" \n" \
2356 " .set pop \n" \
2357 : "=r" (__res)); \
2358 __res; \
2359})
2360
2361#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2362do { \
2363 __asm__ __volatile__( \
2364 " .set push \n" \
2365 " .set reorder \n" \
2366 " "STR(gas_hardfloat)" \n" \
2367 " ctc1 %0,"STR(dest)" \n" \
2368 " .set pop \n" \
2369 : : "r" (val)); \
2370} while (0)
2371
2372#ifdef GAS_HAS_SET_HARDFLOAT
2373#define read_32bit_cp1_register(source) \
2374 _read_32bit_cp1_register(source, .set hardfloat)
2375#define write_32bit_cp1_register(dest, val) \
2376 _write_32bit_cp1_register(dest, val, .set hardfloat)
2377#else
2378#define read_32bit_cp1_register(source) \
2379 _read_32bit_cp1_register(source, )
2380#define write_32bit_cp1_register(dest, val) \
2381 _write_32bit_cp1_register(dest, val, )
2382#endif
2383
2384#ifdef TOOLCHAIN_SUPPORTS_DSP
2385#define rddsp(mask) \
2386({ \
2387 unsigned int __dspctl; \
2388 \
2389 __asm__ __volatile__( \
2390 " .set push \n" \
2391 " .set " MIPS_ISA_LEVEL " \n" \
2392 " .set dsp \n" \
2393 " rddsp %0, %x1 \n" \
2394 " .set pop \n" \
2395 : "=r" (__dspctl) \
2396 : "i" (mask)); \
2397 __dspctl; \
2398})
2399
2400#define wrdsp(val, mask) \
2401do { \
2402 __asm__ __volatile__( \
2403 " .set push \n" \
2404 " .set " MIPS_ISA_LEVEL " \n" \
2405 " .set dsp \n" \
2406 " wrdsp %0, %x1 \n" \
2407 " .set pop \n" \
2408 : \
2409 : "r" (val), "i" (mask)); \
2410} while (0)
2411
2412#define mflo0() \
2413({ \
2414 long mflo0; \
2415 __asm__( \
2416 " .set push \n" \
2417 " .set " MIPS_ISA_LEVEL " \n" \
2418 " .set dsp \n" \
2419 " mflo %0, $ac0 \n" \
2420 " .set pop \n" \
2421 : "=r" (mflo0)); \
2422 mflo0; \
2423})
2424
2425#define mflo1() \
2426({ \
2427 long mflo1; \
2428 __asm__( \
2429 " .set push \n" \
2430 " .set " MIPS_ISA_LEVEL " \n" \
2431 " .set dsp \n" \
2432 " mflo %0, $ac1 \n" \
2433 " .set pop \n" \
2434 : "=r" (mflo1)); \
2435 mflo1; \
2436})
2437
2438#define mflo2() \
2439({ \
2440 long mflo2; \
2441 __asm__( \
2442 " .set push \n" \
2443 " .set " MIPS_ISA_LEVEL " \n" \
2444 " .set dsp \n" \
2445 " mflo %0, $ac2 \n" \
2446 " .set pop \n" \
2447 : "=r" (mflo2)); \
2448 mflo2; \
2449})
2450
2451#define mflo3() \
2452({ \
2453 long mflo3; \
2454 __asm__( \
2455 " .set push \n" \
2456 " .set " MIPS_ISA_LEVEL " \n" \
2457 " .set dsp \n" \
2458 " mflo %0, $ac3 \n" \
2459 " .set pop \n" \
2460 : "=r" (mflo3)); \
2461 mflo3; \
2462})
2463
2464#define mfhi0() \
2465({ \
2466 long mfhi0; \
2467 __asm__( \
2468 " .set push \n" \
2469 " .set " MIPS_ISA_LEVEL " \n" \
2470 " .set dsp \n" \
2471 " mfhi %0, $ac0 \n" \
2472 " .set pop \n" \
2473 : "=r" (mfhi0)); \
2474 mfhi0; \
2475})
2476
2477#define mfhi1() \
2478({ \
2479 long mfhi1; \
2480 __asm__( \
2481 " .set push \n" \
2482 " .set " MIPS_ISA_LEVEL " \n" \
2483 " .set dsp \n" \
2484 " mfhi %0, $ac1 \n" \
2485 " .set pop \n" \
2486 : "=r" (mfhi1)); \
2487 mfhi1; \
2488})
2489
2490#define mfhi2() \
2491({ \
2492 long mfhi2; \
2493 __asm__( \
2494 " .set push \n" \
2495 " .set " MIPS_ISA_LEVEL " \n" \
2496 " .set dsp \n" \
2497 " mfhi %0, $ac2 \n" \
2498 " .set pop \n" \
2499 : "=r" (mfhi2)); \
2500 mfhi2; \
2501})
2502
2503#define mfhi3() \
2504({ \
2505 long mfhi3; \
2506 __asm__( \
2507 " .set push \n" \
2508 " .set " MIPS_ISA_LEVEL " \n" \
2509 " .set dsp \n" \
2510 " mfhi %0, $ac3 \n" \
2511 " .set pop \n" \
2512 : "=r" (mfhi3)); \
2513 mfhi3; \
2514})
2515
2516
2517#define mtlo0(x) \
2518({ \
2519 __asm__( \
2520 " .set push \n" \
2521 " .set " MIPS_ISA_LEVEL " \n" \
2522 " .set dsp \n" \
2523 " mtlo %0, $ac0 \n" \
2524 " .set pop \n" \
2525 : \
2526 : "r" (x)); \
2527})
2528
2529#define mtlo1(x) \
2530({ \
2531 __asm__( \
2532 " .set push \n" \
2533 " .set " MIPS_ISA_LEVEL " \n" \
2534 " .set dsp \n" \
2535 " mtlo %0, $ac1 \n" \
2536 " .set pop \n" \
2537 : \
2538 : "r" (x)); \
2539})
2540
2541#define mtlo2(x) \
2542({ \
2543 __asm__( \
2544 " .set push \n" \
2545 " .set " MIPS_ISA_LEVEL " \n" \
2546 " .set dsp \n" \
2547 " mtlo %0, $ac2 \n" \
2548 " .set pop \n" \
2549 : \
2550 : "r" (x)); \
2551})
2552
2553#define mtlo3(x) \
2554({ \
2555 __asm__( \
2556 " .set push \n" \
2557 " .set " MIPS_ISA_LEVEL " \n" \
2558 " .set dsp \n" \
2559 " mtlo %0, $ac3 \n" \
2560 " .set pop \n" \
2561 : \
2562 : "r" (x)); \
2563})
2564
2565#define mthi0(x) \
2566({ \
2567 __asm__( \
2568 " .set push \n" \
2569 " .set " MIPS_ISA_LEVEL " \n" \
2570 " .set dsp \n" \
2571 " mthi %0, $ac0 \n" \
2572 " .set pop \n" \
2573 : \
2574 : "r" (x)); \
2575})
2576
2577#define mthi1(x) \
2578({ \
2579 __asm__( \
2580 " .set push \n" \
2581 " .set " MIPS_ISA_LEVEL " \n" \
2582 " .set dsp \n" \
2583 " mthi %0, $ac1 \n" \
2584 " .set pop \n" \
2585 : \
2586 : "r" (x)); \
2587})
2588
2589#define mthi2(x) \
2590({ \
2591 __asm__( \
2592 " .set push \n" \
2593 " .set " MIPS_ISA_LEVEL " \n" \
2594 " .set dsp \n" \
2595 " mthi %0, $ac2 \n" \
2596 " .set pop \n" \
2597 : \
2598 : "r" (x)); \
2599})
2600
2601#define mthi3(x) \
2602({ \
2603 __asm__( \
2604 " .set push \n" \
2605 " .set " MIPS_ISA_LEVEL " \n" \
2606 " .set dsp \n" \
2607 " mthi %0, $ac3 \n" \
2608 " .set pop \n" \
2609 : \
2610 : "r" (x)); \
2611})
2612
2613#else
2614
2615#define rddsp(mask) \
2616({ \
2617 unsigned int __res; \
2618 \
2619 __asm__ __volatile__( \
2620 " .set push \n" \
2621 " .set noat \n" \
2622 " # rddsp $1, %x1 \n" \
2623 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2624 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2625 " move %0, $1 \n" \
2626 " .set pop \n" \
2627 : "=r" (__res) \
2628 : "i" (mask)); \
2629 __res; \
2630})
2631
2632#define wrdsp(val, mask) \
2633do { \
2634 __asm__ __volatile__( \
2635 " .set push \n" \
2636 " .set noat \n" \
2637 " move $1, %0 \n" \
2638 " # wrdsp $1, %x1 \n" \
2639 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2640 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2641 " .set pop \n" \
2642 : \
2643 : "r" (val), "i" (mask)); \
2644} while (0)
2645
2646#define _dsp_mfxxx(ins) \
2647({ \
2648 unsigned long __treg; \
2649 \
2650 __asm__ __volatile__( \
2651 " .set push \n" \
2652 " .set noat \n" \
2653 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2654 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2655 " move %0, $1 \n" \
2656 " .set pop \n" \
2657 : "=r" (__treg) \
2658 : "i" (ins)); \
2659 __treg; \
2660})
2661
2662#define _dsp_mtxxx(val, ins) \
2663do { \
2664 __asm__ __volatile__( \
2665 " .set push \n" \
2666 " .set noat \n" \
2667 " move $1, %0 \n" \
2668 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2669 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2670 " .set pop \n" \
2671 : \
2672 : "r" (val), "i" (ins)); \
2673} while (0)
2674
2675#ifdef CONFIG_CPU_MICROMIPS
2676
2677#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2678#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2679
2680#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2681#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2682
2683#else /* !CONFIG_CPU_MICROMIPS */
2684
2685#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2686#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2687
2688#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2689#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2690
2691#endif /* CONFIG_CPU_MICROMIPS */
2692
2693#define mflo0() _dsp_mflo(0)
2694#define mflo1() _dsp_mflo(1)
2695#define mflo2() _dsp_mflo(2)
2696#define mflo3() _dsp_mflo(3)
2697
2698#define mfhi0() _dsp_mfhi(0)
2699#define mfhi1() _dsp_mfhi(1)
2700#define mfhi2() _dsp_mfhi(2)
2701#define mfhi3() _dsp_mfhi(3)
2702
2703#define mtlo0(x) _dsp_mtlo(x, 0)
2704#define mtlo1(x) _dsp_mtlo(x, 1)
2705#define mtlo2(x) _dsp_mtlo(x, 2)
2706#define mtlo3(x) _dsp_mtlo(x, 3)
2707
2708#define mthi0(x) _dsp_mthi(x, 0)
2709#define mthi1(x) _dsp_mthi(x, 1)
2710#define mthi2(x) _dsp_mthi(x, 2)
2711#define mthi3(x) _dsp_mthi(x, 3)
2712
2713#endif
2714
2715/*
2716 * TLB operations.
2717 *
2718 * It is responsibility of the caller to take care of any TLB hazards.
2719 */
2720static inline void tlb_probe(void)
2721{
2722 __asm__ __volatile__(
2723 ".set noreorder\n\t"
2724 "tlbp\n\t"
2725 ".set reorder");
2726}
2727
2728static inline void tlb_read(void)
2729{
2730#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2731 int res = 0;
2732
2733 __asm__ __volatile__(
2734 " .set push \n"
2735 " .set noreorder \n"
2736 " .set noat \n"
2737 " .set mips32r2 \n"
2738 " .word 0x41610001 # dvpe $1 \n"
2739 " move %0, $1 \n"
2740 " ehb \n"
2741 " .set pop \n"
2742 : "=r" (res));
2743
2744 instruction_hazard();
2745#endif
2746
2747 __asm__ __volatile__(
2748 ".set noreorder\n\t"
2749 "tlbr\n\t"
2750 ".set reorder");
2751
2752#ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2753 if ((res & _ULCAST_(1)))
2754 __asm__ __volatile__(
2755 " .set push \n"
2756 " .set noreorder \n"
2757 " .set noat \n"
2758 " .set mips32r2 \n"
2759 " .word 0x41600021 # evpe \n"
2760 " ehb \n"
2761 " .set pop \n");
2762#endif
2763}
2764
2765static inline void tlb_write_indexed(void)
2766{
2767 __asm__ __volatile__(
2768 ".set noreorder\n\t"
2769 "tlbwi\n\t"
2770 ".set reorder");
2771}
2772
2773static inline void tlb_write_random(void)
2774{
2775 __asm__ __volatile__(
2776 ".set noreorder\n\t"
2777 "tlbwr\n\t"
2778 ".set reorder");
2779}
2780
2781/*
2782 * Guest TLB operations.
2783 *
2784 * It is responsibility of the caller to take care of any TLB hazards.
2785 */
2786static inline void guest_tlb_probe(void)
2787{
2788 __asm__ __volatile__(
2789 ".set push\n\t"
2790 ".set noreorder\n\t"
2791 _ASM_SET_VIRT
2792 "tlbgp\n\t"
2793 ".set pop");
2794}
2795
2796static inline void guest_tlb_read(void)
2797{
2798 __asm__ __volatile__(
2799 ".set push\n\t"
2800 ".set noreorder\n\t"
2801 _ASM_SET_VIRT
2802 "tlbgr\n\t"
2803 ".set pop");
2804}
2805
2806static inline void guest_tlb_write_indexed(void)
2807{
2808 __asm__ __volatile__(
2809 ".set push\n\t"
2810 ".set noreorder\n\t"
2811 _ASM_SET_VIRT
2812 "tlbgwi\n\t"
2813 ".set pop");
2814}
2815
2816static inline void guest_tlb_write_random(void)
2817{
2818 __asm__ __volatile__(
2819 ".set push\n\t"
2820 ".set noreorder\n\t"
2821 _ASM_SET_VIRT
2822 "tlbgwr\n\t"
2823 ".set pop");
2824}
2825
2826/*
2827 * Guest TLB Invalidate Flush
2828 */
2829static inline void guest_tlbinvf(void)
2830{
2831 __asm__ __volatile__(
2832 ".set push\n\t"
2833 ".set noreorder\n\t"
2834 _ASM_SET_VIRT
2835 "tlbginvf\n\t"
2836 ".set pop");
2837}
2838
2839/*
2840 * Manipulate bits in a register.
2841 */
2842#define __BUILD_SET_COMMON(name) \
2843static inline unsigned int \
2844set_##name(unsigned int set) \
2845{ \
2846 unsigned int res, new; \
2847 \
2848 res = read_##name(); \
2849 new = res | set; \
2850 write_##name(new); \
2851 \
2852 return res; \
2853} \
2854 \
2855static inline unsigned int \
2856clear_##name(unsigned int clear) \
2857{ \
2858 unsigned int res, new; \
2859 \
2860 res = read_##name(); \
2861 new = res & ~clear; \
2862 write_##name(new); \
2863 \
2864 return res; \
2865} \
2866 \
2867static inline unsigned int \
2868change_##name(unsigned int change, unsigned int val) \
2869{ \
2870 unsigned int res, new; \
2871 \
2872 res = read_##name(); \
2873 new = res & ~change; \
2874 new |= (val & change); \
2875 write_##name(new); \
2876 \
2877 return res; \
2878}
2879
2880/*
2881 * Manipulate bits in a c0 register.
2882 */
2883#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2884
2885__BUILD_SET_C0(status)
2886__BUILD_SET_C0(cause)
2887__BUILD_SET_C0(config)
2888__BUILD_SET_C0(config5)
2889__BUILD_SET_C0(config6)
2890__BUILD_SET_C0(config7)
2891__BUILD_SET_C0(diag)
2892__BUILD_SET_C0(intcontrol)
2893__BUILD_SET_C0(intctl)
2894__BUILD_SET_C0(srsmap)
2895__BUILD_SET_C0(pagegrain)
2896__BUILD_SET_C0(guestctl0)
2897__BUILD_SET_C0(guestctl0ext)
2898__BUILD_SET_C0(guestctl1)
2899__BUILD_SET_C0(guestctl2)
2900__BUILD_SET_C0(guestctl3)
2901__BUILD_SET_C0(brcm_config_0)
2902__BUILD_SET_C0(brcm_bus_pll)
2903__BUILD_SET_C0(brcm_reset)
2904__BUILD_SET_C0(brcm_cmt_intr)
2905__BUILD_SET_C0(brcm_cmt_ctrl)
2906__BUILD_SET_C0(brcm_config)
2907__BUILD_SET_C0(brcm_mode)
2908
2909/*
2910 * Manipulate bits in a guest c0 register.
2911 */
2912#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2913
2914__BUILD_SET_GC0(wired)
2915__BUILD_SET_GC0(status)
2916__BUILD_SET_GC0(cause)
2917__BUILD_SET_GC0(ebase)
2918__BUILD_SET_GC0(config1)
2919
2920/*
2921 * Return low 10 bits of ebase.
2922 * Note that under KVM (MIPSVZ) this returns vcpu id.
2923 */
2924static inline unsigned int get_ebase_cpunum(void)
2925{
2926 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2927}
2928
2929#endif /* !__ASSEMBLY__ */
2930
2931#endif /* _ASM_MIPSREGS_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/isa-rev.h>
20#include <asm/war.h>
21
22/*
23 * The following macros are especially useful for __asm__
24 * inline assembler.
25 */
26#ifndef __STR
27#define __STR(x) #x
28#endif
29#ifndef STR
30#define STR(x) __STR(x)
31#endif
32
33/*
34 * Configure language
35 */
36#ifdef __ASSEMBLY__
37#define _ULCAST_
38#define _U64CAST_
39#else
40#define _ULCAST_ (unsigned long)
41#define _U64CAST_ (u64)
42#endif
43
44/*
45 * Coprocessor 0 register names
46 */
47#define CP0_INDEX $0
48#define CP0_RANDOM $1
49#define CP0_ENTRYLO0 $2
50#define CP0_ENTRYLO1 $3
51#define CP0_CONF $3
52#define CP0_GLOBALNUMBER $3, 1
53#define CP0_CONTEXT $4
54#define CP0_PAGEMASK $5
55#define CP0_PAGEGRAIN $5, 1
56#define CP0_SEGCTL0 $5, 2
57#define CP0_SEGCTL1 $5, 3
58#define CP0_SEGCTL2 $5, 4
59#define CP0_WIRED $6
60#define CP0_INFO $7
61#define CP0_HWRENA $7
62#define CP0_BADVADDR $8
63#define CP0_BADINSTR $8, 1
64#define CP0_COUNT $9
65#define CP0_ENTRYHI $10
66#define CP0_GUESTCTL1 $10, 4
67#define CP0_GUESTCTL2 $10, 5
68#define CP0_GUESTCTL3 $10, 6
69#define CP0_COMPARE $11
70#define CP0_GUESTCTL0EXT $11, 4
71#define CP0_STATUS $12
72#define CP0_GUESTCTL0 $12, 6
73#define CP0_GTOFFSET $12, 7
74#define CP0_CAUSE $13
75#define CP0_EPC $14
76#define CP0_PRID $15
77#define CP0_EBASE $15, 1
78#define CP0_CMGCRBASE $15, 3
79#define CP0_CONFIG $16
80#define CP0_CONFIG3 $16, 3
81#define CP0_CONFIG5 $16, 5
82#define CP0_CONFIG6 $16, 6
83#define CP0_LLADDR $17
84#define CP0_WATCHLO $18
85#define CP0_WATCHHI $19
86#define CP0_XCONTEXT $20
87#define CP0_FRAMEMASK $21
88#define CP0_DIAGNOSTIC $22
89#define CP0_DIAGNOSTIC1 $22, 1
90#define CP0_DEBUG $23
91#define CP0_DEPC $24
92#define CP0_PERFORMANCE $25
93#define CP0_ECC $26
94#define CP0_CACHEERR $27
95#define CP0_TAGLO $28
96#define CP0_TAGHI $29
97#define CP0_ERROREPC $30
98#define CP0_DESAVE $31
99
100/*
101 * R4640/R4650 cp0 register names. These registers are listed
102 * here only for completeness; without MMU these CPUs are not useable
103 * by Linux. A future ELKS port might take make Linux run on them
104 * though ...
105 */
106#define CP0_IBASE $0
107#define CP0_IBOUND $1
108#define CP0_DBASE $2
109#define CP0_DBOUND $3
110#define CP0_CALG $17
111#define CP0_IWATCH $18
112#define CP0_DWATCH $19
113
114/*
115 * Coprocessor 0 Set 1 register names
116 */
117#define CP0_S1_DERRADDR0 $26
118#define CP0_S1_DERRADDR1 $27
119#define CP0_S1_INTCONTROL $20
120
121/*
122 * Coprocessor 0 Set 2 register names
123 */
124#define CP0_S2_SRSCTL $12 /* MIPSR2 */
125
126/*
127 * Coprocessor 0 Set 3 register names
128 */
129#define CP0_S3_SRSMAP $12 /* MIPSR2 */
130
131/*
132 * TX39 Series
133 */
134#define CP0_TX39_CACHE $7
135
136
137/* Generic EntryLo bit definitions */
138#define ENTRYLO_G (_ULCAST_(1) << 0)
139#define ENTRYLO_V (_ULCAST_(1) << 1)
140#define ENTRYLO_D (_ULCAST_(1) << 2)
141#define ENTRYLO_C_SHIFT 3
142#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
143
144/* R3000 EntryLo bit definitions */
145#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
146#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
147#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
148#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
149
150/* MIPS32/64 EntryLo bit definitions */
151#define MIPS_ENTRYLO_PFN_SHIFT 6
152#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
153#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
154
155/*
156 * MIPSr6+ GlobalNumber register definitions
157 */
158#define MIPS_GLOBALNUMBER_VP_SHF 0
159#define MIPS_GLOBALNUMBER_VP (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
160#define MIPS_GLOBALNUMBER_CORE_SHF 8
161#define MIPS_GLOBALNUMBER_CORE (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
162#define MIPS_GLOBALNUMBER_CLUSTER_SHF 16
163#define MIPS_GLOBALNUMBER_CLUSTER (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
164
165/*
166 * Values for PageMask register
167 */
168#ifdef CONFIG_CPU_VR41XX
169
170/* Why doesn't stupidity hurt ... */
171
172#define PM_1K 0x00000000
173#define PM_4K 0x00001800
174#define PM_16K 0x00007800
175#define PM_64K 0x0001f800
176#define PM_256K 0x0007f800
177
178#else
179
180#define PM_4K 0x00000000
181#define PM_8K 0x00002000
182#define PM_16K 0x00006000
183#define PM_32K 0x0000e000
184#define PM_64K 0x0001e000
185#define PM_128K 0x0003e000
186#define PM_256K 0x0007e000
187#define PM_512K 0x000fe000
188#define PM_1M 0x001fe000
189#define PM_2M 0x003fe000
190#define PM_4M 0x007fe000
191#define PM_8M 0x00ffe000
192#define PM_16M 0x01ffe000
193#define PM_32M 0x03ffe000
194#define PM_64M 0x07ffe000
195#define PM_256M 0x1fffe000
196#define PM_1G 0x7fffe000
197
198#endif
199
200/*
201 * Default page size for a given kernel configuration
202 */
203#ifdef CONFIG_PAGE_SIZE_4KB
204#define PM_DEFAULT_MASK PM_4K
205#elif defined(CONFIG_PAGE_SIZE_8KB)
206#define PM_DEFAULT_MASK PM_8K
207#elif defined(CONFIG_PAGE_SIZE_16KB)
208#define PM_DEFAULT_MASK PM_16K
209#elif defined(CONFIG_PAGE_SIZE_32KB)
210#define PM_DEFAULT_MASK PM_32K
211#elif defined(CONFIG_PAGE_SIZE_64KB)
212#define PM_DEFAULT_MASK PM_64K
213#else
214#error Bad page size configuration!
215#endif
216
217/*
218 * Default huge tlb size for a given kernel configuration
219 */
220#ifdef CONFIG_PAGE_SIZE_4KB
221#define PM_HUGE_MASK PM_1M
222#elif defined(CONFIG_PAGE_SIZE_8KB)
223#define PM_HUGE_MASK PM_4M
224#elif defined(CONFIG_PAGE_SIZE_16KB)
225#define PM_HUGE_MASK PM_16M
226#elif defined(CONFIG_PAGE_SIZE_32KB)
227#define PM_HUGE_MASK PM_64M
228#elif defined(CONFIG_PAGE_SIZE_64KB)
229#define PM_HUGE_MASK PM_256M
230#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
231#error Bad page size configuration for hugetlbfs!
232#endif
233
234/*
235 * Wired register bits
236 */
237#define MIPSR6_WIRED_LIMIT_SHIFT 16
238#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
239#define MIPSR6_WIRED_WIRED_SHIFT 0
240#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
241
242/*
243 * Values used for computation of new tlb entries
244 */
245#define PL_4K 12
246#define PL_16K 14
247#define PL_64K 16
248#define PL_256K 18
249#define PL_1M 20
250#define PL_4M 22
251#define PL_16M 24
252#define PL_64M 26
253#define PL_256M 28
254
255/*
256 * PageGrain bits
257 */
258#define PG_RIE (_ULCAST_(1) << 31)
259#define PG_XIE (_ULCAST_(1) << 30)
260#define PG_ELPA (_ULCAST_(1) << 29)
261#define PG_ESP (_ULCAST_(1) << 28)
262#define PG_IEC (_ULCAST_(1) << 27)
263
264/* MIPS32/64 EntryHI bit definitions */
265#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
266#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
267#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
268
269/*
270 * R4x00 interrupt enable / cause bits
271 */
272#define IE_SW0 (_ULCAST_(1) << 8)
273#define IE_SW1 (_ULCAST_(1) << 9)
274#define IE_IRQ0 (_ULCAST_(1) << 10)
275#define IE_IRQ1 (_ULCAST_(1) << 11)
276#define IE_IRQ2 (_ULCAST_(1) << 12)
277#define IE_IRQ3 (_ULCAST_(1) << 13)
278#define IE_IRQ4 (_ULCAST_(1) << 14)
279#define IE_IRQ5 (_ULCAST_(1) << 15)
280
281/*
282 * R4x00 interrupt cause bits
283 */
284#define C_SW0 (_ULCAST_(1) << 8)
285#define C_SW1 (_ULCAST_(1) << 9)
286#define C_IRQ0 (_ULCAST_(1) << 10)
287#define C_IRQ1 (_ULCAST_(1) << 11)
288#define C_IRQ2 (_ULCAST_(1) << 12)
289#define C_IRQ3 (_ULCAST_(1) << 13)
290#define C_IRQ4 (_ULCAST_(1) << 14)
291#define C_IRQ5 (_ULCAST_(1) << 15)
292
293/*
294 * Bitfields in the R4xx0 cp0 status register
295 */
296#define ST0_IE 0x00000001
297#define ST0_EXL 0x00000002
298#define ST0_ERL 0x00000004
299#define ST0_KSU 0x00000018
300# define KSU_USER 0x00000010
301# define KSU_SUPERVISOR 0x00000008
302# define KSU_KERNEL 0x00000000
303#define ST0_UX 0x00000020
304#define ST0_SX 0x00000040
305#define ST0_KX 0x00000080
306#define ST0_DE 0x00010000
307#define ST0_CE 0x00020000
308
309/*
310 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
311 * cacheops in userspace. This bit exists only on RM7000 and RM9000
312 * processors.
313 */
314#define ST0_CO 0x08000000
315
316/*
317 * Bitfields in the R[23]000 cp0 status register.
318 */
319#define ST0_IEC 0x00000001
320#define ST0_KUC 0x00000002
321#define ST0_IEP 0x00000004
322#define ST0_KUP 0x00000008
323#define ST0_IEO 0x00000010
324#define ST0_KUO 0x00000020
325/* bits 6 & 7 are reserved on R[23]000 */
326#define ST0_ISC 0x00010000
327#define ST0_SWC 0x00020000
328#define ST0_CM 0x00080000
329
330/*
331 * Bits specific to the R4640/R4650
332 */
333#define ST0_UM (_ULCAST_(1) << 4)
334#define ST0_IL (_ULCAST_(1) << 23)
335#define ST0_DL (_ULCAST_(1) << 24)
336
337/*
338 * Enable the MIPS MDMX and DSP ASEs
339 */
340#define ST0_MX 0x01000000
341
342/*
343 * Status register bits available in all MIPS CPUs.
344 */
345#define ST0_IM 0x0000ff00
346#define STATUSB_IP0 8
347#define STATUSF_IP0 (_ULCAST_(1) << 8)
348#define STATUSB_IP1 9
349#define STATUSF_IP1 (_ULCAST_(1) << 9)
350#define STATUSB_IP2 10
351#define STATUSF_IP2 (_ULCAST_(1) << 10)
352#define STATUSB_IP3 11
353#define STATUSF_IP3 (_ULCAST_(1) << 11)
354#define STATUSB_IP4 12
355#define STATUSF_IP4 (_ULCAST_(1) << 12)
356#define STATUSB_IP5 13
357#define STATUSF_IP5 (_ULCAST_(1) << 13)
358#define STATUSB_IP6 14
359#define STATUSF_IP6 (_ULCAST_(1) << 14)
360#define STATUSB_IP7 15
361#define STATUSF_IP7 (_ULCAST_(1) << 15)
362#define STATUSB_IP8 0
363#define STATUSF_IP8 (_ULCAST_(1) << 0)
364#define STATUSB_IP9 1
365#define STATUSF_IP9 (_ULCAST_(1) << 1)
366#define STATUSB_IP10 2
367#define STATUSF_IP10 (_ULCAST_(1) << 2)
368#define STATUSB_IP11 3
369#define STATUSF_IP11 (_ULCAST_(1) << 3)
370#define STATUSB_IP12 4
371#define STATUSF_IP12 (_ULCAST_(1) << 4)
372#define STATUSB_IP13 5
373#define STATUSF_IP13 (_ULCAST_(1) << 5)
374#define STATUSB_IP14 6
375#define STATUSF_IP14 (_ULCAST_(1) << 6)
376#define STATUSB_IP15 7
377#define STATUSF_IP15 (_ULCAST_(1) << 7)
378#define ST0_CH 0x00040000
379#define ST0_NMI 0x00080000
380#define ST0_SR 0x00100000
381#define ST0_TS 0x00200000
382#define ST0_BEV 0x00400000
383#define ST0_RE 0x02000000
384#define ST0_FR 0x04000000
385#define ST0_CU 0xf0000000
386#define ST0_CU0 0x10000000
387#define ST0_CU1 0x20000000
388#define ST0_CU2 0x40000000
389#define ST0_CU3 0x80000000
390#define ST0_XX 0x80000000 /* MIPS IV naming */
391
392/*
393 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
394 */
395#define INTCTLB_IPFDC 23
396#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
397#define INTCTLB_IPPCI 26
398#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
399#define INTCTLB_IPTI 29
400#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
401
402/*
403 * Bitfields and bit numbers in the coprocessor 0 cause register.
404 *
405 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
406 */
407#define CAUSEB_EXCCODE 2
408#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
409#define CAUSEB_IP 8
410#define CAUSEF_IP (_ULCAST_(255) << 8)
411#define CAUSEB_IP0 8
412#define CAUSEF_IP0 (_ULCAST_(1) << 8)
413#define CAUSEB_IP1 9
414#define CAUSEF_IP1 (_ULCAST_(1) << 9)
415#define CAUSEB_IP2 10
416#define CAUSEF_IP2 (_ULCAST_(1) << 10)
417#define CAUSEB_IP3 11
418#define CAUSEF_IP3 (_ULCAST_(1) << 11)
419#define CAUSEB_IP4 12
420#define CAUSEF_IP4 (_ULCAST_(1) << 12)
421#define CAUSEB_IP5 13
422#define CAUSEF_IP5 (_ULCAST_(1) << 13)
423#define CAUSEB_IP6 14
424#define CAUSEF_IP6 (_ULCAST_(1) << 14)
425#define CAUSEB_IP7 15
426#define CAUSEF_IP7 (_ULCAST_(1) << 15)
427#define CAUSEB_FDCI 21
428#define CAUSEF_FDCI (_ULCAST_(1) << 21)
429#define CAUSEB_WP 22
430#define CAUSEF_WP (_ULCAST_(1) << 22)
431#define CAUSEB_IV 23
432#define CAUSEF_IV (_ULCAST_(1) << 23)
433#define CAUSEB_PCI 26
434#define CAUSEF_PCI (_ULCAST_(1) << 26)
435#define CAUSEB_DC 27
436#define CAUSEF_DC (_ULCAST_(1) << 27)
437#define CAUSEB_CE 28
438#define CAUSEF_CE (_ULCAST_(3) << 28)
439#define CAUSEB_TI 30
440#define CAUSEF_TI (_ULCAST_(1) << 30)
441#define CAUSEB_BD 31
442#define CAUSEF_BD (_ULCAST_(1) << 31)
443
444/*
445 * Cause.ExcCode trap codes.
446 */
447#define EXCCODE_INT 0 /* Interrupt pending */
448#define EXCCODE_MOD 1 /* TLB modified fault */
449#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
450#define EXCCODE_TLBS 3 /* TLB miss on a store */
451#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
452#define EXCCODE_ADES 5 /* Address error on a store */
453#define EXCCODE_IBE 6 /* Bus error on an ifetch */
454#define EXCCODE_DBE 7 /* Bus error on a load or store */
455#define EXCCODE_SYS 8 /* System call */
456#define EXCCODE_BP 9 /* Breakpoint */
457#define EXCCODE_RI 10 /* Reserved instruction exception */
458#define EXCCODE_CPU 11 /* Coprocessor unusable */
459#define EXCCODE_OV 12 /* Arithmetic overflow */
460#define EXCCODE_TR 13 /* Trap instruction */
461#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
462#define EXCCODE_FPE 15 /* Floating point exception */
463#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
464#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
465#define EXCCODE_MSADIS 21 /* MSA disabled exception */
466#define EXCCODE_MDMX 22 /* MDMX unusable exception */
467#define EXCCODE_WATCH 23 /* Watch address reference */
468#define EXCCODE_MCHECK 24 /* Machine check */
469#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
470#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
471#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
472#define EXCCODE_CACHEERR 30 /* Parity/ECC occured on a core */
473
474/* Implementation specific trap codes used by MIPS cores */
475#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
476
477/* Implementation specific trap codes used by Loongson cores */
478#define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
479
480/*
481 * Bits in the coprocessor 0 config register.
482 */
483/* Generic bits. */
484#define CONF_CM_CACHABLE_NO_WA 0
485#define CONF_CM_CACHABLE_WA 1
486#define CONF_CM_UNCACHED 2
487#define CONF_CM_CACHABLE_NONCOHERENT 3
488#define CONF_CM_CACHABLE_CE 4
489#define CONF_CM_CACHABLE_COW 5
490#define CONF_CM_CACHABLE_CUW 6
491#define CONF_CM_CACHABLE_ACCELERATED 7
492#define CONF_CM_CMASK 7
493#define CONF_BE (_ULCAST_(1) << 15)
494
495/* Bits common to various processors. */
496#define CONF_CU (_ULCAST_(1) << 3)
497#define CONF_DB (_ULCAST_(1) << 4)
498#define CONF_IB (_ULCAST_(1) << 5)
499#define CONF_DC (_ULCAST_(7) << 6)
500#define CONF_IC (_ULCAST_(7) << 9)
501#define CONF_EB (_ULCAST_(1) << 13)
502#define CONF_EM (_ULCAST_(1) << 14)
503#define CONF_SM (_ULCAST_(1) << 16)
504#define CONF_SC (_ULCAST_(1) << 17)
505#define CONF_EW (_ULCAST_(3) << 18)
506#define CONF_EP (_ULCAST_(15)<< 24)
507#define CONF_EC (_ULCAST_(7) << 28)
508#define CONF_CM (_ULCAST_(1) << 31)
509
510/* Bits specific to the R4xx0. */
511#define R4K_CONF_SW (_ULCAST_(1) << 20)
512#define R4K_CONF_SS (_ULCAST_(1) << 21)
513#define R4K_CONF_SB (_ULCAST_(3) << 22)
514
515/* Bits specific to the R5000. */
516#define R5K_CONF_SE (_ULCAST_(1) << 12)
517#define R5K_CONF_SS (_ULCAST_(3) << 20)
518
519/* Bits specific to the RM7000. */
520#define RM7K_CONF_SE (_ULCAST_(1) << 3)
521#define RM7K_CONF_TE (_ULCAST_(1) << 12)
522#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
523#define RM7K_CONF_TC (_ULCAST_(1) << 17)
524#define RM7K_CONF_SI (_ULCAST_(3) << 20)
525#define RM7K_CONF_SC (_ULCAST_(1) << 31)
526
527/* Bits specific to the R10000. */
528#define R10K_CONF_DN (_ULCAST_(3) << 3)
529#define R10K_CONF_CT (_ULCAST_(1) << 5)
530#define R10K_CONF_PE (_ULCAST_(1) << 6)
531#define R10K_CONF_PM (_ULCAST_(3) << 7)
532#define R10K_CONF_EC (_ULCAST_(15)<< 9)
533#define R10K_CONF_SB (_ULCAST_(1) << 13)
534#define R10K_CONF_SK (_ULCAST_(1) << 14)
535#define R10K_CONF_SS (_ULCAST_(7) << 16)
536#define R10K_CONF_SC (_ULCAST_(7) << 19)
537#define R10K_CONF_DC (_ULCAST_(7) << 26)
538#define R10K_CONF_IC (_ULCAST_(7) << 29)
539
540/* Bits specific to the VR41xx. */
541#define VR41_CONF_CS (_ULCAST_(1) << 12)
542#define VR41_CONF_P4K (_ULCAST_(1) << 13)
543#define VR41_CONF_BP (_ULCAST_(1) << 16)
544#define VR41_CONF_M16 (_ULCAST_(1) << 20)
545#define VR41_CONF_AD (_ULCAST_(1) << 23)
546
547/* Bits specific to the R30xx. */
548#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
549#define R30XX_CONF_REV (_ULCAST_(1) << 22)
550#define R30XX_CONF_AC (_ULCAST_(1) << 23)
551#define R30XX_CONF_RF (_ULCAST_(1) << 24)
552#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
553#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
554#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
555#define R30XX_CONF_SB (_ULCAST_(1) << 30)
556#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
557
558/* Bits specific to the TX49. */
559#define TX49_CONF_DC (_ULCAST_(1) << 16)
560#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
561#define TX49_CONF_HALT (_ULCAST_(1) << 18)
562#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
563
564/* Bits specific to the MIPS32/64 PRA. */
565#define MIPS_CONF_VI (_ULCAST_(1) << 3)
566#define MIPS_CONF_MT (_ULCAST_(7) << 7)
567#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
568#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
569#define MIPS_CONF_AR (_ULCAST_(7) << 10)
570#define MIPS_CONF_AT (_ULCAST_(3) << 13)
571#define MIPS_CONF_BE (_ULCAST_(1) << 15)
572#define MIPS_CONF_BM (_ULCAST_(1) << 16)
573#define MIPS_CONF_MM (_ULCAST_(3) << 17)
574#define MIPS_CONF_MM_SYSAD (_ULCAST_(1) << 17)
575#define MIPS_CONF_MM_FULL (_ULCAST_(2) << 17)
576#define MIPS_CONF_SB (_ULCAST_(1) << 21)
577#define MIPS_CONF_UDI (_ULCAST_(1) << 22)
578#define MIPS_CONF_DSP (_ULCAST_(1) << 23)
579#define MIPS_CONF_ISP (_ULCAST_(1) << 24)
580#define MIPS_CONF_KU (_ULCAST_(3) << 25)
581#define MIPS_CONF_K23 (_ULCAST_(3) << 28)
582#define MIPS_CONF_M (_ULCAST_(1) << 31)
583
584/*
585 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
586 */
587#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
588#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
589#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
590#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
591#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
592#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
593#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
594#define MIPS_CONF1_DA_SHF 7
595#define MIPS_CONF1_DA_SZ 3
596#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
597#define MIPS_CONF1_DL_SHF 10
598#define MIPS_CONF1_DL_SZ 3
599#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
600#define MIPS_CONF1_DS_SHF 13
601#define MIPS_CONF1_DS_SZ 3
602#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
603#define MIPS_CONF1_IA_SHF 16
604#define MIPS_CONF1_IA_SZ 3
605#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
606#define MIPS_CONF1_IL_SHF 19
607#define MIPS_CONF1_IL_SZ 3
608#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
609#define MIPS_CONF1_IS_SHF 22
610#define MIPS_CONF1_IS_SZ 3
611#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
612#define MIPS_CONF1_TLBS_SHIFT (25)
613#define MIPS_CONF1_TLBS_SIZE (6)
614#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
615
616#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
617#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
618#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
619#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
620#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
621#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
622#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
623#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
624
625#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
626#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
627#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
628#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
629#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
630#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
631#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
632#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
633#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
634#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
635#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
636#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
637#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
638#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
639#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
640#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
641#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
642#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
643#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
644#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
645#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
646#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
647#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
648#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
649#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
650#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
651#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
652
653#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
654#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
655#define MIPS_CONF4_FTLBSETS_SHIFT (0)
656#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
657#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
658#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
659#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
660/* bits 10:8 in FTLB-only configurations */
661#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
662/* bits 12:8 in VTLB-FTLB only configurations */
663#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
664#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
665#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
666#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
667#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
668#define MIPS_CONF4_KSCREXIST_SHIFT (16)
669#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
670#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
671#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
672#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
673#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
674#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
675
676#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
677#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
678#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
679#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
680#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
681#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
682#define MIPS_CONF5_SBRI (_ULCAST_(1) << 6)
683#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
684#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
685#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
686#define MIPS_CONF5_MI (_ULCAST_(1) << 17)
687#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
688#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
689#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
690#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
691#define MIPS_CONF5_K (_ULCAST_(1) << 30)
692
693/* Config6 feature bits for proAptiv/P5600 */
694
695/* Jump register cache prediction disable */
696#define MTI_CONF6_JRCD (_ULCAST_(1) << 0)
697/* MIPSr6 extensions enable */
698#define MTI_CONF6_R6 (_ULCAST_(1) << 2)
699/* IFU Performance Control */
700#define MTI_CONF6_IFUPERFCTL (_ULCAST_(3) << 10)
701#define MTI_CONF6_SYND (_ULCAST_(1) << 13)
702/* Sleep state performance counter disable */
703#define MTI_CONF6_SPCD (_ULCAST_(1) << 14)
704/* proAptiv FTLB on/off bit */
705#define MTI_CONF6_FTLBEN (_ULCAST_(1) << 15)
706/* Disable load/store bonding */
707#define MTI_CONF6_DLSB (_ULCAST_(1) << 21)
708/* FTLB probability bits */
709#define MTI_CONF6_FTLBP_SHIFT (16)
710
711/* Config6 feature bits for Loongson-3 */
712
713/* Loongson-3 internal timer bit */
714#define LOONGSON_CONF6_INTIMER (_ULCAST_(1) << 6)
715/* Loongson-3 external timer bit */
716#define LOONGSON_CONF6_EXTIMER (_ULCAST_(1) << 7)
717/* Loongson-3 SFB on/off bit, STFill in manual */
718#define LOONGSON_CONF6_SFBEN (_ULCAST_(1) << 8)
719/* Loongson-3's LL on exclusive cacheline */
720#define LOONGSON_CONF6_LLEXC (_ULCAST_(1) << 16)
721/* Loongson-3's SC has a random delay */
722#define LOONGSON_CONF6_SCRAND (_ULCAST_(1) << 17)
723/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
724#define LOONGSON_CONF6_FTLBDIS (_ULCAST_(1) << 22)
725
726#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
727
728#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
729
730#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
731#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
732
733/* Ingenic HPTLB off bits */
734#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
735
736/* Ingenic Config7 bits */
737#define MIPS_CONF7_BTB_LOOP_EN (_ULCAST_(1) << 4)
738
739/* Config7 Bits specific to MIPS Technologies. */
740
741/* Performance counters implemented Per TC */
742#define MTI_CONF7_PTC (_ULCAST_(1) << 19)
743
744/* WatchLo* register definitions */
745#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
746
747/* WatchHi* register definitions */
748#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
749#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
750#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
751#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
752#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
753#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
754#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
755#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
756#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
757#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
758#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
759#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
760#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
761
762/* PerfCnt control register definitions */
763#define MIPS_PERFCTRL_EXL (_ULCAST_(1) << 0)
764#define MIPS_PERFCTRL_K (_ULCAST_(1) << 1)
765#define MIPS_PERFCTRL_S (_ULCAST_(1) << 2)
766#define MIPS_PERFCTRL_U (_ULCAST_(1) << 3)
767#define MIPS_PERFCTRL_IE (_ULCAST_(1) << 4)
768#define MIPS_PERFCTRL_EVENT_S 5
769#define MIPS_PERFCTRL_EVENT (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
770#define MIPS_PERFCTRL_PCTD (_ULCAST_(1) << 15)
771#define MIPS_PERFCTRL_EC (_ULCAST_(0x3) << 23)
772#define MIPS_PERFCTRL_EC_R (_ULCAST_(0) << 23)
773#define MIPS_PERFCTRL_EC_RI (_ULCAST_(1) << 23)
774#define MIPS_PERFCTRL_EC_G (_ULCAST_(2) << 23)
775#define MIPS_PERFCTRL_EC_GRI (_ULCAST_(3) << 23)
776#define MIPS_PERFCTRL_W (_ULCAST_(1) << 30)
777#define MIPS_PERFCTRL_M (_ULCAST_(1) << 31)
778
779/* PerfCnt control register MT extensions used by MIPS cores */
780#define MIPS_PERFCTRL_VPEID_S 16
781#define MIPS_PERFCTRL_VPEID (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
782#define MIPS_PERFCTRL_TCID_S 22
783#define MIPS_PERFCTRL_TCID (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
784#define MIPS_PERFCTRL_MT_EN (_ULCAST_(0x3) << 20)
785#define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
786#define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
787#define MIPS_PERFCTRL_MT_EN_TC (_ULCAST_(2) << 20)
788
789/* PerfCnt control register MT extensions used by BMIPS5000 */
790#define BRCM_PERFCTRL_TC (_ULCAST_(1) << 30)
791
792/* PerfCnt control register MT extensions used by Netlogic XLR */
793#define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
794
795/* MAAR bit definitions */
796#define MIPS_MAAR_VH (_U64CAST_(1) << 63)
797#define MIPS_MAAR_ADDR GENMASK_ULL(55, 12)
798#define MIPS_MAAR_ADDR_SHIFT 12
799#define MIPS_MAAR_S (_ULCAST_(1) << 1)
800#define MIPS_MAAR_VL (_ULCAST_(1) << 0)
801#ifdef CONFIG_XPA
802#define MIPS_MAAR_V (MIPS_MAAR_VH | MIPS_MAAR_VL)
803#else
804#define MIPS_MAAR_V MIPS_MAAR_VL
805#endif
806#define MIPS_MAARX_VH (_ULCAST_(1) << 31)
807#define MIPS_MAARX_ADDR 0xF
808#define MIPS_MAARX_ADDR_SHIFT 32
809
810/* MAARI bit definitions */
811#define MIPS_MAARI_INDEX (_ULCAST_(0x3f) << 0)
812
813/* EBase bit definitions */
814#define MIPS_EBASE_CPUNUM_SHIFT 0
815#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
816#define MIPS_EBASE_WG_SHIFT 11
817#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
818#define MIPS_EBASE_BASE_SHIFT 12
819#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
820
821/* CMGCRBase bit definitions */
822#define MIPS_CMGCRB_BASE 11
823#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
824
825/* LLAddr bit definitions */
826#define MIPS_LLADDR_LLB_SHIFT 0
827#define MIPS_LLADDR_LLB (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
828
829/*
830 * Bits in the MIPS32 Memory Segmentation registers.
831 */
832#define MIPS_SEGCFG_PA_SHIFT 9
833#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
834#define MIPS_SEGCFG_AM_SHIFT 4
835#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
836#define MIPS_SEGCFG_EU_SHIFT 3
837#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
838#define MIPS_SEGCFG_C_SHIFT 0
839#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
840
841#define MIPS_SEGCFG_UUSK _ULCAST_(7)
842#define MIPS_SEGCFG_USK _ULCAST_(5)
843#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
844#define MIPS_SEGCFG_MUSK _ULCAST_(3)
845#define MIPS_SEGCFG_MSK _ULCAST_(2)
846#define MIPS_SEGCFG_MK _ULCAST_(1)
847#define MIPS_SEGCFG_UK _ULCAST_(0)
848
849#define MIPS_PWFIELD_GDI_SHIFT 24
850#define MIPS_PWFIELD_GDI_MASK 0x3f000000
851#define MIPS_PWFIELD_UDI_SHIFT 18
852#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
853#define MIPS_PWFIELD_MDI_SHIFT 12
854#define MIPS_PWFIELD_MDI_MASK 0x0003f000
855#define MIPS_PWFIELD_PTI_SHIFT 6
856#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
857#define MIPS_PWFIELD_PTEI_SHIFT 0
858#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
859
860#define MIPS_PWSIZE_PS_SHIFT 30
861#define MIPS_PWSIZE_PS_MASK 0x40000000
862#define MIPS_PWSIZE_GDW_SHIFT 24
863#define MIPS_PWSIZE_GDW_MASK 0x3f000000
864#define MIPS_PWSIZE_UDW_SHIFT 18
865#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
866#define MIPS_PWSIZE_MDW_SHIFT 12
867#define MIPS_PWSIZE_MDW_MASK 0x0003f000
868#define MIPS_PWSIZE_PTW_SHIFT 6
869#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
870#define MIPS_PWSIZE_PTEW_SHIFT 0
871#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
872
873#define MIPS_PWCTL_PWEN_SHIFT 31
874#define MIPS_PWCTL_PWEN_MASK 0x80000000
875#define MIPS_PWCTL_XK_SHIFT 28
876#define MIPS_PWCTL_XK_MASK 0x10000000
877#define MIPS_PWCTL_XS_SHIFT 27
878#define MIPS_PWCTL_XS_MASK 0x08000000
879#define MIPS_PWCTL_XU_SHIFT 26
880#define MIPS_PWCTL_XU_MASK 0x04000000
881#define MIPS_PWCTL_DPH_SHIFT 7
882#define MIPS_PWCTL_DPH_MASK 0x00000080
883#define MIPS_PWCTL_HUGEPG_SHIFT 6
884#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
885#define MIPS_PWCTL_PSN_SHIFT 0
886#define MIPS_PWCTL_PSN_MASK 0x0000003f
887
888/* GuestCtl0 fields */
889#define MIPS_GCTL0_GM_SHIFT 31
890#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
891#define MIPS_GCTL0_RI_SHIFT 30
892#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
893#define MIPS_GCTL0_MC_SHIFT 29
894#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
895#define MIPS_GCTL0_CP0_SHIFT 28
896#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
897#define MIPS_GCTL0_AT_SHIFT 26
898#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
899#define MIPS_GCTL0_GT_SHIFT 25
900#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
901#define MIPS_GCTL0_CG_SHIFT 24
902#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
903#define MIPS_GCTL0_CF_SHIFT 23
904#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
905#define MIPS_GCTL0_G1_SHIFT 22
906#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
907#define MIPS_GCTL0_G0E_SHIFT 19
908#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
909#define MIPS_GCTL0_PT_SHIFT 18
910#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
911#define MIPS_GCTL0_RAD_SHIFT 9
912#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
913#define MIPS_GCTL0_DRG_SHIFT 8
914#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
915#define MIPS_GCTL0_G2_SHIFT 7
916#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
917#define MIPS_GCTL0_GEXC_SHIFT 2
918#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
919#define MIPS_GCTL0_SFC2_SHIFT 1
920#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
921#define MIPS_GCTL0_SFC1_SHIFT 0
922#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
923
924/* GuestCtl0.AT Guest address translation control */
925#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
926#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
927
928/* GuestCtl0.GExcCode Hypervisor exception cause codes */
929#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
930#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
931#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
932#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
933#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
934#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
935#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
936
937/* GuestCtl0Ext fields */
938#define MIPS_GCTL0EXT_RPW_SHIFT 8
939#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
940#define MIPS_GCTL0EXT_NCC_SHIFT 6
941#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
942#define MIPS_GCTL0EXT_CGI_SHIFT 4
943#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
944#define MIPS_GCTL0EXT_FCD_SHIFT 3
945#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
946#define MIPS_GCTL0EXT_OG_SHIFT 2
947#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
948#define MIPS_GCTL0EXT_BG_SHIFT 1
949#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
950#define MIPS_GCTL0EXT_MG_SHIFT 0
951#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
952
953/* GuestCtl0Ext.RPW Root page walk configuration */
954#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
955#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
956#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
957
958/* GuestCtl0Ext.NCC Nested cache coherency attributes */
959#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
960#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
961
962/* GuestCtl1 fields */
963#define MIPS_GCTL1_ID_SHIFT 0
964#define MIPS_GCTL1_ID_WIDTH 8
965#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
966#define MIPS_GCTL1_RID_SHIFT 16
967#define MIPS_GCTL1_RID_WIDTH 8
968#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
969#define MIPS_GCTL1_EID_SHIFT 24
970#define MIPS_GCTL1_EID_WIDTH 8
971#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
972
973/* GuestID reserved for root context */
974#define MIPS_GCTL1_ROOT_GUESTID 0
975
976/* CDMMBase register bit definitions */
977#define MIPS_CDMMBASE_SIZE_SHIFT 0
978#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
979#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
980#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
981#define MIPS_CDMMBASE_ADDR_SHIFT 11
982#define MIPS_CDMMBASE_ADDR_START 15
983
984/* RDHWR register numbers */
985#define MIPS_HWR_CPUNUM 0 /* CPU number */
986#define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
987#define MIPS_HWR_CC 2 /* Cycle counter */
988#define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
989#define MIPS_HWR_ULR 29 /* UserLocal */
990#define MIPS_HWR_IMPL1 30 /* Implementation dependent */
991#define MIPS_HWR_IMPL2 31 /* Implementation dependent */
992
993/* Bits in HWREna register */
994#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
995#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
996#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
997#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
998#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
999#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
1000#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
1001
1002/*
1003 * Bitfields in the TX39 family CP0 Configuration Register 3
1004 */
1005#define TX39_CONF_ICS_SHIFT 19
1006#define TX39_CONF_ICS_MASK 0x00380000
1007#define TX39_CONF_ICS_1KB 0x00000000
1008#define TX39_CONF_ICS_2KB 0x00080000
1009#define TX39_CONF_ICS_4KB 0x00100000
1010#define TX39_CONF_ICS_8KB 0x00180000
1011#define TX39_CONF_ICS_16KB 0x00200000
1012
1013#define TX39_CONF_DCS_SHIFT 16
1014#define TX39_CONF_DCS_MASK 0x00070000
1015#define TX39_CONF_DCS_1KB 0x00000000
1016#define TX39_CONF_DCS_2KB 0x00010000
1017#define TX39_CONF_DCS_4KB 0x00020000
1018#define TX39_CONF_DCS_8KB 0x00030000
1019#define TX39_CONF_DCS_16KB 0x00040000
1020
1021#define TX39_CONF_CWFON 0x00004000
1022#define TX39_CONF_WBON 0x00002000
1023#define TX39_CONF_RF_SHIFT 10
1024#define TX39_CONF_RF_MASK 0x00000c00
1025#define TX39_CONF_DOZE 0x00000200
1026#define TX39_CONF_HALT 0x00000100
1027#define TX39_CONF_LOCK 0x00000080
1028#define TX39_CONF_ICE 0x00000020
1029#define TX39_CONF_DCE 0x00000010
1030#define TX39_CONF_IRSIZE_SHIFT 2
1031#define TX39_CONF_IRSIZE_MASK 0x0000000c
1032#define TX39_CONF_DRSIZE_SHIFT 0
1033#define TX39_CONF_DRSIZE_MASK 0x00000003
1034
1035/*
1036 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
1037 */
1038/* Disable Branch Target Address Cache */
1039#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
1040/* Enable Branch Prediction Global History */
1041#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
1042/* Disable Branch Return Cache */
1043#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
1044
1045/* Flush BTB */
1046#define LOONGSON_DIAG_BTB (_ULCAST_(1) << 1)
1047/* Flush ITLB */
1048#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
1049/* Flush DTLB */
1050#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
1051/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1052#define LOONGSON_DIAG_UCAC (_ULCAST_(1) << 8)
1053/* Flush VTLB */
1054#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
1055/* Flush FTLB */
1056#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
1057
1058/*
1059 * Diag1 (GSCause in Loongson-speak) fields
1060 */
1061/* Loongson-specific exception code (GSExcCode) */
1062#define LOONGSON_DIAG1_EXCCODE_SHIFT 2
1063#define LOONGSON_DIAG1_EXCCODE GENMASK(6, 2)
1064
1065/* CvmCtl register field definitions */
1066#define CVMCTL_IPPCI_SHIFT 7
1067#define CVMCTL_IPPCI (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1068#define CVMCTL_IPTI_SHIFT 4
1069#define CVMCTL_IPTI (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1070
1071/* CvmMemCtl2 register field definitions */
1072#define CVMMEMCTL2_INHIBITTS (_U64CAST_(1) << 17)
1073
1074/* CvmVMConfig register field definitions */
1075#define CVMVMCONF_DGHT (_U64CAST_(1) << 60)
1076#define CVMVMCONF_MMUSIZEM1_S 12
1077#define CVMVMCONF_MMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1078#define CVMVMCONF_RMMUSIZEM1_S 0
1079#define CVMVMCONF_RMMUSIZEM1 (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1080
1081/*
1082 * Coprocessor 1 (FPU) register names
1083 */
1084#define CP1_REVISION $0
1085#define CP1_UFR $1
1086#define CP1_UNFR $4
1087#define CP1_FCCR $25
1088#define CP1_FEXR $26
1089#define CP1_FENR $28
1090#define CP1_STATUS $31
1091
1092
1093/*
1094 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1095 */
1096#define MIPS_FPIR_S (_ULCAST_(1) << 16)
1097#define MIPS_FPIR_D (_ULCAST_(1) << 17)
1098#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1099#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
1100#define MIPS_FPIR_W (_ULCAST_(1) << 20)
1101#define MIPS_FPIR_L (_ULCAST_(1) << 21)
1102#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
1103#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
1104#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
1105#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
1106
1107/*
1108 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1109 */
1110#define MIPS_FCCR_CONDX_S 0
1111#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1112#define MIPS_FCCR_COND0_S 0
1113#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1114#define MIPS_FCCR_COND1_S 1
1115#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1116#define MIPS_FCCR_COND2_S 2
1117#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1118#define MIPS_FCCR_COND3_S 3
1119#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1120#define MIPS_FCCR_COND4_S 4
1121#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1122#define MIPS_FCCR_COND5_S 5
1123#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1124#define MIPS_FCCR_COND6_S 6
1125#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1126#define MIPS_FCCR_COND7_S 7
1127#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1128
1129/*
1130 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1131 */
1132#define MIPS_FENR_FS_S 2
1133#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
1134
1135/*
1136 * FPU Status Register Values
1137 */
1138#define FPU_CSR_COND_S 23 /* $fcc0 */
1139#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
1140
1141#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
1142#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
1143
1144#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1145#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
1146#define FPU_CSR_COND1_S 25 /* $fcc1 */
1147#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
1148#define FPU_CSR_COND2_S 26 /* $fcc2 */
1149#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1150#define FPU_CSR_COND3_S 27 /* $fcc3 */
1151#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1152#define FPU_CSR_COND4_S 28 /* $fcc4 */
1153#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1154#define FPU_CSR_COND5_S 29 /* $fcc5 */
1155#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1156#define FPU_CSR_COND6_S 30 /* $fcc6 */
1157#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1158#define FPU_CSR_COND7_S 31 /* $fcc7 */
1159#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1160
1161/*
1162 * Bits 22:20 of the FPU Status Register will be read as 0,
1163 * and should be written as zero.
1164 * MAC2008 was removed in Release 5 so we still treat it as
1165 * reserved.
1166 */
1167#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1168
1169#define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1170#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1171#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1172
1173/*
1174 * X the exception cause indicator
1175 * E the exception enable
1176 * S the sticky/flag bit
1177*/
1178#define FPU_CSR_ALL_X 0x0003f000
1179#define FPU_CSR_UNI_X 0x00020000
1180#define FPU_CSR_INV_X 0x00010000
1181#define FPU_CSR_DIV_X 0x00008000
1182#define FPU_CSR_OVF_X 0x00004000
1183#define FPU_CSR_UDF_X 0x00002000
1184#define FPU_CSR_INE_X 0x00001000
1185
1186#define FPU_CSR_ALL_E 0x00000f80
1187#define FPU_CSR_INV_E 0x00000800
1188#define FPU_CSR_DIV_E 0x00000400
1189#define FPU_CSR_OVF_E 0x00000200
1190#define FPU_CSR_UDF_E 0x00000100
1191#define FPU_CSR_INE_E 0x00000080
1192
1193#define FPU_CSR_ALL_S 0x0000007c
1194#define FPU_CSR_INV_S 0x00000040
1195#define FPU_CSR_DIV_S 0x00000020
1196#define FPU_CSR_OVF_S 0x00000010
1197#define FPU_CSR_UDF_S 0x00000008
1198#define FPU_CSR_INE_S 0x00000004
1199
1200/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1201#define FPU_CSR_RM 0x00000003
1202#define FPU_CSR_RN 0x0 /* nearest */
1203#define FPU_CSR_RZ 0x1 /* towards zero */
1204#define FPU_CSR_RU 0x2 /* towards +Infinity */
1205#define FPU_CSR_RD 0x3 /* towards -Infinity */
1206
1207
1208#ifndef __ASSEMBLY__
1209
1210/*
1211 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1212 */
1213#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1214 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1215#define get_isa16_mode(x) ((x) & 0x1)
1216#define msk_isa16_mode(x) ((x) & ~0x1)
1217#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1218#else
1219#define get_isa16_mode(x) 0
1220#define msk_isa16_mode(x) (x)
1221#define set_isa16_mode(x) do { } while(0)
1222#endif
1223
1224/*
1225 * microMIPS instructions can be 16-bit or 32-bit in length. This
1226 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1227 */
1228static inline int mm_insn_16bit(u16 insn)
1229{
1230 u16 opcode = (insn >> 10) & 0x7;
1231
1232 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1233}
1234
1235/*
1236 * Helper macros for generating raw instruction encodings in inline asm.
1237 */
1238#ifdef CONFIG_CPU_MICROMIPS
1239#define _ASM_INSN16_IF_MM(_enc) \
1240 ".insn\n\t" \
1241 ".hword (" #_enc ")\n\t"
1242#define _ASM_INSN32_IF_MM(_enc) \
1243 ".insn\n\t" \
1244 ".hword ((" #_enc ") >> 16)\n\t" \
1245 ".hword ((" #_enc ") & 0xffff)\n\t"
1246#else
1247#define _ASM_INSN_IF_MIPS(_enc) \
1248 ".insn\n\t" \
1249 ".word (" #_enc ")\n\t"
1250#endif
1251
1252#ifndef _ASM_INSN16_IF_MM
1253#define _ASM_INSN16_IF_MM(_enc)
1254#endif
1255#ifndef _ASM_INSN32_IF_MM
1256#define _ASM_INSN32_IF_MM(_enc)
1257#endif
1258#ifndef _ASM_INSN_IF_MIPS
1259#define _ASM_INSN_IF_MIPS(_enc)
1260#endif
1261
1262/*
1263 * parse_r var, r - Helper assembler macro for parsing register names.
1264 *
1265 * This converts the register name in $n form provided in \r to the
1266 * corresponding register number, which is assigned to the variable \var. It is
1267 * needed to allow explicit encoding of instructions in inline assembly where
1268 * registers are chosen by the compiler in $n form, allowing us to avoid using
1269 * fixed register numbers.
1270 *
1271 * It also allows newer instructions (not implemented by the assembler) to be
1272 * transparently implemented using assembler macros, instead of needing separate
1273 * cases depending on toolchain support.
1274 *
1275 * Simple usage example:
1276 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1277 * ".insn\n\t"
1278 * "# di %0\n\t"
1279 * ".word (0x41606000 | (__rt << 16))"
1280 * : "=r" (status);
1281 */
1282
1283/* Match an individual register number and assign to \var */
1284#define _IFC_REG(n) \
1285 ".ifc \\r, $" #n "\n\t" \
1286 "\\var = " #n "\n\t" \
1287 ".endif\n\t"
1288
1289__asm__(".macro parse_r var r\n\t"
1290 "\\var = -1\n\t"
1291 _IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
1292 _IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
1293 _IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
1294 _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1295 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1296 _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1297 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1298 _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1299 ".iflt \\var\n\t"
1300 ".error \"Unable to parse register name \\r\"\n\t"
1301 ".endif\n\t"
1302 ".endm");
1303
1304#undef _IFC_REG
1305
1306/*
1307 * C macros for generating assembler macros for common instruction formats.
1308 *
1309 * The names of the operands can be chosen by the caller, and the encoding of
1310 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1311 * the ENC encodings.
1312 */
1313
1314/* Instructions with no operands */
1315#define _ASM_MACRO_0(OP, ENC) \
1316 __asm__(".macro " #OP "\n\t" \
1317 ENC \
1318 ".endm")
1319
1320/* Instructions with 1 register operand & 1 immediate operand */
1321#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \
1322 __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \
1323 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1324 ENC \
1325 ".endm")
1326
1327/* Instructions with 2 register operands */
1328#define _ASM_MACRO_2R(OP, R1, R2, ENC) \
1329 __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \
1330 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1331 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1332 ENC \
1333 ".endm")
1334
1335/* Instructions with 3 register operands */
1336#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC) \
1337 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t" \
1338 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1339 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1340 "parse_r __" #R3 ", \\" #R3 "\n\t" \
1341 ENC \
1342 ".endm")
1343
1344/* Instructions with 2 register operands and 1 optional select operand */
1345#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC) \
1346 __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t" \
1347 "parse_r __" #R1 ", \\" #R1 "\n\t" \
1348 "parse_r __" #R2 ", \\" #R2 "\n\t" \
1349 ENC \
1350 ".endm")
1351
1352/*
1353 * TLB Invalidate Flush
1354 */
1355static inline void tlbinvf(void)
1356{
1357 __asm__ __volatile__(
1358 ".set push\n\t"
1359 ".set noreorder\n\t"
1360 "# tlbinvf\n\t"
1361 _ASM_INSN_IF_MIPS(0x42000004)
1362 _ASM_INSN32_IF_MM(0x0000537c)
1363 ".set pop");
1364}
1365
1366
1367/*
1368 * Functions to access the R10000 performance counters. These are basically
1369 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1370 * performance counter number encoded into bits 1 ... 5 of the instruction.
1371 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1372 * disassembler these will look like an access to sel 0 or 1.
1373 */
1374#define read_r10k_perf_cntr(counter) \
1375({ \
1376 unsigned int __res; \
1377 __asm__ __volatile__( \
1378 "mfpc\t%0, %1" \
1379 : "=r" (__res) \
1380 : "i" (counter)); \
1381 \
1382 __res; \
1383})
1384
1385#define write_r10k_perf_cntr(counter,val) \
1386do { \
1387 __asm__ __volatile__( \
1388 "mtpc\t%0, %1" \
1389 : \
1390 : "r" (val), "i" (counter)); \
1391} while (0)
1392
1393#define read_r10k_perf_event(counter) \
1394({ \
1395 unsigned int __res; \
1396 __asm__ __volatile__( \
1397 "mfps\t%0, %1" \
1398 : "=r" (__res) \
1399 : "i" (counter)); \
1400 \
1401 __res; \
1402})
1403
1404#define write_r10k_perf_cntl(counter,val) \
1405do { \
1406 __asm__ __volatile__( \
1407 "mtps\t%0, %1" \
1408 : \
1409 : "r" (val), "i" (counter)); \
1410} while (0)
1411
1412
1413/*
1414 * Macros to access the system control coprocessor
1415 */
1416
1417#define ___read_32bit_c0_register(source, sel, vol) \
1418({ unsigned int __res; \
1419 if (sel == 0) \
1420 __asm__ vol( \
1421 "mfc0\t%0, " #source "\n\t" \
1422 : "=r" (__res)); \
1423 else \
1424 __asm__ vol( \
1425 ".set\tpush\n\t" \
1426 ".set\tmips32\n\t" \
1427 "mfc0\t%0, " #source ", " #sel "\n\t" \
1428 ".set\tpop\n\t" \
1429 : "=r" (__res)); \
1430 __res; \
1431})
1432
1433#define ___read_64bit_c0_register(source, sel, vol) \
1434({ unsigned long long __res; \
1435 if (sizeof(unsigned long) == 4) \
1436 __res = __read_64bit_c0_split(source, sel, vol); \
1437 else if (sel == 0) \
1438 __asm__ vol( \
1439 ".set\tpush\n\t" \
1440 ".set\tmips3\n\t" \
1441 "dmfc0\t%0, " #source "\n\t" \
1442 ".set\tpop" \
1443 : "=r" (__res)); \
1444 else \
1445 __asm__ vol( \
1446 ".set\tpush\n\t" \
1447 ".set\tmips64\n\t" \
1448 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1449 ".set\tpop" \
1450 : "=r" (__res)); \
1451 __res; \
1452})
1453
1454#define __read_32bit_c0_register(source, sel) \
1455 ___read_32bit_c0_register(source, sel, __volatile__)
1456
1457#define __read_const_32bit_c0_register(source, sel) \
1458 ___read_32bit_c0_register(source, sel,)
1459
1460#define __read_64bit_c0_register(source, sel) \
1461 ___read_64bit_c0_register(source, sel, __volatile__)
1462
1463#define __read_const_64bit_c0_register(source, sel) \
1464 ___read_64bit_c0_register(source, sel,)
1465
1466#define __write_32bit_c0_register(register, sel, value) \
1467do { \
1468 if (sel == 0) \
1469 __asm__ __volatile__( \
1470 "mtc0\t%z0, " #register "\n\t" \
1471 : : "Jr" ((unsigned int)(value))); \
1472 else \
1473 __asm__ __volatile__( \
1474 ".set\tpush\n\t" \
1475 ".set\tmips32\n\t" \
1476 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1477 ".set\tpop" \
1478 : : "Jr" ((unsigned int)(value))); \
1479} while (0)
1480
1481#define __write_64bit_c0_register(register, sel, value) \
1482do { \
1483 if (sizeof(unsigned long) == 4) \
1484 __write_64bit_c0_split(register, sel, value); \
1485 else if (sel == 0) \
1486 __asm__ __volatile__( \
1487 ".set\tpush\n\t" \
1488 ".set\tmips3\n\t" \
1489 "dmtc0\t%z0, " #register "\n\t" \
1490 ".set\tpop" \
1491 : : "Jr" (value)); \
1492 else \
1493 __asm__ __volatile__( \
1494 ".set\tpush\n\t" \
1495 ".set\tmips64\n\t" \
1496 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1497 ".set\tpop" \
1498 : : "Jr" (value)); \
1499} while (0)
1500
1501#define __read_ulong_c0_register(reg, sel) \
1502 ((sizeof(unsigned long) == 4) ? \
1503 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1504 (unsigned long) __read_64bit_c0_register(reg, sel))
1505
1506#define __read_const_ulong_c0_register(reg, sel) \
1507 ((sizeof(unsigned long) == 4) ? \
1508 (unsigned long) __read_const_32bit_c0_register(reg, sel) : \
1509 (unsigned long) __read_const_64bit_c0_register(reg, sel))
1510
1511#define __write_ulong_c0_register(reg, sel, val) \
1512do { \
1513 if (sizeof(unsigned long) == 4) \
1514 __write_32bit_c0_register(reg, sel, val); \
1515 else \
1516 __write_64bit_c0_register(reg, sel, val); \
1517} while (0)
1518
1519/*
1520 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1521 */
1522#define __read_32bit_c0_ctrl_register(source) \
1523({ unsigned int __res; \
1524 __asm__ __volatile__( \
1525 "cfc0\t%0, " #source "\n\t" \
1526 : "=r" (__res)); \
1527 __res; \
1528})
1529
1530#define __write_32bit_c0_ctrl_register(register, value) \
1531do { \
1532 __asm__ __volatile__( \
1533 "ctc0\t%z0, " #register "\n\t" \
1534 : : "Jr" ((unsigned int)(value))); \
1535} while (0)
1536
1537/*
1538 * These versions are only needed for systems with more than 38 bits of
1539 * physical address space running the 32-bit kernel. That's none atm :-)
1540 */
1541#define __read_64bit_c0_split(source, sel, vol) \
1542({ \
1543 unsigned long long __val; \
1544 unsigned long __flags; \
1545 \
1546 local_irq_save(__flags); \
1547 if (sel == 0) \
1548 __asm__ vol( \
1549 ".set\tpush\n\t" \
1550 ".set\tmips64\n\t" \
1551 "dmfc0\t%L0, " #source "\n\t" \
1552 "dsra\t%M0, %L0, 32\n\t" \
1553 "sll\t%L0, %L0, 0\n\t" \
1554 ".set\tpop" \
1555 : "=r" (__val)); \
1556 else \
1557 __asm__ vol( \
1558 ".set\tpush\n\t" \
1559 ".set\tmips64\n\t" \
1560 "dmfc0\t%L0, " #source ", " #sel "\n\t" \
1561 "dsra\t%M0, %L0, 32\n\t" \
1562 "sll\t%L0, %L0, 0\n\t" \
1563 ".set\tpop" \
1564 : "=r" (__val)); \
1565 local_irq_restore(__flags); \
1566 \
1567 __val; \
1568})
1569
1570#define __write_64bit_c0_split(source, sel, val) \
1571do { \
1572 unsigned long long __tmp = (val); \
1573 unsigned long __flags; \
1574 \
1575 local_irq_save(__flags); \
1576 if (MIPS_ISA_REV >= 2) \
1577 __asm__ __volatile__( \
1578 ".set\tpush\n\t" \
1579 ".set\t" MIPS_ISA_LEVEL "\n\t" \
1580 "dins\t%L0, %M0, 32, 32\n\t" \
1581 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1582 ".set\tpop" \
1583 : "+r" (__tmp)); \
1584 else if (sel == 0) \
1585 __asm__ __volatile__( \
1586 ".set\tpush\n\t" \
1587 ".set\tmips64\n\t" \
1588 "dsll\t%L0, %L0, 32\n\t" \
1589 "dsrl\t%L0, %L0, 32\n\t" \
1590 "dsll\t%M0, %M0, 32\n\t" \
1591 "or\t%L0, %L0, %M0\n\t" \
1592 "dmtc0\t%L0, " #source "\n\t" \
1593 ".set\tpop" \
1594 : "+r" (__tmp)); \
1595 else \
1596 __asm__ __volatile__( \
1597 ".set\tpush\n\t" \
1598 ".set\tmips64\n\t" \
1599 "dsll\t%L0, %L0, 32\n\t" \
1600 "dsrl\t%L0, %L0, 32\n\t" \
1601 "dsll\t%M0, %M0, 32\n\t" \
1602 "or\t%L0, %L0, %M0\n\t" \
1603 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1604 ".set\tpop" \
1605 : "+r" (__tmp)); \
1606 local_irq_restore(__flags); \
1607} while (0)
1608
1609#ifndef TOOLCHAIN_SUPPORTS_XPA
1610_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1611 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1612 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1613_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1614 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1615 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1616#define _ASM_SET_XPA ""
1617#else /* !TOOLCHAIN_SUPPORTS_XPA */
1618#define _ASM_SET_XPA ".set\txpa\n\t"
1619#endif
1620
1621#define __readx_32bit_c0_register(source, sel) \
1622({ \
1623 unsigned int __res; \
1624 \
1625 __asm__ __volatile__( \
1626 " .set push \n" \
1627 " .set mips32r2 \n" \
1628 _ASM_SET_XPA \
1629 " mfhc0 %0, " #source ", %1 \n" \
1630 " .set pop \n" \
1631 : "=r" (__res) \
1632 : "i" (sel)); \
1633 __res; \
1634})
1635
1636#define __writex_32bit_c0_register(register, sel, value) \
1637do { \
1638 __asm__ __volatile__( \
1639 " .set push \n" \
1640 " .set mips32r2 \n" \
1641 _ASM_SET_XPA \
1642 " mthc0 %z0, " #register ", %1 \n" \
1643 " .set pop \n" \
1644 : \
1645 : "Jr" (value), "i" (sel)); \
1646} while (0)
1647
1648#define read_c0_index() __read_32bit_c0_register($0, 0)
1649#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1650
1651#define read_c0_random() __read_32bit_c0_register($1, 0)
1652#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1653
1654#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1655#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1656
1657#define readx_c0_entrylo0() __readx_32bit_c0_register($2, 0)
1658#define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1659
1660#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1661#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1662
1663#define readx_c0_entrylo1() __readx_32bit_c0_register($3, 0)
1664#define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1665
1666#define read_c0_conf() __read_32bit_c0_register($3, 0)
1667#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1668
1669#define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
1670
1671#define read_c0_context() __read_ulong_c0_register($4, 0)
1672#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1673
1674#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1675#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1676
1677#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1678#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1679
1680#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1681#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1682
1683#define read_c0_memorymapid() __read_32bit_c0_register($4, 5)
1684#define write_c0_memorymapid(val) __write_32bit_c0_register($4, 5, val)
1685
1686#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1687#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1688
1689#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1690#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1691
1692#define read_c0_wired() __read_32bit_c0_register($6, 0)
1693#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1694
1695#define read_c0_info() __read_32bit_c0_register($7, 0)
1696
1697#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1698#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1699
1700#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1701#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1702
1703#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1704#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1705
1706#define read_c0_count() __read_32bit_c0_register($9, 0)
1707#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1708
1709#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1710#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1711
1712#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1713#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1714
1715#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1716#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1717
1718#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1719#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1720
1721#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1722#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1723
1724#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1725#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1726
1727#define read_c0_compare() __read_32bit_c0_register($11, 0)
1728#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1729
1730#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1731#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1732
1733#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1734#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1735
1736#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1737#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1738
1739#define read_c0_status() __read_32bit_c0_register($12, 0)
1740
1741#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1742
1743#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1744#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1745
1746#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1747#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1748
1749#define read_c0_cause() __read_32bit_c0_register($13, 0)
1750#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1751
1752#define read_c0_epc() __read_ulong_c0_register($14, 0)
1753#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1754
1755#define read_c0_prid() __read_const_32bit_c0_register($15, 0)
1756
1757#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1758
1759#define read_c0_config() __read_32bit_c0_register($16, 0)
1760#define read_c0_config1() __read_32bit_c0_register($16, 1)
1761#define read_c0_config2() __read_32bit_c0_register($16, 2)
1762#define read_c0_config3() __read_32bit_c0_register($16, 3)
1763#define read_c0_config4() __read_32bit_c0_register($16, 4)
1764#define read_c0_config5() __read_32bit_c0_register($16, 5)
1765#define read_c0_config6() __read_32bit_c0_register($16, 6)
1766#define read_c0_config7() __read_32bit_c0_register($16, 7)
1767#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1768#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1769#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1770#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1771#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1772#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1773#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1774#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1775
1776#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1777#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1778#define read_c0_maar() __read_ulong_c0_register($17, 1)
1779#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1780#define readx_c0_maar() __readx_32bit_c0_register($17, 1)
1781#define writex_c0_maar(val) __writex_32bit_c0_register($17, 1, val)
1782#define read_c0_maari() __read_32bit_c0_register($17, 2)
1783#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1784
1785/*
1786 * The WatchLo register. There may be up to 8 of them.
1787 */
1788#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1789#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1790#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1791#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1792#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1793#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1794#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1795#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1796#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1797#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1798#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1799#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1800#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1801#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1802#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1803#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1804
1805/*
1806 * The WatchHi register. There may be up to 8 of them.
1807 */
1808#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1809#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1810#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1811#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1812#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1813#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1814#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1815#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1816
1817#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1818#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1819#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1820#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1821#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1822#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1823#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1824#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1825
1826#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1827#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1828
1829#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1830#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1831
1832#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1833#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1834
1835#define read_c0_diag() __read_32bit_c0_register($22, 0)
1836#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1837
1838/* R10K CP0 Branch Diagnostic register is 64bits wide */
1839#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1840#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1841
1842#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1843#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1844
1845#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1846#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1847
1848#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1849#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1850
1851#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1852#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1853
1854#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1855#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1856
1857#define read_c0_debug() __read_32bit_c0_register($23, 0)
1858#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1859
1860#define read_c0_depc() __read_ulong_c0_register($24, 0)
1861#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1862
1863/*
1864 * MIPS32 / MIPS64 performance counters
1865 */
1866#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1867#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1868#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1869#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1870#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1871#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1872#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1873#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1874#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1875#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1876#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1877#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1878#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1879#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1880#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1881#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1882#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1883#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1884#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1885#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1886#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1887#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1888#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1889#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1890
1891#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1892#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1893
1894#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1895#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1896
1897#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1898
1899#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1900#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1901
1902#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1903#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1904
1905#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1906#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1907
1908#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1909#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1910
1911#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1912#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1913
1914#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1915#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1916
1917#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1918#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1919
1920/* MIPSR2 */
1921#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1922#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1923
1924#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1925#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1926
1927#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1928#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1929
1930#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1931#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1932
1933#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1934#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1935
1936#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1937#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1938
1939#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1940#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1941
1942/* MIPSR3 */
1943#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1944#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1945
1946#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1947#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1948
1949#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1950#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1951
1952/* Hardware Page Table Walker */
1953#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1954#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1955
1956#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1957#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1958
1959#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1960#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1961
1962#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1963#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1964
1965#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1966#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1967
1968#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1969#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1970
1971/* Cavium OCTEON (cnMIPS) */
1972#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1973#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1974
1975#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1976#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1977
1978#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1979#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1980
1981#define read_c0_cvmmemctl2() __read_64bit_c0_register($16, 6)
1982#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1983
1984#define read_c0_cvmvmconfig() __read_64bit_c0_register($16, 7)
1985#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1986
1987/*
1988 * The cacheerr registers are not standardized. On OCTEON, they are
1989 * 64 bits wide.
1990 */
1991#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1992#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1993
1994#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1995#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1996
1997/* BMIPS3300 */
1998#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1999#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
2000
2001#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
2002#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
2003
2004#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
2005#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
2006
2007/* BMIPS43xx */
2008#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
2009#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
2010
2011#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
2012#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
2013
2014#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
2015#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
2016
2017#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
2018#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
2019
2020#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
2021#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
2022
2023/* BMIPS5000 */
2024#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
2025#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
2026
2027#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
2028#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
2029
2030#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
2031#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
2032
2033#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
2034#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
2035
2036#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
2037#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
2038
2039#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
2040#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
2041
2042/* Ingenic page ctrl register */
2043#define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
2044
2045/*
2046 * Macros to access the guest system control coprocessor
2047 */
2048
2049#ifndef TOOLCHAIN_SUPPORTS_VIRT
2050_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
2051 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
2052 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2053_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
2054 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
2055 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
2056_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
2057 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
2058 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2059_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
2060 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
2061 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2062_ASM_MACRO_0(tlbgp, _ASM_INSN_IF_MIPS(0x42000010)
2063 _ASM_INSN32_IF_MM(0x0000017c));
2064_ASM_MACRO_0(tlbgr, _ASM_INSN_IF_MIPS(0x42000009)
2065 _ASM_INSN32_IF_MM(0x0000117c));
2066_ASM_MACRO_0(tlbgwi, _ASM_INSN_IF_MIPS(0x4200000a)
2067 _ASM_INSN32_IF_MM(0x0000217c));
2068_ASM_MACRO_0(tlbgwr, _ASM_INSN_IF_MIPS(0x4200000e)
2069 _ASM_INSN32_IF_MM(0x0000317c));
2070_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
2071 _ASM_INSN32_IF_MM(0x0000517c));
2072#define _ASM_SET_VIRT ""
2073#else /* !TOOLCHAIN_SUPPORTS_VIRT */
2074#define _ASM_SET_VIRT ".set\tvirt\n\t"
2075#endif
2076
2077#define __read_32bit_gc0_register(source, sel) \
2078({ int __res; \
2079 __asm__ __volatile__( \
2080 ".set\tpush\n\t" \
2081 ".set\tmips32r2\n\t" \
2082 _ASM_SET_VIRT \
2083 "mfgc0\t%0, " #source ", %1\n\t" \
2084 ".set\tpop" \
2085 : "=r" (__res) \
2086 : "i" (sel)); \
2087 __res; \
2088})
2089
2090#define __read_64bit_gc0_register(source, sel) \
2091({ unsigned long long __res; \
2092 __asm__ __volatile__( \
2093 ".set\tpush\n\t" \
2094 ".set\tmips64r2\n\t" \
2095 _ASM_SET_VIRT \
2096 "dmfgc0\t%0, " #source ", %1\n\t" \
2097 ".set\tpop" \
2098 : "=r" (__res) \
2099 : "i" (sel)); \
2100 __res; \
2101})
2102
2103#define __write_32bit_gc0_register(register, sel, value) \
2104do { \
2105 __asm__ __volatile__( \
2106 ".set\tpush\n\t" \
2107 ".set\tmips32r2\n\t" \
2108 _ASM_SET_VIRT \
2109 "mtgc0\t%z0, " #register ", %1\n\t" \
2110 ".set\tpop" \
2111 : : "Jr" ((unsigned int)(value)), \
2112 "i" (sel)); \
2113} while (0)
2114
2115#define __write_64bit_gc0_register(register, sel, value) \
2116do { \
2117 __asm__ __volatile__( \
2118 ".set\tpush\n\t" \
2119 ".set\tmips64r2\n\t" \
2120 _ASM_SET_VIRT \
2121 "dmtgc0\t%z0, " #register ", %1\n\t" \
2122 ".set\tpop" \
2123 : : "Jr" (value), \
2124 "i" (sel)); \
2125} while (0)
2126
2127#define __read_ulong_gc0_register(reg, sel) \
2128 ((sizeof(unsigned long) == 4) ? \
2129 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
2130 (unsigned long) __read_64bit_gc0_register(reg, sel))
2131
2132#define __write_ulong_gc0_register(reg, sel, val) \
2133do { \
2134 if (sizeof(unsigned long) == 4) \
2135 __write_32bit_gc0_register(reg, sel, val); \
2136 else \
2137 __write_64bit_gc0_register(reg, sel, val); \
2138} while (0)
2139
2140#define read_gc0_index() __read_32bit_gc0_register($0, 0)
2141#define write_gc0_index(val) __write_32bit_gc0_register($0, 0, val)
2142
2143#define read_gc0_entrylo0() __read_ulong_gc0_register($2, 0)
2144#define write_gc0_entrylo0(val) __write_ulong_gc0_register($2, 0, val)
2145
2146#define read_gc0_entrylo1() __read_ulong_gc0_register($3, 0)
2147#define write_gc0_entrylo1(val) __write_ulong_gc0_register($3, 0, val)
2148
2149#define read_gc0_context() __read_ulong_gc0_register($4, 0)
2150#define write_gc0_context(val) __write_ulong_gc0_register($4, 0, val)
2151
2152#define read_gc0_contextconfig() __read_32bit_gc0_register($4, 1)
2153#define write_gc0_contextconfig(val) __write_32bit_gc0_register($4, 1, val)
2154
2155#define read_gc0_userlocal() __read_ulong_gc0_register($4, 2)
2156#define write_gc0_userlocal(val) __write_ulong_gc0_register($4, 2, val)
2157
2158#define read_gc0_xcontextconfig() __read_ulong_gc0_register($4, 3)
2159#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register($4, 3, val)
2160
2161#define read_gc0_pagemask() __read_32bit_gc0_register($5, 0)
2162#define write_gc0_pagemask(val) __write_32bit_gc0_register($5, 0, val)
2163
2164#define read_gc0_pagegrain() __read_32bit_gc0_register($5, 1)
2165#define write_gc0_pagegrain(val) __write_32bit_gc0_register($5, 1, val)
2166
2167#define read_gc0_segctl0() __read_ulong_gc0_register($5, 2)
2168#define write_gc0_segctl0(val) __write_ulong_gc0_register($5, 2, val)
2169
2170#define read_gc0_segctl1() __read_ulong_gc0_register($5, 3)
2171#define write_gc0_segctl1(val) __write_ulong_gc0_register($5, 3, val)
2172
2173#define read_gc0_segctl2() __read_ulong_gc0_register($5, 4)
2174#define write_gc0_segctl2(val) __write_ulong_gc0_register($5, 4, val)
2175
2176#define read_gc0_pwbase() __read_ulong_gc0_register($5, 5)
2177#define write_gc0_pwbase(val) __write_ulong_gc0_register($5, 5, val)
2178
2179#define read_gc0_pwfield() __read_ulong_gc0_register($5, 6)
2180#define write_gc0_pwfield(val) __write_ulong_gc0_register($5, 6, val)
2181
2182#define read_gc0_pwsize() __read_ulong_gc0_register($5, 7)
2183#define write_gc0_pwsize(val) __write_ulong_gc0_register($5, 7, val)
2184
2185#define read_gc0_wired() __read_32bit_gc0_register($6, 0)
2186#define write_gc0_wired(val) __write_32bit_gc0_register($6, 0, val)
2187
2188#define read_gc0_pwctl() __read_32bit_gc0_register($6, 6)
2189#define write_gc0_pwctl(val) __write_32bit_gc0_register($6, 6, val)
2190
2191#define read_gc0_hwrena() __read_32bit_gc0_register($7, 0)
2192#define write_gc0_hwrena(val) __write_32bit_gc0_register($7, 0, val)
2193
2194#define read_gc0_badvaddr() __read_ulong_gc0_register($8, 0)
2195#define write_gc0_badvaddr(val) __write_ulong_gc0_register($8, 0, val)
2196
2197#define read_gc0_badinstr() __read_32bit_gc0_register($8, 1)
2198#define write_gc0_badinstr(val) __write_32bit_gc0_register($8, 1, val)
2199
2200#define read_gc0_badinstrp() __read_32bit_gc0_register($8, 2)
2201#define write_gc0_badinstrp(val) __write_32bit_gc0_register($8, 2, val)
2202
2203#define read_gc0_count() __read_32bit_gc0_register($9, 0)
2204
2205#define read_gc0_entryhi() __read_ulong_gc0_register($10, 0)
2206#define write_gc0_entryhi(val) __write_ulong_gc0_register($10, 0, val)
2207
2208#define read_gc0_compare() __read_32bit_gc0_register($11, 0)
2209#define write_gc0_compare(val) __write_32bit_gc0_register($11, 0, val)
2210
2211#define read_gc0_status() __read_32bit_gc0_register($12, 0)
2212#define write_gc0_status(val) __write_32bit_gc0_register($12, 0, val)
2213
2214#define read_gc0_intctl() __read_32bit_gc0_register($12, 1)
2215#define write_gc0_intctl(val) __write_32bit_gc0_register($12, 1, val)
2216
2217#define read_gc0_cause() __read_32bit_gc0_register($13, 0)
2218#define write_gc0_cause(val) __write_32bit_gc0_register($13, 0, val)
2219
2220#define read_gc0_epc() __read_ulong_gc0_register($14, 0)
2221#define write_gc0_epc(val) __write_ulong_gc0_register($14, 0, val)
2222
2223#define read_gc0_prid() __read_32bit_gc0_register($15, 0)
2224
2225#define read_gc0_ebase() __read_32bit_gc0_register($15, 1)
2226#define write_gc0_ebase(val) __write_32bit_gc0_register($15, 1, val)
2227
2228#define read_gc0_ebase_64() __read_64bit_gc0_register($15, 1)
2229#define write_gc0_ebase_64(val) __write_64bit_gc0_register($15, 1, val)
2230
2231#define read_gc0_config() __read_32bit_gc0_register($16, 0)
2232#define read_gc0_config1() __read_32bit_gc0_register($16, 1)
2233#define read_gc0_config2() __read_32bit_gc0_register($16, 2)
2234#define read_gc0_config3() __read_32bit_gc0_register($16, 3)
2235#define read_gc0_config4() __read_32bit_gc0_register($16, 4)
2236#define read_gc0_config5() __read_32bit_gc0_register($16, 5)
2237#define read_gc0_config6() __read_32bit_gc0_register($16, 6)
2238#define read_gc0_config7() __read_32bit_gc0_register($16, 7)
2239#define write_gc0_config(val) __write_32bit_gc0_register($16, 0, val)
2240#define write_gc0_config1(val) __write_32bit_gc0_register($16, 1, val)
2241#define write_gc0_config2(val) __write_32bit_gc0_register($16, 2, val)
2242#define write_gc0_config3(val) __write_32bit_gc0_register($16, 3, val)
2243#define write_gc0_config4(val) __write_32bit_gc0_register($16, 4, val)
2244#define write_gc0_config5(val) __write_32bit_gc0_register($16, 5, val)
2245#define write_gc0_config6(val) __write_32bit_gc0_register($16, 6, val)
2246#define write_gc0_config7(val) __write_32bit_gc0_register($16, 7, val)
2247
2248#define read_gc0_lladdr() __read_ulong_gc0_register($17, 0)
2249#define write_gc0_lladdr(val) __write_ulong_gc0_register($17, 0, val)
2250
2251#define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2252#define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2253#define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2254#define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2255#define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2256#define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2257#define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2258#define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2259#define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2260#define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2261#define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2262#define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2263#define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2264#define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2265#define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2266#define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2267
2268#define read_gc0_watchhi0() __read_32bit_gc0_register($19, 0)
2269#define read_gc0_watchhi1() __read_32bit_gc0_register($19, 1)
2270#define read_gc0_watchhi2() __read_32bit_gc0_register($19, 2)
2271#define read_gc0_watchhi3() __read_32bit_gc0_register($19, 3)
2272#define read_gc0_watchhi4() __read_32bit_gc0_register($19, 4)
2273#define read_gc0_watchhi5() __read_32bit_gc0_register($19, 5)
2274#define read_gc0_watchhi6() __read_32bit_gc0_register($19, 6)
2275#define read_gc0_watchhi7() __read_32bit_gc0_register($19, 7)
2276#define write_gc0_watchhi0(val) __write_32bit_gc0_register($19, 0, val)
2277#define write_gc0_watchhi1(val) __write_32bit_gc0_register($19, 1, val)
2278#define write_gc0_watchhi2(val) __write_32bit_gc0_register($19, 2, val)
2279#define write_gc0_watchhi3(val) __write_32bit_gc0_register($19, 3, val)
2280#define write_gc0_watchhi4(val) __write_32bit_gc0_register($19, 4, val)
2281#define write_gc0_watchhi5(val) __write_32bit_gc0_register($19, 5, val)
2282#define write_gc0_watchhi6(val) __write_32bit_gc0_register($19, 6, val)
2283#define write_gc0_watchhi7(val) __write_32bit_gc0_register($19, 7, val)
2284
2285#define read_gc0_xcontext() __read_ulong_gc0_register($20, 0)
2286#define write_gc0_xcontext(val) __write_ulong_gc0_register($20, 0, val)
2287
2288#define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2289#define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2290#define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2291#define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2292#define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2293#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2294#define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2295#define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2296#define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2297#define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2298#define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2299#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2300#define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2301#define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2302#define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2303#define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2304#define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2305#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2306#define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2307#define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2308#define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2309#define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2310#define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2311#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)
2312
2313#define read_gc0_errorepc() __read_ulong_gc0_register($30, 0)
2314#define write_gc0_errorepc(val) __write_ulong_gc0_register($30, 0, val)
2315
2316#define read_gc0_kscratch1() __read_ulong_gc0_register($31, 2)
2317#define read_gc0_kscratch2() __read_ulong_gc0_register($31, 3)
2318#define read_gc0_kscratch3() __read_ulong_gc0_register($31, 4)
2319#define read_gc0_kscratch4() __read_ulong_gc0_register($31, 5)
2320#define read_gc0_kscratch5() __read_ulong_gc0_register($31, 6)
2321#define read_gc0_kscratch6() __read_ulong_gc0_register($31, 7)
2322#define write_gc0_kscratch1(val) __write_ulong_gc0_register($31, 2, val)
2323#define write_gc0_kscratch2(val) __write_ulong_gc0_register($31, 3, val)
2324#define write_gc0_kscratch3(val) __write_ulong_gc0_register($31, 4, val)
2325#define write_gc0_kscratch4(val) __write_ulong_gc0_register($31, 5, val)
2326#define write_gc0_kscratch5(val) __write_ulong_gc0_register($31, 6, val)
2327#define write_gc0_kscratch6(val) __write_ulong_gc0_register($31, 7, val)
2328
2329/* Cavium OCTEON (cnMIPS) */
2330#define read_gc0_cvmcount() __read_ulong_gc0_register($9, 6)
2331#define write_gc0_cvmcount(val) __write_ulong_gc0_register($9, 6, val)
2332
2333#define read_gc0_cvmctl() __read_64bit_gc0_register($9, 7)
2334#define write_gc0_cvmctl(val) __write_64bit_gc0_register($9, 7, val)
2335
2336#define read_gc0_cvmmemctl() __read_64bit_gc0_register($11, 7)
2337#define write_gc0_cvmmemctl(val) __write_64bit_gc0_register($11, 7, val)
2338
2339#define read_gc0_cvmmemctl2() __read_64bit_gc0_register($16, 6)
2340#define write_gc0_cvmmemctl2(val) __write_64bit_gc0_register($16, 6, val)
2341
2342/*
2343 * Macros to access the floating point coprocessor control registers
2344 */
2345#define _read_32bit_cp1_register(source, gas_hardfloat) \
2346({ \
2347 unsigned int __res; \
2348 \
2349 __asm__ __volatile__( \
2350 " .set push \n" \
2351 " .set reorder \n" \
2352 " # gas fails to assemble cfc1 for some archs, \n" \
2353 " # like Octeon. \n" \
2354 " .set mips1 \n" \
2355 " "STR(gas_hardfloat)" \n" \
2356 " cfc1 %0,"STR(source)" \n" \
2357 " .set pop \n" \
2358 : "=r" (__res)); \
2359 __res; \
2360})
2361
2362#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2363do { \
2364 __asm__ __volatile__( \
2365 " .set push \n" \
2366 " .set reorder \n" \
2367 " "STR(gas_hardfloat)" \n" \
2368 " ctc1 %0,"STR(dest)" \n" \
2369 " .set pop \n" \
2370 : : "r" (val)); \
2371} while (0)
2372
2373#ifdef GAS_HAS_SET_HARDFLOAT
2374#define read_32bit_cp1_register(source) \
2375 _read_32bit_cp1_register(source, .set hardfloat)
2376#define write_32bit_cp1_register(dest, val) \
2377 _write_32bit_cp1_register(dest, val, .set hardfloat)
2378#else
2379#define read_32bit_cp1_register(source) \
2380 _read_32bit_cp1_register(source, )
2381#define write_32bit_cp1_register(dest, val) \
2382 _write_32bit_cp1_register(dest, val, )
2383#endif
2384
2385#ifdef TOOLCHAIN_SUPPORTS_DSP
2386#define rddsp(mask) \
2387({ \
2388 unsigned int __dspctl; \
2389 \
2390 __asm__ __volatile__( \
2391 " .set push \n" \
2392 " .set " MIPS_ISA_LEVEL " \n" \
2393 " .set dsp \n" \
2394 " rddsp %0, %x1 \n" \
2395 " .set pop \n" \
2396 : "=r" (__dspctl) \
2397 : "i" (mask)); \
2398 __dspctl; \
2399})
2400
2401#define wrdsp(val, mask) \
2402do { \
2403 __asm__ __volatile__( \
2404 " .set push \n" \
2405 " .set " MIPS_ISA_LEVEL " \n" \
2406 " .set dsp \n" \
2407 " wrdsp %0, %x1 \n" \
2408 " .set pop \n" \
2409 : \
2410 : "r" (val), "i" (mask)); \
2411} while (0)
2412
2413#define mflo0() \
2414({ \
2415 long mflo0; \
2416 __asm__( \
2417 " .set push \n" \
2418 " .set " MIPS_ISA_LEVEL " \n" \
2419 " .set dsp \n" \
2420 " mflo %0, $ac0 \n" \
2421 " .set pop \n" \
2422 : "=r" (mflo0)); \
2423 mflo0; \
2424})
2425
2426#define mflo1() \
2427({ \
2428 long mflo1; \
2429 __asm__( \
2430 " .set push \n" \
2431 " .set " MIPS_ISA_LEVEL " \n" \
2432 " .set dsp \n" \
2433 " mflo %0, $ac1 \n" \
2434 " .set pop \n" \
2435 : "=r" (mflo1)); \
2436 mflo1; \
2437})
2438
2439#define mflo2() \
2440({ \
2441 long mflo2; \
2442 __asm__( \
2443 " .set push \n" \
2444 " .set " MIPS_ISA_LEVEL " \n" \
2445 " .set dsp \n" \
2446 " mflo %0, $ac2 \n" \
2447 " .set pop \n" \
2448 : "=r" (mflo2)); \
2449 mflo2; \
2450})
2451
2452#define mflo3() \
2453({ \
2454 long mflo3; \
2455 __asm__( \
2456 " .set push \n" \
2457 " .set " MIPS_ISA_LEVEL " \n" \
2458 " .set dsp \n" \
2459 " mflo %0, $ac3 \n" \
2460 " .set pop \n" \
2461 : "=r" (mflo3)); \
2462 mflo3; \
2463})
2464
2465#define mfhi0() \
2466({ \
2467 long mfhi0; \
2468 __asm__( \
2469 " .set push \n" \
2470 " .set " MIPS_ISA_LEVEL " \n" \
2471 " .set dsp \n" \
2472 " mfhi %0, $ac0 \n" \
2473 " .set pop \n" \
2474 : "=r" (mfhi0)); \
2475 mfhi0; \
2476})
2477
2478#define mfhi1() \
2479({ \
2480 long mfhi1; \
2481 __asm__( \
2482 " .set push \n" \
2483 " .set " MIPS_ISA_LEVEL " \n" \
2484 " .set dsp \n" \
2485 " mfhi %0, $ac1 \n" \
2486 " .set pop \n" \
2487 : "=r" (mfhi1)); \
2488 mfhi1; \
2489})
2490
2491#define mfhi2() \
2492({ \
2493 long mfhi2; \
2494 __asm__( \
2495 " .set push \n" \
2496 " .set " MIPS_ISA_LEVEL " \n" \
2497 " .set dsp \n" \
2498 " mfhi %0, $ac2 \n" \
2499 " .set pop \n" \
2500 : "=r" (mfhi2)); \
2501 mfhi2; \
2502})
2503
2504#define mfhi3() \
2505({ \
2506 long mfhi3; \
2507 __asm__( \
2508 " .set push \n" \
2509 " .set " MIPS_ISA_LEVEL " \n" \
2510 " .set dsp \n" \
2511 " mfhi %0, $ac3 \n" \
2512 " .set pop \n" \
2513 : "=r" (mfhi3)); \
2514 mfhi3; \
2515})
2516
2517
2518#define mtlo0(x) \
2519({ \
2520 __asm__( \
2521 " .set push \n" \
2522 " .set " MIPS_ISA_LEVEL " \n" \
2523 " .set dsp \n" \
2524 " mtlo %0, $ac0 \n" \
2525 " .set pop \n" \
2526 : \
2527 : "r" (x)); \
2528})
2529
2530#define mtlo1(x) \
2531({ \
2532 __asm__( \
2533 " .set push \n" \
2534 " .set " MIPS_ISA_LEVEL " \n" \
2535 " .set dsp \n" \
2536 " mtlo %0, $ac1 \n" \
2537 " .set pop \n" \
2538 : \
2539 : "r" (x)); \
2540})
2541
2542#define mtlo2(x) \
2543({ \
2544 __asm__( \
2545 " .set push \n" \
2546 " .set " MIPS_ISA_LEVEL " \n" \
2547 " .set dsp \n" \
2548 " mtlo %0, $ac2 \n" \
2549 " .set pop \n" \
2550 : \
2551 : "r" (x)); \
2552})
2553
2554#define mtlo3(x) \
2555({ \
2556 __asm__( \
2557 " .set push \n" \
2558 " .set " MIPS_ISA_LEVEL " \n" \
2559 " .set dsp \n" \
2560 " mtlo %0, $ac3 \n" \
2561 " .set pop \n" \
2562 : \
2563 : "r" (x)); \
2564})
2565
2566#define mthi0(x) \
2567({ \
2568 __asm__( \
2569 " .set push \n" \
2570 " .set " MIPS_ISA_LEVEL " \n" \
2571 " .set dsp \n" \
2572 " mthi %0, $ac0 \n" \
2573 " .set pop \n" \
2574 : \
2575 : "r" (x)); \
2576})
2577
2578#define mthi1(x) \
2579({ \
2580 __asm__( \
2581 " .set push \n" \
2582 " .set " MIPS_ISA_LEVEL " \n" \
2583 " .set dsp \n" \
2584 " mthi %0, $ac1 \n" \
2585 " .set pop \n" \
2586 : \
2587 : "r" (x)); \
2588})
2589
2590#define mthi2(x) \
2591({ \
2592 __asm__( \
2593 " .set push \n" \
2594 " .set " MIPS_ISA_LEVEL " \n" \
2595 " .set dsp \n" \
2596 " mthi %0, $ac2 \n" \
2597 " .set pop \n" \
2598 : \
2599 : "r" (x)); \
2600})
2601
2602#define mthi3(x) \
2603({ \
2604 __asm__( \
2605 " .set push \n" \
2606 " .set " MIPS_ISA_LEVEL " \n" \
2607 " .set dsp \n" \
2608 " mthi %0, $ac3 \n" \
2609 " .set pop \n" \
2610 : \
2611 : "r" (x)); \
2612})
2613
2614#else
2615
2616#define rddsp(mask) \
2617({ \
2618 unsigned int __res; \
2619 \
2620 __asm__ __volatile__( \
2621 " .set push \n" \
2622 " .set noat \n" \
2623 " # rddsp $1, %x1 \n" \
2624 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2625 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2626 " move %0, $1 \n" \
2627 " .set pop \n" \
2628 : "=r" (__res) \
2629 : "i" (mask)); \
2630 __res; \
2631})
2632
2633#define wrdsp(val, mask) \
2634do { \
2635 __asm__ __volatile__( \
2636 " .set push \n" \
2637 " .set noat \n" \
2638 " move $1, %0 \n" \
2639 " # wrdsp $1, %x1 \n" \
2640 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2641 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2642 " .set pop \n" \
2643 : \
2644 : "r" (val), "i" (mask)); \
2645} while (0)
2646
2647#define _dsp_mfxxx(ins) \
2648({ \
2649 unsigned long __treg; \
2650 \
2651 __asm__ __volatile__( \
2652 " .set push \n" \
2653 " .set noat \n" \
2654 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2655 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2656 " move %0, $1 \n" \
2657 " .set pop \n" \
2658 : "=r" (__treg) \
2659 : "i" (ins)); \
2660 __treg; \
2661})
2662
2663#define _dsp_mtxxx(val, ins) \
2664do { \
2665 __asm__ __volatile__( \
2666 " .set push \n" \
2667 " .set noat \n" \
2668 " move $1, %0 \n" \
2669 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2670 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2671 " .set pop \n" \
2672 : \
2673 : "r" (val), "i" (ins)); \
2674} while (0)
2675
2676#ifdef CONFIG_CPU_MICROMIPS
2677
2678#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2679#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2680
2681#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2682#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2683
2684#else /* !CONFIG_CPU_MICROMIPS */
2685
2686#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2687#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2688
2689#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2690#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2691
2692#endif /* CONFIG_CPU_MICROMIPS */
2693
2694#define mflo0() _dsp_mflo(0)
2695#define mflo1() _dsp_mflo(1)
2696#define mflo2() _dsp_mflo(2)
2697#define mflo3() _dsp_mflo(3)
2698
2699#define mfhi0() _dsp_mfhi(0)
2700#define mfhi1() _dsp_mfhi(1)
2701#define mfhi2() _dsp_mfhi(2)
2702#define mfhi3() _dsp_mfhi(3)
2703
2704#define mtlo0(x) _dsp_mtlo(x, 0)
2705#define mtlo1(x) _dsp_mtlo(x, 1)
2706#define mtlo2(x) _dsp_mtlo(x, 2)
2707#define mtlo3(x) _dsp_mtlo(x, 3)
2708
2709#define mthi0(x) _dsp_mthi(x, 0)
2710#define mthi1(x) _dsp_mthi(x, 1)
2711#define mthi2(x) _dsp_mthi(x, 2)
2712#define mthi3(x) _dsp_mthi(x, 3)
2713
2714#endif
2715
2716/*
2717 * TLB operations.
2718 *
2719 * It is responsibility of the caller to take care of any TLB hazards.
2720 */
2721static inline void tlb_probe(void)
2722{
2723 __asm__ __volatile__(
2724 ".set noreorder\n\t"
2725 "tlbp\n\t"
2726 ".set reorder");
2727}
2728
2729static inline void tlb_read(void)
2730{
2731#if MIPS34K_MISSED_ITLB_WAR
2732 int res = 0;
2733
2734 __asm__ __volatile__(
2735 " .set push \n"
2736 " .set noreorder \n"
2737 " .set noat \n"
2738 " .set mips32r2 \n"
2739 " .word 0x41610001 # dvpe $1 \n"
2740 " move %0, $1 \n"
2741 " ehb \n"
2742 " .set pop \n"
2743 : "=r" (res));
2744
2745 instruction_hazard();
2746#endif
2747
2748 __asm__ __volatile__(
2749 ".set noreorder\n\t"
2750 "tlbr\n\t"
2751 ".set reorder");
2752
2753#if MIPS34K_MISSED_ITLB_WAR
2754 if ((res & _ULCAST_(1)))
2755 __asm__ __volatile__(
2756 " .set push \n"
2757 " .set noreorder \n"
2758 " .set noat \n"
2759 " .set mips32r2 \n"
2760 " .word 0x41600021 # evpe \n"
2761 " ehb \n"
2762 " .set pop \n");
2763#endif
2764}
2765
2766static inline void tlb_write_indexed(void)
2767{
2768 __asm__ __volatile__(
2769 ".set noreorder\n\t"
2770 "tlbwi\n\t"
2771 ".set reorder");
2772}
2773
2774static inline void tlb_write_random(void)
2775{
2776 __asm__ __volatile__(
2777 ".set noreorder\n\t"
2778 "tlbwr\n\t"
2779 ".set reorder");
2780}
2781
2782/*
2783 * Guest TLB operations.
2784 *
2785 * It is responsibility of the caller to take care of any TLB hazards.
2786 */
2787static inline void guest_tlb_probe(void)
2788{
2789 __asm__ __volatile__(
2790 ".set push\n\t"
2791 ".set noreorder\n\t"
2792 _ASM_SET_VIRT
2793 "tlbgp\n\t"
2794 ".set pop");
2795}
2796
2797static inline void guest_tlb_read(void)
2798{
2799 __asm__ __volatile__(
2800 ".set push\n\t"
2801 ".set noreorder\n\t"
2802 _ASM_SET_VIRT
2803 "tlbgr\n\t"
2804 ".set pop");
2805}
2806
2807static inline void guest_tlb_write_indexed(void)
2808{
2809 __asm__ __volatile__(
2810 ".set push\n\t"
2811 ".set noreorder\n\t"
2812 _ASM_SET_VIRT
2813 "tlbgwi\n\t"
2814 ".set pop");
2815}
2816
2817static inline void guest_tlb_write_random(void)
2818{
2819 __asm__ __volatile__(
2820 ".set push\n\t"
2821 ".set noreorder\n\t"
2822 _ASM_SET_VIRT
2823 "tlbgwr\n\t"
2824 ".set pop");
2825}
2826
2827/*
2828 * Guest TLB Invalidate Flush
2829 */
2830static inline void guest_tlbinvf(void)
2831{
2832 __asm__ __volatile__(
2833 ".set push\n\t"
2834 ".set noreorder\n\t"
2835 _ASM_SET_VIRT
2836 "tlbginvf\n\t"
2837 ".set pop");
2838}
2839
2840/*
2841 * Manipulate bits in a register.
2842 */
2843#define __BUILD_SET_COMMON(name) \
2844static inline unsigned int \
2845set_##name(unsigned int set) \
2846{ \
2847 unsigned int res, new; \
2848 \
2849 res = read_##name(); \
2850 new = res | set; \
2851 write_##name(new); \
2852 \
2853 return res; \
2854} \
2855 \
2856static inline unsigned int \
2857clear_##name(unsigned int clear) \
2858{ \
2859 unsigned int res, new; \
2860 \
2861 res = read_##name(); \
2862 new = res & ~clear; \
2863 write_##name(new); \
2864 \
2865 return res; \
2866} \
2867 \
2868static inline unsigned int \
2869change_##name(unsigned int change, unsigned int val) \
2870{ \
2871 unsigned int res, new; \
2872 \
2873 res = read_##name(); \
2874 new = res & ~change; \
2875 new |= (val & change); \
2876 write_##name(new); \
2877 \
2878 return res; \
2879}
2880
2881/*
2882 * Manipulate bits in a c0 register.
2883 */
2884#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2885
2886__BUILD_SET_C0(status)
2887__BUILD_SET_C0(cause)
2888__BUILD_SET_C0(config)
2889__BUILD_SET_C0(config5)
2890__BUILD_SET_C0(config6)
2891__BUILD_SET_C0(config7)
2892__BUILD_SET_C0(diag)
2893__BUILD_SET_C0(intcontrol)
2894__BUILD_SET_C0(intctl)
2895__BUILD_SET_C0(srsmap)
2896__BUILD_SET_C0(pagegrain)
2897__BUILD_SET_C0(guestctl0)
2898__BUILD_SET_C0(guestctl0ext)
2899__BUILD_SET_C0(guestctl1)
2900__BUILD_SET_C0(guestctl2)
2901__BUILD_SET_C0(guestctl3)
2902__BUILD_SET_C0(brcm_config_0)
2903__BUILD_SET_C0(brcm_bus_pll)
2904__BUILD_SET_C0(brcm_reset)
2905__BUILD_SET_C0(brcm_cmt_intr)
2906__BUILD_SET_C0(brcm_cmt_ctrl)
2907__BUILD_SET_C0(brcm_config)
2908__BUILD_SET_C0(brcm_mode)
2909
2910/*
2911 * Manipulate bits in a guest c0 register.
2912 */
2913#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2914
2915__BUILD_SET_GC0(wired)
2916__BUILD_SET_GC0(status)
2917__BUILD_SET_GC0(cause)
2918__BUILD_SET_GC0(ebase)
2919__BUILD_SET_GC0(config1)
2920
2921/*
2922 * Return low 10 bits of ebase.
2923 * Note that under KVM (MIPSVZ) this returns vcpu id.
2924 */
2925static inline unsigned int get_ebase_cpunum(void)
2926{
2927 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2928}
2929
2930#endif /* !__ASSEMBLY__ */
2931
2932#endif /* _ASM_MIPSREGS_H */