1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Driver for OMAP-UART controller.
   4 * Based on drivers/serial/8250.c
   5 *
   6 * Copyright (C) 2010 Texas Instruments.
   7 *
   8 * Authors:
   9 *	Govindraj R	<govindraj.raja@ti.com>
  10 *	Thara Gopinath	<thara@ti.com>
  11 *
 
 
 
 
 
  12 * Note: This driver is made separate from 8250 driver as we cannot
  13 * over load 8250 driver with omap platform specific configuration for
  14 * features like DMA, it makes easier to implement features like DMA and
  15 * hardware flow control and software flow control configuration with
  16 * this driver as required for the omap-platform.
  17 */
  18
 
 
 
 
  19#include <linux/module.h>
  20#include <linux/init.h>
  21#include <linux/console.h>
  22#include <linux/serial_reg.h>
  23#include <linux/delay.h>
  24#include <linux/slab.h>
  25#include <linux/tty.h>
  26#include <linux/tty_flip.h>
  27#include <linux/platform_device.h>
  28#include <linux/io.h>
  29#include <linux/clk.h>
  30#include <linux/serial_core.h>
  31#include <linux/irq.h>
  32#include <linux/pm_runtime.h>
  33#include <linux/pm_wakeirq.h>
  34#include <linux/of.h>
  35#include <linux/of_irq.h>
  36#include <linux/gpio/consumer.h>
 
  37#include <linux/platform_data/serial-omap.h>
  38
 
 
  39#define OMAP_MAX_HSUART_PORTS	10
  40
  41#define UART_BUILD_REVISION(x, y)	(((x) << 8) | (y))
  42
  43#define OMAP_UART_REV_42 0x0402
  44#define OMAP_UART_REV_46 0x0406
  45#define OMAP_UART_REV_52 0x0502
  46#define OMAP_UART_REV_63 0x0603
  47
  48#define OMAP_UART_TX_WAKEUP_EN		BIT(7)
  49
  50/* Feature flags */
  51#define OMAP_UART_WER_HAS_TX_WAKEUP	BIT(0)
  52
  53#define UART_ERRATA_i202_MDR1_ACCESS	BIT(0)
  54#define UART_ERRATA_i291_DMA_FORCEIDLE	BIT(1)
  55
  56#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
  57
  58/* SCR register bitmasks */
  59#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK		(1 << 7)
  60#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK		(1 << 6)
  61#define OMAP_UART_SCR_TX_EMPTY			(1 << 3)
  62
  63/* FCR register bitmasks */
  64#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK			(0x3 << 6)
  65#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK			(0x3 << 4)
  66
  67/* MVR register bitmasks */
  68#define OMAP_UART_MVR_SCHEME_SHIFT	30
  69
  70#define OMAP_UART_LEGACY_MVR_MAJ_MASK	0xf0
  71#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT	4
  72#define OMAP_UART_LEGACY_MVR_MIN_MASK	0x0f
  73
  74#define OMAP_UART_MVR_MAJ_MASK		0x700
  75#define OMAP_UART_MVR_MAJ_SHIFT		8
  76#define OMAP_UART_MVR_MIN_MASK		0x3f
  77
  78#define OMAP_UART_DMA_CH_FREE	-1
  79
  80#define MSR_SAVE_FLAGS		UART_MSR_ANY_DELTA
  81#define OMAP_MODE13X_SPEED	230400
  82
  83/* WER = 0x7F
  84 * Enable module level wakeup in WER reg
  85 */
  86#define OMAP_UART_WER_MOD_WKUP	0x7F
  87
  88/* Enable XON/XOFF flow control on output */
  89#define OMAP_UART_SW_TX		0x08
  90
  91/* Enable XON/XOFF flow control on input */
  92#define OMAP_UART_SW_RX		0x02
  93
  94#define OMAP_UART_SW_CLR	0xF0
  95
  96#define OMAP_UART_TCR_TRIG	0x0F
  97
  98struct uart_omap_dma {
  99	u8			uart_dma_tx;
 100	u8			uart_dma_rx;
 101	int			rx_dma_channel;
 102	int			tx_dma_channel;
 103	dma_addr_t		rx_buf_dma_phys;
 104	dma_addr_t		tx_buf_dma_phys;
 105	unsigned int		uart_base;
 106	/*
 107	 * Buffer for rx dma. It is not required for tx because the buffer
 108	 * comes from port structure.
 109	 */
 110	unsigned char		*rx_buf;
 111	unsigned int		prev_rx_dma_pos;
 112	int			tx_buf_size;
 113	int			tx_dma_used;
 114	int			rx_dma_used;
 115	spinlock_t		tx_lock;
 116	spinlock_t		rx_lock;
 117	/* timer to poll activity on rx dma */
 118	struct timer_list	rx_timer;
 119	unsigned int		rx_buf_size;
 120	unsigned int		rx_poll_rate;
 121	unsigned int		rx_timeout;
 122};
 123
 124struct uart_omap_port {
 125	struct uart_port	port;
 126	struct uart_omap_dma	uart_dma;
 127	struct device		*dev;
 128	int			wakeirq;
 129
 130	unsigned char		ier;
 131	unsigned char		lcr;
 132	unsigned char		mcr;
 133	unsigned char		fcr;
 134	unsigned char		efr;
 135	unsigned char		dll;
 136	unsigned char		dlh;
 137	unsigned char		mdr1;
 138	unsigned char		scr;
 139	unsigned char		wer;
 140
 141	int			use_dma;
 142	/*
 143	 * Some bits in registers are cleared on a read, so they must
 144	 * be saved whenever the register is read, but the bits will not
 145	 * be immediately processed.
 146	 */
 147	unsigned int		lsr_break_flag;
 148	unsigned char		msr_saved_flags;
 149	char			name[20];
 150	unsigned long		port_activity;
 151	int			context_loss_cnt;
 152	u32			errata;
 153	u32			features;
 154
 155	struct gpio_desc	*rts_gpiod;
 156
 157	struct pm_qos_request	pm_qos_request;
 158	u32			latency;
 159	u32			calc_latency;
 160	struct work_struct	qos_work;
 161	bool			is_suspending;
 162
 163	unsigned int		rs485_tx_filter_count;
 164};
 165
 166#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
 167
 168static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 169
 170/* Forward declaration of functions */
 171static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 172
 173static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 174{
 175	offset <<= up->port.regshift;
 176	return readw(up->port.membase + offset);
 177}
 178
 179static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 180{
 181	offset <<= up->port.regshift;
 182	writew(value, up->port.membase + offset);
 183}
 184
 185static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 186{
 187	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 188	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 189		       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 190	serial_out(up, UART_FCR, 0);
 191}
 192
 193#ifdef CONFIG_PM
 194static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 195{
 196	struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 197
 198	if (!pdata || !pdata->get_context_loss_count)
 199		return -EINVAL;
 200
 201	return pdata->get_context_loss_count(up->dev);
 202}
 203
 204/* REVISIT: Remove this when omap3 boots in device tree only mode */
 205static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 206{
 207	struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 208
 209	if (!pdata || !pdata->enable_wakeup)
 210		return;
 211
 212	pdata->enable_wakeup(up->dev, enable);
 213}
 214#endif /* CONFIG_PM */
 215
 216/*
 217 * Calculate the absolute difference between the desired and actual baud
 218 * rate for the given mode.
 219 */
 220static inline int calculate_baud_abs_diff(struct uart_port *port,
 221				unsigned int baud, unsigned int mode)
 222{
 223	unsigned int n = port->uartclk / (mode * baud);
 224	int abs_diff;
 225
 226	if (n == 0)
 227		n = 1;
 228
 229	abs_diff = baud - (port->uartclk / (mode * n));
 230	if (abs_diff < 0)
 231		abs_diff = -abs_diff;
 232
 233	return abs_diff;
 234}
 235
 236/*
 237 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 238 * @port: uart port info
 239 * @baud: baudrate for which mode needs to be determined
 240 *
 241 * Returns true if baud rate is MODE16X and false if MODE13X
 242 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 243 * and Error Rates" determines modes not for all common baud rates.
 244 * E.g. for 1000000 baud rate mode must be 16x, but according to that
 245 * table it's determined as 13x.
 246 */
 247static bool
 248serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 249{
 250	int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
 251	int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
 252
 253	return (abs_diff_13 >= abs_diff_16);
 254}
 255
 256/*
 257 * serial_omap_get_divisor - calculate divisor value
 258 * @port: uart port info
 259 * @baud: baudrate for which divisor needs to be calculated.
 260 */
 261static unsigned int
 262serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 263{
 264	unsigned int mode;
 265
 266	if (!serial_omap_baud_is_mode16(port, baud))
 267		mode = 13;
 268	else
 269		mode = 16;
 270	return port->uartclk/(mode * baud);
 271}
 272
 273static void serial_omap_enable_ms(struct uart_port *port)
 274{
 275	struct uart_omap_port *up = to_uart_omap_port(port);
 276
 277	dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 278
 279	pm_runtime_get_sync(up->dev);
 280	up->ier |= UART_IER_MSI;
 281	serial_out(up, UART_IER, up->ier);
 282	pm_runtime_mark_last_busy(up->dev);
 283	pm_runtime_put_autosuspend(up->dev);
 284}
 285
 286static void serial_omap_stop_tx(struct uart_port *port)
 287{
 288	struct uart_omap_port *up = to_uart_omap_port(port);
 289	int res;
 290
 291	pm_runtime_get_sync(up->dev);
 292
 293	/* Handle RS-485 */
 294	if (port->rs485.flags & SER_RS485_ENABLED) {
 295		if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 296			/* THR interrupt is fired when both TX FIFO and TX
 297			 * shift register are empty. This means there's nothing
 298			 * left to transmit now, so make sure the THR interrupt
 299			 * is fired when TX FIFO is below the trigger level,
 300			 * disable THR interrupts and toggle the RS-485 GPIO
 301			 * data direction pin if needed.
 302			 */
 303			up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 304			serial_out(up, UART_OMAP_SCR, up->scr);
 305			res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
 306				1 : 0;
 307			if (up->rts_gpiod &&
 308			    gpiod_get_value(up->rts_gpiod) != res) {
 309				if (port->rs485.delay_rts_after_send > 0)
 310					mdelay(
 311					port->rs485.delay_rts_after_send);
 312				gpiod_set_value(up->rts_gpiod, res);
 313			}
 314		} else {
 315			/* We're asked to stop, but there's still stuff in the
 316			 * UART FIFO, so make sure the THR interrupt is fired
 317			 * when both TX FIFO and TX shift register are empty.
 318			 * The next THR interrupt (if no transmission is started
 319			 * in the meantime) will indicate the end of a
 320			 * transmission. Therefore we _don't_ disable THR
 321			 * interrupts in this situation.
 322			 */
 323			up->scr |= OMAP_UART_SCR_TX_EMPTY;
 324			serial_out(up, UART_OMAP_SCR, up->scr);
 325			return;
 326		}
 327	}
 328
 329	if (up->ier & UART_IER_THRI) {
 330		up->ier &= ~UART_IER_THRI;
 331		serial_out(up, UART_IER, up->ier);
 332	}
 333
 
 
 
 
 
 
 
 
 
 
 
 
 
 334	pm_runtime_mark_last_busy(up->dev);
 335	pm_runtime_put_autosuspend(up->dev);
 336}
 337
 338static void serial_omap_stop_rx(struct uart_port *port)
 339{
 340	struct uart_omap_port *up = to_uart_omap_port(port);
 341
 342	pm_runtime_get_sync(up->dev);
 343	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 344	up->port.read_status_mask &= ~UART_LSR_DR;
 345	serial_out(up, UART_IER, up->ier);
 346	pm_runtime_mark_last_busy(up->dev);
 347	pm_runtime_put_autosuspend(up->dev);
 348}
 349
 350static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 351{
 352	struct circ_buf *xmit = &up->port.state->xmit;
 353	int count;
 354
 355	if (up->port.x_char) {
 356		serial_out(up, UART_TX, up->port.x_char);
 357		up->port.icount.tx++;
 358		up->port.x_char = 0;
 359		if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 360		    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
 361			up->rs485_tx_filter_count++;
 362
 363		return;
 364	}
 365	if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 366		serial_omap_stop_tx(&up->port);
 367		return;
 368	}
 369	count = up->port.fifosize / 4;
 370	do {
 371		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 372		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 373		up->port.icount.tx++;
 374		if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 375		    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
 376			up->rs485_tx_filter_count++;
 377
 378		if (uart_circ_empty(xmit))
 379			break;
 380	} while (--count > 0);
 381
 382	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 383		uart_write_wakeup(&up->port);
 384
 385	if (uart_circ_empty(xmit))
 386		serial_omap_stop_tx(&up->port);
 387}
 388
 389static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 390{
 391	if (!(up->ier & UART_IER_THRI)) {
 392		up->ier |= UART_IER_THRI;
 393		serial_out(up, UART_IER, up->ier);
 394	}
 395}
 396
 397static void serial_omap_start_tx(struct uart_port *port)
 398{
 399	struct uart_omap_port *up = to_uart_omap_port(port);
 400	int res;
 401
 402	pm_runtime_get_sync(up->dev);
 403
 404	/* Handle RS-485 */
 405	if (port->rs485.flags & SER_RS485_ENABLED) {
 406		/* Fire THR interrupts when FIFO is below trigger level */
 407		up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 408		serial_out(up, UART_OMAP_SCR, up->scr);
 409
 410		/* if rts not already enabled */
 411		res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 412		if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) {
 413			gpiod_set_value(up->rts_gpiod, res);
 414			if (port->rs485.delay_rts_before_send > 0)
 415				mdelay(port->rs485.delay_rts_before_send);
 416		}
 417	}
 418
 419	if ((port->rs485.flags & SER_RS485_ENABLED) &&
 420	    !(port->rs485.flags & SER_RS485_RX_DURING_TX))
 421		up->rs485_tx_filter_count = 0;
 422
 423	serial_omap_enable_ier_thri(up);
 424	pm_runtime_mark_last_busy(up->dev);
 425	pm_runtime_put_autosuspend(up->dev);
 426}
 427
 428static void serial_omap_throttle(struct uart_port *port)
 429{
 430	struct uart_omap_port *up = to_uart_omap_port(port);
 431	unsigned long flags;
 432
 433	pm_runtime_get_sync(up->dev);
 434	spin_lock_irqsave(&up->port.lock, flags);
 435	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 436	serial_out(up, UART_IER, up->ier);
 437	spin_unlock_irqrestore(&up->port.lock, flags);
 438	pm_runtime_mark_last_busy(up->dev);
 439	pm_runtime_put_autosuspend(up->dev);
 440}
 441
 442static void serial_omap_unthrottle(struct uart_port *port)
 443{
 444	struct uart_omap_port *up = to_uart_omap_port(port);
 445	unsigned long flags;
 446
 447	pm_runtime_get_sync(up->dev);
 448	spin_lock_irqsave(&up->port.lock, flags);
 449	up->ier |= UART_IER_RLSI | UART_IER_RDI;
 450	serial_out(up, UART_IER, up->ier);
 451	spin_unlock_irqrestore(&up->port.lock, flags);
 452	pm_runtime_mark_last_busy(up->dev);
 453	pm_runtime_put_autosuspend(up->dev);
 454}
 455
 456static unsigned int check_modem_status(struct uart_omap_port *up)
 457{
 458	unsigned int status;
 459
 460	status = serial_in(up, UART_MSR);
 461	status |= up->msr_saved_flags;
 462	up->msr_saved_flags = 0;
 463	if ((status & UART_MSR_ANY_DELTA) == 0)
 464		return status;
 465
 466	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 467	    up->port.state != NULL) {
 468		if (status & UART_MSR_TERI)
 469			up->port.icount.rng++;
 470		if (status & UART_MSR_DDSR)
 471			up->port.icount.dsr++;
 472		if (status & UART_MSR_DDCD)
 473			uart_handle_dcd_change
 474				(&up->port, status & UART_MSR_DCD);
 475		if (status & UART_MSR_DCTS)
 476			uart_handle_cts_change
 477				(&up->port, status & UART_MSR_CTS);
 478		wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 479	}
 480
 481	return status;
 482}
 483
 484static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 485{
 486	unsigned int flag;
 
 487
 488	/*
 489	 * Read one data character out to avoid stalling the receiver according
 490	 * to the table 23-246 of the omap4 TRM.
 491	 */
 492	if (likely(lsr & UART_LSR_DR)) {
 493		serial_in(up, UART_RX);
 494		if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 495		    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
 496		    up->rs485_tx_filter_count)
 497			up->rs485_tx_filter_count--;
 498	}
 499
 500	up->port.icount.rx++;
 501	flag = TTY_NORMAL;
 502
 503	if (lsr & UART_LSR_BI) {
 504		flag = TTY_BREAK;
 505		lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 506		up->port.icount.brk++;
 507		/*
 508		 * We do the SysRQ and SAK checking
 509		 * here because otherwise the break
 510		 * may get masked by ignore_status_mask
 511		 * or read_status_mask.
 512		 */
 513		if (uart_handle_break(&up->port))
 514			return;
 515
 516	}
 517
 518	if (lsr & UART_LSR_PE) {
 519		flag = TTY_PARITY;
 520		up->port.icount.parity++;
 521	}
 522
 523	if (lsr & UART_LSR_FE) {
 524		flag = TTY_FRAME;
 525		up->port.icount.frame++;
 526	}
 527
 528	if (lsr & UART_LSR_OE)
 529		up->port.icount.overrun++;
 530
 531#ifdef CONFIG_SERIAL_OMAP_CONSOLE
 532	if (up->port.line == up->port.cons->index) {
 533		/* Recover the break flag from console xmit */
 534		lsr |= up->lsr_break_flag;
 535	}
 536#endif
 537	uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 538}
 539
 540static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 541{
 542	unsigned char ch = 0;
 543	unsigned int flag;
 544
 545	if (!(lsr & UART_LSR_DR))
 546		return;
 547
 548	ch = serial_in(up, UART_RX);
 549	if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 550	    !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
 551	    up->rs485_tx_filter_count) {
 552		up->rs485_tx_filter_count--;
 553		return;
 554	}
 555
 556	flag = TTY_NORMAL;
 557	up->port.icount.rx++;
 558
 559	if (uart_handle_sysrq_char(&up->port, ch))
 560		return;
 561
 562	uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 563}
 564
 565/**
 566 * serial_omap_irq() - This handles the interrupt from one port
 567 * @irq: uart port irq number
 568 * @dev_id: uart port info
 569 */
 570static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 571{
 572	struct uart_omap_port *up = dev_id;
 573	unsigned int iir, lsr;
 574	unsigned int type;
 575	irqreturn_t ret = IRQ_NONE;
 576	int max_count = 256;
 577
 578	spin_lock(&up->port.lock);
 579	pm_runtime_get_sync(up->dev);
 580
 581	do {
 582		iir = serial_in(up, UART_IIR);
 583		if (iir & UART_IIR_NO_INT)
 584			break;
 585
 586		ret = IRQ_HANDLED;
 587		lsr = serial_in(up, UART_LSR);
 588
 589		/* extract IRQ type from IIR register */
 590		type = iir & 0x3e;
 591
 592		switch (type) {
 593		case UART_IIR_MSI:
 594			check_modem_status(up);
 595			break;
 596		case UART_IIR_THRI:
 597			transmit_chars(up, lsr);
 598			break;
 599		case UART_IIR_RX_TIMEOUT:
 
 600		case UART_IIR_RDI:
 601			serial_omap_rdi(up, lsr);
 602			break;
 603		case UART_IIR_RLSI:
 604			serial_omap_rlsi(up, lsr);
 605			break;
 606		case UART_IIR_CTS_RTS_DSR:
 607			/* simply try again */
 608			break;
 609		case UART_IIR_XOFF:
 
 610		default:
 611			break;
 612		}
 613	} while (max_count--);
 614
 615	spin_unlock(&up->port.lock);
 616
 617	tty_flip_buffer_push(&up->port.state->port);
 618
 619	pm_runtime_mark_last_busy(up->dev);
 620	pm_runtime_put_autosuspend(up->dev);
 621	up->port_activity = jiffies;
 622
 623	return ret;
 624}
 625
 626static unsigned int serial_omap_tx_empty(struct uart_port *port)
 627{
 628	struct uart_omap_port *up = to_uart_omap_port(port);
 629	unsigned long flags;
 630	unsigned int ret = 0;
 631
 632	pm_runtime_get_sync(up->dev);
 633	dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 634	spin_lock_irqsave(&up->port.lock, flags);
 635	ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 636	spin_unlock_irqrestore(&up->port.lock, flags);
 637	pm_runtime_mark_last_busy(up->dev);
 638	pm_runtime_put_autosuspend(up->dev);
 639	return ret;
 640}
 641
 642static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 643{
 644	struct uart_omap_port *up = to_uart_omap_port(port);
 645	unsigned int status;
 646	unsigned int ret = 0;
 647
 648	pm_runtime_get_sync(up->dev);
 649	status = check_modem_status(up);
 650	pm_runtime_mark_last_busy(up->dev);
 651	pm_runtime_put_autosuspend(up->dev);
 652
 653	dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 654
 655	if (status & UART_MSR_DCD)
 656		ret |= TIOCM_CAR;
 657	if (status & UART_MSR_RI)
 658		ret |= TIOCM_RNG;
 659	if (status & UART_MSR_DSR)
 660		ret |= TIOCM_DSR;
 661	if (status & UART_MSR_CTS)
 662		ret |= TIOCM_CTS;
 663	return ret;
 664}
 665
 666static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 667{
 668	struct uart_omap_port *up = to_uart_omap_port(port);
 669	unsigned char mcr = 0, old_mcr, lcr;
 670
 671	dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 672	if (mctrl & TIOCM_RTS)
 673		mcr |= UART_MCR_RTS;
 674	if (mctrl & TIOCM_DTR)
 675		mcr |= UART_MCR_DTR;
 676	if (mctrl & TIOCM_OUT1)
 677		mcr |= UART_MCR_OUT1;
 678	if (mctrl & TIOCM_OUT2)
 679		mcr |= UART_MCR_OUT2;
 680	if (mctrl & TIOCM_LOOP)
 681		mcr |= UART_MCR_LOOP;
 682
 683	pm_runtime_get_sync(up->dev);
 684	old_mcr = serial_in(up, UART_MCR);
 685	old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 686		     UART_MCR_DTR | UART_MCR_RTS);
 687	up->mcr = old_mcr | mcr;
 688	serial_out(up, UART_MCR, up->mcr);
 689
 690	/* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
 691	lcr = serial_in(up, UART_LCR);
 692	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 693	if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 694		up->efr |= UART_EFR_RTS;
 695	else
 696		up->efr &= ~UART_EFR_RTS;
 697	serial_out(up, UART_EFR, up->efr);
 698	serial_out(up, UART_LCR, lcr);
 699
 700	pm_runtime_mark_last_busy(up->dev);
 701	pm_runtime_put_autosuspend(up->dev);
 702}
 703
 704static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 705{
 706	struct uart_omap_port *up = to_uart_omap_port(port);
 707	unsigned long flags;
 708
 709	dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 710	pm_runtime_get_sync(up->dev);
 711	spin_lock_irqsave(&up->port.lock, flags);
 712	if (break_state == -1)
 713		up->lcr |= UART_LCR_SBC;
 714	else
 715		up->lcr &= ~UART_LCR_SBC;
 716	serial_out(up, UART_LCR, up->lcr);
 717	spin_unlock_irqrestore(&up->port.lock, flags);
 718	pm_runtime_mark_last_busy(up->dev);
 719	pm_runtime_put_autosuspend(up->dev);
 720}
 721
 722static int serial_omap_startup(struct uart_port *port)
 723{
 724	struct uart_omap_port *up = to_uart_omap_port(port);
 725	unsigned long flags;
 726	int retval;
 727
 728	/*
 729	 * Allocate the IRQ
 730	 */
 731	retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 732				up->name, up);
 733	if (retval)
 734		return retval;
 735
 736	/* Optional wake-up IRQ */
 737	if (up->wakeirq) {
 738		retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
 739		if (retval) {
 740			free_irq(up->port.irq, up);
 741			return retval;
 742		}
 743	}
 744
 745	dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 746
 747	pm_runtime_get_sync(up->dev);
 748	/*
 749	 * Clear the FIFO buffers and disable them.
 750	 * (they will be reenabled in set_termios())
 751	 */
 752	serial_omap_clear_fifos(up);
 753
 754	/*
 755	 * Clear the interrupt registers.
 756	 */
 757	(void) serial_in(up, UART_LSR);
 758	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 759		(void) serial_in(up, UART_RX);
 760	(void) serial_in(up, UART_IIR);
 761	(void) serial_in(up, UART_MSR);
 762
 763	/*
 764	 * Now, initialize the UART
 765	 */
 766	serial_out(up, UART_LCR, UART_LCR_WLEN8);
 767	spin_lock_irqsave(&up->port.lock, flags);
 768	/*
 769	 * Most PC uarts need OUT2 raised to enable interrupts.
 770	 */
 771	up->port.mctrl |= TIOCM_OUT2;
 772	serial_omap_set_mctrl(&up->port, up->port.mctrl);
 773	spin_unlock_irqrestore(&up->port.lock, flags);
 774
 775	up->msr_saved_flags = 0;
 776	/*
 777	 * Finally, enable interrupts. Note: Modem status interrupts
 778	 * are set via set_termios(), which will be occurring imminently
 779	 * anyway, so we don't enable them here.
 780	 */
 781	up->ier = UART_IER_RLSI | UART_IER_RDI;
 782	serial_out(up, UART_IER, up->ier);
 783
 784	/* Enable module level wake up */
 785	up->wer = OMAP_UART_WER_MOD_WKUP;
 786	if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 787		up->wer |= OMAP_UART_TX_WAKEUP_EN;
 788
 789	serial_out(up, UART_OMAP_WER, up->wer);
 790
 791	pm_runtime_mark_last_busy(up->dev);
 792	pm_runtime_put_autosuspend(up->dev);
 793	up->port_activity = jiffies;
 794	return 0;
 795}
 796
 797static void serial_omap_shutdown(struct uart_port *port)
 798{
 799	struct uart_omap_port *up = to_uart_omap_port(port);
 800	unsigned long flags;
 801
 802	dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 803
 804	pm_runtime_get_sync(up->dev);
 805	/*
 806	 * Disable interrupts from this port
 807	 */
 808	up->ier = 0;
 809	serial_out(up, UART_IER, 0);
 810
 811	spin_lock_irqsave(&up->port.lock, flags);
 812	up->port.mctrl &= ~TIOCM_OUT2;
 813	serial_omap_set_mctrl(&up->port, up->port.mctrl);
 814	spin_unlock_irqrestore(&up->port.lock, flags);
 815
 816	/*
 817	 * Disable break condition and FIFOs
 818	 */
 819	serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 820	serial_omap_clear_fifos(up);
 821
 822	/*
 823	 * Read data port to reset things, and then free the irq
 824	 */
 825	if (serial_in(up, UART_LSR) & UART_LSR_DR)
 826		(void) serial_in(up, UART_RX);
 827
 828	pm_runtime_mark_last_busy(up->dev);
 829	pm_runtime_put_autosuspend(up->dev);
 830	free_irq(up->port.irq, up);
 831	dev_pm_clear_wake_irq(up->dev);
 832}
 833
 834static void serial_omap_uart_qos_work(struct work_struct *work)
 835{
 836	struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 837						qos_work);
 838
 839	cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
 840}
 841
 842static void
 843serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 844			struct ktermios *old)
 845{
 846	struct uart_omap_port *up = to_uart_omap_port(port);
 847	unsigned char cval = 0;
 848	unsigned long flags;
 849	unsigned int baud, quot;
 850
 851	switch (termios->c_cflag & CSIZE) {
 852	case CS5:
 853		cval = UART_LCR_WLEN5;
 854		break;
 855	case CS6:
 856		cval = UART_LCR_WLEN6;
 857		break;
 858	case CS7:
 859		cval = UART_LCR_WLEN7;
 860		break;
 861	default:
 862	case CS8:
 863		cval = UART_LCR_WLEN8;
 864		break;
 865	}
 866
 867	if (termios->c_cflag & CSTOPB)
 868		cval |= UART_LCR_STOP;
 869	if (termios->c_cflag & PARENB)
 870		cval |= UART_LCR_PARITY;
 871	if (!(termios->c_cflag & PARODD))
 872		cval |= UART_LCR_EPAR;
 873	if (termios->c_cflag & CMSPAR)
 874		cval |= UART_LCR_SPAR;
 875
 876	/*
 877	 * Ask the core to calculate the divisor for us.
 878	 */
 879
 880	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 881	quot = serial_omap_get_divisor(port, baud);
 882
 883	/* calculate wakeup latency constraint */
 884	up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 885	up->latency = up->calc_latency;
 886	schedule_work(&up->qos_work);
 887
 888	up->dll = quot & 0xff;
 889	up->dlh = quot >> 8;
 890	up->mdr1 = UART_OMAP_MDR1_DISABLE;
 891
 892	up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 893			UART_FCR_ENABLE_FIFO;
 894
 895	/*
 896	 * Ok, we're now changing the port state. Do it with
 897	 * interrupts disabled.
 898	 */
 899	pm_runtime_get_sync(up->dev);
 900	spin_lock_irqsave(&up->port.lock, flags);
 901
 902	/*
 903	 * Update the per-port timeout.
 904	 */
 905	uart_update_timeout(port, termios->c_cflag, baud);
 906
 907	up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 908	if (termios->c_iflag & INPCK)
 909		up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 910	if (termios->c_iflag & (BRKINT | PARMRK))
 911		up->port.read_status_mask |= UART_LSR_BI;
 912
 913	/*
 914	 * Characters to ignore
 915	 */
 916	up->port.ignore_status_mask = 0;
 917	if (termios->c_iflag & IGNPAR)
 918		up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 919	if (termios->c_iflag & IGNBRK) {
 920		up->port.ignore_status_mask |= UART_LSR_BI;
 921		/*
 922		 * If we're ignoring parity and break indicators,
 923		 * ignore overruns too (for real raw support).
 924		 */
 925		if (termios->c_iflag & IGNPAR)
 926			up->port.ignore_status_mask |= UART_LSR_OE;
 927	}
 928
 929	/*
 930	 * ignore all characters if CREAD is not set
 931	 */
 932	if ((termios->c_cflag & CREAD) == 0)
 933		up->port.ignore_status_mask |= UART_LSR_DR;
 934
 935	/*
 936	 * Modem status interrupts
 937	 */
 938	up->ier &= ~UART_IER_MSI;
 939	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 940		up->ier |= UART_IER_MSI;
 941	serial_out(up, UART_IER, up->ier);
 942	serial_out(up, UART_LCR, cval);		/* reset DLAB */
 943	up->lcr = cval;
 944	up->scr = 0;
 945
 946	/* FIFOs and DMA Settings */
 947
 948	/* FCR can be changed only when the
 949	 * baud clock is not running
 950	 * DLL_REG and DLH_REG set to 0.
 951	 */
 952	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 953	serial_out(up, UART_DLL, 0);
 954	serial_out(up, UART_DLM, 0);
 955	serial_out(up, UART_LCR, 0);
 956
 957	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 958
 959	up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 960	up->efr &= ~UART_EFR_SCD;
 961	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 962
 963	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 964	up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 965	serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 966	/* FIFO ENABLE, DMA MODE */
 967
 968	up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 969	/*
 970	 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 971	 * sets Enables the granularity of 1 for TRIGGER RX
 972	 * level. Along with setting RX FIFO trigger level
 973	 * to 1 (as noted below, 16 characters) and TLR[3:0]
 974	 * to zero this will result RX FIFO threshold level
 975	 * to 1 character, instead of 16 as noted in comment
 976	 * below.
 977	 */
 978
 979	/* Set receive FIFO threshold to 16 characters and
 980	 * transmit FIFO threshold to 32 spaces
 981	 */
 982	up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 983	up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 984	up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 985		UART_FCR_ENABLE_FIFO;
 986
 987	serial_out(up, UART_FCR, up->fcr);
 988	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 989
 990	serial_out(up, UART_OMAP_SCR, up->scr);
 991
 992	/* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 993	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 994	serial_out(up, UART_MCR, up->mcr);
 995	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 996	serial_out(up, UART_EFR, up->efr);
 997	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 998
 999	/* Protocol, Baud Rate, and Interrupt Settings */
1000
1001	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1002		serial_omap_mdr1_errataset(up, up->mdr1);
1003	else
1004		serial_out(up, UART_OMAP_MDR1, up->mdr1);
1005
1006	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1007	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1008
1009	serial_out(up, UART_LCR, 0);
1010	serial_out(up, UART_IER, 0);
1011	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1012
1013	serial_out(up, UART_DLL, up->dll);	/* LS of divisor */
1014	serial_out(up, UART_DLM, up->dlh);	/* MS of divisor */
1015
1016	serial_out(up, UART_LCR, 0);
1017	serial_out(up, UART_IER, up->ier);
1018	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1019
1020	serial_out(up, UART_EFR, up->efr);
1021	serial_out(up, UART_LCR, cval);
1022
1023	if (!serial_omap_baud_is_mode16(port, baud))
1024		up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1025	else
1026		up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1027
1028	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1029		serial_omap_mdr1_errataset(up, up->mdr1);
1030	else
1031		serial_out(up, UART_OMAP_MDR1, up->mdr1);
1032
1033	/* Configure flow control */
1034	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1035
1036	/* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1037	serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1038	serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1039
1040	/* Enable access to TCR/TLR */
1041	serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1042	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1043	serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1044
1045	serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1046
1047	up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1048
1049	if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1050		/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1051		up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1052		up->efr |= UART_EFR_CTS;
1053	} else {
1054		/* Disable AUTORTS and AUTOCTS */
1055		up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1056	}
1057
1058	if (up->port.flags & UPF_SOFT_FLOW) {
1059		/* clear SW control mode bits */
1060		up->efr &= OMAP_UART_SW_CLR;
1061
1062		/*
1063		 * IXON Flag:
1064		 * Enable XON/XOFF flow control on input.
1065		 * Receiver compares XON1, XOFF1.
1066		 */
1067		if (termios->c_iflag & IXON)
1068			up->efr |= OMAP_UART_SW_RX;
1069
1070		/*
1071		 * IXOFF Flag:
1072		 * Enable XON/XOFF flow control on output.
1073		 * Transmit XON1, XOFF1
1074		 */
1075		if (termios->c_iflag & IXOFF) {
1076			up->port.status |= UPSTAT_AUTOXOFF;
1077			up->efr |= OMAP_UART_SW_TX;
1078		}
1079
1080		/*
1081		 * IXANY Flag:
1082		 * Enable any character to restart output.
1083		 * Operation resumes after receiving any
1084		 * character after recognition of the XOFF character
1085		 */
1086		if (termios->c_iflag & IXANY)
1087			up->mcr |= UART_MCR_XONANY;
1088		else
1089			up->mcr &= ~UART_MCR_XONANY;
1090	}
1091	serial_out(up, UART_MCR, up->mcr);
1092	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1093	serial_out(up, UART_EFR, up->efr);
1094	serial_out(up, UART_LCR, up->lcr);
1095
1096	serial_omap_set_mctrl(&up->port, up->port.mctrl);
1097
1098	spin_unlock_irqrestore(&up->port.lock, flags);
1099	pm_runtime_mark_last_busy(up->dev);
1100	pm_runtime_put_autosuspend(up->dev);
1101	dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1102}
1103
1104static void
1105serial_omap_pm(struct uart_port *port, unsigned int state,
1106	       unsigned int oldstate)
1107{
1108	struct uart_omap_port *up = to_uart_omap_port(port);
1109	unsigned char efr;
1110
1111	dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1112
1113	pm_runtime_get_sync(up->dev);
1114	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1115	efr = serial_in(up, UART_EFR);
1116	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1117	serial_out(up, UART_LCR, 0);
1118
1119	serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1120	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1121	serial_out(up, UART_EFR, efr);
1122	serial_out(up, UART_LCR, 0);
1123
1124	pm_runtime_mark_last_busy(up->dev);
1125	pm_runtime_put_autosuspend(up->dev);
1126}
1127
1128static void serial_omap_release_port(struct uart_port *port)
1129{
1130	dev_dbg(port->dev, "serial_omap_release_port+\n");
1131}
1132
1133static int serial_omap_request_port(struct uart_port *port)
1134{
1135	dev_dbg(port->dev, "serial_omap_request_port+\n");
1136	return 0;
1137}
1138
1139static void serial_omap_config_port(struct uart_port *port, int flags)
1140{
1141	struct uart_omap_port *up = to_uart_omap_port(port);
1142
1143	dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1144							up->port.line);
1145	up->port.type = PORT_OMAP;
1146	up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1147}
1148
1149static int
1150serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1151{
1152	/* we don't want the core code to modify any port params */
1153	dev_dbg(port->dev, "serial_omap_verify_port+\n");
1154	return -EINVAL;
1155}
1156
1157static const char *
1158serial_omap_type(struct uart_port *port)
1159{
1160	struct uart_omap_port *up = to_uart_omap_port(port);
1161
1162	dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1163	return up->name;
1164}
1165
1166#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1167
1168static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1169{
1170	unsigned int status, tmout = 10000;
1171
1172	/* Wait up to 10ms for the character(s) to be sent. */
1173	do {
1174		status = serial_in(up, UART_LSR);
1175
1176		if (status & UART_LSR_BI)
1177			up->lsr_break_flag = UART_LSR_BI;
1178
1179		if (--tmout == 0)
1180			break;
1181		udelay(1);
1182	} while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1183
1184	/* Wait up to 1s for flow control if necessary */
1185	if (up->port.flags & UPF_CONS_FLOW) {
1186		tmout = 1000000;
1187		for (tmout = 1000000; tmout; tmout--) {
1188			unsigned int msr = serial_in(up, UART_MSR);
1189
1190			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1191			if (msr & UART_MSR_CTS)
1192				break;
1193
1194			udelay(1);
1195		}
1196	}
1197}
1198
1199#ifdef CONFIG_CONSOLE_POLL
1200
1201static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1202{
1203	struct uart_omap_port *up = to_uart_omap_port(port);
1204
1205	pm_runtime_get_sync(up->dev);
1206	wait_for_xmitr(up);
1207	serial_out(up, UART_TX, ch);
1208	pm_runtime_mark_last_busy(up->dev);
1209	pm_runtime_put_autosuspend(up->dev);
1210}
1211
1212static int serial_omap_poll_get_char(struct uart_port *port)
1213{
1214	struct uart_omap_port *up = to_uart_omap_port(port);
1215	unsigned int status;
1216
1217	pm_runtime_get_sync(up->dev);
1218	status = serial_in(up, UART_LSR);
1219	if (!(status & UART_LSR_DR)) {
1220		status = NO_POLL_CHAR;
1221		goto out;
1222	}
1223
1224	status = serial_in(up, UART_RX);
1225
1226out:
1227	pm_runtime_mark_last_busy(up->dev);
1228	pm_runtime_put_autosuspend(up->dev);
1229
1230	return status;
1231}
1232
1233#endif /* CONFIG_CONSOLE_POLL */
1234
1235#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1236
1237#ifdef CONFIG_SERIAL_EARLYCON
1238static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1239{
1240	offset <<= port->regshift;
1241	return readw(port->membase + offset);
1242}
1243
1244static void omap_serial_early_out(struct uart_port *port, int offset,
1245				  int value)
1246{
1247	offset <<= port->regshift;
1248	writew(value, port->membase + offset);
1249}
1250
1251static void omap_serial_early_putc(struct uart_port *port, int c)
1252{
1253	unsigned int status;
1254
1255	for (;;) {
1256		status = omap_serial_early_in(port, UART_LSR);
1257		if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1258			break;
1259		cpu_relax();
1260	}
1261	omap_serial_early_out(port, UART_TX, c);
1262}
1263
1264static void early_omap_serial_write(struct console *console, const char *s,
1265				    unsigned int count)
1266{
1267	struct earlycon_device *device = console->data;
1268	struct uart_port *port = &device->port;
1269
1270	uart_console_write(port, s, count, omap_serial_early_putc);
1271}
1272
1273static int __init early_omap_serial_setup(struct earlycon_device *device,
1274					  const char *options)
1275{
1276	struct uart_port *port = &device->port;
1277
1278	if (!(device->port.membase || device->port.iobase))
1279		return -ENODEV;
1280
1281	port->regshift = 2;
1282	device->con->write = early_omap_serial_write;
1283	return 0;
1284}
1285
1286OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1287OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1288OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1289#endif /* CONFIG_SERIAL_EARLYCON */
1290
1291static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1292
1293static struct uart_driver serial_omap_reg;
1294
1295static void serial_omap_console_putchar(struct uart_port *port, int ch)
1296{
1297	struct uart_omap_port *up = to_uart_omap_port(port);
1298
1299	wait_for_xmitr(up);
1300	serial_out(up, UART_TX, ch);
1301}
1302
1303static void
1304serial_omap_console_write(struct console *co, const char *s,
1305		unsigned int count)
1306{
1307	struct uart_omap_port *up = serial_omap_console_ports[co->index];
1308	unsigned long flags;
1309	unsigned int ier;
1310	int locked = 1;
1311
1312	pm_runtime_get_sync(up->dev);
1313
1314	local_irq_save(flags);
1315	if (up->port.sysrq)
1316		locked = 0;
1317	else if (oops_in_progress)
1318		locked = spin_trylock(&up->port.lock);
1319	else
1320		spin_lock(&up->port.lock);
1321
1322	/*
1323	 * First save the IER then disable the interrupts
1324	 */
1325	ier = serial_in(up, UART_IER);
1326	serial_out(up, UART_IER, 0);
1327
1328	uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1329
1330	/*
1331	 * Finally, wait for transmitter to become empty
1332	 * and restore the IER
1333	 */
1334	wait_for_xmitr(up);
1335	serial_out(up, UART_IER, ier);
1336	/*
1337	 * The receive handling will happen properly because the
1338	 * receive ready bit will still be set; it is not cleared
1339	 * on read.  However, modem control will not, we must
1340	 * call it if we have saved something in the saved flags
1341	 * while processing with interrupts off.
1342	 */
1343	if (up->msr_saved_flags)
1344		check_modem_status(up);
1345
1346	pm_runtime_mark_last_busy(up->dev);
1347	pm_runtime_put_autosuspend(up->dev);
1348	if (locked)
1349		spin_unlock(&up->port.lock);
1350	local_irq_restore(flags);
1351}
1352
1353static int __init
1354serial_omap_console_setup(struct console *co, char *options)
1355{
1356	struct uart_omap_port *up;
1357	int baud = 115200;
1358	int bits = 8;
1359	int parity = 'n';
1360	int flow = 'n';
1361
1362	if (serial_omap_console_ports[co->index] == NULL)
1363		return -ENODEV;
1364	up = serial_omap_console_ports[co->index];
1365
1366	if (options)
1367		uart_parse_options(options, &baud, &parity, &bits, &flow);
1368
1369	return uart_set_options(&up->port, co, baud, parity, bits, flow);
1370}
1371
1372static struct console serial_omap_console = {
1373	.name		= OMAP_SERIAL_NAME,
1374	.write		= serial_omap_console_write,
1375	.device		= uart_console_device,
1376	.setup		= serial_omap_console_setup,
1377	.flags		= CON_PRINTBUFFER,
1378	.index		= -1,
1379	.data		= &serial_omap_reg,
1380};
1381
1382static void serial_omap_add_console_port(struct uart_omap_port *up)
1383{
1384	serial_omap_console_ports[up->port.line] = up;
1385}
1386
1387#define OMAP_CONSOLE	(&serial_omap_console)
1388
1389#else
1390
1391#define OMAP_CONSOLE	NULL
1392
1393static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1394{}
1395
1396#endif
1397
1398/* Enable or disable the rs485 support */
1399static int
1400serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1401{
1402	struct uart_omap_port *up = to_uart_omap_port(port);
1403	unsigned int mode;
1404	int val;
1405
1406	pm_runtime_get_sync(up->dev);
1407
1408	/* Disable interrupts from this port */
1409	mode = up->ier;
1410	up->ier = 0;
1411	serial_out(up, UART_IER, 0);
1412
1413	/* Clamp the delays to [0, 100ms] */
1414	rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1415	rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
1416
1417	/* store new config */
1418	port->rs485 = *rs485;
1419
1420	if (up->rts_gpiod) {
 
 
 
 
1421		/* enable / disable rts */
1422		val = (port->rs485.flags & SER_RS485_ENABLED) ?
1423			SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1424		val = (port->rs485.flags & val) ? 1 : 0;
1425		gpiod_set_value(up->rts_gpiod, val);
1426	}
 
1427
1428	/* Enable interrupts */
1429	up->ier = mode;
1430	serial_out(up, UART_IER, up->ier);
1431
1432	/* If RS-485 is disabled, make sure the THR interrupt is fired when
1433	 * TX FIFO is below the trigger level.
1434	 */
1435	if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1436	    (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1437		up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1438		serial_out(up, UART_OMAP_SCR, up->scr);
1439	}
1440
1441	pm_runtime_mark_last_busy(up->dev);
1442	pm_runtime_put_autosuspend(up->dev);
1443
1444	return 0;
1445}
1446
1447static const struct uart_ops serial_omap_pops = {
1448	.tx_empty	= serial_omap_tx_empty,
1449	.set_mctrl	= serial_omap_set_mctrl,
1450	.get_mctrl	= serial_omap_get_mctrl,
1451	.stop_tx	= serial_omap_stop_tx,
1452	.start_tx	= serial_omap_start_tx,
1453	.throttle	= serial_omap_throttle,
1454	.unthrottle	= serial_omap_unthrottle,
1455	.stop_rx	= serial_omap_stop_rx,
1456	.enable_ms	= serial_omap_enable_ms,
1457	.break_ctl	= serial_omap_break_ctl,
1458	.startup	= serial_omap_startup,
1459	.shutdown	= serial_omap_shutdown,
1460	.set_termios	= serial_omap_set_termios,
1461	.pm		= serial_omap_pm,
1462	.type		= serial_omap_type,
1463	.release_port	= serial_omap_release_port,
1464	.request_port	= serial_omap_request_port,
1465	.config_port	= serial_omap_config_port,
1466	.verify_port	= serial_omap_verify_port,
1467#ifdef CONFIG_CONSOLE_POLL
1468	.poll_put_char  = serial_omap_poll_put_char,
1469	.poll_get_char  = serial_omap_poll_get_char,
1470#endif
1471};
1472
1473static struct uart_driver serial_omap_reg = {
1474	.owner		= THIS_MODULE,
1475	.driver_name	= "OMAP-SERIAL",
1476	.dev_name	= OMAP_SERIAL_NAME,
1477	.nr		= OMAP_MAX_HSUART_PORTS,
1478	.cons		= OMAP_CONSOLE,
1479};
1480
1481#ifdef CONFIG_PM_SLEEP
1482static int serial_omap_prepare(struct device *dev)
1483{
1484	struct uart_omap_port *up = dev_get_drvdata(dev);
1485
1486	up->is_suspending = true;
1487
1488	return 0;
1489}
1490
1491static void serial_omap_complete(struct device *dev)
1492{
1493	struct uart_omap_port *up = dev_get_drvdata(dev);
1494
1495	up->is_suspending = false;
1496}
1497
1498static int serial_omap_suspend(struct device *dev)
1499{
1500	struct uart_omap_port *up = dev_get_drvdata(dev);
1501
1502	uart_suspend_port(&serial_omap_reg, &up->port);
1503	flush_work(&up->qos_work);
1504
1505	if (device_may_wakeup(dev))
1506		serial_omap_enable_wakeup(up, true);
1507	else
1508		serial_omap_enable_wakeup(up, false);
1509
1510	return 0;
1511}
1512
1513static int serial_omap_resume(struct device *dev)
1514{
1515	struct uart_omap_port *up = dev_get_drvdata(dev);
1516
1517	if (device_may_wakeup(dev))
1518		serial_omap_enable_wakeup(up, false);
1519
1520	uart_resume_port(&serial_omap_reg, &up->port);
1521
1522	return 0;
1523}
1524#else
1525#define serial_omap_prepare NULL
1526#define serial_omap_complete NULL
1527#endif /* CONFIG_PM_SLEEP */
1528
1529static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1530{
1531	u32 mvr, scheme;
1532	u16 revision, major, minor;
1533
1534	mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1535
1536	/* Check revision register scheme */
1537	scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1538
1539	switch (scheme) {
1540	case 0: /* Legacy Scheme: OMAP2/3 */
1541		/* MINOR_REV[0:4], MAJOR_REV[4:7] */
1542		major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1543					OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1544		minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1545		break;
1546	case 1:
1547		/* New Scheme: OMAP4+ */
1548		/* MINOR_REV[0:5], MAJOR_REV[8:10] */
1549		major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1550					OMAP_UART_MVR_MAJ_SHIFT;
1551		minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1552		break;
1553	default:
1554		dev_warn(up->dev,
1555			"Unknown %s revision, defaulting to highest\n",
1556			up->name);
1557		/* highest possible revision */
1558		major = 0xff;
1559		minor = 0xff;
1560	}
1561
1562	/* normalize revision for the driver */
1563	revision = UART_BUILD_REVISION(major, minor);
1564
1565	switch (revision) {
1566	case OMAP_UART_REV_46:
1567		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1568				UART_ERRATA_i291_DMA_FORCEIDLE);
1569		break;
1570	case OMAP_UART_REV_52:
1571		up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1572				UART_ERRATA_i291_DMA_FORCEIDLE);
1573		up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1574		break;
1575	case OMAP_UART_REV_63:
1576		up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1577		up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1578		break;
1579	default:
1580		break;
1581	}
1582}
1583
1584static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1585{
1586	struct omap_uart_port_info *omap_up_info;
1587
1588	omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1589	if (!omap_up_info)
1590		return NULL; /* out of memory */
1591
1592	of_property_read_u32(dev->of_node, "clock-frequency",
1593					 &omap_up_info->uartclk);
1594
1595	omap_up_info->flags = UPF_BOOT_AUTOCONF;
1596
1597	return omap_up_info;
1598}
1599
1600static int serial_omap_probe_rs485(struct uart_omap_port *up,
1601				   struct device *dev)
1602{
1603	struct serial_rs485 *rs485conf = &up->port.rs485;
1604	struct device_node *np = dev->of_node;
1605	enum gpiod_flags gflags;
1606	int ret;
1607
1608	rs485conf->flags = 0;
1609	up->rts_gpiod = NULL;
1610
1611	if (!np)
1612		return 0;
1613
1614	ret = uart_get_rs485_mode(&up->port);
1615	if (ret)
1616		return ret;
1617
1618	if (of_property_read_bool(np, "rs485-rts-active-high")) {
1619		rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1620		rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1621	} else {
1622		rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1623		rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1624	}
1625
1626	/* check for tx enable gpio */
1627	gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1628		GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1629	up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1630	if (IS_ERR(up->rts_gpiod)) {
1631		ret = PTR_ERR(up->rts_gpiod);
1632	        if (ret == -EPROBE_DEFER)
1633			return ret;
1634		/*
1635		 * FIXME: the code historically ignored any other error than
1636		 * -EPROBE_DEFER and just went on without GPIO.
1637		 */
1638		up->rts_gpiod = NULL;
 
1639	} else {
1640		gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1641	}
1642
 
 
 
 
 
 
 
 
 
 
 
 
1643	return 0;
1644}
1645
1646static int serial_omap_probe(struct platform_device *pdev)
1647{
1648	struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1649	struct uart_omap_port *up;
1650	struct resource *mem;
1651	void __iomem *base;
1652	int uartirq = 0;
1653	int wakeirq = 0;
1654	int ret;
1655
1656	/* The optional wakeirq may be specified in the board dts file */
1657	if (pdev->dev.of_node) {
1658		uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1659		if (!uartirq)
1660			return -EPROBE_DEFER;
1661		wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1662		omap_up_info = of_get_uart_port_info(&pdev->dev);
1663		pdev->dev.platform_data = omap_up_info;
1664	} else {
1665		uartirq = platform_get_irq(pdev, 0);
1666		if (uartirq < 0)
1667			return -EPROBE_DEFER;
1668	}
1669
1670	up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1671	if (!up)
1672		return -ENOMEM;
1673
1674	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1675	base = devm_ioremap_resource(&pdev->dev, mem);
1676	if (IS_ERR(base))
1677		return PTR_ERR(base);
1678
1679	up->dev = &pdev->dev;
1680	up->port.dev = &pdev->dev;
1681	up->port.type = PORT_OMAP;
1682	up->port.iotype = UPIO_MEM;
1683	up->port.irq = uartirq;
1684	up->port.regshift = 2;
1685	up->port.fifosize = 64;
1686	up->port.ops = &serial_omap_pops;
1687	up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1688
1689	if (pdev->dev.of_node)
1690		ret = of_alias_get_id(pdev->dev.of_node, "serial");
1691	else
1692		ret = pdev->id;
1693
1694	if (ret < 0) {
1695		dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1696			ret);
1697		goto err_port_line;
1698	}
1699	up->port.line = ret;
1700
1701	if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1702		dev_err(&pdev->dev, "uart ID %d >  MAX %d.\n", up->port.line,
1703			OMAP_MAX_HSUART_PORTS);
1704		ret = -ENXIO;
1705		goto err_port_line;
1706	}
1707
1708	up->wakeirq = wakeirq;
1709	if (!up->wakeirq)
1710		dev_info(up->port.dev, "no wakeirq for uart%d\n",
1711			 up->port.line);
1712
1713	ret = serial_omap_probe_rs485(up, &pdev->dev);
1714	if (ret < 0)
1715		goto err_rs485;
1716
1717	sprintf(up->name, "OMAP UART%d", up->port.line);
1718	up->port.mapbase = mem->start;
1719	up->port.membase = base;
1720	up->port.flags = omap_up_info->flags;
1721	up->port.uartclk = omap_up_info->uartclk;
1722	up->port.rs485_config = serial_omap_config_rs485;
1723	if (!up->port.uartclk) {
1724		up->port.uartclk = DEFAULT_CLK_SPEED;
1725		dev_warn(&pdev->dev,
1726			 "No clock speed specified: using default: %d\n",
1727			 DEFAULT_CLK_SPEED);
1728	}
1729
1730	up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1731	up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1732	cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
 
1733	INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1734
1735	platform_set_drvdata(pdev, up);
1736	if (omap_up_info->autosuspend_timeout == 0)
1737		omap_up_info->autosuspend_timeout = -1;
1738
1739	device_init_wakeup(up->dev, true);
1740	pm_runtime_use_autosuspend(&pdev->dev);
1741	pm_runtime_set_autosuspend_delay(&pdev->dev,
1742			omap_up_info->autosuspend_timeout);
1743
1744	pm_runtime_irq_safe(&pdev->dev);
1745	pm_runtime_enable(&pdev->dev);
1746
1747	pm_runtime_get_sync(&pdev->dev);
1748
1749	omap_serial_fill_features_erratas(up);
1750
1751	ui[up->port.line] = up;
1752	serial_omap_add_console_port(up);
1753
1754	ret = uart_add_one_port(&serial_omap_reg, &up->port);
1755	if (ret != 0)
1756		goto err_add_port;
1757
1758	pm_runtime_mark_last_busy(up->dev);
1759	pm_runtime_put_autosuspend(up->dev);
1760	return 0;
1761
1762err_add_port:
1763	pm_runtime_dont_use_autosuspend(&pdev->dev);
1764	pm_runtime_put_sync(&pdev->dev);
1765	pm_runtime_disable(&pdev->dev);
1766	cpu_latency_qos_remove_request(&up->pm_qos_request);
1767	device_init_wakeup(up->dev, false);
1768err_rs485:
1769err_port_line:
1770	return ret;
1771}
1772
1773static int serial_omap_remove(struct platform_device *dev)
1774{
1775	struct uart_omap_port *up = platform_get_drvdata(dev);
1776
1777	pm_runtime_get_sync(up->dev);
1778
1779	uart_remove_one_port(&serial_omap_reg, &up->port);
1780
1781	pm_runtime_dont_use_autosuspend(up->dev);
1782	pm_runtime_put_sync(up->dev);
1783	pm_runtime_disable(up->dev);
1784	cpu_latency_qos_remove_request(&up->pm_qos_request);
 
1785	device_init_wakeup(&dev->dev, false);
1786
1787	return 0;
1788}
1789
1790/*
1791 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1792 * The access to uart register after MDR1 Access
1793 * causes UART to corrupt data.
1794 *
1795 * Need a delay =
1796 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1797 * give 10 times as much
1798 */
1799static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1800{
1801	u8 timeout = 255;
1802
1803	serial_out(up, UART_OMAP_MDR1, mdr1);
1804	udelay(2);
1805	serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1806			UART_FCR_CLEAR_RCVR);
1807	/*
1808	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1809	 * TX_FIFO_E bit is 1.
1810	 */
1811	while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1812				(UART_LSR_THRE | UART_LSR_DR))) {
1813		timeout--;
1814		if (!timeout) {
1815			/* Should *never* happen. we warn and carry on */
1816			dev_crit(up->dev, "Errata i202: timedout %x\n",
1817						serial_in(up, UART_LSR));
1818			break;
1819		}
1820		udelay(1);
1821	}
1822}
1823
1824#ifdef CONFIG_PM
1825static void serial_omap_restore_context(struct uart_omap_port *up)
1826{
1827	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1828		serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1829	else
1830		serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1831
1832	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1833	serial_out(up, UART_EFR, UART_EFR_ECB);
1834	serial_out(up, UART_LCR, 0x0); /* Operational mode */
1835	serial_out(up, UART_IER, 0x0);
1836	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1837	serial_out(up, UART_DLL, up->dll);
1838	serial_out(up, UART_DLM, up->dlh);
1839	serial_out(up, UART_LCR, 0x0); /* Operational mode */
1840	serial_out(up, UART_IER, up->ier);
1841	serial_out(up, UART_FCR, up->fcr);
1842	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1843	serial_out(up, UART_MCR, up->mcr);
1844	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1845	serial_out(up, UART_OMAP_SCR, up->scr);
1846	serial_out(up, UART_EFR, up->efr);
1847	serial_out(up, UART_LCR, up->lcr);
1848	if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1849		serial_omap_mdr1_errataset(up, up->mdr1);
1850	else
1851		serial_out(up, UART_OMAP_MDR1, up->mdr1);
1852	serial_out(up, UART_OMAP_WER, up->wer);
1853}
1854
1855static int serial_omap_runtime_suspend(struct device *dev)
1856{
1857	struct uart_omap_port *up = dev_get_drvdata(dev);
1858
1859	if (!up)
1860		return -EINVAL;
1861
1862	/*
1863	* When using 'no_console_suspend', the console UART must not be
1864	* suspended. Since driver suspend is managed by runtime suspend,
1865	* preventing runtime suspend (by returning error) will keep device
1866	* active during suspend.
1867	*/
1868	if (up->is_suspending && !console_suspend_enabled &&
1869	    uart_console(&up->port))
1870		return -EBUSY;
1871
1872	up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1873
1874	serial_omap_enable_wakeup(up, true);
1875
1876	up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1877	schedule_work(&up->qos_work);
1878
1879	return 0;
1880}
1881
1882static int serial_omap_runtime_resume(struct device *dev)
1883{
1884	struct uart_omap_port *up = dev_get_drvdata(dev);
1885
1886	int loss_cnt = serial_omap_get_context_loss_count(up);
1887
1888	serial_omap_enable_wakeup(up, false);
1889
1890	if (loss_cnt < 0) {
1891		dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1892			loss_cnt);
1893		serial_omap_restore_context(up);
1894	} else if (up->context_loss_cnt != loss_cnt) {
1895		serial_omap_restore_context(up);
1896	}
1897	up->latency = up->calc_latency;
1898	schedule_work(&up->qos_work);
1899
1900	return 0;
1901}
1902#endif
1903
1904static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1905	SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1906	SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1907				serial_omap_runtime_resume, NULL)
1908	.prepare        = serial_omap_prepare,
1909	.complete       = serial_omap_complete,
1910};
1911
1912#if defined(CONFIG_OF)
1913static const struct of_device_id omap_serial_of_match[] = {
1914	{ .compatible = "ti,omap2-uart" },
1915	{ .compatible = "ti,omap3-uart" },
1916	{ .compatible = "ti,omap4-uart" },
1917	{},
1918};
1919MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1920#endif
1921
1922static struct platform_driver serial_omap_driver = {
1923	.probe          = serial_omap_probe,
1924	.remove         = serial_omap_remove,
1925	.driver		= {
1926		.name	= OMAP_SERIAL_DRIVER_NAME,
1927		.pm	= &serial_omap_dev_pm_ops,
1928		.of_match_table = of_match_ptr(omap_serial_of_match),
1929	},
1930};
1931
1932static int __init serial_omap_init(void)
1933{
1934	int ret;
1935
1936	ret = uart_register_driver(&serial_omap_reg);
1937	if (ret != 0)
1938		return ret;
1939	ret = platform_driver_register(&serial_omap_driver);
1940	if (ret != 0)
1941		uart_unregister_driver(&serial_omap_reg);
1942	return ret;
1943}
1944
1945static void __exit serial_omap_exit(void)
1946{
1947	platform_driver_unregister(&serial_omap_driver);
1948	uart_unregister_driver(&serial_omap_reg);
1949}
1950
1951module_init(serial_omap_init);
1952module_exit(serial_omap_exit);
1953
1954MODULE_DESCRIPTION("OMAP High Speed UART driver");
1955MODULE_LICENSE("GPL");
1956MODULE_AUTHOR("Texas Instruments Inc");