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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for OMAP-UART controller.
4 * Based on drivers/serial/8250.c
5 *
6 * Copyright (C) 2010 Texas Instruments.
7 *
8 * Authors:
9 * Govindraj R <govindraj.raja@ti.com>
10 * Thara Gopinath <thara@ti.com>
11 *
12 * Note: This driver is made separate from 8250 driver as we cannot
13 * over load 8250 driver with omap platform specific configuration for
14 * features like DMA, it makes easier to implement features like DMA and
15 * hardware flow control and software flow control configuration with
16 * this driver as required for the omap-platform.
17 */
18
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/console.h>
22#include <linux/serial_reg.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/serial_core.h>
31#include <linux/irq.h>
32#include <linux/pm_runtime.h>
33#include <linux/pm_wakeirq.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/gpio/consumer.h>
37#include <linux/platform_data/serial-omap.h>
38
39#define OMAP_MAX_HSUART_PORTS 10
40
41#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
42
43#define OMAP_UART_REV_42 0x0402
44#define OMAP_UART_REV_46 0x0406
45#define OMAP_UART_REV_52 0x0502
46#define OMAP_UART_REV_63 0x0603
47
48#define OMAP_UART_TX_WAKEUP_EN BIT(7)
49
50/* Feature flags */
51#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
52
53#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
54#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
55
56#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
57
58/* SCR register bitmasks */
59#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
60#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
61#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
62
63/* FCR register bitmasks */
64#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
65#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
66
67/* MVR register bitmasks */
68#define OMAP_UART_MVR_SCHEME_SHIFT 30
69
70#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
71#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
72#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
73
74#define OMAP_UART_MVR_MAJ_MASK 0x700
75#define OMAP_UART_MVR_MAJ_SHIFT 8
76#define OMAP_UART_MVR_MIN_MASK 0x3f
77
78#define OMAP_UART_DMA_CH_FREE -1
79
80#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
81#define OMAP_MODE13X_SPEED 230400
82
83/* WER = 0x7F
84 * Enable module level wakeup in WER reg
85 */
86#define OMAP_UART_WER_MOD_WKUP 0x7F
87
88/* Enable XON/XOFF flow control on output */
89#define OMAP_UART_SW_TX 0x08
90
91/* Enable XON/XOFF flow control on input */
92#define OMAP_UART_SW_RX 0x02
93
94#define OMAP_UART_SW_CLR 0xF0
95
96#define OMAP_UART_TCR_TRIG 0x0F
97
98struct uart_omap_dma {
99 u8 uart_dma_tx;
100 u8 uart_dma_rx;
101 int rx_dma_channel;
102 int tx_dma_channel;
103 dma_addr_t rx_buf_dma_phys;
104 dma_addr_t tx_buf_dma_phys;
105 unsigned int uart_base;
106 /*
107 * Buffer for rx dma. It is not required for tx because the buffer
108 * comes from port structure.
109 */
110 unsigned char *rx_buf;
111 unsigned int prev_rx_dma_pos;
112 int tx_buf_size;
113 int tx_dma_used;
114 int rx_dma_used;
115 spinlock_t tx_lock;
116 spinlock_t rx_lock;
117 /* timer to poll activity on rx dma */
118 struct timer_list rx_timer;
119 unsigned int rx_buf_size;
120 unsigned int rx_poll_rate;
121 unsigned int rx_timeout;
122};
123
124struct uart_omap_port {
125 struct uart_port port;
126 struct uart_omap_dma uart_dma;
127 struct device *dev;
128 int wakeirq;
129
130 unsigned char ier;
131 unsigned char lcr;
132 unsigned char mcr;
133 unsigned char fcr;
134 unsigned char efr;
135 unsigned char dll;
136 unsigned char dlh;
137 unsigned char mdr1;
138 unsigned char scr;
139 unsigned char wer;
140
141 int use_dma;
142 /*
143 * Some bits in registers are cleared on a read, so they must
144 * be saved whenever the register is read, but the bits will not
145 * be immediately processed.
146 */
147 unsigned int lsr_break_flag;
148 unsigned char msr_saved_flags;
149 char name[20];
150 unsigned long port_activity;
151 int context_loss_cnt;
152 u32 errata;
153 u32 features;
154
155 struct gpio_desc *rts_gpiod;
156
157 struct pm_qos_request pm_qos_request;
158 u32 latency;
159 u32 calc_latency;
160 struct work_struct qos_work;
161 bool is_suspending;
162
163 unsigned int rs485_tx_filter_count;
164};
165
166#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
167
168static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
169
170/* Forward declaration of functions */
171static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
172
173static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
174{
175 offset <<= up->port.regshift;
176 return readw(up->port.membase + offset);
177}
178
179static inline void serial_out(struct uart_omap_port *up, int offset, int value)
180{
181 offset <<= up->port.regshift;
182 writew(value, up->port.membase + offset);
183}
184
185static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
186{
187 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
189 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
190 serial_out(up, UART_FCR, 0);
191}
192
193#ifdef CONFIG_PM
194static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
195{
196 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
197
198 if (!pdata || !pdata->get_context_loss_count)
199 return -EINVAL;
200
201 return pdata->get_context_loss_count(up->dev);
202}
203
204/* REVISIT: Remove this when omap3 boots in device tree only mode */
205static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
206{
207 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
208
209 if (!pdata || !pdata->enable_wakeup)
210 return;
211
212 pdata->enable_wakeup(up->dev, enable);
213}
214#endif /* CONFIG_PM */
215
216/*
217 * Calculate the absolute difference between the desired and actual baud
218 * rate for the given mode.
219 */
220static inline int calculate_baud_abs_diff(struct uart_port *port,
221 unsigned int baud, unsigned int mode)
222{
223 unsigned int n = port->uartclk / (mode * baud);
224 int abs_diff;
225
226 if (n == 0)
227 n = 1;
228
229 abs_diff = baud - (port->uartclk / (mode * n));
230 if (abs_diff < 0)
231 abs_diff = -abs_diff;
232
233 return abs_diff;
234}
235
236/*
237 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
238 * @port: uart port info
239 * @baud: baudrate for which mode needs to be determined
240 *
241 * Returns true if baud rate is MODE16X and false if MODE13X
242 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
243 * and Error Rates" determines modes not for all common baud rates.
244 * E.g. for 1000000 baud rate mode must be 16x, but according to that
245 * table it's determined as 13x.
246 */
247static bool
248serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
249{
250 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
251 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
252
253 return (abs_diff_13 >= abs_diff_16);
254}
255
256/*
257 * serial_omap_get_divisor - calculate divisor value
258 * @port: uart port info
259 * @baud: baudrate for which divisor needs to be calculated.
260 */
261static unsigned int
262serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
263{
264 unsigned int mode;
265
266 if (!serial_omap_baud_is_mode16(port, baud))
267 mode = 13;
268 else
269 mode = 16;
270 return port->uartclk/(mode * baud);
271}
272
273static void serial_omap_enable_ms(struct uart_port *port)
274{
275 struct uart_omap_port *up = to_uart_omap_port(port);
276
277 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
278
279 pm_runtime_get_sync(up->dev);
280 up->ier |= UART_IER_MSI;
281 serial_out(up, UART_IER, up->ier);
282 pm_runtime_mark_last_busy(up->dev);
283 pm_runtime_put_autosuspend(up->dev);
284}
285
286static void serial_omap_stop_tx(struct uart_port *port)
287{
288 struct uart_omap_port *up = to_uart_omap_port(port);
289 int res;
290
291 pm_runtime_get_sync(up->dev);
292
293 /* Handle RS-485 */
294 if (port->rs485.flags & SER_RS485_ENABLED) {
295 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
296 /* THR interrupt is fired when both TX FIFO and TX
297 * shift register are empty. This means there's nothing
298 * left to transmit now, so make sure the THR interrupt
299 * is fired when TX FIFO is below the trigger level,
300 * disable THR interrupts and toggle the RS-485 GPIO
301 * data direction pin if needed.
302 */
303 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
304 serial_out(up, UART_OMAP_SCR, up->scr);
305 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
306 1 : 0;
307 if (up->rts_gpiod &&
308 gpiod_get_value(up->rts_gpiod) != res) {
309 if (port->rs485.delay_rts_after_send > 0)
310 mdelay(
311 port->rs485.delay_rts_after_send);
312 gpiod_set_value(up->rts_gpiod, res);
313 }
314 } else {
315 /* We're asked to stop, but there's still stuff in the
316 * UART FIFO, so make sure the THR interrupt is fired
317 * when both TX FIFO and TX shift register are empty.
318 * The next THR interrupt (if no transmission is started
319 * in the meantime) will indicate the end of a
320 * transmission. Therefore we _don't_ disable THR
321 * interrupts in this situation.
322 */
323 up->scr |= OMAP_UART_SCR_TX_EMPTY;
324 serial_out(up, UART_OMAP_SCR, up->scr);
325 return;
326 }
327 }
328
329 if (up->ier & UART_IER_THRI) {
330 up->ier &= ~UART_IER_THRI;
331 serial_out(up, UART_IER, up->ier);
332 }
333
334 pm_runtime_mark_last_busy(up->dev);
335 pm_runtime_put_autosuspend(up->dev);
336}
337
338static void serial_omap_stop_rx(struct uart_port *port)
339{
340 struct uart_omap_port *up = to_uart_omap_port(port);
341
342 pm_runtime_get_sync(up->dev);
343 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
344 up->port.read_status_mask &= ~UART_LSR_DR;
345 serial_out(up, UART_IER, up->ier);
346 pm_runtime_mark_last_busy(up->dev);
347 pm_runtime_put_autosuspend(up->dev);
348}
349
350static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
351{
352 struct circ_buf *xmit = &up->port.state->xmit;
353 int count;
354
355 if (up->port.x_char) {
356 serial_out(up, UART_TX, up->port.x_char);
357 up->port.icount.tx++;
358 up->port.x_char = 0;
359 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
360 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
361 up->rs485_tx_filter_count++;
362
363 return;
364 }
365 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
366 serial_omap_stop_tx(&up->port);
367 return;
368 }
369 count = up->port.fifosize / 4;
370 do {
371 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
372 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
373 up->port.icount.tx++;
374 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
375 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
376 up->rs485_tx_filter_count++;
377
378 if (uart_circ_empty(xmit))
379 break;
380 } while (--count > 0);
381
382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
383 uart_write_wakeup(&up->port);
384
385 if (uart_circ_empty(xmit))
386 serial_omap_stop_tx(&up->port);
387}
388
389static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
390{
391 if (!(up->ier & UART_IER_THRI)) {
392 up->ier |= UART_IER_THRI;
393 serial_out(up, UART_IER, up->ier);
394 }
395}
396
397static void serial_omap_start_tx(struct uart_port *port)
398{
399 struct uart_omap_port *up = to_uart_omap_port(port);
400 int res;
401
402 pm_runtime_get_sync(up->dev);
403
404 /* Handle RS-485 */
405 if (port->rs485.flags & SER_RS485_ENABLED) {
406 /* Fire THR interrupts when FIFO is below trigger level */
407 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
408 serial_out(up, UART_OMAP_SCR, up->scr);
409
410 /* if rts not already enabled */
411 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
412 if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) {
413 gpiod_set_value(up->rts_gpiod, res);
414 if (port->rs485.delay_rts_before_send > 0)
415 mdelay(port->rs485.delay_rts_before_send);
416 }
417 }
418
419 if ((port->rs485.flags & SER_RS485_ENABLED) &&
420 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
421 up->rs485_tx_filter_count = 0;
422
423 serial_omap_enable_ier_thri(up);
424 pm_runtime_mark_last_busy(up->dev);
425 pm_runtime_put_autosuspend(up->dev);
426}
427
428static void serial_omap_throttle(struct uart_port *port)
429{
430 struct uart_omap_port *up = to_uart_omap_port(port);
431 unsigned long flags;
432
433 pm_runtime_get_sync(up->dev);
434 spin_lock_irqsave(&up->port.lock, flags);
435 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
436 serial_out(up, UART_IER, up->ier);
437 spin_unlock_irqrestore(&up->port.lock, flags);
438 pm_runtime_mark_last_busy(up->dev);
439 pm_runtime_put_autosuspend(up->dev);
440}
441
442static void serial_omap_unthrottle(struct uart_port *port)
443{
444 struct uart_omap_port *up = to_uart_omap_port(port);
445 unsigned long flags;
446
447 pm_runtime_get_sync(up->dev);
448 spin_lock_irqsave(&up->port.lock, flags);
449 up->ier |= UART_IER_RLSI | UART_IER_RDI;
450 serial_out(up, UART_IER, up->ier);
451 spin_unlock_irqrestore(&up->port.lock, flags);
452 pm_runtime_mark_last_busy(up->dev);
453 pm_runtime_put_autosuspend(up->dev);
454}
455
456static unsigned int check_modem_status(struct uart_omap_port *up)
457{
458 unsigned int status;
459
460 status = serial_in(up, UART_MSR);
461 status |= up->msr_saved_flags;
462 up->msr_saved_flags = 0;
463 if ((status & UART_MSR_ANY_DELTA) == 0)
464 return status;
465
466 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
467 up->port.state != NULL) {
468 if (status & UART_MSR_TERI)
469 up->port.icount.rng++;
470 if (status & UART_MSR_DDSR)
471 up->port.icount.dsr++;
472 if (status & UART_MSR_DDCD)
473 uart_handle_dcd_change
474 (&up->port, status & UART_MSR_DCD);
475 if (status & UART_MSR_DCTS)
476 uart_handle_cts_change
477 (&up->port, status & UART_MSR_CTS);
478 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
479 }
480
481 return status;
482}
483
484static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
485{
486 unsigned int flag;
487
488 /*
489 * Read one data character out to avoid stalling the receiver according
490 * to the table 23-246 of the omap4 TRM.
491 */
492 if (likely(lsr & UART_LSR_DR)) {
493 serial_in(up, UART_RX);
494 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
495 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
496 up->rs485_tx_filter_count)
497 up->rs485_tx_filter_count--;
498 }
499
500 up->port.icount.rx++;
501 flag = TTY_NORMAL;
502
503 if (lsr & UART_LSR_BI) {
504 flag = TTY_BREAK;
505 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
506 up->port.icount.brk++;
507 /*
508 * We do the SysRQ and SAK checking
509 * here because otherwise the break
510 * may get masked by ignore_status_mask
511 * or read_status_mask.
512 */
513 if (uart_handle_break(&up->port))
514 return;
515
516 }
517
518 if (lsr & UART_LSR_PE) {
519 flag = TTY_PARITY;
520 up->port.icount.parity++;
521 }
522
523 if (lsr & UART_LSR_FE) {
524 flag = TTY_FRAME;
525 up->port.icount.frame++;
526 }
527
528 if (lsr & UART_LSR_OE)
529 up->port.icount.overrun++;
530
531#ifdef CONFIG_SERIAL_OMAP_CONSOLE
532 if (up->port.line == up->port.cons->index) {
533 /* Recover the break flag from console xmit */
534 lsr |= up->lsr_break_flag;
535 }
536#endif
537 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
538}
539
540static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
541{
542 unsigned char ch = 0;
543 unsigned int flag;
544
545 if (!(lsr & UART_LSR_DR))
546 return;
547
548 ch = serial_in(up, UART_RX);
549 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
550 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
551 up->rs485_tx_filter_count) {
552 up->rs485_tx_filter_count--;
553 return;
554 }
555
556 flag = TTY_NORMAL;
557 up->port.icount.rx++;
558
559 if (uart_handle_sysrq_char(&up->port, ch))
560 return;
561
562 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
563}
564
565/**
566 * serial_omap_irq() - This handles the interrupt from one port
567 * @irq: uart port irq number
568 * @dev_id: uart port info
569 */
570static irqreturn_t serial_omap_irq(int irq, void *dev_id)
571{
572 struct uart_omap_port *up = dev_id;
573 unsigned int iir, lsr;
574 unsigned int type;
575 irqreturn_t ret = IRQ_NONE;
576 int max_count = 256;
577
578 spin_lock(&up->port.lock);
579 pm_runtime_get_sync(up->dev);
580
581 do {
582 iir = serial_in(up, UART_IIR);
583 if (iir & UART_IIR_NO_INT)
584 break;
585
586 ret = IRQ_HANDLED;
587 lsr = serial_in(up, UART_LSR);
588
589 /* extract IRQ type from IIR register */
590 type = iir & 0x3e;
591
592 switch (type) {
593 case UART_IIR_MSI:
594 check_modem_status(up);
595 break;
596 case UART_IIR_THRI:
597 transmit_chars(up, lsr);
598 break;
599 case UART_IIR_RX_TIMEOUT:
600 case UART_IIR_RDI:
601 serial_omap_rdi(up, lsr);
602 break;
603 case UART_IIR_RLSI:
604 serial_omap_rlsi(up, lsr);
605 break;
606 case UART_IIR_CTS_RTS_DSR:
607 /* simply try again */
608 break;
609 case UART_IIR_XOFF:
610 default:
611 break;
612 }
613 } while (max_count--);
614
615 spin_unlock(&up->port.lock);
616
617 tty_flip_buffer_push(&up->port.state->port);
618
619 pm_runtime_mark_last_busy(up->dev);
620 pm_runtime_put_autosuspend(up->dev);
621 up->port_activity = jiffies;
622
623 return ret;
624}
625
626static unsigned int serial_omap_tx_empty(struct uart_port *port)
627{
628 struct uart_omap_port *up = to_uart_omap_port(port);
629 unsigned long flags;
630 unsigned int ret = 0;
631
632 pm_runtime_get_sync(up->dev);
633 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
634 spin_lock_irqsave(&up->port.lock, flags);
635 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
636 spin_unlock_irqrestore(&up->port.lock, flags);
637 pm_runtime_mark_last_busy(up->dev);
638 pm_runtime_put_autosuspend(up->dev);
639 return ret;
640}
641
642static unsigned int serial_omap_get_mctrl(struct uart_port *port)
643{
644 struct uart_omap_port *up = to_uart_omap_port(port);
645 unsigned int status;
646 unsigned int ret = 0;
647
648 pm_runtime_get_sync(up->dev);
649 status = check_modem_status(up);
650 pm_runtime_mark_last_busy(up->dev);
651 pm_runtime_put_autosuspend(up->dev);
652
653 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
654
655 if (status & UART_MSR_DCD)
656 ret |= TIOCM_CAR;
657 if (status & UART_MSR_RI)
658 ret |= TIOCM_RNG;
659 if (status & UART_MSR_DSR)
660 ret |= TIOCM_DSR;
661 if (status & UART_MSR_CTS)
662 ret |= TIOCM_CTS;
663 return ret;
664}
665
666static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
667{
668 struct uart_omap_port *up = to_uart_omap_port(port);
669 unsigned char mcr = 0, old_mcr, lcr;
670
671 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
672 if (mctrl & TIOCM_RTS)
673 mcr |= UART_MCR_RTS;
674 if (mctrl & TIOCM_DTR)
675 mcr |= UART_MCR_DTR;
676 if (mctrl & TIOCM_OUT1)
677 mcr |= UART_MCR_OUT1;
678 if (mctrl & TIOCM_OUT2)
679 mcr |= UART_MCR_OUT2;
680 if (mctrl & TIOCM_LOOP)
681 mcr |= UART_MCR_LOOP;
682
683 pm_runtime_get_sync(up->dev);
684 old_mcr = serial_in(up, UART_MCR);
685 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
686 UART_MCR_DTR | UART_MCR_RTS);
687 up->mcr = old_mcr | mcr;
688 serial_out(up, UART_MCR, up->mcr);
689
690 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
691 lcr = serial_in(up, UART_LCR);
692 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
693 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
694 up->efr |= UART_EFR_RTS;
695 else
696 up->efr &= ~UART_EFR_RTS;
697 serial_out(up, UART_EFR, up->efr);
698 serial_out(up, UART_LCR, lcr);
699
700 pm_runtime_mark_last_busy(up->dev);
701 pm_runtime_put_autosuspend(up->dev);
702}
703
704static void serial_omap_break_ctl(struct uart_port *port, int break_state)
705{
706 struct uart_omap_port *up = to_uart_omap_port(port);
707 unsigned long flags;
708
709 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
710 pm_runtime_get_sync(up->dev);
711 spin_lock_irqsave(&up->port.lock, flags);
712 if (break_state == -1)
713 up->lcr |= UART_LCR_SBC;
714 else
715 up->lcr &= ~UART_LCR_SBC;
716 serial_out(up, UART_LCR, up->lcr);
717 spin_unlock_irqrestore(&up->port.lock, flags);
718 pm_runtime_mark_last_busy(up->dev);
719 pm_runtime_put_autosuspend(up->dev);
720}
721
722static int serial_omap_startup(struct uart_port *port)
723{
724 struct uart_omap_port *up = to_uart_omap_port(port);
725 unsigned long flags;
726 int retval;
727
728 /*
729 * Allocate the IRQ
730 */
731 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
732 up->name, up);
733 if (retval)
734 return retval;
735
736 /* Optional wake-up IRQ */
737 if (up->wakeirq) {
738 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
739 if (retval) {
740 free_irq(up->port.irq, up);
741 return retval;
742 }
743 }
744
745 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
746
747 pm_runtime_get_sync(up->dev);
748 /*
749 * Clear the FIFO buffers and disable them.
750 * (they will be reenabled in set_termios())
751 */
752 serial_omap_clear_fifos(up);
753
754 /*
755 * Clear the interrupt registers.
756 */
757 (void) serial_in(up, UART_LSR);
758 if (serial_in(up, UART_LSR) & UART_LSR_DR)
759 (void) serial_in(up, UART_RX);
760 (void) serial_in(up, UART_IIR);
761 (void) serial_in(up, UART_MSR);
762
763 /*
764 * Now, initialize the UART
765 */
766 serial_out(up, UART_LCR, UART_LCR_WLEN8);
767 spin_lock_irqsave(&up->port.lock, flags);
768 /*
769 * Most PC uarts need OUT2 raised to enable interrupts.
770 */
771 up->port.mctrl |= TIOCM_OUT2;
772 serial_omap_set_mctrl(&up->port, up->port.mctrl);
773 spin_unlock_irqrestore(&up->port.lock, flags);
774
775 up->msr_saved_flags = 0;
776 /*
777 * Finally, enable interrupts. Note: Modem status interrupts
778 * are set via set_termios(), which will be occurring imminently
779 * anyway, so we don't enable them here.
780 */
781 up->ier = UART_IER_RLSI | UART_IER_RDI;
782 serial_out(up, UART_IER, up->ier);
783
784 /* Enable module level wake up */
785 up->wer = OMAP_UART_WER_MOD_WKUP;
786 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
787 up->wer |= OMAP_UART_TX_WAKEUP_EN;
788
789 serial_out(up, UART_OMAP_WER, up->wer);
790
791 pm_runtime_mark_last_busy(up->dev);
792 pm_runtime_put_autosuspend(up->dev);
793 up->port_activity = jiffies;
794 return 0;
795}
796
797static void serial_omap_shutdown(struct uart_port *port)
798{
799 struct uart_omap_port *up = to_uart_omap_port(port);
800 unsigned long flags;
801
802 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
803
804 pm_runtime_get_sync(up->dev);
805 /*
806 * Disable interrupts from this port
807 */
808 up->ier = 0;
809 serial_out(up, UART_IER, 0);
810
811 spin_lock_irqsave(&up->port.lock, flags);
812 up->port.mctrl &= ~TIOCM_OUT2;
813 serial_omap_set_mctrl(&up->port, up->port.mctrl);
814 spin_unlock_irqrestore(&up->port.lock, flags);
815
816 /*
817 * Disable break condition and FIFOs
818 */
819 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
820 serial_omap_clear_fifos(up);
821
822 /*
823 * Read data port to reset things, and then free the irq
824 */
825 if (serial_in(up, UART_LSR) & UART_LSR_DR)
826 (void) serial_in(up, UART_RX);
827
828 pm_runtime_mark_last_busy(up->dev);
829 pm_runtime_put_autosuspend(up->dev);
830 free_irq(up->port.irq, up);
831 dev_pm_clear_wake_irq(up->dev);
832}
833
834static void serial_omap_uart_qos_work(struct work_struct *work)
835{
836 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
837 qos_work);
838
839 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
840}
841
842static void
843serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
844 struct ktermios *old)
845{
846 struct uart_omap_port *up = to_uart_omap_port(port);
847 unsigned char cval = 0;
848 unsigned long flags;
849 unsigned int baud, quot;
850
851 switch (termios->c_cflag & CSIZE) {
852 case CS5:
853 cval = UART_LCR_WLEN5;
854 break;
855 case CS6:
856 cval = UART_LCR_WLEN6;
857 break;
858 case CS7:
859 cval = UART_LCR_WLEN7;
860 break;
861 default:
862 case CS8:
863 cval = UART_LCR_WLEN8;
864 break;
865 }
866
867 if (termios->c_cflag & CSTOPB)
868 cval |= UART_LCR_STOP;
869 if (termios->c_cflag & PARENB)
870 cval |= UART_LCR_PARITY;
871 if (!(termios->c_cflag & PARODD))
872 cval |= UART_LCR_EPAR;
873 if (termios->c_cflag & CMSPAR)
874 cval |= UART_LCR_SPAR;
875
876 /*
877 * Ask the core to calculate the divisor for us.
878 */
879
880 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
881 quot = serial_omap_get_divisor(port, baud);
882
883 /* calculate wakeup latency constraint */
884 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
885 up->latency = up->calc_latency;
886 schedule_work(&up->qos_work);
887
888 up->dll = quot & 0xff;
889 up->dlh = quot >> 8;
890 up->mdr1 = UART_OMAP_MDR1_DISABLE;
891
892 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
893 UART_FCR_ENABLE_FIFO;
894
895 /*
896 * Ok, we're now changing the port state. Do it with
897 * interrupts disabled.
898 */
899 pm_runtime_get_sync(up->dev);
900 spin_lock_irqsave(&up->port.lock, flags);
901
902 /*
903 * Update the per-port timeout.
904 */
905 uart_update_timeout(port, termios->c_cflag, baud);
906
907 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
908 if (termios->c_iflag & INPCK)
909 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
910 if (termios->c_iflag & (BRKINT | PARMRK))
911 up->port.read_status_mask |= UART_LSR_BI;
912
913 /*
914 * Characters to ignore
915 */
916 up->port.ignore_status_mask = 0;
917 if (termios->c_iflag & IGNPAR)
918 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
919 if (termios->c_iflag & IGNBRK) {
920 up->port.ignore_status_mask |= UART_LSR_BI;
921 /*
922 * If we're ignoring parity and break indicators,
923 * ignore overruns too (for real raw support).
924 */
925 if (termios->c_iflag & IGNPAR)
926 up->port.ignore_status_mask |= UART_LSR_OE;
927 }
928
929 /*
930 * ignore all characters if CREAD is not set
931 */
932 if ((termios->c_cflag & CREAD) == 0)
933 up->port.ignore_status_mask |= UART_LSR_DR;
934
935 /*
936 * Modem status interrupts
937 */
938 up->ier &= ~UART_IER_MSI;
939 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
940 up->ier |= UART_IER_MSI;
941 serial_out(up, UART_IER, up->ier);
942 serial_out(up, UART_LCR, cval); /* reset DLAB */
943 up->lcr = cval;
944 up->scr = 0;
945
946 /* FIFOs and DMA Settings */
947
948 /* FCR can be changed only when the
949 * baud clock is not running
950 * DLL_REG and DLH_REG set to 0.
951 */
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
953 serial_out(up, UART_DLL, 0);
954 serial_out(up, UART_DLM, 0);
955 serial_out(up, UART_LCR, 0);
956
957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
958
959 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
960 up->efr &= ~UART_EFR_SCD;
961 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
962
963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
964 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
965 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
966 /* FIFO ENABLE, DMA MODE */
967
968 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
969 /*
970 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
971 * sets Enables the granularity of 1 for TRIGGER RX
972 * level. Along with setting RX FIFO trigger level
973 * to 1 (as noted below, 16 characters) and TLR[3:0]
974 * to zero this will result RX FIFO threshold level
975 * to 1 character, instead of 16 as noted in comment
976 * below.
977 */
978
979 /* Set receive FIFO threshold to 16 characters and
980 * transmit FIFO threshold to 32 spaces
981 */
982 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
983 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
984 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
985 UART_FCR_ENABLE_FIFO;
986
987 serial_out(up, UART_FCR, up->fcr);
988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
989
990 serial_out(up, UART_OMAP_SCR, up->scr);
991
992 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
994 serial_out(up, UART_MCR, up->mcr);
995 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
996 serial_out(up, UART_EFR, up->efr);
997 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
998
999 /* Protocol, Baud Rate, and Interrupt Settings */
1000
1001 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1002 serial_omap_mdr1_errataset(up, up->mdr1);
1003 else
1004 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1005
1006 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1007 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1008
1009 serial_out(up, UART_LCR, 0);
1010 serial_out(up, UART_IER, 0);
1011 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1012
1013 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1014 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1015
1016 serial_out(up, UART_LCR, 0);
1017 serial_out(up, UART_IER, up->ier);
1018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1019
1020 serial_out(up, UART_EFR, up->efr);
1021 serial_out(up, UART_LCR, cval);
1022
1023 if (!serial_omap_baud_is_mode16(port, baud))
1024 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1025 else
1026 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1027
1028 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1029 serial_omap_mdr1_errataset(up, up->mdr1);
1030 else
1031 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1032
1033 /* Configure flow control */
1034 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1035
1036 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1037 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1038 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1039
1040 /* Enable access to TCR/TLR */
1041 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1042 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1043 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1044
1045 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1046
1047 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1048
1049 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1050 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
1051 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1052 up->efr |= UART_EFR_CTS;
1053 } else {
1054 /* Disable AUTORTS and AUTOCTS */
1055 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1056 }
1057
1058 if (up->port.flags & UPF_SOFT_FLOW) {
1059 /* clear SW control mode bits */
1060 up->efr &= OMAP_UART_SW_CLR;
1061
1062 /*
1063 * IXON Flag:
1064 * Enable XON/XOFF flow control on input.
1065 * Receiver compares XON1, XOFF1.
1066 */
1067 if (termios->c_iflag & IXON)
1068 up->efr |= OMAP_UART_SW_RX;
1069
1070 /*
1071 * IXOFF Flag:
1072 * Enable XON/XOFF flow control on output.
1073 * Transmit XON1, XOFF1
1074 */
1075 if (termios->c_iflag & IXOFF) {
1076 up->port.status |= UPSTAT_AUTOXOFF;
1077 up->efr |= OMAP_UART_SW_TX;
1078 }
1079
1080 /*
1081 * IXANY Flag:
1082 * Enable any character to restart output.
1083 * Operation resumes after receiving any
1084 * character after recognition of the XOFF character
1085 */
1086 if (termios->c_iflag & IXANY)
1087 up->mcr |= UART_MCR_XONANY;
1088 else
1089 up->mcr &= ~UART_MCR_XONANY;
1090 }
1091 serial_out(up, UART_MCR, up->mcr);
1092 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1093 serial_out(up, UART_EFR, up->efr);
1094 serial_out(up, UART_LCR, up->lcr);
1095
1096 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1097
1098 spin_unlock_irqrestore(&up->port.lock, flags);
1099 pm_runtime_mark_last_busy(up->dev);
1100 pm_runtime_put_autosuspend(up->dev);
1101 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1102}
1103
1104static void
1105serial_omap_pm(struct uart_port *port, unsigned int state,
1106 unsigned int oldstate)
1107{
1108 struct uart_omap_port *up = to_uart_omap_port(port);
1109 unsigned char efr;
1110
1111 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1112
1113 pm_runtime_get_sync(up->dev);
1114 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1115 efr = serial_in(up, UART_EFR);
1116 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1117 serial_out(up, UART_LCR, 0);
1118
1119 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1120 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1121 serial_out(up, UART_EFR, efr);
1122 serial_out(up, UART_LCR, 0);
1123
1124 pm_runtime_mark_last_busy(up->dev);
1125 pm_runtime_put_autosuspend(up->dev);
1126}
1127
1128static void serial_omap_release_port(struct uart_port *port)
1129{
1130 dev_dbg(port->dev, "serial_omap_release_port+\n");
1131}
1132
1133static int serial_omap_request_port(struct uart_port *port)
1134{
1135 dev_dbg(port->dev, "serial_omap_request_port+\n");
1136 return 0;
1137}
1138
1139static void serial_omap_config_port(struct uart_port *port, int flags)
1140{
1141 struct uart_omap_port *up = to_uart_omap_port(port);
1142
1143 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1144 up->port.line);
1145 up->port.type = PORT_OMAP;
1146 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1147}
1148
1149static int
1150serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1151{
1152 /* we don't want the core code to modify any port params */
1153 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1154 return -EINVAL;
1155}
1156
1157static const char *
1158serial_omap_type(struct uart_port *port)
1159{
1160 struct uart_omap_port *up = to_uart_omap_port(port);
1161
1162 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1163 return up->name;
1164}
1165
1166#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1167
1168static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1169{
1170 unsigned int status, tmout = 10000;
1171
1172 /* Wait up to 10ms for the character(s) to be sent. */
1173 do {
1174 status = serial_in(up, UART_LSR);
1175
1176 if (status & UART_LSR_BI)
1177 up->lsr_break_flag = UART_LSR_BI;
1178
1179 if (--tmout == 0)
1180 break;
1181 udelay(1);
1182 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1183
1184 /* Wait up to 1s for flow control if necessary */
1185 if (up->port.flags & UPF_CONS_FLOW) {
1186 tmout = 1000000;
1187 for (tmout = 1000000; tmout; tmout--) {
1188 unsigned int msr = serial_in(up, UART_MSR);
1189
1190 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1191 if (msr & UART_MSR_CTS)
1192 break;
1193
1194 udelay(1);
1195 }
1196 }
1197}
1198
1199#ifdef CONFIG_CONSOLE_POLL
1200
1201static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1202{
1203 struct uart_omap_port *up = to_uart_omap_port(port);
1204
1205 pm_runtime_get_sync(up->dev);
1206 wait_for_xmitr(up);
1207 serial_out(up, UART_TX, ch);
1208 pm_runtime_mark_last_busy(up->dev);
1209 pm_runtime_put_autosuspend(up->dev);
1210}
1211
1212static int serial_omap_poll_get_char(struct uart_port *port)
1213{
1214 struct uart_omap_port *up = to_uart_omap_port(port);
1215 unsigned int status;
1216
1217 pm_runtime_get_sync(up->dev);
1218 status = serial_in(up, UART_LSR);
1219 if (!(status & UART_LSR_DR)) {
1220 status = NO_POLL_CHAR;
1221 goto out;
1222 }
1223
1224 status = serial_in(up, UART_RX);
1225
1226out:
1227 pm_runtime_mark_last_busy(up->dev);
1228 pm_runtime_put_autosuspend(up->dev);
1229
1230 return status;
1231}
1232
1233#endif /* CONFIG_CONSOLE_POLL */
1234
1235#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1236
1237#ifdef CONFIG_SERIAL_EARLYCON
1238static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1239{
1240 offset <<= port->regshift;
1241 return readw(port->membase + offset);
1242}
1243
1244static void omap_serial_early_out(struct uart_port *port, int offset,
1245 int value)
1246{
1247 offset <<= port->regshift;
1248 writew(value, port->membase + offset);
1249}
1250
1251static void omap_serial_early_putc(struct uart_port *port, int c)
1252{
1253 unsigned int status;
1254
1255 for (;;) {
1256 status = omap_serial_early_in(port, UART_LSR);
1257 if ((status & BOTH_EMPTY) == BOTH_EMPTY)
1258 break;
1259 cpu_relax();
1260 }
1261 omap_serial_early_out(port, UART_TX, c);
1262}
1263
1264static void early_omap_serial_write(struct console *console, const char *s,
1265 unsigned int count)
1266{
1267 struct earlycon_device *device = console->data;
1268 struct uart_port *port = &device->port;
1269
1270 uart_console_write(port, s, count, omap_serial_early_putc);
1271}
1272
1273static int __init early_omap_serial_setup(struct earlycon_device *device,
1274 const char *options)
1275{
1276 struct uart_port *port = &device->port;
1277
1278 if (!(device->port.membase || device->port.iobase))
1279 return -ENODEV;
1280
1281 port->regshift = 2;
1282 device->con->write = early_omap_serial_write;
1283 return 0;
1284}
1285
1286OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1287OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1288OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1289#endif /* CONFIG_SERIAL_EARLYCON */
1290
1291static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1292
1293static struct uart_driver serial_omap_reg;
1294
1295static void serial_omap_console_putchar(struct uart_port *port, int ch)
1296{
1297 struct uart_omap_port *up = to_uart_omap_port(port);
1298
1299 wait_for_xmitr(up);
1300 serial_out(up, UART_TX, ch);
1301}
1302
1303static void
1304serial_omap_console_write(struct console *co, const char *s,
1305 unsigned int count)
1306{
1307 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1308 unsigned long flags;
1309 unsigned int ier;
1310 int locked = 1;
1311
1312 pm_runtime_get_sync(up->dev);
1313
1314 local_irq_save(flags);
1315 if (up->port.sysrq)
1316 locked = 0;
1317 else if (oops_in_progress)
1318 locked = spin_trylock(&up->port.lock);
1319 else
1320 spin_lock(&up->port.lock);
1321
1322 /*
1323 * First save the IER then disable the interrupts
1324 */
1325 ier = serial_in(up, UART_IER);
1326 serial_out(up, UART_IER, 0);
1327
1328 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1329
1330 /*
1331 * Finally, wait for transmitter to become empty
1332 * and restore the IER
1333 */
1334 wait_for_xmitr(up);
1335 serial_out(up, UART_IER, ier);
1336 /*
1337 * The receive handling will happen properly because the
1338 * receive ready bit will still be set; it is not cleared
1339 * on read. However, modem control will not, we must
1340 * call it if we have saved something in the saved flags
1341 * while processing with interrupts off.
1342 */
1343 if (up->msr_saved_flags)
1344 check_modem_status(up);
1345
1346 pm_runtime_mark_last_busy(up->dev);
1347 pm_runtime_put_autosuspend(up->dev);
1348 if (locked)
1349 spin_unlock(&up->port.lock);
1350 local_irq_restore(flags);
1351}
1352
1353static int __init
1354serial_omap_console_setup(struct console *co, char *options)
1355{
1356 struct uart_omap_port *up;
1357 int baud = 115200;
1358 int bits = 8;
1359 int parity = 'n';
1360 int flow = 'n';
1361
1362 if (serial_omap_console_ports[co->index] == NULL)
1363 return -ENODEV;
1364 up = serial_omap_console_ports[co->index];
1365
1366 if (options)
1367 uart_parse_options(options, &baud, &parity, &bits, &flow);
1368
1369 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1370}
1371
1372static struct console serial_omap_console = {
1373 .name = OMAP_SERIAL_NAME,
1374 .write = serial_omap_console_write,
1375 .device = uart_console_device,
1376 .setup = serial_omap_console_setup,
1377 .flags = CON_PRINTBUFFER,
1378 .index = -1,
1379 .data = &serial_omap_reg,
1380};
1381
1382static void serial_omap_add_console_port(struct uart_omap_port *up)
1383{
1384 serial_omap_console_ports[up->port.line] = up;
1385}
1386
1387#define OMAP_CONSOLE (&serial_omap_console)
1388
1389#else
1390
1391#define OMAP_CONSOLE NULL
1392
1393static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1394{}
1395
1396#endif
1397
1398/* Enable or disable the rs485 support */
1399static int
1400serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
1401{
1402 struct uart_omap_port *up = to_uart_omap_port(port);
1403 unsigned int mode;
1404 int val;
1405
1406 pm_runtime_get_sync(up->dev);
1407
1408 /* Disable interrupts from this port */
1409 mode = up->ier;
1410 up->ier = 0;
1411 serial_out(up, UART_IER, 0);
1412
1413 /* Clamp the delays to [0, 100ms] */
1414 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
1415 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
1416
1417 /* store new config */
1418 port->rs485 = *rs485;
1419
1420 if (up->rts_gpiod) {
1421 /* enable / disable rts */
1422 val = (port->rs485.flags & SER_RS485_ENABLED) ?
1423 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1424 val = (port->rs485.flags & val) ? 1 : 0;
1425 gpiod_set_value(up->rts_gpiod, val);
1426 }
1427
1428 /* Enable interrupts */
1429 up->ier = mode;
1430 serial_out(up, UART_IER, up->ier);
1431
1432 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1433 * TX FIFO is below the trigger level.
1434 */
1435 if (!(port->rs485.flags & SER_RS485_ENABLED) &&
1436 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1437 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1438 serial_out(up, UART_OMAP_SCR, up->scr);
1439 }
1440
1441 pm_runtime_mark_last_busy(up->dev);
1442 pm_runtime_put_autosuspend(up->dev);
1443
1444 return 0;
1445}
1446
1447static const struct uart_ops serial_omap_pops = {
1448 .tx_empty = serial_omap_tx_empty,
1449 .set_mctrl = serial_omap_set_mctrl,
1450 .get_mctrl = serial_omap_get_mctrl,
1451 .stop_tx = serial_omap_stop_tx,
1452 .start_tx = serial_omap_start_tx,
1453 .throttle = serial_omap_throttle,
1454 .unthrottle = serial_omap_unthrottle,
1455 .stop_rx = serial_omap_stop_rx,
1456 .enable_ms = serial_omap_enable_ms,
1457 .break_ctl = serial_omap_break_ctl,
1458 .startup = serial_omap_startup,
1459 .shutdown = serial_omap_shutdown,
1460 .set_termios = serial_omap_set_termios,
1461 .pm = serial_omap_pm,
1462 .type = serial_omap_type,
1463 .release_port = serial_omap_release_port,
1464 .request_port = serial_omap_request_port,
1465 .config_port = serial_omap_config_port,
1466 .verify_port = serial_omap_verify_port,
1467#ifdef CONFIG_CONSOLE_POLL
1468 .poll_put_char = serial_omap_poll_put_char,
1469 .poll_get_char = serial_omap_poll_get_char,
1470#endif
1471};
1472
1473static struct uart_driver serial_omap_reg = {
1474 .owner = THIS_MODULE,
1475 .driver_name = "OMAP-SERIAL",
1476 .dev_name = OMAP_SERIAL_NAME,
1477 .nr = OMAP_MAX_HSUART_PORTS,
1478 .cons = OMAP_CONSOLE,
1479};
1480
1481#ifdef CONFIG_PM_SLEEP
1482static int serial_omap_prepare(struct device *dev)
1483{
1484 struct uart_omap_port *up = dev_get_drvdata(dev);
1485
1486 up->is_suspending = true;
1487
1488 return 0;
1489}
1490
1491static void serial_omap_complete(struct device *dev)
1492{
1493 struct uart_omap_port *up = dev_get_drvdata(dev);
1494
1495 up->is_suspending = false;
1496}
1497
1498static int serial_omap_suspend(struct device *dev)
1499{
1500 struct uart_omap_port *up = dev_get_drvdata(dev);
1501
1502 uart_suspend_port(&serial_omap_reg, &up->port);
1503 flush_work(&up->qos_work);
1504
1505 if (device_may_wakeup(dev))
1506 serial_omap_enable_wakeup(up, true);
1507 else
1508 serial_omap_enable_wakeup(up, false);
1509
1510 return 0;
1511}
1512
1513static int serial_omap_resume(struct device *dev)
1514{
1515 struct uart_omap_port *up = dev_get_drvdata(dev);
1516
1517 if (device_may_wakeup(dev))
1518 serial_omap_enable_wakeup(up, false);
1519
1520 uart_resume_port(&serial_omap_reg, &up->port);
1521
1522 return 0;
1523}
1524#else
1525#define serial_omap_prepare NULL
1526#define serial_omap_complete NULL
1527#endif /* CONFIG_PM_SLEEP */
1528
1529static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1530{
1531 u32 mvr, scheme;
1532 u16 revision, major, minor;
1533
1534 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1535
1536 /* Check revision register scheme */
1537 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1538
1539 switch (scheme) {
1540 case 0: /* Legacy Scheme: OMAP2/3 */
1541 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1542 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1543 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1544 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1545 break;
1546 case 1:
1547 /* New Scheme: OMAP4+ */
1548 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1549 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1550 OMAP_UART_MVR_MAJ_SHIFT;
1551 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1552 break;
1553 default:
1554 dev_warn(up->dev,
1555 "Unknown %s revision, defaulting to highest\n",
1556 up->name);
1557 /* highest possible revision */
1558 major = 0xff;
1559 minor = 0xff;
1560 }
1561
1562 /* normalize revision for the driver */
1563 revision = UART_BUILD_REVISION(major, minor);
1564
1565 switch (revision) {
1566 case OMAP_UART_REV_46:
1567 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1568 UART_ERRATA_i291_DMA_FORCEIDLE);
1569 break;
1570 case OMAP_UART_REV_52:
1571 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1572 UART_ERRATA_i291_DMA_FORCEIDLE);
1573 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1574 break;
1575 case OMAP_UART_REV_63:
1576 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1577 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1578 break;
1579 default:
1580 break;
1581 }
1582}
1583
1584static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1585{
1586 struct omap_uart_port_info *omap_up_info;
1587
1588 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1589 if (!omap_up_info)
1590 return NULL; /* out of memory */
1591
1592 of_property_read_u32(dev->of_node, "clock-frequency",
1593 &omap_up_info->uartclk);
1594
1595 omap_up_info->flags = UPF_BOOT_AUTOCONF;
1596
1597 return omap_up_info;
1598}
1599
1600static int serial_omap_probe_rs485(struct uart_omap_port *up,
1601 struct device *dev)
1602{
1603 struct serial_rs485 *rs485conf = &up->port.rs485;
1604 struct device_node *np = dev->of_node;
1605 enum gpiod_flags gflags;
1606 int ret;
1607
1608 rs485conf->flags = 0;
1609 up->rts_gpiod = NULL;
1610
1611 if (!np)
1612 return 0;
1613
1614 ret = uart_get_rs485_mode(&up->port);
1615 if (ret)
1616 return ret;
1617
1618 if (of_property_read_bool(np, "rs485-rts-active-high")) {
1619 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1620 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1621 } else {
1622 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1623 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1624 }
1625
1626 /* check for tx enable gpio */
1627 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1628 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1629 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1630 if (IS_ERR(up->rts_gpiod)) {
1631 ret = PTR_ERR(up->rts_gpiod);
1632 if (ret == -EPROBE_DEFER)
1633 return ret;
1634 /*
1635 * FIXME: the code historically ignored any other error than
1636 * -EPROBE_DEFER and just went on without GPIO.
1637 */
1638 up->rts_gpiod = NULL;
1639 } else {
1640 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1641 }
1642
1643 return 0;
1644}
1645
1646static int serial_omap_probe(struct platform_device *pdev)
1647{
1648 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1649 struct uart_omap_port *up;
1650 struct resource *mem;
1651 void __iomem *base;
1652 int uartirq = 0;
1653 int wakeirq = 0;
1654 int ret;
1655
1656 /* The optional wakeirq may be specified in the board dts file */
1657 if (pdev->dev.of_node) {
1658 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1659 if (!uartirq)
1660 return -EPROBE_DEFER;
1661 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1662 omap_up_info = of_get_uart_port_info(&pdev->dev);
1663 pdev->dev.platform_data = omap_up_info;
1664 } else {
1665 uartirq = platform_get_irq(pdev, 0);
1666 if (uartirq < 0)
1667 return -EPROBE_DEFER;
1668 }
1669
1670 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1671 if (!up)
1672 return -ENOMEM;
1673
1674 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1675 base = devm_ioremap_resource(&pdev->dev, mem);
1676 if (IS_ERR(base))
1677 return PTR_ERR(base);
1678
1679 up->dev = &pdev->dev;
1680 up->port.dev = &pdev->dev;
1681 up->port.type = PORT_OMAP;
1682 up->port.iotype = UPIO_MEM;
1683 up->port.irq = uartirq;
1684 up->port.regshift = 2;
1685 up->port.fifosize = 64;
1686 up->port.ops = &serial_omap_pops;
1687 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1688
1689 if (pdev->dev.of_node)
1690 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1691 else
1692 ret = pdev->id;
1693
1694 if (ret < 0) {
1695 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1696 ret);
1697 goto err_port_line;
1698 }
1699 up->port.line = ret;
1700
1701 if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1702 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
1703 OMAP_MAX_HSUART_PORTS);
1704 ret = -ENXIO;
1705 goto err_port_line;
1706 }
1707
1708 up->wakeirq = wakeirq;
1709 if (!up->wakeirq)
1710 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1711 up->port.line);
1712
1713 ret = serial_omap_probe_rs485(up, &pdev->dev);
1714 if (ret < 0)
1715 goto err_rs485;
1716
1717 sprintf(up->name, "OMAP UART%d", up->port.line);
1718 up->port.mapbase = mem->start;
1719 up->port.membase = base;
1720 up->port.flags = omap_up_info->flags;
1721 up->port.uartclk = omap_up_info->uartclk;
1722 up->port.rs485_config = serial_omap_config_rs485;
1723 if (!up->port.uartclk) {
1724 up->port.uartclk = DEFAULT_CLK_SPEED;
1725 dev_warn(&pdev->dev,
1726 "No clock speed specified: using default: %d\n",
1727 DEFAULT_CLK_SPEED);
1728 }
1729
1730 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1731 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1732 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1733 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1734
1735 platform_set_drvdata(pdev, up);
1736 if (omap_up_info->autosuspend_timeout == 0)
1737 omap_up_info->autosuspend_timeout = -1;
1738
1739 device_init_wakeup(up->dev, true);
1740 pm_runtime_use_autosuspend(&pdev->dev);
1741 pm_runtime_set_autosuspend_delay(&pdev->dev,
1742 omap_up_info->autosuspend_timeout);
1743
1744 pm_runtime_irq_safe(&pdev->dev);
1745 pm_runtime_enable(&pdev->dev);
1746
1747 pm_runtime_get_sync(&pdev->dev);
1748
1749 omap_serial_fill_features_erratas(up);
1750
1751 ui[up->port.line] = up;
1752 serial_omap_add_console_port(up);
1753
1754 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1755 if (ret != 0)
1756 goto err_add_port;
1757
1758 pm_runtime_mark_last_busy(up->dev);
1759 pm_runtime_put_autosuspend(up->dev);
1760 return 0;
1761
1762err_add_port:
1763 pm_runtime_dont_use_autosuspend(&pdev->dev);
1764 pm_runtime_put_sync(&pdev->dev);
1765 pm_runtime_disable(&pdev->dev);
1766 cpu_latency_qos_remove_request(&up->pm_qos_request);
1767 device_init_wakeup(up->dev, false);
1768err_rs485:
1769err_port_line:
1770 return ret;
1771}
1772
1773static int serial_omap_remove(struct platform_device *dev)
1774{
1775 struct uart_omap_port *up = platform_get_drvdata(dev);
1776
1777 pm_runtime_get_sync(up->dev);
1778
1779 uart_remove_one_port(&serial_omap_reg, &up->port);
1780
1781 pm_runtime_dont_use_autosuspend(up->dev);
1782 pm_runtime_put_sync(up->dev);
1783 pm_runtime_disable(up->dev);
1784 cpu_latency_qos_remove_request(&up->pm_qos_request);
1785 device_init_wakeup(&dev->dev, false);
1786
1787 return 0;
1788}
1789
1790/*
1791 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1792 * The access to uart register after MDR1 Access
1793 * causes UART to corrupt data.
1794 *
1795 * Need a delay =
1796 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1797 * give 10 times as much
1798 */
1799static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1800{
1801 u8 timeout = 255;
1802
1803 serial_out(up, UART_OMAP_MDR1, mdr1);
1804 udelay(2);
1805 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1806 UART_FCR_CLEAR_RCVR);
1807 /*
1808 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1809 * TX_FIFO_E bit is 1.
1810 */
1811 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1812 (UART_LSR_THRE | UART_LSR_DR))) {
1813 timeout--;
1814 if (!timeout) {
1815 /* Should *never* happen. we warn and carry on */
1816 dev_crit(up->dev, "Errata i202: timedout %x\n",
1817 serial_in(up, UART_LSR));
1818 break;
1819 }
1820 udelay(1);
1821 }
1822}
1823
1824#ifdef CONFIG_PM
1825static void serial_omap_restore_context(struct uart_omap_port *up)
1826{
1827 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1828 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1829 else
1830 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1831
1832 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1833 serial_out(up, UART_EFR, UART_EFR_ECB);
1834 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1835 serial_out(up, UART_IER, 0x0);
1836 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1837 serial_out(up, UART_DLL, up->dll);
1838 serial_out(up, UART_DLM, up->dlh);
1839 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1840 serial_out(up, UART_IER, up->ier);
1841 serial_out(up, UART_FCR, up->fcr);
1842 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1843 serial_out(up, UART_MCR, up->mcr);
1844 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1845 serial_out(up, UART_OMAP_SCR, up->scr);
1846 serial_out(up, UART_EFR, up->efr);
1847 serial_out(up, UART_LCR, up->lcr);
1848 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1849 serial_omap_mdr1_errataset(up, up->mdr1);
1850 else
1851 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1852 serial_out(up, UART_OMAP_WER, up->wer);
1853}
1854
1855static int serial_omap_runtime_suspend(struct device *dev)
1856{
1857 struct uart_omap_port *up = dev_get_drvdata(dev);
1858
1859 if (!up)
1860 return -EINVAL;
1861
1862 /*
1863 * When using 'no_console_suspend', the console UART must not be
1864 * suspended. Since driver suspend is managed by runtime suspend,
1865 * preventing runtime suspend (by returning error) will keep device
1866 * active during suspend.
1867 */
1868 if (up->is_suspending && !console_suspend_enabled &&
1869 uart_console(&up->port))
1870 return -EBUSY;
1871
1872 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1873
1874 serial_omap_enable_wakeup(up, true);
1875
1876 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1877 schedule_work(&up->qos_work);
1878
1879 return 0;
1880}
1881
1882static int serial_omap_runtime_resume(struct device *dev)
1883{
1884 struct uart_omap_port *up = dev_get_drvdata(dev);
1885
1886 int loss_cnt = serial_omap_get_context_loss_count(up);
1887
1888 serial_omap_enable_wakeup(up, false);
1889
1890 if (loss_cnt < 0) {
1891 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1892 loss_cnt);
1893 serial_omap_restore_context(up);
1894 } else if (up->context_loss_cnt != loss_cnt) {
1895 serial_omap_restore_context(up);
1896 }
1897 up->latency = up->calc_latency;
1898 schedule_work(&up->qos_work);
1899
1900 return 0;
1901}
1902#endif
1903
1904static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1905 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1906 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1907 serial_omap_runtime_resume, NULL)
1908 .prepare = serial_omap_prepare,
1909 .complete = serial_omap_complete,
1910};
1911
1912#if defined(CONFIG_OF)
1913static const struct of_device_id omap_serial_of_match[] = {
1914 { .compatible = "ti,omap2-uart" },
1915 { .compatible = "ti,omap3-uart" },
1916 { .compatible = "ti,omap4-uart" },
1917 {},
1918};
1919MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1920#endif
1921
1922static struct platform_driver serial_omap_driver = {
1923 .probe = serial_omap_probe,
1924 .remove = serial_omap_remove,
1925 .driver = {
1926 .name = OMAP_SERIAL_DRIVER_NAME,
1927 .pm = &serial_omap_dev_pm_ops,
1928 .of_match_table = of_match_ptr(omap_serial_of_match),
1929 },
1930};
1931
1932static int __init serial_omap_init(void)
1933{
1934 int ret;
1935
1936 ret = uart_register_driver(&serial_omap_reg);
1937 if (ret != 0)
1938 return ret;
1939 ret = platform_driver_register(&serial_omap_driver);
1940 if (ret != 0)
1941 uart_unregister_driver(&serial_omap_reg);
1942 return ret;
1943}
1944
1945static void __exit serial_omap_exit(void)
1946{
1947 platform_driver_unregister(&serial_omap_driver);
1948 uart_unregister_driver(&serial_omap_reg);
1949}
1950
1951module_init(serial_omap_init);
1952module_exit(serial_omap_exit);
1953
1954MODULE_DESCRIPTION("OMAP High Speed UART driver");
1955MODULE_LICENSE("GPL");
1956MODULE_AUTHOR("Texas Instruments Inc");
1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
23#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/serial_reg.h>
31#include <linux/delay.h>
32#include <linux/slab.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/platform_device.h>
36#include <linux/io.h>
37#include <linux/clk.h>
38#include <linux/serial_core.h>
39#include <linux/irq.h>
40#include <linux/pm_runtime.h>
41#include <linux/of.h>
42#include <linux/of_irq.h>
43#include <linux/gpio.h>
44#include <linux/of_gpio.h>
45#include <linux/platform_data/serial-omap.h>
46
47#include <dt-bindings/gpio/gpio.h>
48
49#define OMAP_MAX_HSUART_PORTS 6
50
51#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
52
53#define OMAP_UART_REV_42 0x0402
54#define OMAP_UART_REV_46 0x0406
55#define OMAP_UART_REV_52 0x0502
56#define OMAP_UART_REV_63 0x0603
57
58#define OMAP_UART_TX_WAKEUP_EN BIT(7)
59
60/* Feature flags */
61#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
62
63#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
64#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
65
66#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
67
68/* SCR register bitmasks */
69#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
70#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
71#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
72
73/* FCR register bitmasks */
74#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
75#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
76
77/* MVR register bitmasks */
78#define OMAP_UART_MVR_SCHEME_SHIFT 30
79
80#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
81#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
82#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
83
84#define OMAP_UART_MVR_MAJ_MASK 0x700
85#define OMAP_UART_MVR_MAJ_SHIFT 8
86#define OMAP_UART_MVR_MIN_MASK 0x3f
87
88#define OMAP_UART_DMA_CH_FREE -1
89
90#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
91#define OMAP_MODE13X_SPEED 230400
92
93/* WER = 0x7F
94 * Enable module level wakeup in WER reg
95 */
96#define OMAP_UART_WER_MOD_WKUP 0X7F
97
98/* Enable XON/XOFF flow control on output */
99#define OMAP_UART_SW_TX 0x08
100
101/* Enable XON/XOFF flow control on input */
102#define OMAP_UART_SW_RX 0x02
103
104#define OMAP_UART_SW_CLR 0xF0
105
106#define OMAP_UART_TCR_TRIG 0x0F
107
108struct uart_omap_dma {
109 u8 uart_dma_tx;
110 u8 uart_dma_rx;
111 int rx_dma_channel;
112 int tx_dma_channel;
113 dma_addr_t rx_buf_dma_phys;
114 dma_addr_t tx_buf_dma_phys;
115 unsigned int uart_base;
116 /*
117 * Buffer for rx dma.It is not required for tx because the buffer
118 * comes from port structure.
119 */
120 unsigned char *rx_buf;
121 unsigned int prev_rx_dma_pos;
122 int tx_buf_size;
123 int tx_dma_used;
124 int rx_dma_used;
125 spinlock_t tx_lock;
126 spinlock_t rx_lock;
127 /* timer to poll activity on rx dma */
128 struct timer_list rx_timer;
129 unsigned int rx_buf_size;
130 unsigned int rx_poll_rate;
131 unsigned int rx_timeout;
132};
133
134struct uart_omap_port {
135 struct uart_port port;
136 struct uart_omap_dma uart_dma;
137 struct device *dev;
138 int wakeirq;
139
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char fcr;
144 unsigned char efr;
145 unsigned char dll;
146 unsigned char dlh;
147 unsigned char mdr1;
148 unsigned char scr;
149 unsigned char wer;
150
151 int use_dma;
152 /*
153 * Some bits in registers are cleared on a read, so they must
154 * be saved whenever the register is read but the bits will not
155 * be immediately processed.
156 */
157 unsigned int lsr_break_flag;
158 unsigned char msr_saved_flags;
159 char name[20];
160 unsigned long port_activity;
161 int context_loss_cnt;
162 u32 errata;
163 u8 wakeups_enabled;
164 u32 features;
165
166 int DTR_gpio;
167 int DTR_inverted;
168 int DTR_active;
169
170 struct serial_rs485 rs485;
171 int rts_gpio;
172
173 struct pm_qos_request pm_qos_request;
174 u32 latency;
175 u32 calc_latency;
176 struct work_struct qos_work;
177 bool is_suspending;
178};
179
180#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
181
182static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
183
184/* Forward declaration of functions */
185static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
186
187static struct workqueue_struct *serial_omap_uart_wq;
188
189static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
190{
191 offset <<= up->port.regshift;
192 return readw(up->port.membase + offset);
193}
194
195static inline void serial_out(struct uart_omap_port *up, int offset, int value)
196{
197 offset <<= up->port.regshift;
198 writew(value, up->port.membase + offset);
199}
200
201static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
202{
203 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
204 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
205 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
206 serial_out(up, UART_FCR, 0);
207}
208
209static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
210{
211 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
212
213 if (!pdata || !pdata->get_context_loss_count)
214 return -EINVAL;
215
216 return pdata->get_context_loss_count(up->dev);
217}
218
219static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
220 bool enable)
221{
222 if (!up->wakeirq)
223 return;
224
225 if (enable)
226 enable_irq(up->wakeirq);
227 else
228 disable_irq_nosync(up->wakeirq);
229}
230
231static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
232{
233 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
234
235 if (enable == up->wakeups_enabled)
236 return;
237
238 serial_omap_enable_wakeirq(up, enable);
239 up->wakeups_enabled = enable;
240
241 if (!pdata || !pdata->enable_wakeup)
242 return;
243
244 pdata->enable_wakeup(up->dev, enable);
245}
246
247/*
248 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
249 * @port: uart port info
250 * @baud: baudrate for which mode needs to be determined
251 *
252 * Returns true if baud rate is MODE16X and false if MODE13X
253 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
254 * and Error Rates" determines modes not for all common baud rates.
255 * E.g. for 1000000 baud rate mode must be 16x, but according to that
256 * table it's determined as 13x.
257 */
258static bool
259serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
260{
261 unsigned int n13 = port->uartclk / (13 * baud);
262 unsigned int n16 = port->uartclk / (16 * baud);
263 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
264 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
265 if (baudAbsDiff13 < 0)
266 baudAbsDiff13 = -baudAbsDiff13;
267 if (baudAbsDiff16 < 0)
268 baudAbsDiff16 = -baudAbsDiff16;
269
270 return (baudAbsDiff13 >= baudAbsDiff16);
271}
272
273/*
274 * serial_omap_get_divisor - calculate divisor value
275 * @port: uart port info
276 * @baud: baudrate for which divisor needs to be calculated.
277 */
278static unsigned int
279serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
280{
281 unsigned int mode;
282
283 if (!serial_omap_baud_is_mode16(port, baud))
284 mode = 13;
285 else
286 mode = 16;
287 return port->uartclk/(mode * baud);
288}
289
290static void serial_omap_enable_ms(struct uart_port *port)
291{
292 struct uart_omap_port *up = to_uart_omap_port(port);
293
294 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
295
296 pm_runtime_get_sync(up->dev);
297 up->ier |= UART_IER_MSI;
298 serial_out(up, UART_IER, up->ier);
299 pm_runtime_mark_last_busy(up->dev);
300 pm_runtime_put_autosuspend(up->dev);
301}
302
303static void serial_omap_stop_tx(struct uart_port *port)
304{
305 struct uart_omap_port *up = to_uart_omap_port(port);
306 int res;
307
308 pm_runtime_get_sync(up->dev);
309
310 /* Handle RS-485 */
311 if (up->rs485.flags & SER_RS485_ENABLED) {
312 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
313 /* THR interrupt is fired when both TX FIFO and TX
314 * shift register are empty. This means there's nothing
315 * left to transmit now, so make sure the THR interrupt
316 * is fired when TX FIFO is below the trigger level,
317 * disable THR interrupts and toggle the RS-485 GPIO
318 * data direction pin if needed.
319 */
320 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
321 serial_out(up, UART_OMAP_SCR, up->scr);
322 res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
323 if (gpio_get_value(up->rts_gpio) != res) {
324 if (up->rs485.delay_rts_after_send > 0)
325 mdelay(up->rs485.delay_rts_after_send);
326 gpio_set_value(up->rts_gpio, res);
327 }
328 } else {
329 /* We're asked to stop, but there's still stuff in the
330 * UART FIFO, so make sure the THR interrupt is fired
331 * when both TX FIFO and TX shift register are empty.
332 * The next THR interrupt (if no transmission is started
333 * in the meantime) will indicate the end of a
334 * transmission. Therefore we _don't_ disable THR
335 * interrupts in this situation.
336 */
337 up->scr |= OMAP_UART_SCR_TX_EMPTY;
338 serial_out(up, UART_OMAP_SCR, up->scr);
339 return;
340 }
341 }
342
343 if (up->ier & UART_IER_THRI) {
344 up->ier &= ~UART_IER_THRI;
345 serial_out(up, UART_IER, up->ier);
346 }
347
348 if ((up->rs485.flags & SER_RS485_ENABLED) &&
349 !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
350 /*
351 * Empty the RX FIFO, we are not interested in anything
352 * received during the half-duplex transmission.
353 */
354 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
355 /* Re-enable RX interrupts */
356 up->ier |= UART_IER_RLSI | UART_IER_RDI;
357 up->port.read_status_mask |= UART_LSR_DR;
358 serial_out(up, UART_IER, up->ier);
359 }
360
361 pm_runtime_mark_last_busy(up->dev);
362 pm_runtime_put_autosuspend(up->dev);
363}
364
365static void serial_omap_stop_rx(struct uart_port *port)
366{
367 struct uart_omap_port *up = to_uart_omap_port(port);
368
369 pm_runtime_get_sync(up->dev);
370 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
371 up->port.read_status_mask &= ~UART_LSR_DR;
372 serial_out(up, UART_IER, up->ier);
373 pm_runtime_mark_last_busy(up->dev);
374 pm_runtime_put_autosuspend(up->dev);
375}
376
377static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
378{
379 struct circ_buf *xmit = &up->port.state->xmit;
380 int count;
381
382 if (up->port.x_char) {
383 serial_out(up, UART_TX, up->port.x_char);
384 up->port.icount.tx++;
385 up->port.x_char = 0;
386 return;
387 }
388 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
389 serial_omap_stop_tx(&up->port);
390 return;
391 }
392 count = up->port.fifosize / 4;
393 do {
394 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
395 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
396 up->port.icount.tx++;
397 if (uart_circ_empty(xmit))
398 break;
399 } while (--count > 0);
400
401 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
402 spin_unlock(&up->port.lock);
403 uart_write_wakeup(&up->port);
404 spin_lock(&up->port.lock);
405 }
406
407 if (uart_circ_empty(xmit))
408 serial_omap_stop_tx(&up->port);
409}
410
411static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
412{
413 if (!(up->ier & UART_IER_THRI)) {
414 up->ier |= UART_IER_THRI;
415 serial_out(up, UART_IER, up->ier);
416 }
417}
418
419static void serial_omap_start_tx(struct uart_port *port)
420{
421 struct uart_omap_port *up = to_uart_omap_port(port);
422 int res;
423
424 pm_runtime_get_sync(up->dev);
425
426 /* Handle RS-485 */
427 if (up->rs485.flags & SER_RS485_ENABLED) {
428 /* Fire THR interrupts when FIFO is below trigger level */
429 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
430 serial_out(up, UART_OMAP_SCR, up->scr);
431
432 /* if rts not already enabled */
433 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
434 if (gpio_get_value(up->rts_gpio) != res) {
435 gpio_set_value(up->rts_gpio, res);
436 if (up->rs485.delay_rts_before_send > 0)
437 mdelay(up->rs485.delay_rts_before_send);
438 }
439 }
440
441 if ((up->rs485.flags & SER_RS485_ENABLED) &&
442 !(up->rs485.flags & SER_RS485_RX_DURING_TX))
443 serial_omap_stop_rx(port);
444
445 serial_omap_enable_ier_thri(up);
446 pm_runtime_mark_last_busy(up->dev);
447 pm_runtime_put_autosuspend(up->dev);
448}
449
450static void serial_omap_throttle(struct uart_port *port)
451{
452 struct uart_omap_port *up = to_uart_omap_port(port);
453 unsigned long flags;
454
455 pm_runtime_get_sync(up->dev);
456 spin_lock_irqsave(&up->port.lock, flags);
457 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
458 serial_out(up, UART_IER, up->ier);
459 spin_unlock_irqrestore(&up->port.lock, flags);
460 pm_runtime_mark_last_busy(up->dev);
461 pm_runtime_put_autosuspend(up->dev);
462}
463
464static void serial_omap_unthrottle(struct uart_port *port)
465{
466 struct uart_omap_port *up = to_uart_omap_port(port);
467 unsigned long flags;
468
469 pm_runtime_get_sync(up->dev);
470 spin_lock_irqsave(&up->port.lock, flags);
471 up->ier |= UART_IER_RLSI | UART_IER_RDI;
472 serial_out(up, UART_IER, up->ier);
473 spin_unlock_irqrestore(&up->port.lock, flags);
474 pm_runtime_mark_last_busy(up->dev);
475 pm_runtime_put_autosuspend(up->dev);
476}
477
478static unsigned int check_modem_status(struct uart_omap_port *up)
479{
480 unsigned int status;
481
482 status = serial_in(up, UART_MSR);
483 status |= up->msr_saved_flags;
484 up->msr_saved_flags = 0;
485 if ((status & UART_MSR_ANY_DELTA) == 0)
486 return status;
487
488 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
489 up->port.state != NULL) {
490 if (status & UART_MSR_TERI)
491 up->port.icount.rng++;
492 if (status & UART_MSR_DDSR)
493 up->port.icount.dsr++;
494 if (status & UART_MSR_DDCD)
495 uart_handle_dcd_change
496 (&up->port, status & UART_MSR_DCD);
497 if (status & UART_MSR_DCTS)
498 uart_handle_cts_change
499 (&up->port, status & UART_MSR_CTS);
500 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
501 }
502
503 return status;
504}
505
506static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
507{
508 unsigned int flag;
509 unsigned char ch = 0;
510
511 if (likely(lsr & UART_LSR_DR))
512 ch = serial_in(up, UART_RX);
513
514 up->port.icount.rx++;
515 flag = TTY_NORMAL;
516
517 if (lsr & UART_LSR_BI) {
518 flag = TTY_BREAK;
519 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
520 up->port.icount.brk++;
521 /*
522 * We do the SysRQ and SAK checking
523 * here because otherwise the break
524 * may get masked by ignore_status_mask
525 * or read_status_mask.
526 */
527 if (uart_handle_break(&up->port))
528 return;
529
530 }
531
532 if (lsr & UART_LSR_PE) {
533 flag = TTY_PARITY;
534 up->port.icount.parity++;
535 }
536
537 if (lsr & UART_LSR_FE) {
538 flag = TTY_FRAME;
539 up->port.icount.frame++;
540 }
541
542 if (lsr & UART_LSR_OE)
543 up->port.icount.overrun++;
544
545#ifdef CONFIG_SERIAL_OMAP_CONSOLE
546 if (up->port.line == up->port.cons->index) {
547 /* Recover the break flag from console xmit */
548 lsr |= up->lsr_break_flag;
549 }
550#endif
551 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
552}
553
554static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
555{
556 unsigned char ch = 0;
557 unsigned int flag;
558
559 if (!(lsr & UART_LSR_DR))
560 return;
561
562 ch = serial_in(up, UART_RX);
563 flag = TTY_NORMAL;
564 up->port.icount.rx++;
565
566 if (uart_handle_sysrq_char(&up->port, ch))
567 return;
568
569 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
570}
571
572/**
573 * serial_omap_irq() - This handles the interrupt from one port
574 * @irq: uart port irq number
575 * @dev_id: uart port info
576 */
577static irqreturn_t serial_omap_irq(int irq, void *dev_id)
578{
579 struct uart_omap_port *up = dev_id;
580 unsigned int iir, lsr;
581 unsigned int type;
582 irqreturn_t ret = IRQ_NONE;
583 int max_count = 256;
584
585 spin_lock(&up->port.lock);
586 pm_runtime_get_sync(up->dev);
587
588 do {
589 iir = serial_in(up, UART_IIR);
590 if (iir & UART_IIR_NO_INT)
591 break;
592
593 ret = IRQ_HANDLED;
594 lsr = serial_in(up, UART_LSR);
595
596 /* extract IRQ type from IIR register */
597 type = iir & 0x3e;
598
599 switch (type) {
600 case UART_IIR_MSI:
601 check_modem_status(up);
602 break;
603 case UART_IIR_THRI:
604 transmit_chars(up, lsr);
605 break;
606 case UART_IIR_RX_TIMEOUT:
607 /* FALLTHROUGH */
608 case UART_IIR_RDI:
609 serial_omap_rdi(up, lsr);
610 break;
611 case UART_IIR_RLSI:
612 serial_omap_rlsi(up, lsr);
613 break;
614 case UART_IIR_CTS_RTS_DSR:
615 /* simply try again */
616 break;
617 case UART_IIR_XOFF:
618 /* FALLTHROUGH */
619 default:
620 break;
621 }
622 } while (!(iir & UART_IIR_NO_INT) && max_count--);
623
624 spin_unlock(&up->port.lock);
625
626 tty_flip_buffer_push(&up->port.state->port);
627
628 pm_runtime_mark_last_busy(up->dev);
629 pm_runtime_put_autosuspend(up->dev);
630 up->port_activity = jiffies;
631
632 return ret;
633}
634
635static unsigned int serial_omap_tx_empty(struct uart_port *port)
636{
637 struct uart_omap_port *up = to_uart_omap_port(port);
638 unsigned long flags = 0;
639 unsigned int ret = 0;
640
641 pm_runtime_get_sync(up->dev);
642 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
643 spin_lock_irqsave(&up->port.lock, flags);
644 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
645 spin_unlock_irqrestore(&up->port.lock, flags);
646 pm_runtime_mark_last_busy(up->dev);
647 pm_runtime_put_autosuspend(up->dev);
648 return ret;
649}
650
651static unsigned int serial_omap_get_mctrl(struct uart_port *port)
652{
653 struct uart_omap_port *up = to_uart_omap_port(port);
654 unsigned int status;
655 unsigned int ret = 0;
656
657 pm_runtime_get_sync(up->dev);
658 status = check_modem_status(up);
659 pm_runtime_mark_last_busy(up->dev);
660 pm_runtime_put_autosuspend(up->dev);
661
662 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
663
664 if (status & UART_MSR_DCD)
665 ret |= TIOCM_CAR;
666 if (status & UART_MSR_RI)
667 ret |= TIOCM_RNG;
668 if (status & UART_MSR_DSR)
669 ret |= TIOCM_DSR;
670 if (status & UART_MSR_CTS)
671 ret |= TIOCM_CTS;
672 return ret;
673}
674
675static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
676{
677 struct uart_omap_port *up = to_uart_omap_port(port);
678 unsigned char mcr = 0, old_mcr;
679
680 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
681 if (mctrl & TIOCM_RTS)
682 mcr |= UART_MCR_RTS;
683 if (mctrl & TIOCM_DTR)
684 mcr |= UART_MCR_DTR;
685 if (mctrl & TIOCM_OUT1)
686 mcr |= UART_MCR_OUT1;
687 if (mctrl & TIOCM_OUT2)
688 mcr |= UART_MCR_OUT2;
689 if (mctrl & TIOCM_LOOP)
690 mcr |= UART_MCR_LOOP;
691
692 pm_runtime_get_sync(up->dev);
693 old_mcr = serial_in(up, UART_MCR);
694 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
695 UART_MCR_DTR | UART_MCR_RTS);
696 up->mcr = old_mcr | mcr;
697 serial_out(up, UART_MCR, up->mcr);
698 pm_runtime_mark_last_busy(up->dev);
699 pm_runtime_put_autosuspend(up->dev);
700
701 if (gpio_is_valid(up->DTR_gpio) &&
702 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
703 up->DTR_active = !up->DTR_active;
704 if (gpio_cansleep(up->DTR_gpio))
705 schedule_work(&up->qos_work);
706 else
707 gpio_set_value(up->DTR_gpio,
708 up->DTR_active != up->DTR_inverted);
709 }
710}
711
712static void serial_omap_break_ctl(struct uart_port *port, int break_state)
713{
714 struct uart_omap_port *up = to_uart_omap_port(port);
715 unsigned long flags = 0;
716
717 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
718 pm_runtime_get_sync(up->dev);
719 spin_lock_irqsave(&up->port.lock, flags);
720 if (break_state == -1)
721 up->lcr |= UART_LCR_SBC;
722 else
723 up->lcr &= ~UART_LCR_SBC;
724 serial_out(up, UART_LCR, up->lcr);
725 spin_unlock_irqrestore(&up->port.lock, flags);
726 pm_runtime_mark_last_busy(up->dev);
727 pm_runtime_put_autosuspend(up->dev);
728}
729
730static int serial_omap_startup(struct uart_port *port)
731{
732 struct uart_omap_port *up = to_uart_omap_port(port);
733 unsigned long flags = 0;
734 int retval;
735
736 /*
737 * Allocate the IRQ
738 */
739 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
740 up->name, up);
741 if (retval)
742 return retval;
743
744 /* Optional wake-up IRQ */
745 if (up->wakeirq) {
746 retval = request_irq(up->wakeirq, serial_omap_irq,
747 up->port.irqflags, up->name, up);
748 if (retval) {
749 free_irq(up->port.irq, up);
750 return retval;
751 }
752 disable_irq(up->wakeirq);
753 }
754
755 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
756
757 pm_runtime_get_sync(up->dev);
758 /*
759 * Clear the FIFO buffers and disable them.
760 * (they will be reenabled in set_termios())
761 */
762 serial_omap_clear_fifos(up);
763 /* For Hardware flow control */
764 serial_out(up, UART_MCR, UART_MCR_RTS);
765
766 /*
767 * Clear the interrupt registers.
768 */
769 (void) serial_in(up, UART_LSR);
770 if (serial_in(up, UART_LSR) & UART_LSR_DR)
771 (void) serial_in(up, UART_RX);
772 (void) serial_in(up, UART_IIR);
773 (void) serial_in(up, UART_MSR);
774
775 /*
776 * Now, initialize the UART
777 */
778 serial_out(up, UART_LCR, UART_LCR_WLEN8);
779 spin_lock_irqsave(&up->port.lock, flags);
780 /*
781 * Most PC uarts need OUT2 raised to enable interrupts.
782 */
783 up->port.mctrl |= TIOCM_OUT2;
784 serial_omap_set_mctrl(&up->port, up->port.mctrl);
785 spin_unlock_irqrestore(&up->port.lock, flags);
786
787 up->msr_saved_flags = 0;
788 /*
789 * Finally, enable interrupts. Note: Modem status interrupts
790 * are set via set_termios(), which will be occurring imminently
791 * anyway, so we don't enable them here.
792 */
793 up->ier = UART_IER_RLSI | UART_IER_RDI;
794 serial_out(up, UART_IER, up->ier);
795
796 /* Enable module level wake up */
797 up->wer = OMAP_UART_WER_MOD_WKUP;
798 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
799 up->wer |= OMAP_UART_TX_WAKEUP_EN;
800
801 serial_out(up, UART_OMAP_WER, up->wer);
802
803 pm_runtime_mark_last_busy(up->dev);
804 pm_runtime_put_autosuspend(up->dev);
805 up->port_activity = jiffies;
806 return 0;
807}
808
809static void serial_omap_shutdown(struct uart_port *port)
810{
811 struct uart_omap_port *up = to_uart_omap_port(port);
812 unsigned long flags = 0;
813
814 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
815
816 pm_runtime_get_sync(up->dev);
817 /*
818 * Disable interrupts from this port
819 */
820 up->ier = 0;
821 serial_out(up, UART_IER, 0);
822
823 spin_lock_irqsave(&up->port.lock, flags);
824 up->port.mctrl &= ~TIOCM_OUT2;
825 serial_omap_set_mctrl(&up->port, up->port.mctrl);
826 spin_unlock_irqrestore(&up->port.lock, flags);
827
828 /*
829 * Disable break condition and FIFOs
830 */
831 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
832 serial_omap_clear_fifos(up);
833
834 /*
835 * Read data port to reset things, and then free the irq
836 */
837 if (serial_in(up, UART_LSR) & UART_LSR_DR)
838 (void) serial_in(up, UART_RX);
839
840 pm_runtime_mark_last_busy(up->dev);
841 pm_runtime_put_autosuspend(up->dev);
842 free_irq(up->port.irq, up);
843 if (up->wakeirq)
844 free_irq(up->wakeirq, up);
845}
846
847static void serial_omap_uart_qos_work(struct work_struct *work)
848{
849 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
850 qos_work);
851
852 pm_qos_update_request(&up->pm_qos_request, up->latency);
853 if (gpio_is_valid(up->DTR_gpio))
854 gpio_set_value_cansleep(up->DTR_gpio,
855 up->DTR_active != up->DTR_inverted);
856}
857
858static void
859serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
860 struct ktermios *old)
861{
862 struct uart_omap_port *up = to_uart_omap_port(port);
863 unsigned char cval = 0;
864 unsigned long flags = 0;
865 unsigned int baud, quot;
866
867 switch (termios->c_cflag & CSIZE) {
868 case CS5:
869 cval = UART_LCR_WLEN5;
870 break;
871 case CS6:
872 cval = UART_LCR_WLEN6;
873 break;
874 case CS7:
875 cval = UART_LCR_WLEN7;
876 break;
877 default:
878 case CS8:
879 cval = UART_LCR_WLEN8;
880 break;
881 }
882
883 if (termios->c_cflag & CSTOPB)
884 cval |= UART_LCR_STOP;
885 if (termios->c_cflag & PARENB)
886 cval |= UART_LCR_PARITY;
887 if (!(termios->c_cflag & PARODD))
888 cval |= UART_LCR_EPAR;
889 if (termios->c_cflag & CMSPAR)
890 cval |= UART_LCR_SPAR;
891
892 /*
893 * Ask the core to calculate the divisor for us.
894 */
895
896 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
897 quot = serial_omap_get_divisor(port, baud);
898
899 /* calculate wakeup latency constraint */
900 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
901 up->latency = up->calc_latency;
902 schedule_work(&up->qos_work);
903
904 up->dll = quot & 0xff;
905 up->dlh = quot >> 8;
906 up->mdr1 = UART_OMAP_MDR1_DISABLE;
907
908 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
909 UART_FCR_ENABLE_FIFO;
910
911 /*
912 * Ok, we're now changing the port state. Do it with
913 * interrupts disabled.
914 */
915 pm_runtime_get_sync(up->dev);
916 spin_lock_irqsave(&up->port.lock, flags);
917
918 /*
919 * Update the per-port timeout.
920 */
921 uart_update_timeout(port, termios->c_cflag, baud);
922
923 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
924 if (termios->c_iflag & INPCK)
925 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
926 if (termios->c_iflag & (BRKINT | PARMRK))
927 up->port.read_status_mask |= UART_LSR_BI;
928
929 /*
930 * Characters to ignore
931 */
932 up->port.ignore_status_mask = 0;
933 if (termios->c_iflag & IGNPAR)
934 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
935 if (termios->c_iflag & IGNBRK) {
936 up->port.ignore_status_mask |= UART_LSR_BI;
937 /*
938 * If we're ignoring parity and break indicators,
939 * ignore overruns too (for real raw support).
940 */
941 if (termios->c_iflag & IGNPAR)
942 up->port.ignore_status_mask |= UART_LSR_OE;
943 }
944
945 /*
946 * ignore all characters if CREAD is not set
947 */
948 if ((termios->c_cflag & CREAD) == 0)
949 up->port.ignore_status_mask |= UART_LSR_DR;
950
951 /*
952 * Modem status interrupts
953 */
954 up->ier &= ~UART_IER_MSI;
955 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
956 up->ier |= UART_IER_MSI;
957 serial_out(up, UART_IER, up->ier);
958 serial_out(up, UART_LCR, cval); /* reset DLAB */
959 up->lcr = cval;
960 up->scr = 0;
961
962 /* FIFOs and DMA Settings */
963
964 /* FCR can be changed only when the
965 * baud clock is not running
966 * DLL_REG and DLH_REG set to 0.
967 */
968 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
969 serial_out(up, UART_DLL, 0);
970 serial_out(up, UART_DLM, 0);
971 serial_out(up, UART_LCR, 0);
972
973 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
974
975 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
976 up->efr &= ~UART_EFR_SCD;
977 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
978
979 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
980 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
981 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
982 /* FIFO ENABLE, DMA MODE */
983
984 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
985 /*
986 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
987 * sets Enables the granularity of 1 for TRIGGER RX
988 * level. Along with setting RX FIFO trigger level
989 * to 1 (as noted below, 16 characters) and TLR[3:0]
990 * to zero this will result RX FIFO threshold level
991 * to 1 character, instead of 16 as noted in comment
992 * below.
993 */
994
995 /* Set receive FIFO threshold to 16 characters and
996 * transmit FIFO threshold to 32 spaces
997 */
998 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
999 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
1000 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
1001 UART_FCR_ENABLE_FIFO;
1002
1003 serial_out(up, UART_FCR, up->fcr);
1004 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1005
1006 serial_out(up, UART_OMAP_SCR, up->scr);
1007
1008 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1009 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1010 serial_out(up, UART_MCR, up->mcr);
1011 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1012 serial_out(up, UART_EFR, up->efr);
1013 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1014
1015 /* Protocol, Baud Rate, and Interrupt Settings */
1016
1017 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1018 serial_omap_mdr1_errataset(up, up->mdr1);
1019 else
1020 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1021
1022 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1023 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1024
1025 serial_out(up, UART_LCR, 0);
1026 serial_out(up, UART_IER, 0);
1027 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1028
1029 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1030 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1031
1032 serial_out(up, UART_LCR, 0);
1033 serial_out(up, UART_IER, up->ier);
1034 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1035
1036 serial_out(up, UART_EFR, up->efr);
1037 serial_out(up, UART_LCR, cval);
1038
1039 if (!serial_omap_baud_is_mode16(port, baud))
1040 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1041 else
1042 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1043
1044 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1045 serial_omap_mdr1_errataset(up, up->mdr1);
1046 else
1047 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1048
1049 /* Configure flow control */
1050 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1051
1052 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1053 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1054 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1055
1056 /* Enable access to TCR/TLR */
1057 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1058 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1059 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1060
1061 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1062
1063 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1064 /* Enable AUTORTS and AUTOCTS */
1065 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1066
1067 /* Ensure MCR RTS is asserted */
1068 up->mcr |= UART_MCR_RTS;
1069 } else {
1070 /* Disable AUTORTS and AUTOCTS */
1071 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1072 }
1073
1074 if (up->port.flags & UPF_SOFT_FLOW) {
1075 /* clear SW control mode bits */
1076 up->efr &= OMAP_UART_SW_CLR;
1077
1078 /*
1079 * IXON Flag:
1080 * Enable XON/XOFF flow control on input.
1081 * Receiver compares XON1, XOFF1.
1082 */
1083 if (termios->c_iflag & IXON)
1084 up->efr |= OMAP_UART_SW_RX;
1085
1086 /*
1087 * IXOFF Flag:
1088 * Enable XON/XOFF flow control on output.
1089 * Transmit XON1, XOFF1
1090 */
1091 if (termios->c_iflag & IXOFF)
1092 up->efr |= OMAP_UART_SW_TX;
1093
1094 /*
1095 * IXANY Flag:
1096 * Enable any character to restart output.
1097 * Operation resumes after receiving any
1098 * character after recognition of the XOFF character
1099 */
1100 if (termios->c_iflag & IXANY)
1101 up->mcr |= UART_MCR_XONANY;
1102 else
1103 up->mcr &= ~UART_MCR_XONANY;
1104 }
1105 serial_out(up, UART_MCR, up->mcr);
1106 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1107 serial_out(up, UART_EFR, up->efr);
1108 serial_out(up, UART_LCR, up->lcr);
1109
1110 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1111
1112 spin_unlock_irqrestore(&up->port.lock, flags);
1113 pm_runtime_mark_last_busy(up->dev);
1114 pm_runtime_put_autosuspend(up->dev);
1115 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1116}
1117
1118static void
1119serial_omap_pm(struct uart_port *port, unsigned int state,
1120 unsigned int oldstate)
1121{
1122 struct uart_omap_port *up = to_uart_omap_port(port);
1123 unsigned char efr;
1124
1125 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1126
1127 pm_runtime_get_sync(up->dev);
1128 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1129 efr = serial_in(up, UART_EFR);
1130 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1131 serial_out(up, UART_LCR, 0);
1132
1133 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1134 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1135 serial_out(up, UART_EFR, efr);
1136 serial_out(up, UART_LCR, 0);
1137
1138 if (!device_may_wakeup(up->dev)) {
1139 if (!state)
1140 pm_runtime_forbid(up->dev);
1141 else
1142 pm_runtime_allow(up->dev);
1143 }
1144
1145 pm_runtime_mark_last_busy(up->dev);
1146 pm_runtime_put_autosuspend(up->dev);
1147}
1148
1149static void serial_omap_release_port(struct uart_port *port)
1150{
1151 dev_dbg(port->dev, "serial_omap_release_port+\n");
1152}
1153
1154static int serial_omap_request_port(struct uart_port *port)
1155{
1156 dev_dbg(port->dev, "serial_omap_request_port+\n");
1157 return 0;
1158}
1159
1160static void serial_omap_config_port(struct uart_port *port, int flags)
1161{
1162 struct uart_omap_port *up = to_uart_omap_port(port);
1163
1164 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1165 up->port.line);
1166 up->port.type = PORT_OMAP;
1167 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1168}
1169
1170static int
1171serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1172{
1173 /* we don't want the core code to modify any port params */
1174 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1175 return -EINVAL;
1176}
1177
1178static const char *
1179serial_omap_type(struct uart_port *port)
1180{
1181 struct uart_omap_port *up = to_uart_omap_port(port);
1182
1183 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1184 return up->name;
1185}
1186
1187#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1188
1189static inline void wait_for_xmitr(struct uart_omap_port *up)
1190{
1191 unsigned int status, tmout = 10000;
1192
1193 /* Wait up to 10ms for the character(s) to be sent. */
1194 do {
1195 status = serial_in(up, UART_LSR);
1196
1197 if (status & UART_LSR_BI)
1198 up->lsr_break_flag = UART_LSR_BI;
1199
1200 if (--tmout == 0)
1201 break;
1202 udelay(1);
1203 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1204
1205 /* Wait up to 1s for flow control if necessary */
1206 if (up->port.flags & UPF_CONS_FLOW) {
1207 tmout = 1000000;
1208 for (tmout = 1000000; tmout; tmout--) {
1209 unsigned int msr = serial_in(up, UART_MSR);
1210
1211 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1212 if (msr & UART_MSR_CTS)
1213 break;
1214
1215 udelay(1);
1216 }
1217 }
1218}
1219
1220#ifdef CONFIG_CONSOLE_POLL
1221
1222static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1223{
1224 struct uart_omap_port *up = to_uart_omap_port(port);
1225
1226 pm_runtime_get_sync(up->dev);
1227 wait_for_xmitr(up);
1228 serial_out(up, UART_TX, ch);
1229 pm_runtime_mark_last_busy(up->dev);
1230 pm_runtime_put_autosuspend(up->dev);
1231}
1232
1233static int serial_omap_poll_get_char(struct uart_port *port)
1234{
1235 struct uart_omap_port *up = to_uart_omap_port(port);
1236 unsigned int status;
1237
1238 pm_runtime_get_sync(up->dev);
1239 status = serial_in(up, UART_LSR);
1240 if (!(status & UART_LSR_DR)) {
1241 status = NO_POLL_CHAR;
1242 goto out;
1243 }
1244
1245 status = serial_in(up, UART_RX);
1246
1247out:
1248 pm_runtime_mark_last_busy(up->dev);
1249 pm_runtime_put_autosuspend(up->dev);
1250
1251 return status;
1252}
1253
1254#endif /* CONFIG_CONSOLE_POLL */
1255
1256#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1257
1258static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1259
1260static struct uart_driver serial_omap_reg;
1261
1262static void serial_omap_console_putchar(struct uart_port *port, int ch)
1263{
1264 struct uart_omap_port *up = to_uart_omap_port(port);
1265
1266 wait_for_xmitr(up);
1267 serial_out(up, UART_TX, ch);
1268}
1269
1270static void
1271serial_omap_console_write(struct console *co, const char *s,
1272 unsigned int count)
1273{
1274 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1275 unsigned long flags;
1276 unsigned int ier;
1277 int locked = 1;
1278
1279 pm_runtime_get_sync(up->dev);
1280
1281 local_irq_save(flags);
1282 if (up->port.sysrq)
1283 locked = 0;
1284 else if (oops_in_progress)
1285 locked = spin_trylock(&up->port.lock);
1286 else
1287 spin_lock(&up->port.lock);
1288
1289 /*
1290 * First save the IER then disable the interrupts
1291 */
1292 ier = serial_in(up, UART_IER);
1293 serial_out(up, UART_IER, 0);
1294
1295 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1296
1297 /*
1298 * Finally, wait for transmitter to become empty
1299 * and restore the IER
1300 */
1301 wait_for_xmitr(up);
1302 serial_out(up, UART_IER, ier);
1303 /*
1304 * The receive handling will happen properly because the
1305 * receive ready bit will still be set; it is not cleared
1306 * on read. However, modem control will not, we must
1307 * call it if we have saved something in the saved flags
1308 * while processing with interrupts off.
1309 */
1310 if (up->msr_saved_flags)
1311 check_modem_status(up);
1312
1313 pm_runtime_mark_last_busy(up->dev);
1314 pm_runtime_put_autosuspend(up->dev);
1315 if (locked)
1316 spin_unlock(&up->port.lock);
1317 local_irq_restore(flags);
1318}
1319
1320static int __init
1321serial_omap_console_setup(struct console *co, char *options)
1322{
1323 struct uart_omap_port *up;
1324 int baud = 115200;
1325 int bits = 8;
1326 int parity = 'n';
1327 int flow = 'n';
1328
1329 if (serial_omap_console_ports[co->index] == NULL)
1330 return -ENODEV;
1331 up = serial_omap_console_ports[co->index];
1332
1333 if (options)
1334 uart_parse_options(options, &baud, &parity, &bits, &flow);
1335
1336 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1337}
1338
1339static struct console serial_omap_console = {
1340 .name = OMAP_SERIAL_NAME,
1341 .write = serial_omap_console_write,
1342 .device = uart_console_device,
1343 .setup = serial_omap_console_setup,
1344 .flags = CON_PRINTBUFFER,
1345 .index = -1,
1346 .data = &serial_omap_reg,
1347};
1348
1349static void serial_omap_add_console_port(struct uart_omap_port *up)
1350{
1351 serial_omap_console_ports[up->port.line] = up;
1352}
1353
1354#define OMAP_CONSOLE (&serial_omap_console)
1355
1356#else
1357
1358#define OMAP_CONSOLE NULL
1359
1360static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1361{}
1362
1363#endif
1364
1365/* Enable or disable the rs485 support */
1366static void
1367serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1368{
1369 struct uart_omap_port *up = to_uart_omap_port(port);
1370 unsigned long flags;
1371 unsigned int mode;
1372 int val;
1373
1374 pm_runtime_get_sync(up->dev);
1375 spin_lock_irqsave(&up->port.lock, flags);
1376
1377 /* Disable interrupts from this port */
1378 mode = up->ier;
1379 up->ier = 0;
1380 serial_out(up, UART_IER, 0);
1381
1382 /* store new config */
1383 up->rs485 = *rs485conf;
1384
1385 /*
1386 * Just as a precaution, only allow rs485
1387 * to be enabled if the gpio pin is valid
1388 */
1389 if (gpio_is_valid(up->rts_gpio)) {
1390 /* enable / disable rts */
1391 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1392 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1393 val = (up->rs485.flags & val) ? 1 : 0;
1394 gpio_set_value(up->rts_gpio, val);
1395 } else
1396 up->rs485.flags &= ~SER_RS485_ENABLED;
1397
1398 /* Enable interrupts */
1399 up->ier = mode;
1400 serial_out(up, UART_IER, up->ier);
1401
1402 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1403 * TX FIFO is below the trigger level.
1404 */
1405 if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1406 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1407 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1408 serial_out(up, UART_OMAP_SCR, up->scr);
1409 }
1410
1411 spin_unlock_irqrestore(&up->port.lock, flags);
1412 pm_runtime_mark_last_busy(up->dev);
1413 pm_runtime_put_autosuspend(up->dev);
1414}
1415
1416static int
1417serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1418{
1419 struct serial_rs485 rs485conf;
1420
1421 switch (cmd) {
1422 case TIOCSRS485:
1423 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1424 sizeof(rs485conf)))
1425 return -EFAULT;
1426
1427 serial_omap_config_rs485(port, &rs485conf);
1428 break;
1429
1430 case TIOCGRS485:
1431 if (copy_to_user((struct serial_rs485 *) arg,
1432 &(to_uart_omap_port(port)->rs485),
1433 sizeof(rs485conf)))
1434 return -EFAULT;
1435 break;
1436
1437 default:
1438 return -ENOIOCTLCMD;
1439 }
1440 return 0;
1441}
1442
1443
1444static struct uart_ops serial_omap_pops = {
1445 .tx_empty = serial_omap_tx_empty,
1446 .set_mctrl = serial_omap_set_mctrl,
1447 .get_mctrl = serial_omap_get_mctrl,
1448 .stop_tx = serial_omap_stop_tx,
1449 .start_tx = serial_omap_start_tx,
1450 .throttle = serial_omap_throttle,
1451 .unthrottle = serial_omap_unthrottle,
1452 .stop_rx = serial_omap_stop_rx,
1453 .enable_ms = serial_omap_enable_ms,
1454 .break_ctl = serial_omap_break_ctl,
1455 .startup = serial_omap_startup,
1456 .shutdown = serial_omap_shutdown,
1457 .set_termios = serial_omap_set_termios,
1458 .pm = serial_omap_pm,
1459 .type = serial_omap_type,
1460 .release_port = serial_omap_release_port,
1461 .request_port = serial_omap_request_port,
1462 .config_port = serial_omap_config_port,
1463 .verify_port = serial_omap_verify_port,
1464 .ioctl = serial_omap_ioctl,
1465#ifdef CONFIG_CONSOLE_POLL
1466 .poll_put_char = serial_omap_poll_put_char,
1467 .poll_get_char = serial_omap_poll_get_char,
1468#endif
1469};
1470
1471static struct uart_driver serial_omap_reg = {
1472 .owner = THIS_MODULE,
1473 .driver_name = "OMAP-SERIAL",
1474 .dev_name = OMAP_SERIAL_NAME,
1475 .nr = OMAP_MAX_HSUART_PORTS,
1476 .cons = OMAP_CONSOLE,
1477};
1478
1479#ifdef CONFIG_PM_SLEEP
1480static int serial_omap_prepare(struct device *dev)
1481{
1482 struct uart_omap_port *up = dev_get_drvdata(dev);
1483
1484 up->is_suspending = true;
1485
1486 return 0;
1487}
1488
1489static void serial_omap_complete(struct device *dev)
1490{
1491 struct uart_omap_port *up = dev_get_drvdata(dev);
1492
1493 up->is_suspending = false;
1494}
1495
1496static int serial_omap_suspend(struct device *dev)
1497{
1498 struct uart_omap_port *up = dev_get_drvdata(dev);
1499
1500 uart_suspend_port(&serial_omap_reg, &up->port);
1501 flush_work(&up->qos_work);
1502
1503 if (device_may_wakeup(dev))
1504 serial_omap_enable_wakeup(up, true);
1505 else
1506 serial_omap_enable_wakeup(up, false);
1507
1508 return 0;
1509}
1510
1511static int serial_omap_resume(struct device *dev)
1512{
1513 struct uart_omap_port *up = dev_get_drvdata(dev);
1514
1515 if (device_may_wakeup(dev))
1516 serial_omap_enable_wakeup(up, false);
1517
1518 uart_resume_port(&serial_omap_reg, &up->port);
1519
1520 return 0;
1521}
1522#else
1523#define serial_omap_prepare NULL
1524#define serial_omap_complete NULL
1525#endif /* CONFIG_PM_SLEEP */
1526
1527static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1528{
1529 u32 mvr, scheme;
1530 u16 revision, major, minor;
1531
1532 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1533
1534 /* Check revision register scheme */
1535 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1536
1537 switch (scheme) {
1538 case 0: /* Legacy Scheme: OMAP2/3 */
1539 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1540 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1541 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1542 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1543 break;
1544 case 1:
1545 /* New Scheme: OMAP4+ */
1546 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1547 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1548 OMAP_UART_MVR_MAJ_SHIFT;
1549 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1550 break;
1551 default:
1552 dev_warn(up->dev,
1553 "Unknown %s revision, defaulting to highest\n",
1554 up->name);
1555 /* highest possible revision */
1556 major = 0xff;
1557 minor = 0xff;
1558 }
1559
1560 /* normalize revision for the driver */
1561 revision = UART_BUILD_REVISION(major, minor);
1562
1563 switch (revision) {
1564 case OMAP_UART_REV_46:
1565 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1566 UART_ERRATA_i291_DMA_FORCEIDLE);
1567 break;
1568 case OMAP_UART_REV_52:
1569 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1570 UART_ERRATA_i291_DMA_FORCEIDLE);
1571 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1572 break;
1573 case OMAP_UART_REV_63:
1574 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1575 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1576 break;
1577 default:
1578 break;
1579 }
1580}
1581
1582static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1583{
1584 struct omap_uart_port_info *omap_up_info;
1585
1586 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1587 if (!omap_up_info)
1588 return NULL; /* out of memory */
1589
1590 of_property_read_u32(dev->of_node, "clock-frequency",
1591 &omap_up_info->uartclk);
1592 return omap_up_info;
1593}
1594
1595static int serial_omap_probe_rs485(struct uart_omap_port *up,
1596 struct device_node *np)
1597{
1598 struct serial_rs485 *rs485conf = &up->rs485;
1599 u32 rs485_delay[2];
1600 enum of_gpio_flags flags;
1601 int ret;
1602
1603 rs485conf->flags = 0;
1604 up->rts_gpio = -EINVAL;
1605
1606 if (!np)
1607 return 0;
1608
1609 if (of_property_read_bool(np, "rs485-rts-active-high"))
1610 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1611 else
1612 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1613
1614 /* check for tx enable gpio */
1615 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1616 if (gpio_is_valid(up->rts_gpio)) {
1617 ret = gpio_request(up->rts_gpio, "omap-serial");
1618 if (ret < 0)
1619 return ret;
1620 ret = gpio_direction_output(up->rts_gpio,
1621 flags & SER_RS485_RTS_AFTER_SEND);
1622 if (ret < 0)
1623 return ret;
1624 } else if (up->rts_gpio == -EPROBE_DEFER) {
1625 return -EPROBE_DEFER;
1626 } else {
1627 up->rts_gpio = -EINVAL;
1628 }
1629
1630 if (of_property_read_u32_array(np, "rs485-rts-delay",
1631 rs485_delay, 2) == 0) {
1632 rs485conf->delay_rts_before_send = rs485_delay[0];
1633 rs485conf->delay_rts_after_send = rs485_delay[1];
1634 }
1635
1636 if (of_property_read_bool(np, "rs485-rx-during-tx"))
1637 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1638
1639 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1640 rs485conf->flags |= SER_RS485_ENABLED;
1641
1642 return 0;
1643}
1644
1645static int serial_omap_probe(struct platform_device *pdev)
1646{
1647 struct uart_omap_port *up;
1648 struct resource *mem, *irq;
1649 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1650 int ret, uartirq = 0, wakeirq = 0;
1651
1652 /* The optional wakeirq may be specified in the board dts file */
1653 if (pdev->dev.of_node) {
1654 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1655 if (!uartirq)
1656 return -EPROBE_DEFER;
1657 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1658 omap_up_info = of_get_uart_port_info(&pdev->dev);
1659 pdev->dev.platform_data = omap_up_info;
1660 } else {
1661 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1662 if (!irq) {
1663 dev_err(&pdev->dev, "no irq resource?\n");
1664 return -ENODEV;
1665 }
1666 uartirq = irq->start;
1667 }
1668
1669 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 if (!mem) {
1671 dev_err(&pdev->dev, "no mem resource?\n");
1672 return -ENODEV;
1673 }
1674
1675 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1676 pdev->dev.driver->name)) {
1677 dev_err(&pdev->dev, "memory region already claimed\n");
1678 return -EBUSY;
1679 }
1680
1681 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1682 omap_up_info->DTR_present) {
1683 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1684 if (ret < 0)
1685 return ret;
1686 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1687 omap_up_info->DTR_inverted);
1688 if (ret < 0)
1689 return ret;
1690 }
1691
1692 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1693 if (!up)
1694 return -ENOMEM;
1695
1696 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1697 omap_up_info->DTR_present) {
1698 up->DTR_gpio = omap_up_info->DTR_gpio;
1699 up->DTR_inverted = omap_up_info->DTR_inverted;
1700 } else
1701 up->DTR_gpio = -EINVAL;
1702 up->DTR_active = 0;
1703
1704 up->dev = &pdev->dev;
1705 up->port.dev = &pdev->dev;
1706 up->port.type = PORT_OMAP;
1707 up->port.iotype = UPIO_MEM;
1708 up->port.irq = uartirq;
1709 up->wakeirq = wakeirq;
1710 if (!up->wakeirq)
1711 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1712 up->port.line);
1713
1714 up->port.regshift = 2;
1715 up->port.fifosize = 64;
1716 up->port.ops = &serial_omap_pops;
1717
1718 if (pdev->dev.of_node)
1719 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1720 else
1721 up->port.line = pdev->id;
1722
1723 if (up->port.line < 0) {
1724 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1725 up->port.line);
1726 ret = -ENODEV;
1727 goto err_port_line;
1728 }
1729
1730 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1731 if (ret < 0)
1732 goto err_rs485;
1733
1734 sprintf(up->name, "OMAP UART%d", up->port.line);
1735 up->port.mapbase = mem->start;
1736 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1737 resource_size(mem));
1738 if (!up->port.membase) {
1739 dev_err(&pdev->dev, "can't ioremap UART\n");
1740 ret = -ENOMEM;
1741 goto err_ioremap;
1742 }
1743
1744 up->port.flags = omap_up_info->flags;
1745 up->port.uartclk = omap_up_info->uartclk;
1746 if (!up->port.uartclk) {
1747 up->port.uartclk = DEFAULT_CLK_SPEED;
1748 dev_warn(&pdev->dev,
1749 "No clock speed specified: using default: %d\n",
1750 DEFAULT_CLK_SPEED);
1751 }
1752
1753 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1754 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1755 pm_qos_add_request(&up->pm_qos_request,
1756 PM_QOS_CPU_DMA_LATENCY, up->latency);
1757 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1758 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1759
1760 platform_set_drvdata(pdev, up);
1761 if (omap_up_info->autosuspend_timeout == 0)
1762 omap_up_info->autosuspend_timeout = -1;
1763 device_init_wakeup(up->dev, true);
1764 pm_runtime_use_autosuspend(&pdev->dev);
1765 pm_runtime_set_autosuspend_delay(&pdev->dev,
1766 omap_up_info->autosuspend_timeout);
1767
1768 pm_runtime_irq_safe(&pdev->dev);
1769 pm_runtime_enable(&pdev->dev);
1770
1771 pm_runtime_get_sync(&pdev->dev);
1772
1773 omap_serial_fill_features_erratas(up);
1774
1775 ui[up->port.line] = up;
1776 serial_omap_add_console_port(up);
1777
1778 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1779 if (ret != 0)
1780 goto err_add_port;
1781
1782 pm_runtime_mark_last_busy(up->dev);
1783 pm_runtime_put_autosuspend(up->dev);
1784 return 0;
1785
1786err_add_port:
1787 pm_runtime_put(&pdev->dev);
1788 pm_runtime_disable(&pdev->dev);
1789err_ioremap:
1790err_rs485:
1791err_port_line:
1792 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1793 pdev->id, __func__, ret);
1794 return ret;
1795}
1796
1797static int serial_omap_remove(struct platform_device *dev)
1798{
1799 struct uart_omap_port *up = platform_get_drvdata(dev);
1800
1801 pm_runtime_put_sync(up->dev);
1802 pm_runtime_disable(up->dev);
1803 uart_remove_one_port(&serial_omap_reg, &up->port);
1804 pm_qos_remove_request(&up->pm_qos_request);
1805 device_init_wakeup(&dev->dev, false);
1806
1807 return 0;
1808}
1809
1810/*
1811 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1812 * The access to uart register after MDR1 Access
1813 * causes UART to corrupt data.
1814 *
1815 * Need a delay =
1816 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1817 * give 10 times as much
1818 */
1819static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1820{
1821 u8 timeout = 255;
1822
1823 serial_out(up, UART_OMAP_MDR1, mdr1);
1824 udelay(2);
1825 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1826 UART_FCR_CLEAR_RCVR);
1827 /*
1828 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1829 * TX_FIFO_E bit is 1.
1830 */
1831 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1832 (UART_LSR_THRE | UART_LSR_DR))) {
1833 timeout--;
1834 if (!timeout) {
1835 /* Should *never* happen. we warn and carry on */
1836 dev_crit(up->dev, "Errata i202: timedout %x\n",
1837 serial_in(up, UART_LSR));
1838 break;
1839 }
1840 udelay(1);
1841 }
1842}
1843
1844#ifdef CONFIG_PM_RUNTIME
1845static void serial_omap_restore_context(struct uart_omap_port *up)
1846{
1847 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1848 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1849 else
1850 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1851
1852 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1853 serial_out(up, UART_EFR, UART_EFR_ECB);
1854 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1855 serial_out(up, UART_IER, 0x0);
1856 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1857 serial_out(up, UART_DLL, up->dll);
1858 serial_out(up, UART_DLM, up->dlh);
1859 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1860 serial_out(up, UART_IER, up->ier);
1861 serial_out(up, UART_FCR, up->fcr);
1862 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1863 serial_out(up, UART_MCR, up->mcr);
1864 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1865 serial_out(up, UART_OMAP_SCR, up->scr);
1866 serial_out(up, UART_EFR, up->efr);
1867 serial_out(up, UART_LCR, up->lcr);
1868 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1869 serial_omap_mdr1_errataset(up, up->mdr1);
1870 else
1871 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1872 serial_out(up, UART_OMAP_WER, up->wer);
1873}
1874
1875static int serial_omap_runtime_suspend(struct device *dev)
1876{
1877 struct uart_omap_port *up = dev_get_drvdata(dev);
1878
1879 if (!up)
1880 return -EINVAL;
1881
1882 /*
1883 * When using 'no_console_suspend', the console UART must not be
1884 * suspended. Since driver suspend is managed by runtime suspend,
1885 * preventing runtime suspend (by returning error) will keep device
1886 * active during suspend.
1887 */
1888 if (up->is_suspending && !console_suspend_enabled &&
1889 uart_console(&up->port))
1890 return -EBUSY;
1891
1892 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1893
1894 serial_omap_enable_wakeup(up, true);
1895
1896 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1897 schedule_work(&up->qos_work);
1898
1899 return 0;
1900}
1901
1902static int serial_omap_runtime_resume(struct device *dev)
1903{
1904 struct uart_omap_port *up = dev_get_drvdata(dev);
1905
1906 int loss_cnt = serial_omap_get_context_loss_count(up);
1907
1908 serial_omap_enable_wakeup(up, false);
1909
1910 if (loss_cnt < 0) {
1911 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1912 loss_cnt);
1913 serial_omap_restore_context(up);
1914 } else if (up->context_loss_cnt != loss_cnt) {
1915 serial_omap_restore_context(up);
1916 }
1917 up->latency = up->calc_latency;
1918 schedule_work(&up->qos_work);
1919
1920 return 0;
1921}
1922#endif
1923
1924static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1925 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1926 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1927 serial_omap_runtime_resume, NULL)
1928 .prepare = serial_omap_prepare,
1929 .complete = serial_omap_complete,
1930};
1931
1932#if defined(CONFIG_OF)
1933static const struct of_device_id omap_serial_of_match[] = {
1934 { .compatible = "ti,omap2-uart" },
1935 { .compatible = "ti,omap3-uart" },
1936 { .compatible = "ti,omap4-uart" },
1937 {},
1938};
1939MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1940#endif
1941
1942static struct platform_driver serial_omap_driver = {
1943 .probe = serial_omap_probe,
1944 .remove = serial_omap_remove,
1945 .driver = {
1946 .name = DRIVER_NAME,
1947 .pm = &serial_omap_dev_pm_ops,
1948 .of_match_table = of_match_ptr(omap_serial_of_match),
1949 },
1950};
1951
1952static int __init serial_omap_init(void)
1953{
1954 int ret;
1955
1956 ret = uart_register_driver(&serial_omap_reg);
1957 if (ret != 0)
1958 return ret;
1959 ret = platform_driver_register(&serial_omap_driver);
1960 if (ret != 0)
1961 uart_unregister_driver(&serial_omap_reg);
1962 return ret;
1963}
1964
1965static void __exit serial_omap_exit(void)
1966{
1967 platform_driver_unregister(&serial_omap_driver);
1968 uart_unregister_driver(&serial_omap_reg);
1969}
1970
1971module_init(serial_omap_init);
1972module_exit(serial_omap_exit);
1973
1974MODULE_DESCRIPTION("OMAP High Speed UART driver");
1975MODULE_LICENSE("GPL");
1976MODULE_AUTHOR("Texas Instruments Inc");