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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
12 * bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include "exynos4.dtsi"
20#include "exynos4-cpu-thermal.dtsi"
21
22/ {
23 compatible = "samsung,exynos4210", "samsung,exynos4";
24
25 aliases {
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu0: cpu@900 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0x900>;
39 clocks = <&clock CLK_ARM_CLK>;
40 clock-names = "cpu";
41 clock-latency = <160000>;
42
43 operating-points = <
44 1200000 1250000
45 1000000 1150000
46 800000 1075000
47 500000 975000
48 400000 975000
49 200000 950000
50 >;
51 #cooling-cells = <2>; /* min followed by max */
52 };
53
54 cpu1: cpu@901 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a9";
57 reg = <0x901>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <160000>;
61
62 operating-points = <
63 1200000 1250000
64 1000000 1150000
65 800000 1075000
66 500000 975000
67 400000 975000
68 200000 950000
69 >;
70 #cooling-cells = <2>; /* min followed by max */
71 };
72 };
73
74 soc: soc {
75 sysram: sram@2020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x20000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x02020000 0x20000>;
81
82 smp-sram@0 {
83 compatible = "samsung,exynos4210-sysram";
84 reg = <0x0 0x1000>;
85 };
86
87 smp-sram@1f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x1f000 0x1000>;
90 };
91 };
92
93 pd_lcd1: power-domain@10023ca0 {
94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10023CA0 0x20>;
96 #power-domain-cells = <0>;
97 label = "LCD1";
98 };
99
100 l2c: cache-controller@10502000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x10502000 0x1000>;
103 cache-unified;
104 cache-level = <2>;
105 prefetch-data = <1>;
106 prefetch-instr = <1>;
107 arm,tag-latency = <2 2 1>;
108 arm,data-latency = <2 2 1>;
109 };
110
111 mct: timer@10050000 {
112 compatible = "samsung,exynos4210-mct";
113 reg = <0x10050000 0x800>;
114 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
115 clock-names = "fin_pll", "mct";
116 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
117 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
118 <&combiner 12 6>,
119 <&combiner 12 7>,
120 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
121 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
122 };
123
124 watchdog: watchdog@10060000 {
125 compatible = "samsung,s3c6410-wdt";
126 reg = <0x10060000 0x100>;
127 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&clock CLK_WDT>;
129 clock-names = "watchdog";
130 };
131
132 clock: clock-controller@10030000 {
133 compatible = "samsung,exynos4210-clock";
134 reg = <0x10030000 0x20000>;
135 #clock-cells = <1>;
136 };
137
138 pinctrl_0: pinctrl@11400000 {
139 compatible = "samsung,exynos4210-pinctrl";
140 reg = <0x11400000 0x1000>;
141 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
142 };
143
144 pinctrl_1: pinctrl@11000000 {
145 compatible = "samsung,exynos4210-pinctrl";
146 reg = <0x11000000 0x1000>;
147 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
148
149 wakup_eint: wakeup-interrupt-controller {
150 compatible = "samsung,exynos4210-wakeup-eint";
151 interrupt-parent = <&gic>;
152 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
153 };
154 };
155
156 pinctrl_2: pinctrl@3860000 {
157 compatible = "samsung,exynos4210-pinctrl";
158 reg = <0x03860000 0x1000>;
159 };
160
161 g2d: g2d@12800000 {
162 compatible = "samsung,s5pv210-g2d";
163 reg = <0x12800000 0x1000>;
164 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
166 clock-names = "sclk_fimg2d", "fimg2d";
167 power-domains = <&pd_lcd0>;
168 iommus = <&sysmmu_g2d>;
169 };
170
171 ppmu_acp: ppmu@10ae0000 {
172 compatible = "samsung,exynos-ppmu";
173 reg = <0x10ae0000 0x2000>;
174 status = "disabled";
175 };
176
177 ppmu_lcd1: ppmu@12240000 {
178 compatible = "samsung,exynos-ppmu";
179 reg = <0x12240000 0x2000>;
180 clocks = <&clock CLK_PPMULCD1>;
181 clock-names = "ppmu";
182 status = "disabled";
183 };
184
185 sysmmu_g2d: sysmmu@12a20000 {
186 compatible = "samsung,exynos-sysmmu";
187 reg = <0x12A20000 0x1000>;
188 interrupt-parent = <&combiner>;
189 interrupts = <4 7>;
190 clock-names = "sysmmu", "master";
191 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
192 power-domains = <&pd_lcd0>;
193 #iommu-cells = <0>;
194 };
195
196 sysmmu_fimd1: sysmmu@12220000 {
197 compatible = "samsung,exynos-sysmmu";
198 interrupt-parent = <&combiner>;
199 reg = <0x12220000 0x1000>;
200 interrupts = <5 3>;
201 clock-names = "sysmmu", "master";
202 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
203 power-domains = <&pd_lcd1>;
204 #iommu-cells = <0>;
205 };
206
207 bus_dmc: bus-dmc {
208 compatible = "samsung,exynos-bus";
209 clocks = <&clock CLK_DIV_DMC>;
210 clock-names = "bus";
211 operating-points-v2 = <&bus_dmc_opp_table>;
212 status = "disabled";
213 };
214
215 bus_acp: bus-acp {
216 compatible = "samsung,exynos-bus";
217 clocks = <&clock CLK_DIV_ACP>;
218 clock-names = "bus";
219 operating-points-v2 = <&bus_acp_opp_table>;
220 status = "disabled";
221 };
222
223 bus_peri: bus-peri {
224 compatible = "samsung,exynos-bus";
225 clocks = <&clock CLK_ACLK100>;
226 clock-names = "bus";
227 operating-points-v2 = <&bus_peri_opp_table>;
228 status = "disabled";
229 };
230
231 bus_fsys: bus-fsys {
232 compatible = "samsung,exynos-bus";
233 clocks = <&clock CLK_ACLK133>;
234 clock-names = "bus";
235 operating-points-v2 = <&bus_fsys_opp_table>;
236 status = "disabled";
237 };
238
239 bus_display: bus-display {
240 compatible = "samsung,exynos-bus";
241 clocks = <&clock CLK_ACLK160>;
242 clock-names = "bus";
243 operating-points-v2 = <&bus_display_opp_table>;
244 status = "disabled";
245 };
246
247 bus_lcd0: bus-lcd0 {
248 compatible = "samsung,exynos-bus";
249 clocks = <&clock CLK_ACLK200>;
250 clock-names = "bus";
251 operating-points-v2 = <&bus_leftbus_opp_table>;
252 status = "disabled";
253 };
254
255 bus_leftbus: bus-leftbus {
256 compatible = "samsung,exynos-bus";
257 clocks = <&clock CLK_DIV_GDL>;
258 clock-names = "bus";
259 operating-points-v2 = <&bus_leftbus_opp_table>;
260 status = "disabled";
261 };
262
263 bus_rightbus: bus-rightbus {
264 compatible = "samsung,exynos-bus";
265 clocks = <&clock CLK_DIV_GDR>;
266 clock-names = "bus";
267 operating-points-v2 = <&bus_leftbus_opp_table>;
268 status = "disabled";
269 };
270
271 bus_mfc: bus-mfc {
272 compatible = "samsung,exynos-bus";
273 clocks = <&clock CLK_SCLK_MFC>;
274 clock-names = "bus";
275 operating-points-v2 = <&bus_leftbus_opp_table>;
276 status = "disabled";
277 };
278
279 bus_dmc_opp_table: opp-table1 {
280 compatible = "operating-points-v2";
281 opp-shared;
282
283 opp-134000000 {
284 opp-hz = /bits/ 64 <134000000>;
285 opp-microvolt = <1025000>;
286 };
287 opp-267000000 {
288 opp-hz = /bits/ 64 <267000000>;
289 opp-microvolt = <1050000>;
290 };
291 opp-400000000 {
292 opp-hz = /bits/ 64 <400000000>;
293 opp-microvolt = <1150000>;
294 opp-suspend;
295 };
296 };
297
298 bus_acp_opp_table: opp-table2 {
299 compatible = "operating-points-v2";
300 opp-shared;
301
302 opp-134000000 {
303 opp-hz = /bits/ 64 <134000000>;
304 };
305 opp-160000000 {
306 opp-hz = /bits/ 64 <160000000>;
307 };
308 opp-200000000 {
309 opp-hz = /bits/ 64 <200000000>;
310 };
311 };
312
313 bus_peri_opp_table: opp-table3 {
314 compatible = "operating-points-v2";
315 opp-shared;
316
317 opp-5000000 {
318 opp-hz = /bits/ 64 <5000000>;
319 };
320 opp-100000000 {
321 opp-hz = /bits/ 64 <100000000>;
322 };
323 };
324
325 bus_fsys_opp_table: opp-table4 {
326 compatible = "operating-points-v2";
327 opp-shared;
328
329 opp-10000000 {
330 opp-hz = /bits/ 64 <10000000>;
331 };
332 opp-134000000 {
333 opp-hz = /bits/ 64 <134000000>;
334 };
335 };
336
337 bus_display_opp_table: opp-table5 {
338 compatible = "operating-points-v2";
339 opp-shared;
340
341 opp-100000000 {
342 opp-hz = /bits/ 64 <100000000>;
343 };
344 opp-134000000 {
345 opp-hz = /bits/ 64 <134000000>;
346 };
347 opp-160000000 {
348 opp-hz = /bits/ 64 <160000000>;
349 };
350 };
351
352 bus_leftbus_opp_table: opp-table6 {
353 compatible = "operating-points-v2";
354 opp-shared;
355
356 opp-100000000 {
357 opp-hz = /bits/ 64 <100000000>;
358 };
359 opp-160000000 {
360 opp-hz = /bits/ 64 <160000000>;
361 };
362 opp-200000000 {
363 opp-hz = /bits/ 64 <200000000>;
364 opp-suspend;
365 };
366 };
367 };
368};
369
370&cpu_alert0 {
371 temperature = <85000>; /* millicelsius */
372};
373
374&cpu_alert1 {
375 temperature = <100000>; /* millicelsius */
376};
377
378&cpu_alert2 {
379 temperature = <110000>; /* millicelsius */
380};
381
382&cpu_thermal {
383 polling-delay-passive = <0>;
384 polling-delay = <0>;
385 thermal-sensors = <&tmu 0>;
386};
387
388&gic {
389 cpu-offset = <0x8000>;
390};
391
392&camera {
393 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
394 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
395 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
396};
397
398&combiner {
399 samsung,combiner-nr = <16>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
416};
417
418&fimc_0 {
419 samsung,pix-limits = <4224 8192 1920 4224>;
420 samsung,mainscaler-ext;
421 samsung,cam-if;
422};
423
424&fimc_1 {
425 samsung,pix-limits = <4224 8192 1920 4224>;
426 samsung,mainscaler-ext;
427 samsung,cam-if;
428};
429
430&fimc_2 {
431 samsung,pix-limits = <4224 8192 1920 4224>;
432 samsung,mainscaler-ext;
433 samsung,lcd-wb;
434};
435
436&fimc_3 {
437 samsung,pix-limits = <1920 8192 1366 1920>;
438 samsung,rotators = <0>;
439 samsung,mainscaler-ext;
440 samsung,lcd-wb;
441};
442
443&gpu {
444 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-names = "gp",
455 "gpmmu",
456 "pp0",
457 "ppmmu0",
458 "pp1",
459 "ppmmu1",
460 "pp2",
461 "ppmmu2",
462 "pp3",
463 "ppmmu3";
464 operating-points-v2 = <&gpu_opp_table>;
465
466 gpu_opp_table: opp-table {
467 compatible = "operating-points-v2";
468
469 opp-160000000 {
470 opp-hz = /bits/ 64 <160000000>;
471 opp-microvolt = <950000>;
472 };
473 opp-267000000 {
474 opp-hz = /bits/ 64 <267000000>;
475 opp-microvolt = <1050000>;
476 };
477 };
478};
479
480&mdma1 {
481 power-domains = <&pd_lcd0>;
482};
483
484&mixer {
485 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
486 "sclk_mixer";
487 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
488 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
489 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
490};
491
492&pmu {
493 interrupts = <2 2>, <3 2>;
494 interrupt-affinity = <&cpu0>, <&cpu1>;
495 status = "okay";
496};
497
498&pmu_system_controller {
499 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
500 "clkout4", "clkout8", "clkout9";
501 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
502 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
503 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
504 #clock-cells = <1>;
505};
506
507&rotator {
508 power-domains = <&pd_lcd0>;
509};
510
511&sysmmu_rotator {
512 power-domains = <&pd_lcd0>;
513};
514
515&tmu {
516 compatible = "samsung,exynos4210-tmu";
517 clocks = <&clock CLK_TMU_APBIF>;
518 clock-names = "tmu_apbif";
519 samsung,tmu_gain = <15>;
520 samsung,tmu_reference_voltage = <7>;
521};
522
523#include "exynos4210-pinctrl.dtsi"
1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22#include "exynos4.dtsi"
23#include "exynos4210-pinctrl.dtsi"
24#include "exynos4-cpu-thermal.dtsi"
25
26/ {
27 compatible = "samsung,exynos4210", "samsung,exynos4";
28
29 aliases {
30 pinctrl0 = &pinctrl_0;
31 pinctrl1 = &pinctrl_1;
32 pinctrl2 = &pinctrl_2;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu0: cpu@900 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a9";
42 reg = <0x900>;
43 clocks = <&clock CLK_ARM_CLK>;
44 clock-names = "cpu";
45 clock-latency = <160000>;
46
47 operating-points = <
48 1200000 1250000
49 1000000 1150000
50 800000 1075000
51 500000 975000
52 400000 975000
53 200000 950000
54 >;
55 cooling-min-level = <4>;
56 cooling-max-level = <2>;
57 #cooling-cells = <2>; /* min followed by max */
58 };
59
60 cpu@901 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a9";
63 reg = <0x901>;
64 };
65 };
66
67 sysram: sysram@02020000 {
68 compatible = "mmio-sram";
69 reg = <0x02020000 0x20000>;
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 0x02020000 0x20000>;
73
74 smp-sysram@0 {
75 compatible = "samsung,exynos4210-sysram";
76 reg = <0x0 0x1000>;
77 };
78
79 smp-sysram@1f000 {
80 compatible = "samsung,exynos4210-sysram-ns";
81 reg = <0x1f000 0x1000>;
82 };
83 };
84
85 pd_lcd1: lcd1-power-domain@10023CA0 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023CA0 0x20>;
88 #power-domain-cells = <0>;
89 };
90
91 l2c: l2-cache-controller@10502000 {
92 compatible = "arm,pl310-cache";
93 reg = <0x10502000 0x1000>;
94 cache-unified;
95 cache-level = <2>;
96 arm,tag-latency = <2 2 1>;
97 arm,data-latency = <2 2 1>;
98 };
99
100 mct: mct@10050000 {
101 compatible = "samsung,exynos4210-mct";
102 reg = <0x10050000 0x800>;
103 interrupt-parent = <&mct_map>;
104 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
105 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
106 clock-names = "fin_pll", "mct";
107
108 mct_map: mct-map {
109 #interrupt-cells = <1>;
110 #address-cells = <0>;
111 #size-cells = <0>;
112 interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
113 <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
114 <2 &combiner 12 6>,
115 <3 &combiner 12 7>,
116 <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
117 <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
118 };
119 };
120
121 clock: clock-controller@10030000 {
122 compatible = "samsung,exynos4210-clock";
123 reg = <0x10030000 0x20000>;
124 #clock-cells = <1>;
125 };
126
127 pinctrl_0: pinctrl@11400000 {
128 compatible = "samsung,exynos4210-pinctrl";
129 reg = <0x11400000 0x1000>;
130 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
131 };
132
133 pinctrl_1: pinctrl@11000000 {
134 compatible = "samsung,exynos4210-pinctrl";
135 reg = <0x11000000 0x1000>;
136 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
137
138 wakup_eint: wakeup-interrupt-controller {
139 compatible = "samsung,exynos4210-wakeup-eint";
140 interrupt-parent = <&gic>;
141 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
142 };
143 };
144
145 pinctrl_2: pinctrl@03860000 {
146 compatible = "samsung,exynos4210-pinctrl";
147 reg = <0x03860000 0x1000>;
148 };
149
150 tmu: tmu@100C0000 {
151 compatible = "samsung,exynos4210-tmu";
152 interrupt-parent = <&combiner>;
153 reg = <0x100C0000 0x100>;
154 interrupts = <2 4>;
155 clocks = <&clock CLK_TMU_APBIF>;
156 clock-names = "tmu_apbif";
157 samsung,tmu_gain = <15>;
158 samsung,tmu_reference_voltage = <7>;
159 status = "disabled";
160 };
161
162 thermal-zones {
163 cpu_thermal: cpu-thermal {
164 polling-delay-passive = <0>;
165 polling-delay = <0>;
166 thermal-sensors = <&tmu 0>;
167
168 trips {
169 cpu_alert0: cpu-alert-0 {
170 temperature = <85000>; /* millicelsius */
171 };
172 cpu_alert1: cpu-alert-1 {
173 temperature = <100000>; /* millicelsius */
174 };
175 cpu_alert2: cpu-alert-2 {
176 temperature = <110000>; /* millicelsius */
177 };
178 };
179 };
180 };
181
182 g2d: g2d@12800000 {
183 compatible = "samsung,s5pv210-g2d";
184 reg = <0x12800000 0x1000>;
185 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
187 clock-names = "sclk_fimg2d", "fimg2d";
188 power-domains = <&pd_lcd0>;
189 iommus = <&sysmmu_g2d>;
190 };
191
192 camera {
193 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
194 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
195 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
196
197 fimc_0: fimc@11800000 {
198 samsung,pix-limits = <4224 8192 1920 4224>;
199 samsung,mainscaler-ext;
200 samsung,cam-if;
201 };
202
203 fimc_1: fimc@11810000 {
204 samsung,pix-limits = <4224 8192 1920 4224>;
205 samsung,mainscaler-ext;
206 samsung,cam-if;
207 };
208
209 fimc_2: fimc@11820000 {
210 samsung,pix-limits = <4224 8192 1920 4224>;
211 samsung,mainscaler-ext;
212 samsung,lcd-wb;
213 };
214
215 fimc_3: fimc@11830000 {
216 samsung,pix-limits = <1920 8192 1366 1920>;
217 samsung,rotators = <0>;
218 samsung,mainscaler-ext;
219 samsung,lcd-wb;
220 };
221 };
222
223 mixer: mixer@12C10000 {
224 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
225 "sclk_mixer";
226 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
227 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
228 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
229 };
230
231 ppmu_lcd1: ppmu_lcd1@12240000 {
232 compatible = "samsung,exynos-ppmu";
233 reg = <0x12240000 0x2000>;
234 clocks = <&clock CLK_PPMULCD1>;
235 clock-names = "ppmu";
236 status = "disabled";
237 };
238
239 sysmmu_g2d: sysmmu@12A20000 {
240 compatible = "samsung,exynos-sysmmu";
241 reg = <0x12A20000 0x1000>;
242 interrupt-parent = <&combiner>;
243 interrupts = <4 7>;
244 clock-names = "sysmmu", "master";
245 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
246 power-domains = <&pd_lcd0>;
247 #iommu-cells = <0>;
248 };
249
250 sysmmu_fimd1: sysmmu@12220000 {
251 compatible = "samsung,exynos-sysmmu";
252 interrupt-parent = <&combiner>;
253 reg = <0x12220000 0x1000>;
254 interrupts = <5 3>;
255 clock-names = "sysmmu", "master";
256 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
257 power-domains = <&pd_lcd1>;
258 #iommu-cells = <0>;
259 };
260
261 bus_dmc: bus_dmc {
262 compatible = "samsung,exynos-bus";
263 clocks = <&clock CLK_DIV_DMC>;
264 clock-names = "bus";
265 operating-points-v2 = <&bus_dmc_opp_table>;
266 status = "disabled";
267 };
268
269 bus_acp: bus_acp {
270 compatible = "samsung,exynos-bus";
271 clocks = <&clock CLK_DIV_ACP>;
272 clock-names = "bus";
273 operating-points-v2 = <&bus_acp_opp_table>;
274 status = "disabled";
275 };
276
277 bus_peri: bus_peri {
278 compatible = "samsung,exynos-bus";
279 clocks = <&clock CLK_ACLK100>;
280 clock-names = "bus";
281 operating-points-v2 = <&bus_peri_opp_table>;
282 status = "disabled";
283 };
284
285 bus_fsys: bus_fsys {
286 compatible = "samsung,exynos-bus";
287 clocks = <&clock CLK_ACLK133>;
288 clock-names = "bus";
289 operating-points-v2 = <&bus_fsys_opp_table>;
290 status = "disabled";
291 };
292
293 bus_display: bus_display {
294 compatible = "samsung,exynos-bus";
295 clocks = <&clock CLK_ACLK160>;
296 clock-names = "bus";
297 operating-points-v2 = <&bus_display_opp_table>;
298 status = "disabled";
299 };
300
301 bus_lcd0: bus_lcd0 {
302 compatible = "samsung,exynos-bus";
303 clocks = <&clock CLK_ACLK200>;
304 clock-names = "bus";
305 operating-points-v2 = <&bus_leftbus_opp_table>;
306 status = "disabled";
307 };
308
309 bus_leftbus: bus_leftbus {
310 compatible = "samsung,exynos-bus";
311 clocks = <&clock CLK_DIV_GDL>;
312 clock-names = "bus";
313 operating-points-v2 = <&bus_leftbus_opp_table>;
314 status = "disabled";
315 };
316
317 bus_rightbus: bus_rightbus {
318 compatible = "samsung,exynos-bus";
319 clocks = <&clock CLK_DIV_GDR>;
320 clock-names = "bus";
321 operating-points-v2 = <&bus_leftbus_opp_table>;
322 status = "disabled";
323 };
324
325 bus_mfc: bus_mfc {
326 compatible = "samsung,exynos-bus";
327 clocks = <&clock CLK_SCLK_MFC>;
328 clock-names = "bus";
329 operating-points-v2 = <&bus_leftbus_opp_table>;
330 status = "disabled";
331 };
332
333 bus_dmc_opp_table: opp_table1 {
334 compatible = "operating-points-v2";
335 opp-shared;
336
337 opp@134000000 {
338 opp-hz = /bits/ 64 <134000000>;
339 opp-microvolt = <1025000>;
340 };
341 opp@267000000 {
342 opp-hz = /bits/ 64 <267000000>;
343 opp-microvolt = <1050000>;
344 };
345 opp@400000000 {
346 opp-hz = /bits/ 64 <400000000>;
347 opp-microvolt = <1150000>;
348 };
349 };
350
351 bus_acp_opp_table: opp_table2 {
352 compatible = "operating-points-v2";
353 opp-shared;
354
355 opp@134000000 {
356 opp-hz = /bits/ 64 <134000000>;
357 };
358 opp@160000000 {
359 opp-hz = /bits/ 64 <160000000>;
360 };
361 opp@200000000 {
362 opp-hz = /bits/ 64 <200000000>;
363 };
364 };
365
366 bus_peri_opp_table: opp_table3 {
367 compatible = "operating-points-v2";
368 opp-shared;
369
370 opp@5000000 {
371 opp-hz = /bits/ 64 <5000000>;
372 };
373 opp@100000000 {
374 opp-hz = /bits/ 64 <100000000>;
375 };
376 };
377
378 bus_fsys_opp_table: opp_table4 {
379 compatible = "operating-points-v2";
380 opp-shared;
381
382 opp@10000000 {
383 opp-hz = /bits/ 64 <10000000>;
384 };
385 opp@134000000 {
386 opp-hz = /bits/ 64 <134000000>;
387 };
388 };
389
390 bus_display_opp_table: opp_table5 {
391 compatible = "operating-points-v2";
392 opp-shared;
393
394 opp@100000000 {
395 opp-hz = /bits/ 64 <100000000>;
396 };
397 opp@134000000 {
398 opp-hz = /bits/ 64 <134000000>;
399 };
400 opp@160000000 {
401 opp-hz = /bits/ 64 <160000000>;
402 };
403 };
404
405 bus_leftbus_opp_table: opp_table6 {
406 compatible = "operating-points-v2";
407 opp-shared;
408
409 opp@100000000 {
410 opp-hz = /bits/ 64 <100000000>;
411 };
412 opp@160000000 {
413 opp-hz = /bits/ 64 <160000000>;
414 };
415 opp@200000000 {
416 opp-hz = /bits/ 64 <200000000>;
417 };
418 };
419};
420
421&gic {
422 cpu-offset = <0x8000>;
423};
424
425&combiner {
426 samsung,combiner-nr = <16>;
427 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
443};
444
445&mdma1 {
446 power-domains = <&pd_lcd0>;
447};
448
449&pmu_system_controller {
450 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
451 "clkout4", "clkout8", "clkout9";
452 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
453 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
454 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
455 #clock-cells = <1>;
456};
457
458&rotator {
459 power-domains = <&pd_lcd0>;
460};
461
462&sysmmu_rotator {
463 power-domains = <&pd_lcd0>;
464};