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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
12 * bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
17 */
18
19#include "exynos4.dtsi"
20#include "exynos4-cpu-thermal.dtsi"
21
22/ {
23 compatible = "samsung,exynos4210", "samsung,exynos4";
24
25 aliases {
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu0: cpu@900 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0x900>;
39 clocks = <&clock CLK_ARM_CLK>;
40 clock-names = "cpu";
41 clock-latency = <160000>;
42
43 operating-points = <
44 1200000 1250000
45 1000000 1150000
46 800000 1075000
47 500000 975000
48 400000 975000
49 200000 950000
50 >;
51 #cooling-cells = <2>; /* min followed by max */
52 };
53
54 cpu1: cpu@901 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a9";
57 reg = <0x901>;
58 clocks = <&clock CLK_ARM_CLK>;
59 clock-names = "cpu";
60 clock-latency = <160000>;
61
62 operating-points = <
63 1200000 1250000
64 1000000 1150000
65 800000 1075000
66 500000 975000
67 400000 975000
68 200000 950000
69 >;
70 #cooling-cells = <2>; /* min followed by max */
71 };
72 };
73
74 soc: soc {
75 sysram: sram@2020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x20000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x02020000 0x20000>;
81
82 smp-sram@0 {
83 compatible = "samsung,exynos4210-sysram";
84 reg = <0x0 0x1000>;
85 };
86
87 smp-sram@1f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x1f000 0x1000>;
90 };
91 };
92
93 pd_lcd1: power-domain@10023ca0 {
94 compatible = "samsung,exynos4210-pd";
95 reg = <0x10023CA0 0x20>;
96 #power-domain-cells = <0>;
97 label = "LCD1";
98 };
99
100 l2c: cache-controller@10502000 {
101 compatible = "arm,pl310-cache";
102 reg = <0x10502000 0x1000>;
103 cache-unified;
104 cache-level = <2>;
105 prefetch-data = <1>;
106 prefetch-instr = <1>;
107 arm,tag-latency = <2 2 1>;
108 arm,data-latency = <2 2 1>;
109 };
110
111 mct: timer@10050000 {
112 compatible = "samsung,exynos4210-mct";
113 reg = <0x10050000 0x800>;
114 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
115 clock-names = "fin_pll", "mct";
116 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
117 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
118 <&combiner 12 6>,
119 <&combiner 12 7>,
120 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
121 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
122 };
123
124 watchdog: watchdog@10060000 {
125 compatible = "samsung,s3c6410-wdt";
126 reg = <0x10060000 0x100>;
127 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&clock CLK_WDT>;
129 clock-names = "watchdog";
130 };
131
132 clock: clock-controller@10030000 {
133 compatible = "samsung,exynos4210-clock";
134 reg = <0x10030000 0x20000>;
135 #clock-cells = <1>;
136 };
137
138 pinctrl_0: pinctrl@11400000 {
139 compatible = "samsung,exynos4210-pinctrl";
140 reg = <0x11400000 0x1000>;
141 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
142 };
143
144 pinctrl_1: pinctrl@11000000 {
145 compatible = "samsung,exynos4210-pinctrl";
146 reg = <0x11000000 0x1000>;
147 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
148
149 wakup_eint: wakeup-interrupt-controller {
150 compatible = "samsung,exynos4210-wakeup-eint";
151 interrupt-parent = <&gic>;
152 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
153 };
154 };
155
156 pinctrl_2: pinctrl@3860000 {
157 compatible = "samsung,exynos4210-pinctrl";
158 reg = <0x03860000 0x1000>;
159 };
160
161 g2d: g2d@12800000 {
162 compatible = "samsung,s5pv210-g2d";
163 reg = <0x12800000 0x1000>;
164 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
166 clock-names = "sclk_fimg2d", "fimg2d";
167 power-domains = <&pd_lcd0>;
168 iommus = <&sysmmu_g2d>;
169 };
170
171 ppmu_acp: ppmu@10ae0000 {
172 compatible = "samsung,exynos-ppmu";
173 reg = <0x10ae0000 0x2000>;
174 status = "disabled";
175 };
176
177 ppmu_lcd1: ppmu@12240000 {
178 compatible = "samsung,exynos-ppmu";
179 reg = <0x12240000 0x2000>;
180 clocks = <&clock CLK_PPMULCD1>;
181 clock-names = "ppmu";
182 status = "disabled";
183 };
184
185 sysmmu_g2d: sysmmu@12a20000 {
186 compatible = "samsung,exynos-sysmmu";
187 reg = <0x12A20000 0x1000>;
188 interrupt-parent = <&combiner>;
189 interrupts = <4 7>;
190 clock-names = "sysmmu", "master";
191 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
192 power-domains = <&pd_lcd0>;
193 #iommu-cells = <0>;
194 };
195
196 sysmmu_fimd1: sysmmu@12220000 {
197 compatible = "samsung,exynos-sysmmu";
198 interrupt-parent = <&combiner>;
199 reg = <0x12220000 0x1000>;
200 interrupts = <5 3>;
201 clock-names = "sysmmu", "master";
202 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
203 power-domains = <&pd_lcd1>;
204 #iommu-cells = <0>;
205 };
206
207 bus_dmc: bus-dmc {
208 compatible = "samsung,exynos-bus";
209 clocks = <&clock CLK_DIV_DMC>;
210 clock-names = "bus";
211 operating-points-v2 = <&bus_dmc_opp_table>;
212 status = "disabled";
213 };
214
215 bus_acp: bus-acp {
216 compatible = "samsung,exynos-bus";
217 clocks = <&clock CLK_DIV_ACP>;
218 clock-names = "bus";
219 operating-points-v2 = <&bus_acp_opp_table>;
220 status = "disabled";
221 };
222
223 bus_peri: bus-peri {
224 compatible = "samsung,exynos-bus";
225 clocks = <&clock CLK_ACLK100>;
226 clock-names = "bus";
227 operating-points-v2 = <&bus_peri_opp_table>;
228 status = "disabled";
229 };
230
231 bus_fsys: bus-fsys {
232 compatible = "samsung,exynos-bus";
233 clocks = <&clock CLK_ACLK133>;
234 clock-names = "bus";
235 operating-points-v2 = <&bus_fsys_opp_table>;
236 status = "disabled";
237 };
238
239 bus_display: bus-display {
240 compatible = "samsung,exynos-bus";
241 clocks = <&clock CLK_ACLK160>;
242 clock-names = "bus";
243 operating-points-v2 = <&bus_display_opp_table>;
244 status = "disabled";
245 };
246
247 bus_lcd0: bus-lcd0 {
248 compatible = "samsung,exynos-bus";
249 clocks = <&clock CLK_ACLK200>;
250 clock-names = "bus";
251 operating-points-v2 = <&bus_leftbus_opp_table>;
252 status = "disabled";
253 };
254
255 bus_leftbus: bus-leftbus {
256 compatible = "samsung,exynos-bus";
257 clocks = <&clock CLK_DIV_GDL>;
258 clock-names = "bus";
259 operating-points-v2 = <&bus_leftbus_opp_table>;
260 status = "disabled";
261 };
262
263 bus_rightbus: bus-rightbus {
264 compatible = "samsung,exynos-bus";
265 clocks = <&clock CLK_DIV_GDR>;
266 clock-names = "bus";
267 operating-points-v2 = <&bus_leftbus_opp_table>;
268 status = "disabled";
269 };
270
271 bus_mfc: bus-mfc {
272 compatible = "samsung,exynos-bus";
273 clocks = <&clock CLK_SCLK_MFC>;
274 clock-names = "bus";
275 operating-points-v2 = <&bus_leftbus_opp_table>;
276 status = "disabled";
277 };
278
279 bus_dmc_opp_table: opp-table1 {
280 compatible = "operating-points-v2";
281 opp-shared;
282
283 opp-134000000 {
284 opp-hz = /bits/ 64 <134000000>;
285 opp-microvolt = <1025000>;
286 };
287 opp-267000000 {
288 opp-hz = /bits/ 64 <267000000>;
289 opp-microvolt = <1050000>;
290 };
291 opp-400000000 {
292 opp-hz = /bits/ 64 <400000000>;
293 opp-microvolt = <1150000>;
294 opp-suspend;
295 };
296 };
297
298 bus_acp_opp_table: opp-table2 {
299 compatible = "operating-points-v2";
300 opp-shared;
301
302 opp-134000000 {
303 opp-hz = /bits/ 64 <134000000>;
304 };
305 opp-160000000 {
306 opp-hz = /bits/ 64 <160000000>;
307 };
308 opp-200000000 {
309 opp-hz = /bits/ 64 <200000000>;
310 };
311 };
312
313 bus_peri_opp_table: opp-table3 {
314 compatible = "operating-points-v2";
315 opp-shared;
316
317 opp-5000000 {
318 opp-hz = /bits/ 64 <5000000>;
319 };
320 opp-100000000 {
321 opp-hz = /bits/ 64 <100000000>;
322 };
323 };
324
325 bus_fsys_opp_table: opp-table4 {
326 compatible = "operating-points-v2";
327 opp-shared;
328
329 opp-10000000 {
330 opp-hz = /bits/ 64 <10000000>;
331 };
332 opp-134000000 {
333 opp-hz = /bits/ 64 <134000000>;
334 };
335 };
336
337 bus_display_opp_table: opp-table5 {
338 compatible = "operating-points-v2";
339 opp-shared;
340
341 opp-100000000 {
342 opp-hz = /bits/ 64 <100000000>;
343 };
344 opp-134000000 {
345 opp-hz = /bits/ 64 <134000000>;
346 };
347 opp-160000000 {
348 opp-hz = /bits/ 64 <160000000>;
349 };
350 };
351
352 bus_leftbus_opp_table: opp-table6 {
353 compatible = "operating-points-v2";
354 opp-shared;
355
356 opp-100000000 {
357 opp-hz = /bits/ 64 <100000000>;
358 };
359 opp-160000000 {
360 opp-hz = /bits/ 64 <160000000>;
361 };
362 opp-200000000 {
363 opp-hz = /bits/ 64 <200000000>;
364 opp-suspend;
365 };
366 };
367 };
368};
369
370&cpu_alert0 {
371 temperature = <85000>; /* millicelsius */
372};
373
374&cpu_alert1 {
375 temperature = <100000>; /* millicelsius */
376};
377
378&cpu_alert2 {
379 temperature = <110000>; /* millicelsius */
380};
381
382&cpu_thermal {
383 polling-delay-passive = <0>;
384 polling-delay = <0>;
385 thermal-sensors = <&tmu 0>;
386};
387
388&gic {
389 cpu-offset = <0x8000>;
390};
391
392&camera {
393 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
394 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
395 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
396};
397
398&combiner {
399 samsung,combiner-nr = <16>;
400 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
416};
417
418&fimc_0 {
419 samsung,pix-limits = <4224 8192 1920 4224>;
420 samsung,mainscaler-ext;
421 samsung,cam-if;
422};
423
424&fimc_1 {
425 samsung,pix-limits = <4224 8192 1920 4224>;
426 samsung,mainscaler-ext;
427 samsung,cam-if;
428};
429
430&fimc_2 {
431 samsung,pix-limits = <4224 8192 1920 4224>;
432 samsung,mainscaler-ext;
433 samsung,lcd-wb;
434};
435
436&fimc_3 {
437 samsung,pix-limits = <1920 8192 1366 1920>;
438 samsung,rotators = <0>;
439 samsung,mainscaler-ext;
440 samsung,lcd-wb;
441};
442
443&gpu {
444 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-names = "gp",
455 "gpmmu",
456 "pp0",
457 "ppmmu0",
458 "pp1",
459 "ppmmu1",
460 "pp2",
461 "ppmmu2",
462 "pp3",
463 "ppmmu3";
464 operating-points-v2 = <&gpu_opp_table>;
465
466 gpu_opp_table: opp-table {
467 compatible = "operating-points-v2";
468
469 opp-160000000 {
470 opp-hz = /bits/ 64 <160000000>;
471 opp-microvolt = <950000>;
472 };
473 opp-267000000 {
474 opp-hz = /bits/ 64 <267000000>;
475 opp-microvolt = <1050000>;
476 };
477 };
478};
479
480&mdma1 {
481 power-domains = <&pd_lcd0>;
482};
483
484&mixer {
485 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
486 "sclk_mixer";
487 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
488 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
489 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
490};
491
492&pmu {
493 interrupts = <2 2>, <3 2>;
494 interrupt-affinity = <&cpu0>, <&cpu1>;
495 status = "okay";
496};
497
498&pmu_system_controller {
499 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
500 "clkout4", "clkout8", "clkout9";
501 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
502 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
503 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
504 #clock-cells = <1>;
505};
506
507&rotator {
508 power-domains = <&pd_lcd0>;
509};
510
511&sysmmu_rotator {
512 power-domains = <&pd_lcd0>;
513};
514
515&tmu {
516 compatible = "samsung,exynos4210-tmu";
517 clocks = <&clock CLK_TMU_APBIF>;
518 clock-names = "tmu_apbif";
519 samsung,tmu_gain = <15>;
520 samsung,tmu_reference_voltage = <7>;
521};
522
523#include "exynos4210-pinctrl.dtsi"
1/*
2 * Samsung's Exynos4210 SoC device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
9 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
10 * based board files can include this file and provide values for board specfic
11 * bindings.
12 *
13 * Note: This file does not include device nodes for all the controllers in
14 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
15 * nodes can be added to this file.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20*/
21
22/include/ "skeleton.dtsi"
23
24/ {
25 compatible = "samsung,exynos4210";
26 interrupt-parent = <&gic>;
27
28 gic:interrupt-controller@10490000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 interrupt-controller;
32 cpu-offset = <0x8000>;
33 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
34 };
35
36 watchdog@10060000 {
37 compatible = "samsung,s3c2410-wdt";
38 reg = <0x10060000 0x100>;
39 interrupts = <0 43 0>;
40 };
41
42 rtc@10070000 {
43 compatible = "samsung,s3c6410-rtc";
44 reg = <0x10070000 0x100>;
45 interrupts = <0 44 0>, <0 45 0>;
46 };
47
48 keypad@100A0000 {
49 compatible = "samsung,s5pv210-keypad";
50 reg = <0x100A0000 0x100>;
51 interrupts = <0 109 0>;
52 };
53
54 sdhci@12510000 {
55 compatible = "samsung,exynos4210-sdhci";
56 reg = <0x12510000 0x100>;
57 interrupts = <0 73 0>;
58 };
59
60 sdhci@12520000 {
61 compatible = "samsung,exynos4210-sdhci";
62 reg = <0x12520000 0x100>;
63 interrupts = <0 74 0>;
64 };
65
66 sdhci@12530000 {
67 compatible = "samsung,exynos4210-sdhci";
68 reg = <0x12530000 0x100>;
69 interrupts = <0 75 0>;
70 };
71
72 sdhci@12540000 {
73 compatible = "samsung,exynos4210-sdhci";
74 reg = <0x12540000 0x100>;
75 interrupts = <0 76 0>;
76 };
77
78 serial@13800000 {
79 compatible = "samsung,exynos4210-uart";
80 reg = <0x13800000 0x100>;
81 interrupts = <0 52 0>;
82 };
83
84 serial@13810000 {
85 compatible = "samsung,exynos4210-uart";
86 reg = <0x13810000 0x100>;
87 interrupts = <0 53 0>;
88 };
89
90 serial@13820000 {
91 compatible = "samsung,exynos4210-uart";
92 reg = <0x13820000 0x100>;
93 interrupts = <0 54 0>;
94 };
95
96 serial@13830000 {
97 compatible = "samsung,exynos4210-uart";
98 reg = <0x13830000 0x100>;
99 interrupts = <0 55 0>;
100 };
101
102 i2c@13860000 {
103 compatible = "samsung,s3c2440-i2c";
104 reg = <0x13860000 0x100>;
105 interrupts = <0 58 0>;
106 };
107
108 i2c@13870000 {
109 compatible = "samsung,s3c2440-i2c";
110 reg = <0x13870000 0x100>;
111 interrupts = <0 59 0>;
112 };
113
114 i2c@13880000 {
115 compatible = "samsung,s3c2440-i2c";
116 reg = <0x13880000 0x100>;
117 interrupts = <0 60 0>;
118 };
119
120 i2c@13890000 {
121 compatible = "samsung,s3c2440-i2c";
122 reg = <0x13890000 0x100>;
123 interrupts = <0 61 0>;
124 };
125
126 i2c@138A0000 {
127 compatible = "samsung,s3c2440-i2c";
128 reg = <0x138A0000 0x100>;
129 interrupts = <0 62 0>;
130 };
131
132 i2c@138B0000 {
133 compatible = "samsung,s3c2440-i2c";
134 reg = <0x138B0000 0x100>;
135 interrupts = <0 63 0>;
136 };
137
138 i2c@138C0000 {
139 compatible = "samsung,s3c2440-i2c";
140 reg = <0x138C0000 0x100>;
141 interrupts = <0 64 0>;
142 };
143
144 i2c@138D0000 {
145 compatible = "samsung,s3c2440-i2c";
146 reg = <0x138D0000 0x100>;
147 interrupts = <0 65 0>;
148 };
149
150 amba {
151 #address-cells = <1>;
152 #size-cells = <1>;
153 compatible = "arm,amba-bus";
154 interrupt-parent = <&gic>;
155 ranges;
156
157 pdma0: pdma@12680000 {
158 compatible = "arm,pl330", "arm,primecell";
159 reg = <0x12680000 0x1000>;
160 interrupts = <0 35 0>;
161 };
162
163 pdma1: pdma@12690000 {
164 compatible = "arm,pl330", "arm,primecell";
165 reg = <0x12690000 0x1000>;
166 interrupts = <0 36 0>;
167 };
168 };
169
170 gpio-controllers {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 gpio-controller;
174 ranges;
175
176 gpa0: gpio-controller@11400000 {
177 compatible = "samsung,exynos4-gpio";
178 reg = <0x11400000 0x20>;
179 #gpio-cells = <4>;
180 };
181
182 gpa1: gpio-controller@11400020 {
183 compatible = "samsung,exynos4-gpio";
184 reg = <0x11400020 0x20>;
185 #gpio-cells = <4>;
186 };
187
188 gpb: gpio-controller@11400040 {
189 compatible = "samsung,exynos4-gpio";
190 reg = <0x11400040 0x20>;
191 #gpio-cells = <4>;
192 };
193
194 gpc0: gpio-controller@11400060 {
195 compatible = "samsung,exynos4-gpio";
196 reg = <0x11400060 0x20>;
197 #gpio-cells = <4>;
198 };
199
200 gpc1: gpio-controller@11400080 {
201 compatible = "samsung,exynos4-gpio";
202 reg = <0x11400080 0x20>;
203 #gpio-cells = <4>;
204 };
205
206 gpd0: gpio-controller@114000A0 {
207 compatible = "samsung,exynos4-gpio";
208 reg = <0x114000A0 0x20>;
209 #gpio-cells = <4>;
210 };
211
212 gpd1: gpio-controller@114000C0 {
213 compatible = "samsung,exynos4-gpio";
214 reg = <0x114000C0 0x20>;
215 #gpio-cells = <4>;
216 };
217
218 gpe0: gpio-controller@114000E0 {
219 compatible = "samsung,exynos4-gpio";
220 reg = <0x114000E0 0x20>;
221 #gpio-cells = <4>;
222 };
223
224 gpe1: gpio-controller@11400100 {
225 compatible = "samsung,exynos4-gpio";
226 reg = <0x11400100 0x20>;
227 #gpio-cells = <4>;
228 };
229
230 gpe2: gpio-controller@11400120 {
231 compatible = "samsung,exynos4-gpio";
232 reg = <0x11400120 0x20>;
233 #gpio-cells = <4>;
234 };
235
236 gpe3: gpio-controller@11400140 {
237 compatible = "samsung,exynos4-gpio";
238 reg = <0x11400140 0x20>;
239 #gpio-cells = <4>;
240 };
241
242 gpe4: gpio-controller@11400160 {
243 compatible = "samsung,exynos4-gpio";
244 reg = <0x11400160 0x20>;
245 #gpio-cells = <4>;
246 };
247
248 gpf0: gpio-controller@11400180 {
249 compatible = "samsung,exynos4-gpio";
250 reg = <0x11400180 0x20>;
251 #gpio-cells = <4>;
252 };
253
254 gpf1: gpio-controller@114001A0 {
255 compatible = "samsung,exynos4-gpio";
256 reg = <0x114001A0 0x20>;
257 #gpio-cells = <4>;
258 };
259
260 gpf2: gpio-controller@114001C0 {
261 compatible = "samsung,exynos4-gpio";
262 reg = <0x114001C0 0x20>;
263 #gpio-cells = <4>;
264 };
265
266 gpf3: gpio-controller@114001E0 {
267 compatible = "samsung,exynos4-gpio";
268 reg = <0x114001E0 0x20>;
269 #gpio-cells = <4>;
270 };
271
272 gpj0: gpio-controller@11000000 {
273 compatible = "samsung,exynos4-gpio";
274 reg = <0x11000000 0x20>;
275 #gpio-cells = <4>;
276 };
277
278 gpj1: gpio-controller@11000020 {
279 compatible = "samsung,exynos4-gpio";
280 reg = <0x11000020 0x20>;
281 #gpio-cells = <4>;
282 };
283
284 gpk0: gpio-controller@11000040 {
285 compatible = "samsung,exynos4-gpio";
286 reg = <0x11000040 0x20>;
287 #gpio-cells = <4>;
288 };
289
290 gpk1: gpio-controller@11000060 {
291 compatible = "samsung,exynos4-gpio";
292 reg = <0x11000060 0x20>;
293 #gpio-cells = <4>;
294 };
295
296 gpk2: gpio-controller@11000080 {
297 compatible = "samsung,exynos4-gpio";
298 reg = <0x11000080 0x20>;
299 #gpio-cells = <4>;
300 };
301
302 gpk3: gpio-controller@110000A0 {
303 compatible = "samsung,exynos4-gpio";
304 reg = <0x110000A0 0x20>;
305 #gpio-cells = <4>;
306 };
307
308 gpl0: gpio-controller@110000C0 {
309 compatible = "samsung,exynos4-gpio";
310 reg = <0x110000C0 0x20>;
311 #gpio-cells = <4>;
312 };
313
314 gpl1: gpio-controller@110000E0 {
315 compatible = "samsung,exynos4-gpio";
316 reg = <0x110000E0 0x20>;
317 #gpio-cells = <4>;
318 };
319
320 gpl2: gpio-controller@11000100 {
321 compatible = "samsung,exynos4-gpio";
322 reg = <0x11000100 0x20>;
323 #gpio-cells = <4>;
324 };
325
326 gpy0: gpio-controller@11000120 {
327 compatible = "samsung,exynos4-gpio";
328 reg = <0x11000120 0x20>;
329 #gpio-cells = <4>;
330 };
331
332 gpy1: gpio-controller@11000140 {
333 compatible = "samsung,exynos4-gpio";
334 reg = <0x11000140 0x20>;
335 #gpio-cells = <4>;
336 };
337
338 gpy2: gpio-controller@11000160 {
339 compatible = "samsung,exynos4-gpio";
340 reg = <0x11000160 0x20>;
341 #gpio-cells = <4>;
342 };
343
344 gpy3: gpio-controller@11000180 {
345 compatible = "samsung,exynos4-gpio";
346 reg = <0x11000180 0x20>;
347 #gpio-cells = <4>;
348 };
349
350 gpy4: gpio-controller@110001A0 {
351 compatible = "samsung,exynos4-gpio";
352 reg = <0x110001A0 0x20>;
353 #gpio-cells = <4>;
354 };
355
356 gpy5: gpio-controller@110001C0 {
357 compatible = "samsung,exynos4-gpio";
358 reg = <0x110001C0 0x20>;
359 #gpio-cells = <4>;
360 };
361
362 gpy6: gpio-controller@110001E0 {
363 compatible = "samsung,exynos4-gpio";
364 reg = <0x110001E0 0x20>;
365 #gpio-cells = <4>;
366 };
367
368 gpx0: gpio-controller@11000C00 {
369 compatible = "samsung,exynos4-gpio";
370 reg = <0x11000C00 0x20>;
371 #gpio-cells = <4>;
372 };
373
374 gpx1: gpio-controller@11000C20 {
375 compatible = "samsung,exynos4-gpio";
376 reg = <0x11000C20 0x20>;
377 #gpio-cells = <4>;
378 };
379
380 gpx2: gpio-controller@11000C40 {
381 compatible = "samsung,exynos4-gpio";
382 reg = <0x11000C40 0x20>;
383 #gpio-cells = <4>;
384 };
385
386 gpx3: gpio-controller@11000C60 {
387 compatible = "samsung,exynos4-gpio";
388 reg = <0x11000C60 0x20>;
389 #gpio-cells = <4>;
390 };
391
392 gpz: gpio-controller@03860000 {
393 compatible = "samsung,exynos4-gpio";
394 reg = <0x03860000 0x20>;
395 #gpio-cells = <4>;
396 };
397 };
398};