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1/*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#undef DEBUG
26
27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
35#include <linux/errno.h>
36#include <linux/init.h>
37#include <linux/interrupt.h>
38#include <linux/ioport.h>
39#include <linux/major.h>
40#include <linux/module.h>
41#include <linux/mm.h>
42#include <linux/of.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/scatterlist.h>
46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
49#include <linux/slab.h>
50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55
56#ifdef CONFIG_SUPERH
57#include <asm/sh_bios.h>
58#endif
59
60#include "sh-sci.h"
61
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct sci_port {
104 struct uart_port port;
105
106 /* Platform configuration */
107 struct plat_sci_port *cfg;
108 unsigned int overrun_reg;
109 unsigned int overrun_mask;
110 unsigned int error_mask;
111 unsigned int error_clear;
112 unsigned int sampling_rate_mask;
113 resource_size_t reg_size;
114
115 /* Break timer */
116 struct timer_list break_timer;
117 int break_flag;
118
119 /* Clocks */
120 struct clk *clks[SCI_NUM_CLKS];
121 unsigned long clk_rates[SCI_NUM_CLKS];
122
123 int irqs[SCIx_NR_IRQS];
124 char *irqstr[SCIx_NR_IRQS];
125
126 struct dma_chan *chan_tx;
127 struct dma_chan *chan_rx;
128
129#ifdef CONFIG_SERIAL_SH_SCI_DMA
130 dma_cookie_t cookie_tx;
131 dma_cookie_t cookie_rx[2];
132 dma_cookie_t active_rx;
133 dma_addr_t tx_dma_addr;
134 unsigned int tx_dma_len;
135 struct scatterlist sg_rx[2];
136 void *rx_buf[2];
137 size_t buf_len_rx;
138 struct work_struct work_tx;
139 struct timer_list rx_timer;
140 unsigned int rx_timeout;
141#endif
142};
143
144#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
145
146static struct sci_port sci_ports[SCI_NPORTS];
147static struct uart_driver sci_uart_driver;
148
149static inline struct sci_port *
150to_sci_port(struct uart_port *uart)
151{
152 return container_of(uart, struct sci_port, port);
153}
154
155struct plat_sci_reg {
156 u8 offset, size;
157};
158
159/* Helper for invalidating specific entries of an inherited map. */
160#define sci_reg_invalid { .offset = 0, .size = 0 }
161
162static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
163 [SCIx_PROBE_REGTYPE] = {
164 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
165 },
166
167 /*
168 * Common SCI definitions, dependent on the port's regshift
169 * value.
170 */
171 [SCIx_SCI_REGTYPE] = {
172 [SCSMR] = { 0x00, 8 },
173 [SCBRR] = { 0x01, 8 },
174 [SCSCR] = { 0x02, 8 },
175 [SCxTDR] = { 0x03, 8 },
176 [SCxSR] = { 0x04, 8 },
177 [SCxRDR] = { 0x05, 8 },
178 [SCFCR] = sci_reg_invalid,
179 [SCFDR] = sci_reg_invalid,
180 [SCTFDR] = sci_reg_invalid,
181 [SCRFDR] = sci_reg_invalid,
182 [SCSPTR] = sci_reg_invalid,
183 [SCLSR] = sci_reg_invalid,
184 [HSSRR] = sci_reg_invalid,
185 [SCPCR] = sci_reg_invalid,
186 [SCPDR] = sci_reg_invalid,
187 [SCDL] = sci_reg_invalid,
188 [SCCKS] = sci_reg_invalid,
189 },
190
191 /*
192 * Common definitions for legacy IrDA ports, dependent on
193 * regshift value.
194 */
195 [SCIx_IRDA_REGTYPE] = {
196 [SCSMR] = { 0x00, 8 },
197 [SCBRR] = { 0x01, 8 },
198 [SCSCR] = { 0x02, 8 },
199 [SCxTDR] = { 0x03, 8 },
200 [SCxSR] = { 0x04, 8 },
201 [SCxRDR] = { 0x05, 8 },
202 [SCFCR] = { 0x06, 8 },
203 [SCFDR] = { 0x07, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
208 [HSSRR] = sci_reg_invalid,
209 [SCPCR] = sci_reg_invalid,
210 [SCPDR] = sci_reg_invalid,
211 [SCDL] = sci_reg_invalid,
212 [SCCKS] = sci_reg_invalid,
213 },
214
215 /*
216 * Common SCIFA definitions.
217 */
218 [SCIx_SCIFA_REGTYPE] = {
219 [SCSMR] = { 0x00, 16 },
220 [SCBRR] = { 0x04, 8 },
221 [SCSCR] = { 0x08, 16 },
222 [SCxTDR] = { 0x20, 8 },
223 [SCxSR] = { 0x14, 16 },
224 [SCxRDR] = { 0x24, 8 },
225 [SCFCR] = { 0x18, 16 },
226 [SCFDR] = { 0x1c, 16 },
227 [SCTFDR] = sci_reg_invalid,
228 [SCRFDR] = sci_reg_invalid,
229 [SCSPTR] = sci_reg_invalid,
230 [SCLSR] = sci_reg_invalid,
231 [HSSRR] = sci_reg_invalid,
232 [SCPCR] = { 0x30, 16 },
233 [SCPDR] = { 0x34, 16 },
234 [SCDL] = sci_reg_invalid,
235 [SCCKS] = sci_reg_invalid,
236 },
237
238 /*
239 * Common SCIFB definitions.
240 */
241 [SCIx_SCIFB_REGTYPE] = {
242 [SCSMR] = { 0x00, 16 },
243 [SCBRR] = { 0x04, 8 },
244 [SCSCR] = { 0x08, 16 },
245 [SCxTDR] = { 0x40, 8 },
246 [SCxSR] = { 0x14, 16 },
247 [SCxRDR] = { 0x60, 8 },
248 [SCFCR] = { 0x18, 16 },
249 [SCFDR] = sci_reg_invalid,
250 [SCTFDR] = { 0x38, 16 },
251 [SCRFDR] = { 0x3c, 16 },
252 [SCSPTR] = sci_reg_invalid,
253 [SCLSR] = sci_reg_invalid,
254 [HSSRR] = sci_reg_invalid,
255 [SCPCR] = { 0x30, 16 },
256 [SCPDR] = { 0x34, 16 },
257 [SCDL] = sci_reg_invalid,
258 [SCCKS] = sci_reg_invalid,
259 },
260
261 /*
262 * Common SH-2(A) SCIF definitions for ports with FIFO data
263 * count registers.
264 */
265 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = { 0x20, 16 },
277 [SCLSR] = { 0x24, 16 },
278 [HSSRR] = sci_reg_invalid,
279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
281 [SCDL] = sci_reg_invalid,
282 [SCCKS] = sci_reg_invalid,
283 },
284
285 /*
286 * Common SH-3 SCIF definitions.
287 */
288 [SCIx_SH3_SCIF_REGTYPE] = {
289 [SCSMR] = { 0x00, 8 },
290 [SCBRR] = { 0x02, 8 },
291 [SCSCR] = { 0x04, 8 },
292 [SCxTDR] = { 0x06, 8 },
293 [SCxSR] = { 0x08, 16 },
294 [SCxRDR] = { 0x0a, 8 },
295 [SCFCR] = { 0x0c, 8 },
296 [SCFDR] = { 0x0e, 16 },
297 [SCTFDR] = sci_reg_invalid,
298 [SCRFDR] = sci_reg_invalid,
299 [SCSPTR] = sci_reg_invalid,
300 [SCLSR] = sci_reg_invalid,
301 [HSSRR] = sci_reg_invalid,
302 [SCPCR] = sci_reg_invalid,
303 [SCPDR] = sci_reg_invalid,
304 [SCDL] = sci_reg_invalid,
305 [SCCKS] = sci_reg_invalid,
306 },
307
308 /*
309 * Common SH-4(A) SCIF(B) definitions.
310 */
311 [SCIx_SH4_SCIF_REGTYPE] = {
312 [SCSMR] = { 0x00, 16 },
313 [SCBRR] = { 0x04, 8 },
314 [SCSCR] = { 0x08, 16 },
315 [SCxTDR] = { 0x0c, 8 },
316 [SCxSR] = { 0x10, 16 },
317 [SCxRDR] = { 0x14, 8 },
318 [SCFCR] = { 0x18, 16 },
319 [SCFDR] = { 0x1c, 16 },
320 [SCTFDR] = sci_reg_invalid,
321 [SCRFDR] = sci_reg_invalid,
322 [SCSPTR] = { 0x20, 16 },
323 [SCLSR] = { 0x24, 16 },
324 [HSSRR] = sci_reg_invalid,
325 [SCPCR] = sci_reg_invalid,
326 [SCPDR] = sci_reg_invalid,
327 [SCDL] = sci_reg_invalid,
328 [SCCKS] = sci_reg_invalid,
329 },
330
331 /*
332 * Common SCIF definitions for ports with a Baud Rate Generator for
333 * External Clock (BRG).
334 */
335 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
336 [SCSMR] = { 0x00, 16 },
337 [SCBRR] = { 0x04, 8 },
338 [SCSCR] = { 0x08, 16 },
339 [SCxTDR] = { 0x0c, 8 },
340 [SCxSR] = { 0x10, 16 },
341 [SCxRDR] = { 0x14, 8 },
342 [SCFCR] = { 0x18, 16 },
343 [SCFDR] = { 0x1c, 16 },
344 [SCTFDR] = sci_reg_invalid,
345 [SCRFDR] = sci_reg_invalid,
346 [SCSPTR] = { 0x20, 16 },
347 [SCLSR] = { 0x24, 16 },
348 [HSSRR] = sci_reg_invalid,
349 [SCPCR] = sci_reg_invalid,
350 [SCPDR] = sci_reg_invalid,
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
353 },
354
355 /*
356 * Common HSCIF definitions.
357 */
358 [SCIx_HSCIF_REGTYPE] = {
359 [SCSMR] = { 0x00, 16 },
360 [SCBRR] = { 0x04, 8 },
361 [SCSCR] = { 0x08, 16 },
362 [SCxTDR] = { 0x0c, 8 },
363 [SCxSR] = { 0x10, 16 },
364 [SCxRDR] = { 0x14, 8 },
365 [SCFCR] = { 0x18, 16 },
366 [SCFDR] = { 0x1c, 16 },
367 [SCTFDR] = sci_reg_invalid,
368 [SCRFDR] = sci_reg_invalid,
369 [SCSPTR] = { 0x20, 16 },
370 [SCLSR] = { 0x24, 16 },
371 [HSSRR] = { 0x40, 16 },
372 [SCPCR] = sci_reg_invalid,
373 [SCPDR] = sci_reg_invalid,
374 [SCDL] = { 0x30, 16 },
375 [SCCKS] = { 0x34, 16 },
376 },
377
378 /*
379 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
380 * register.
381 */
382 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
383 [SCSMR] = { 0x00, 16 },
384 [SCBRR] = { 0x04, 8 },
385 [SCSCR] = { 0x08, 16 },
386 [SCxTDR] = { 0x0c, 8 },
387 [SCxSR] = { 0x10, 16 },
388 [SCxRDR] = { 0x14, 8 },
389 [SCFCR] = { 0x18, 16 },
390 [SCFDR] = { 0x1c, 16 },
391 [SCTFDR] = sci_reg_invalid,
392 [SCRFDR] = sci_reg_invalid,
393 [SCSPTR] = sci_reg_invalid,
394 [SCLSR] = { 0x24, 16 },
395 [HSSRR] = sci_reg_invalid,
396 [SCPCR] = sci_reg_invalid,
397 [SCPDR] = sci_reg_invalid,
398 [SCDL] = sci_reg_invalid,
399 [SCCKS] = sci_reg_invalid,
400 },
401
402 /*
403 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
404 * count registers.
405 */
406 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
407 [SCSMR] = { 0x00, 16 },
408 [SCBRR] = { 0x04, 8 },
409 [SCSCR] = { 0x08, 16 },
410 [SCxTDR] = { 0x0c, 8 },
411 [SCxSR] = { 0x10, 16 },
412 [SCxRDR] = { 0x14, 8 },
413 [SCFCR] = { 0x18, 16 },
414 [SCFDR] = { 0x1c, 16 },
415 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
416 [SCRFDR] = { 0x20, 16 },
417 [SCSPTR] = { 0x24, 16 },
418 [SCLSR] = { 0x28, 16 },
419 [HSSRR] = sci_reg_invalid,
420 [SCPCR] = sci_reg_invalid,
421 [SCPDR] = sci_reg_invalid,
422 [SCDL] = sci_reg_invalid,
423 [SCCKS] = sci_reg_invalid,
424 },
425
426 /*
427 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
428 * registers.
429 */
430 [SCIx_SH7705_SCIF_REGTYPE] = {
431 [SCSMR] = { 0x00, 16 },
432 [SCBRR] = { 0x04, 8 },
433 [SCSCR] = { 0x08, 16 },
434 [SCxTDR] = { 0x20, 8 },
435 [SCxSR] = { 0x14, 16 },
436 [SCxRDR] = { 0x24, 8 },
437 [SCFCR] = { 0x18, 16 },
438 [SCFDR] = { 0x1c, 16 },
439 [SCTFDR] = sci_reg_invalid,
440 [SCRFDR] = sci_reg_invalid,
441 [SCSPTR] = sci_reg_invalid,
442 [SCLSR] = sci_reg_invalid,
443 [HSSRR] = sci_reg_invalid,
444 [SCPCR] = sci_reg_invalid,
445 [SCPDR] = sci_reg_invalid,
446 [SCDL] = sci_reg_invalid,
447 [SCCKS] = sci_reg_invalid,
448 },
449};
450
451#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
452
453/*
454 * The "offset" here is rather misleading, in that it refers to an enum
455 * value relative to the port mapping rather than the fixed offset
456 * itself, which needs to be manually retrieved from the platform's
457 * register map for the given port.
458 */
459static unsigned int sci_serial_in(struct uart_port *p, int offset)
460{
461 const struct plat_sci_reg *reg = sci_getreg(p, offset);
462
463 if (reg->size == 8)
464 return ioread8(p->membase + (reg->offset << p->regshift));
465 else if (reg->size == 16)
466 return ioread16(p->membase + (reg->offset << p->regshift));
467 else
468 WARN(1, "Invalid register access\n");
469
470 return 0;
471}
472
473static void sci_serial_out(struct uart_port *p, int offset, int value)
474{
475 const struct plat_sci_reg *reg = sci_getreg(p, offset);
476
477 if (reg->size == 8)
478 iowrite8(value, p->membase + (reg->offset << p->regshift));
479 else if (reg->size == 16)
480 iowrite16(value, p->membase + (reg->offset << p->regshift));
481 else
482 WARN(1, "Invalid register access\n");
483}
484
485static int sci_probe_regmap(struct plat_sci_port *cfg)
486{
487 switch (cfg->type) {
488 case PORT_SCI:
489 cfg->regtype = SCIx_SCI_REGTYPE;
490 break;
491 case PORT_IRDA:
492 cfg->regtype = SCIx_IRDA_REGTYPE;
493 break;
494 case PORT_SCIFA:
495 cfg->regtype = SCIx_SCIFA_REGTYPE;
496 break;
497 case PORT_SCIFB:
498 cfg->regtype = SCIx_SCIFB_REGTYPE;
499 break;
500 case PORT_SCIF:
501 /*
502 * The SH-4 is a bit of a misnomer here, although that's
503 * where this particular port layout originated. This
504 * configuration (or some slight variation thereof)
505 * remains the dominant model for all SCIFs.
506 */
507 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
508 break;
509 case PORT_HSCIF:
510 cfg->regtype = SCIx_HSCIF_REGTYPE;
511 break;
512 default:
513 pr_err("Can't probe register map for given port\n");
514 return -EINVAL;
515 }
516
517 return 0;
518}
519
520static void sci_port_enable(struct sci_port *sci_port)
521{
522 unsigned int i;
523
524 if (!sci_port->port.dev)
525 return;
526
527 pm_runtime_get_sync(sci_port->port.dev);
528
529 for (i = 0; i < SCI_NUM_CLKS; i++) {
530 clk_prepare_enable(sci_port->clks[i]);
531 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
532 }
533 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
534}
535
536static void sci_port_disable(struct sci_port *sci_port)
537{
538 unsigned int i;
539
540 if (!sci_port->port.dev)
541 return;
542
543 /* Cancel the break timer to ensure that the timer handler will not try
544 * to access the hardware with clocks and power disabled. Reset the
545 * break flag to make the break debouncing state machine ready for the
546 * next break.
547 */
548 del_timer_sync(&sci_port->break_timer);
549 sci_port->break_flag = 0;
550
551 for (i = SCI_NUM_CLKS; i-- > 0; )
552 clk_disable_unprepare(sci_port->clks[i]);
553
554 pm_runtime_put_sync(sci_port->port.dev);
555}
556
557static inline unsigned long port_rx_irq_mask(struct uart_port *port)
558{
559 /*
560 * Not all ports (such as SCIFA) will support REIE. Rather than
561 * special-casing the port type, we check the port initialization
562 * IRQ enable mask to see whether the IRQ is desired at all. If
563 * it's unset, it's logically inferred that there's no point in
564 * testing for it.
565 */
566 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
567}
568
569static void sci_start_tx(struct uart_port *port)
570{
571 struct sci_port *s = to_sci_port(port);
572 unsigned short ctrl;
573
574#ifdef CONFIG_SERIAL_SH_SCI_DMA
575 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
576 u16 new, scr = serial_port_in(port, SCSCR);
577 if (s->chan_tx)
578 new = scr | SCSCR_TDRQE;
579 else
580 new = scr & ~SCSCR_TDRQE;
581 if (new != scr)
582 serial_port_out(port, SCSCR, new);
583 }
584
585 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
586 dma_submit_error(s->cookie_tx)) {
587 s->cookie_tx = 0;
588 schedule_work(&s->work_tx);
589 }
590#endif
591
592 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
593 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
594 ctrl = serial_port_in(port, SCSCR);
595 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
596 }
597}
598
599static void sci_stop_tx(struct uart_port *port)
600{
601 unsigned short ctrl;
602
603 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
604 ctrl = serial_port_in(port, SCSCR);
605
606 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
607 ctrl &= ~SCSCR_TDRQE;
608
609 ctrl &= ~SCSCR_TIE;
610
611 serial_port_out(port, SCSCR, ctrl);
612}
613
614static void sci_start_rx(struct uart_port *port)
615{
616 unsigned short ctrl;
617
618 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
619
620 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
621 ctrl &= ~SCSCR_RDRQE;
622
623 serial_port_out(port, SCSCR, ctrl);
624}
625
626static void sci_stop_rx(struct uart_port *port)
627{
628 unsigned short ctrl;
629
630 ctrl = serial_port_in(port, SCSCR);
631
632 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
633 ctrl &= ~SCSCR_RDRQE;
634
635 ctrl &= ~port_rx_irq_mask(port);
636
637 serial_port_out(port, SCSCR, ctrl);
638}
639
640static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
641{
642 if (port->type == PORT_SCI) {
643 /* Just store the mask */
644 serial_port_out(port, SCxSR, mask);
645 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
646 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
647 /* Only clear the status bits we want to clear */
648 serial_port_out(port, SCxSR,
649 serial_port_in(port, SCxSR) & mask);
650 } else {
651 /* Store the mask, clear parity/framing errors */
652 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
653 }
654}
655
656#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
657 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
658
659#ifdef CONFIG_CONSOLE_POLL
660static int sci_poll_get_char(struct uart_port *port)
661{
662 unsigned short status;
663 int c;
664
665 do {
666 status = serial_port_in(port, SCxSR);
667 if (status & SCxSR_ERRORS(port)) {
668 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
669 continue;
670 }
671 break;
672 } while (1);
673
674 if (!(status & SCxSR_RDxF(port)))
675 return NO_POLL_CHAR;
676
677 c = serial_port_in(port, SCxRDR);
678
679 /* Dummy read */
680 serial_port_in(port, SCxSR);
681 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
682
683 return c;
684}
685#endif
686
687static void sci_poll_put_char(struct uart_port *port, unsigned char c)
688{
689 unsigned short status;
690
691 do {
692 status = serial_port_in(port, SCxSR);
693 } while (!(status & SCxSR_TDxE(port)));
694
695 serial_port_out(port, SCxTDR, c);
696 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
697}
698#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
699 CONFIG_SERIAL_SH_SCI_EARLYCON */
700
701static void sci_init_pins(struct uart_port *port, unsigned int cflag)
702{
703 struct sci_port *s = to_sci_port(port);
704 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
705
706 /*
707 * Use port-specific handler if provided.
708 */
709 if (s->cfg->ops && s->cfg->ops->init_pins) {
710 s->cfg->ops->init_pins(port, cflag);
711 return;
712 }
713
714 /*
715 * For the generic path SCSPTR is necessary. Bail out if that's
716 * unavailable, too.
717 */
718 if (!reg->size)
719 return;
720
721 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
722 ((!(cflag & CRTSCTS)))) {
723 unsigned short status;
724
725 status = serial_port_in(port, SCSPTR);
726 status &= ~SCSPTR_CTSIO;
727 status |= SCSPTR_RTSIO;
728 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
729 }
730}
731
732static int sci_txfill(struct uart_port *port)
733{
734 const struct plat_sci_reg *reg;
735
736 reg = sci_getreg(port, SCTFDR);
737 if (reg->size)
738 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
739
740 reg = sci_getreg(port, SCFDR);
741 if (reg->size)
742 return serial_port_in(port, SCFDR) >> 8;
743
744 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
745}
746
747static int sci_txroom(struct uart_port *port)
748{
749 return port->fifosize - sci_txfill(port);
750}
751
752static int sci_rxfill(struct uart_port *port)
753{
754 const struct plat_sci_reg *reg;
755
756 reg = sci_getreg(port, SCRFDR);
757 if (reg->size)
758 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
759
760 reg = sci_getreg(port, SCFDR);
761 if (reg->size)
762 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
763
764 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
765}
766
767/*
768 * SCI helper for checking the state of the muxed port/RXD pins.
769 */
770static inline int sci_rxd_in(struct uart_port *port)
771{
772 struct sci_port *s = to_sci_port(port);
773
774 if (s->cfg->port_reg <= 0)
775 return 1;
776
777 /* Cast for ARM damage */
778 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
779}
780
781/* ********************************************************************** *
782 * the interrupt related routines *
783 * ********************************************************************** */
784
785static void sci_transmit_chars(struct uart_port *port)
786{
787 struct circ_buf *xmit = &port->state->xmit;
788 unsigned int stopped = uart_tx_stopped(port);
789 unsigned short status;
790 unsigned short ctrl;
791 int count;
792
793 status = serial_port_in(port, SCxSR);
794 if (!(status & SCxSR_TDxE(port))) {
795 ctrl = serial_port_in(port, SCSCR);
796 if (uart_circ_empty(xmit))
797 ctrl &= ~SCSCR_TIE;
798 else
799 ctrl |= SCSCR_TIE;
800 serial_port_out(port, SCSCR, ctrl);
801 return;
802 }
803
804 count = sci_txroom(port);
805
806 do {
807 unsigned char c;
808
809 if (port->x_char) {
810 c = port->x_char;
811 port->x_char = 0;
812 } else if (!uart_circ_empty(xmit) && !stopped) {
813 c = xmit->buf[xmit->tail];
814 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
815 } else {
816 break;
817 }
818
819 serial_port_out(port, SCxTDR, c);
820
821 port->icount.tx++;
822 } while (--count > 0);
823
824 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
825
826 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
827 uart_write_wakeup(port);
828 if (uart_circ_empty(xmit)) {
829 sci_stop_tx(port);
830 } else {
831 ctrl = serial_port_in(port, SCSCR);
832
833 if (port->type != PORT_SCI) {
834 serial_port_in(port, SCxSR); /* Dummy read */
835 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
836 }
837
838 ctrl |= SCSCR_TIE;
839 serial_port_out(port, SCSCR, ctrl);
840 }
841}
842
843/* On SH3, SCIF may read end-of-break as a space->mark char */
844#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
845
846static void sci_receive_chars(struct uart_port *port)
847{
848 struct sci_port *sci_port = to_sci_port(port);
849 struct tty_port *tport = &port->state->port;
850 int i, count, copied = 0;
851 unsigned short status;
852 unsigned char flag;
853
854 status = serial_port_in(port, SCxSR);
855 if (!(status & SCxSR_RDxF(port)))
856 return;
857
858 while (1) {
859 /* Don't copy more bytes than there is room for in the buffer */
860 count = tty_buffer_request_room(tport, sci_rxfill(port));
861
862 /* If for any reason we can't copy more data, we're done! */
863 if (count == 0)
864 break;
865
866 if (port->type == PORT_SCI) {
867 char c = serial_port_in(port, SCxRDR);
868 if (uart_handle_sysrq_char(port, c) ||
869 sci_port->break_flag)
870 count = 0;
871 else
872 tty_insert_flip_char(tport, c, TTY_NORMAL);
873 } else {
874 for (i = 0; i < count; i++) {
875 char c = serial_port_in(port, SCxRDR);
876
877 status = serial_port_in(port, SCxSR);
878#if defined(CONFIG_CPU_SH3)
879 /* Skip "chars" during break */
880 if (sci_port->break_flag) {
881 if ((c == 0) &&
882 (status & SCxSR_FER(port))) {
883 count--; i--;
884 continue;
885 }
886
887 /* Nonzero => end-of-break */
888 dev_dbg(port->dev, "debounce<%02x>\n", c);
889 sci_port->break_flag = 0;
890
891 if (STEPFN(c)) {
892 count--; i--;
893 continue;
894 }
895 }
896#endif /* CONFIG_CPU_SH3 */
897 if (uart_handle_sysrq_char(port, c)) {
898 count--; i--;
899 continue;
900 }
901
902 /* Store data and status */
903 if (status & SCxSR_FER(port)) {
904 flag = TTY_FRAME;
905 port->icount.frame++;
906 dev_notice(port->dev, "frame error\n");
907 } else if (status & SCxSR_PER(port)) {
908 flag = TTY_PARITY;
909 port->icount.parity++;
910 dev_notice(port->dev, "parity error\n");
911 } else
912 flag = TTY_NORMAL;
913
914 tty_insert_flip_char(tport, c, flag);
915 }
916 }
917
918 serial_port_in(port, SCxSR); /* dummy read */
919 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
920
921 copied += count;
922 port->icount.rx += count;
923 }
924
925 if (copied) {
926 /* Tell the rest of the system the news. New characters! */
927 tty_flip_buffer_push(tport);
928 } else {
929 serial_port_in(port, SCxSR); /* dummy read */
930 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
931 }
932}
933
934#define SCI_BREAK_JIFFIES (HZ/20)
935
936/*
937 * The sci generates interrupts during the break,
938 * 1 per millisecond or so during the break period, for 9600 baud.
939 * So dont bother disabling interrupts.
940 * But dont want more than 1 break event.
941 * Use a kernel timer to periodically poll the rx line until
942 * the break is finished.
943 */
944static inline void sci_schedule_break_timer(struct sci_port *port)
945{
946 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
947}
948
949/* Ensure that two consecutive samples find the break over. */
950static void sci_break_timer(unsigned long data)
951{
952 struct sci_port *port = (struct sci_port *)data;
953
954 if (sci_rxd_in(&port->port) == 0) {
955 port->break_flag = 1;
956 sci_schedule_break_timer(port);
957 } else if (port->break_flag == 1) {
958 /* break is over. */
959 port->break_flag = 2;
960 sci_schedule_break_timer(port);
961 } else
962 port->break_flag = 0;
963}
964
965static int sci_handle_errors(struct uart_port *port)
966{
967 int copied = 0;
968 unsigned short status = serial_port_in(port, SCxSR);
969 struct tty_port *tport = &port->state->port;
970 struct sci_port *s = to_sci_port(port);
971
972 /* Handle overruns */
973 if (status & s->overrun_mask) {
974 port->icount.overrun++;
975
976 /* overrun error */
977 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
978 copied++;
979
980 dev_notice(port->dev, "overrun error\n");
981 }
982
983 if (status & SCxSR_FER(port)) {
984 if (sci_rxd_in(port) == 0) {
985 /* Notify of BREAK */
986 struct sci_port *sci_port = to_sci_port(port);
987
988 if (!sci_port->break_flag) {
989 port->icount.brk++;
990
991 sci_port->break_flag = 1;
992 sci_schedule_break_timer(sci_port);
993
994 /* Do sysrq handling. */
995 if (uart_handle_break(port))
996 return 0;
997
998 dev_dbg(port->dev, "BREAK detected\n");
999
1000 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1001 copied++;
1002 }
1003
1004 } else {
1005 /* frame error */
1006 port->icount.frame++;
1007
1008 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1009 copied++;
1010
1011 dev_notice(port->dev, "frame error\n");
1012 }
1013 }
1014
1015 if (status & SCxSR_PER(port)) {
1016 /* parity error */
1017 port->icount.parity++;
1018
1019 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1020 copied++;
1021
1022 dev_notice(port->dev, "parity error\n");
1023 }
1024
1025 if (copied)
1026 tty_flip_buffer_push(tport);
1027
1028 return copied;
1029}
1030
1031static int sci_handle_fifo_overrun(struct uart_port *port)
1032{
1033 struct tty_port *tport = &port->state->port;
1034 struct sci_port *s = to_sci_port(port);
1035 const struct plat_sci_reg *reg;
1036 int copied = 0;
1037 u16 status;
1038
1039 reg = sci_getreg(port, s->overrun_reg);
1040 if (!reg->size)
1041 return 0;
1042
1043 status = serial_port_in(port, s->overrun_reg);
1044 if (status & s->overrun_mask) {
1045 status &= ~s->overrun_mask;
1046 serial_port_out(port, s->overrun_reg, status);
1047
1048 port->icount.overrun++;
1049
1050 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1051 tty_flip_buffer_push(tport);
1052
1053 dev_dbg(port->dev, "overrun error\n");
1054 copied++;
1055 }
1056
1057 return copied;
1058}
1059
1060static int sci_handle_breaks(struct uart_port *port)
1061{
1062 int copied = 0;
1063 unsigned short status = serial_port_in(port, SCxSR);
1064 struct tty_port *tport = &port->state->port;
1065 struct sci_port *s = to_sci_port(port);
1066
1067 if (uart_handle_break(port))
1068 return 0;
1069
1070 if (!s->break_flag && status & SCxSR_BRK(port)) {
1071#if defined(CONFIG_CPU_SH3)
1072 /* Debounce break */
1073 s->break_flag = 1;
1074#endif
1075
1076 port->icount.brk++;
1077
1078 /* Notify of BREAK */
1079 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1080 copied++;
1081
1082 dev_dbg(port->dev, "BREAK detected\n");
1083 }
1084
1085 if (copied)
1086 tty_flip_buffer_push(tport);
1087
1088 copied += sci_handle_fifo_overrun(port);
1089
1090 return copied;
1091}
1092
1093#ifdef CONFIG_SERIAL_SH_SCI_DMA
1094static void sci_dma_tx_complete(void *arg)
1095{
1096 struct sci_port *s = arg;
1097 struct uart_port *port = &s->port;
1098 struct circ_buf *xmit = &port->state->xmit;
1099 unsigned long flags;
1100
1101 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1102
1103 spin_lock_irqsave(&port->lock, flags);
1104
1105 xmit->tail += s->tx_dma_len;
1106 xmit->tail &= UART_XMIT_SIZE - 1;
1107
1108 port->icount.tx += s->tx_dma_len;
1109
1110 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1111 uart_write_wakeup(port);
1112
1113 if (!uart_circ_empty(xmit)) {
1114 s->cookie_tx = 0;
1115 schedule_work(&s->work_tx);
1116 } else {
1117 s->cookie_tx = -EINVAL;
1118 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1119 u16 ctrl = serial_port_in(port, SCSCR);
1120 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1121 }
1122 }
1123
1124 spin_unlock_irqrestore(&port->lock, flags);
1125}
1126
1127/* Locking: called with port lock held */
1128static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1129{
1130 struct uart_port *port = &s->port;
1131 struct tty_port *tport = &port->state->port;
1132 int copied;
1133
1134 copied = tty_insert_flip_string(tport, buf, count);
1135 if (copied < count) {
1136 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1137 count - copied);
1138 port->icount.buf_overrun++;
1139 }
1140
1141 port->icount.rx += copied;
1142
1143 return copied;
1144}
1145
1146static int sci_dma_rx_find_active(struct sci_port *s)
1147{
1148 unsigned int i;
1149
1150 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1151 if (s->active_rx == s->cookie_rx[i])
1152 return i;
1153
1154 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1155 s->active_rx);
1156 return -1;
1157}
1158
1159static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1160{
1161 struct dma_chan *chan = s->chan_rx;
1162 struct uart_port *port = &s->port;
1163 unsigned long flags;
1164
1165 spin_lock_irqsave(&port->lock, flags);
1166 s->chan_rx = NULL;
1167 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1168 spin_unlock_irqrestore(&port->lock, flags);
1169 dmaengine_terminate_all(chan);
1170 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1171 sg_dma_address(&s->sg_rx[0]));
1172 dma_release_channel(chan);
1173 if (enable_pio)
1174 sci_start_rx(port);
1175}
1176
1177static void sci_dma_rx_complete(void *arg)
1178{
1179 struct sci_port *s = arg;
1180 struct dma_chan *chan = s->chan_rx;
1181 struct uart_port *port = &s->port;
1182 struct dma_async_tx_descriptor *desc;
1183 unsigned long flags;
1184 int active, count = 0;
1185
1186 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1187 s->active_rx);
1188
1189 spin_lock_irqsave(&port->lock, flags);
1190
1191 active = sci_dma_rx_find_active(s);
1192 if (active >= 0)
1193 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1194
1195 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1196
1197 if (count)
1198 tty_flip_buffer_push(&port->state->port);
1199
1200 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1201 DMA_DEV_TO_MEM,
1202 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1203 if (!desc)
1204 goto fail;
1205
1206 desc->callback = sci_dma_rx_complete;
1207 desc->callback_param = s;
1208 s->cookie_rx[active] = dmaengine_submit(desc);
1209 if (dma_submit_error(s->cookie_rx[active]))
1210 goto fail;
1211
1212 s->active_rx = s->cookie_rx[!active];
1213
1214 dma_async_issue_pending(chan);
1215
1216 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1217 __func__, s->cookie_rx[active], active, s->active_rx);
1218 spin_unlock_irqrestore(&port->lock, flags);
1219 return;
1220
1221fail:
1222 spin_unlock_irqrestore(&port->lock, flags);
1223 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1224 sci_rx_dma_release(s, true);
1225}
1226
1227static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1228{
1229 struct dma_chan *chan = s->chan_tx;
1230 struct uart_port *port = &s->port;
1231 unsigned long flags;
1232
1233 spin_lock_irqsave(&port->lock, flags);
1234 s->chan_tx = NULL;
1235 s->cookie_tx = -EINVAL;
1236 spin_unlock_irqrestore(&port->lock, flags);
1237 dmaengine_terminate_all(chan);
1238 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1239 DMA_TO_DEVICE);
1240 dma_release_channel(chan);
1241 if (enable_pio)
1242 sci_start_tx(port);
1243}
1244
1245static void sci_submit_rx(struct sci_port *s)
1246{
1247 struct dma_chan *chan = s->chan_rx;
1248 int i;
1249
1250 for (i = 0; i < 2; i++) {
1251 struct scatterlist *sg = &s->sg_rx[i];
1252 struct dma_async_tx_descriptor *desc;
1253
1254 desc = dmaengine_prep_slave_sg(chan,
1255 sg, 1, DMA_DEV_TO_MEM,
1256 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1257 if (!desc)
1258 goto fail;
1259
1260 desc->callback = sci_dma_rx_complete;
1261 desc->callback_param = s;
1262 s->cookie_rx[i] = dmaengine_submit(desc);
1263 if (dma_submit_error(s->cookie_rx[i]))
1264 goto fail;
1265
1266 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1267 s->cookie_rx[i], i);
1268 }
1269
1270 s->active_rx = s->cookie_rx[0];
1271
1272 dma_async_issue_pending(chan);
1273 return;
1274
1275fail:
1276 if (i)
1277 dmaengine_terminate_all(chan);
1278 for (i = 0; i < 2; i++)
1279 s->cookie_rx[i] = -EINVAL;
1280 s->active_rx = -EINVAL;
1281 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1282 sci_rx_dma_release(s, true);
1283}
1284
1285static void work_fn_tx(struct work_struct *work)
1286{
1287 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1288 struct dma_async_tx_descriptor *desc;
1289 struct dma_chan *chan = s->chan_tx;
1290 struct uart_port *port = &s->port;
1291 struct circ_buf *xmit = &port->state->xmit;
1292 dma_addr_t buf;
1293
1294 /*
1295 * DMA is idle now.
1296 * Port xmit buffer is already mapped, and it is one page... Just adjust
1297 * offsets and lengths. Since it is a circular buffer, we have to
1298 * transmit till the end, and then the rest. Take the port lock to get a
1299 * consistent xmit buffer state.
1300 */
1301 spin_lock_irq(&port->lock);
1302 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1303 s->tx_dma_len = min_t(unsigned int,
1304 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1305 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1306 spin_unlock_irq(&port->lock);
1307
1308 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1309 DMA_MEM_TO_DEV,
1310 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1311 if (!desc) {
1312 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1313 /* switch to PIO */
1314 sci_tx_dma_release(s, true);
1315 return;
1316 }
1317
1318 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1319 DMA_TO_DEVICE);
1320
1321 spin_lock_irq(&port->lock);
1322 desc->callback = sci_dma_tx_complete;
1323 desc->callback_param = s;
1324 spin_unlock_irq(&port->lock);
1325 s->cookie_tx = dmaengine_submit(desc);
1326 if (dma_submit_error(s->cookie_tx)) {
1327 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1328 /* switch to PIO */
1329 sci_tx_dma_release(s, true);
1330 return;
1331 }
1332
1333 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1334 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1335
1336 dma_async_issue_pending(chan);
1337}
1338
1339static void rx_timer_fn(unsigned long arg)
1340{
1341 struct sci_port *s = (struct sci_port *)arg;
1342 struct dma_chan *chan = s->chan_rx;
1343 struct uart_port *port = &s->port;
1344 struct dma_tx_state state;
1345 enum dma_status status;
1346 unsigned long flags;
1347 unsigned int read;
1348 int active, count;
1349 u16 scr;
1350
1351 spin_lock_irqsave(&port->lock, flags);
1352
1353 dev_dbg(port->dev, "DMA Rx timed out\n");
1354
1355 active = sci_dma_rx_find_active(s);
1356 if (active < 0) {
1357 spin_unlock_irqrestore(&port->lock, flags);
1358 return;
1359 }
1360
1361 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1362 if (status == DMA_COMPLETE) {
1363 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1364 s->active_rx, active);
1365 spin_unlock_irqrestore(&port->lock, flags);
1366
1367 /* Let packet complete handler take care of the packet */
1368 return;
1369 }
1370
1371 dmaengine_pause(chan);
1372
1373 /*
1374 * sometimes DMA transfer doesn't stop even if it is stopped and
1375 * data keeps on coming until transaction is complete so check
1376 * for DMA_COMPLETE again
1377 * Let packet complete handler take care of the packet
1378 */
1379 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1380 if (status == DMA_COMPLETE) {
1381 spin_unlock_irqrestore(&port->lock, flags);
1382 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1383 return;
1384 }
1385
1386 /* Handle incomplete DMA receive */
1387 dmaengine_terminate_all(s->chan_rx);
1388 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1389 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1390 s->active_rx);
1391
1392 if (read) {
1393 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1394 if (count)
1395 tty_flip_buffer_push(&port->state->port);
1396 }
1397
1398 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1399 sci_submit_rx(s);
1400
1401 /* Direct new serial port interrupts back to CPU */
1402 scr = serial_port_in(port, SCSCR);
1403 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1404 scr &= ~SCSCR_RDRQE;
1405 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1406 }
1407 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1408
1409 spin_unlock_irqrestore(&port->lock, flags);
1410}
1411
1412static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1413 enum dma_transfer_direction dir,
1414 unsigned int id)
1415{
1416 dma_cap_mask_t mask;
1417 struct dma_chan *chan;
1418 struct dma_slave_config cfg;
1419 int ret;
1420
1421 dma_cap_zero(mask);
1422 dma_cap_set(DMA_SLAVE, mask);
1423
1424 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1425 (void *)(unsigned long)id, port->dev,
1426 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1427 if (!chan) {
1428 dev_warn(port->dev,
1429 "dma_request_slave_channel_compat failed\n");
1430 return NULL;
1431 }
1432
1433 memset(&cfg, 0, sizeof(cfg));
1434 cfg.direction = dir;
1435 if (dir == DMA_MEM_TO_DEV) {
1436 cfg.dst_addr = port->mapbase +
1437 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1438 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1439 } else {
1440 cfg.src_addr = port->mapbase +
1441 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1442 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1443 }
1444
1445 ret = dmaengine_slave_config(chan, &cfg);
1446 if (ret) {
1447 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1448 dma_release_channel(chan);
1449 return NULL;
1450 }
1451
1452 return chan;
1453}
1454
1455static void sci_request_dma(struct uart_port *port)
1456{
1457 struct sci_port *s = to_sci_port(port);
1458 struct dma_chan *chan;
1459
1460 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1461
1462 if (!port->dev->of_node &&
1463 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1464 return;
1465
1466 s->cookie_tx = -EINVAL;
1467 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1468 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1469 if (chan) {
1470 s->chan_tx = chan;
1471 /* UART circular tx buffer is an aligned page. */
1472 s->tx_dma_addr = dma_map_single(chan->device->dev,
1473 port->state->xmit.buf,
1474 UART_XMIT_SIZE,
1475 DMA_TO_DEVICE);
1476 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1477 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1478 dma_release_channel(chan);
1479 s->chan_tx = NULL;
1480 } else {
1481 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1482 __func__, UART_XMIT_SIZE,
1483 port->state->xmit.buf, &s->tx_dma_addr);
1484 }
1485
1486 INIT_WORK(&s->work_tx, work_fn_tx);
1487 }
1488
1489 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1490 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1491 if (chan) {
1492 unsigned int i;
1493 dma_addr_t dma;
1494 void *buf;
1495
1496 s->chan_rx = chan;
1497
1498 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1499 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1500 &dma, GFP_KERNEL);
1501 if (!buf) {
1502 dev_warn(port->dev,
1503 "Failed to allocate Rx dma buffer, using PIO\n");
1504 dma_release_channel(chan);
1505 s->chan_rx = NULL;
1506 return;
1507 }
1508
1509 for (i = 0; i < 2; i++) {
1510 struct scatterlist *sg = &s->sg_rx[i];
1511
1512 sg_init_table(sg, 1);
1513 s->rx_buf[i] = buf;
1514 sg_dma_address(sg) = dma;
1515 sg_dma_len(sg) = s->buf_len_rx;
1516
1517 buf += s->buf_len_rx;
1518 dma += s->buf_len_rx;
1519 }
1520
1521 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1522
1523 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1524 sci_submit_rx(s);
1525 }
1526}
1527
1528static void sci_free_dma(struct uart_port *port)
1529{
1530 struct sci_port *s = to_sci_port(port);
1531
1532 if (s->chan_tx)
1533 sci_tx_dma_release(s, false);
1534 if (s->chan_rx)
1535 sci_rx_dma_release(s, false);
1536}
1537#else
1538static inline void sci_request_dma(struct uart_port *port)
1539{
1540}
1541
1542static inline void sci_free_dma(struct uart_port *port)
1543{
1544}
1545#endif
1546
1547static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1548{
1549#ifdef CONFIG_SERIAL_SH_SCI_DMA
1550 struct uart_port *port = ptr;
1551 struct sci_port *s = to_sci_port(port);
1552
1553 if (s->chan_rx) {
1554 u16 scr = serial_port_in(port, SCSCR);
1555 u16 ssr = serial_port_in(port, SCxSR);
1556
1557 /* Disable future Rx interrupts */
1558 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1559 disable_irq_nosync(irq);
1560 scr |= SCSCR_RDRQE;
1561 } else {
1562 scr &= ~SCSCR_RIE;
1563 sci_submit_rx(s);
1564 }
1565 serial_port_out(port, SCSCR, scr);
1566 /* Clear current interrupt */
1567 serial_port_out(port, SCxSR,
1568 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1569 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1570 jiffies, s->rx_timeout);
1571 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1572
1573 return IRQ_HANDLED;
1574 }
1575#endif
1576
1577 /* I think sci_receive_chars has to be called irrespective
1578 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1579 * to be disabled?
1580 */
1581 sci_receive_chars(ptr);
1582
1583 return IRQ_HANDLED;
1584}
1585
1586static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1587{
1588 struct uart_port *port = ptr;
1589 unsigned long flags;
1590
1591 spin_lock_irqsave(&port->lock, flags);
1592 sci_transmit_chars(port);
1593 spin_unlock_irqrestore(&port->lock, flags);
1594
1595 return IRQ_HANDLED;
1596}
1597
1598static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1599{
1600 struct uart_port *port = ptr;
1601 struct sci_port *s = to_sci_port(port);
1602
1603 /* Handle errors */
1604 if (port->type == PORT_SCI) {
1605 if (sci_handle_errors(port)) {
1606 /* discard character in rx buffer */
1607 serial_port_in(port, SCxSR);
1608 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1609 }
1610 } else {
1611 sci_handle_fifo_overrun(port);
1612 if (!s->chan_rx)
1613 sci_receive_chars(ptr);
1614 }
1615
1616 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1617
1618 /* Kick the transmission */
1619 if (!s->chan_tx)
1620 sci_tx_interrupt(irq, ptr);
1621
1622 return IRQ_HANDLED;
1623}
1624
1625static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1626{
1627 struct uart_port *port = ptr;
1628
1629 /* Handle BREAKs */
1630 sci_handle_breaks(port);
1631 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1632
1633 return IRQ_HANDLED;
1634}
1635
1636static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1637{
1638 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1639 struct uart_port *port = ptr;
1640 struct sci_port *s = to_sci_port(port);
1641 irqreturn_t ret = IRQ_NONE;
1642
1643 ssr_status = serial_port_in(port, SCxSR);
1644 scr_status = serial_port_in(port, SCSCR);
1645 if (s->overrun_reg == SCxSR)
1646 orer_status = ssr_status;
1647 else {
1648 if (sci_getreg(port, s->overrun_reg)->size)
1649 orer_status = serial_port_in(port, s->overrun_reg);
1650 }
1651
1652 err_enabled = scr_status & port_rx_irq_mask(port);
1653
1654 /* Tx Interrupt */
1655 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1656 !s->chan_tx)
1657 ret = sci_tx_interrupt(irq, ptr);
1658
1659 /*
1660 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1661 * DR flags
1662 */
1663 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1664 (scr_status & SCSCR_RIE))
1665 ret = sci_rx_interrupt(irq, ptr);
1666
1667 /* Error Interrupt */
1668 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1669 ret = sci_er_interrupt(irq, ptr);
1670
1671 /* Break Interrupt */
1672 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1673 ret = sci_br_interrupt(irq, ptr);
1674
1675 /* Overrun Interrupt */
1676 if (orer_status & s->overrun_mask) {
1677 sci_handle_fifo_overrun(port);
1678 ret = IRQ_HANDLED;
1679 }
1680
1681 return ret;
1682}
1683
1684static const struct sci_irq_desc {
1685 const char *desc;
1686 irq_handler_t handler;
1687} sci_irq_desc[] = {
1688 /*
1689 * Split out handlers, the default case.
1690 */
1691 [SCIx_ERI_IRQ] = {
1692 .desc = "rx err",
1693 .handler = sci_er_interrupt,
1694 },
1695
1696 [SCIx_RXI_IRQ] = {
1697 .desc = "rx full",
1698 .handler = sci_rx_interrupt,
1699 },
1700
1701 [SCIx_TXI_IRQ] = {
1702 .desc = "tx empty",
1703 .handler = sci_tx_interrupt,
1704 },
1705
1706 [SCIx_BRI_IRQ] = {
1707 .desc = "break",
1708 .handler = sci_br_interrupt,
1709 },
1710
1711 /*
1712 * Special muxed handler.
1713 */
1714 [SCIx_MUX_IRQ] = {
1715 .desc = "mux",
1716 .handler = sci_mpxed_interrupt,
1717 },
1718};
1719
1720static int sci_request_irq(struct sci_port *port)
1721{
1722 struct uart_port *up = &port->port;
1723 int i, j, ret = 0;
1724
1725 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1726 const struct sci_irq_desc *desc;
1727 int irq;
1728
1729 if (SCIx_IRQ_IS_MUXED(port)) {
1730 i = SCIx_MUX_IRQ;
1731 irq = up->irq;
1732 } else {
1733 irq = port->irqs[i];
1734
1735 /*
1736 * Certain port types won't support all of the
1737 * available interrupt sources.
1738 */
1739 if (unlikely(irq < 0))
1740 continue;
1741 }
1742
1743 desc = sci_irq_desc + i;
1744 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1745 dev_name(up->dev), desc->desc);
1746 if (!port->irqstr[j])
1747 goto out_nomem;
1748
1749 ret = request_irq(irq, desc->handler, up->irqflags,
1750 port->irqstr[j], port);
1751 if (unlikely(ret)) {
1752 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1753 goto out_noirq;
1754 }
1755 }
1756
1757 return 0;
1758
1759out_noirq:
1760 while (--i >= 0)
1761 free_irq(port->irqs[i], port);
1762
1763out_nomem:
1764 while (--j >= 0)
1765 kfree(port->irqstr[j]);
1766
1767 return ret;
1768}
1769
1770static void sci_free_irq(struct sci_port *port)
1771{
1772 int i;
1773
1774 /*
1775 * Intentionally in reverse order so we iterate over the muxed
1776 * IRQ first.
1777 */
1778 for (i = 0; i < SCIx_NR_IRQS; i++) {
1779 int irq = port->irqs[i];
1780
1781 /*
1782 * Certain port types won't support all of the available
1783 * interrupt sources.
1784 */
1785 if (unlikely(irq < 0))
1786 continue;
1787
1788 free_irq(port->irqs[i], port);
1789 kfree(port->irqstr[i]);
1790
1791 if (SCIx_IRQ_IS_MUXED(port)) {
1792 /* If there's only one IRQ, we're done. */
1793 return;
1794 }
1795 }
1796}
1797
1798static unsigned int sci_tx_empty(struct uart_port *port)
1799{
1800 unsigned short status = serial_port_in(port, SCxSR);
1801 unsigned short in_tx_fifo = sci_txfill(port);
1802
1803 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1804}
1805
1806/*
1807 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1808 * CTS/RTS is supported in hardware by at least one port and controlled
1809 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1810 * handled via the ->init_pins() op, which is a bit of a one-way street,
1811 * lacking any ability to defer pin control -- this will later be
1812 * converted over to the GPIO framework).
1813 *
1814 * Other modes (such as loopback) are supported generically on certain
1815 * port types, but not others. For these it's sufficient to test for the
1816 * existence of the support register and simply ignore the port type.
1817 */
1818static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1819{
1820 if (mctrl & TIOCM_LOOP) {
1821 const struct plat_sci_reg *reg;
1822
1823 /*
1824 * Standard loopback mode for SCFCR ports.
1825 */
1826 reg = sci_getreg(port, SCFCR);
1827 if (reg->size)
1828 serial_port_out(port, SCFCR,
1829 serial_port_in(port, SCFCR) |
1830 SCFCR_LOOP);
1831 }
1832}
1833
1834static unsigned int sci_get_mctrl(struct uart_port *port)
1835{
1836 /*
1837 * CTS/RTS is handled in hardware when supported, while nothing
1838 * else is wired up. Keep it simple and simply assert DSR/CAR.
1839 */
1840 return TIOCM_DSR | TIOCM_CAR;
1841}
1842
1843static void sci_break_ctl(struct uart_port *port, int break_state)
1844{
1845 struct sci_port *s = to_sci_port(port);
1846 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1847 unsigned short scscr, scsptr;
1848
1849 /* check wheter the port has SCSPTR */
1850 if (!reg->size) {
1851 /*
1852 * Not supported by hardware. Most parts couple break and rx
1853 * interrupts together, with break detection always enabled.
1854 */
1855 return;
1856 }
1857
1858 scsptr = serial_port_in(port, SCSPTR);
1859 scscr = serial_port_in(port, SCSCR);
1860
1861 if (break_state == -1) {
1862 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1863 scscr &= ~SCSCR_TE;
1864 } else {
1865 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1866 scscr |= SCSCR_TE;
1867 }
1868
1869 serial_port_out(port, SCSPTR, scsptr);
1870 serial_port_out(port, SCSCR, scscr);
1871}
1872
1873static int sci_startup(struct uart_port *port)
1874{
1875 struct sci_port *s = to_sci_port(port);
1876 unsigned long flags;
1877 int ret;
1878
1879 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1880
1881 ret = sci_request_irq(s);
1882 if (unlikely(ret < 0))
1883 return ret;
1884
1885 sci_request_dma(port);
1886
1887 spin_lock_irqsave(&port->lock, flags);
1888 sci_start_tx(port);
1889 sci_start_rx(port);
1890 spin_unlock_irqrestore(&port->lock, flags);
1891
1892 return 0;
1893}
1894
1895static void sci_shutdown(struct uart_port *port)
1896{
1897 struct sci_port *s = to_sci_port(port);
1898 unsigned long flags;
1899
1900 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1901
1902 spin_lock_irqsave(&port->lock, flags);
1903 sci_stop_rx(port);
1904 sci_stop_tx(port);
1905 spin_unlock_irqrestore(&port->lock, flags);
1906
1907#ifdef CONFIG_SERIAL_SH_SCI_DMA
1908 if (s->chan_rx) {
1909 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1910 port->line);
1911 del_timer_sync(&s->rx_timer);
1912 }
1913#endif
1914
1915 sci_free_dma(port);
1916 sci_free_irq(s);
1917}
1918
1919static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1920 unsigned int *srr)
1921{
1922 unsigned long freq = s->clk_rates[SCI_SCK];
1923 int err, min_err = INT_MAX;
1924 unsigned int sr;
1925
1926 if (s->port.type != PORT_HSCIF)
1927 freq *= 2;
1928
1929 for_each_sr(sr, s) {
1930 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1931 if (abs(err) >= abs(min_err))
1932 continue;
1933
1934 min_err = err;
1935 *srr = sr - 1;
1936
1937 if (!err)
1938 break;
1939 }
1940
1941 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1942 *srr + 1);
1943 return min_err;
1944}
1945
1946static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1947 unsigned long freq, unsigned int *dlr,
1948 unsigned int *srr)
1949{
1950 int err, min_err = INT_MAX;
1951 unsigned int sr, dl;
1952
1953 if (s->port.type != PORT_HSCIF)
1954 freq *= 2;
1955
1956 for_each_sr(sr, s) {
1957 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1958 dl = clamp(dl, 1U, 65535U);
1959
1960 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1961 if (abs(err) >= abs(min_err))
1962 continue;
1963
1964 min_err = err;
1965 *dlr = dl;
1966 *srr = sr - 1;
1967
1968 if (!err)
1969 break;
1970 }
1971
1972 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1973 min_err, *dlr, *srr + 1);
1974 return min_err;
1975}
1976
1977/* calculate sample rate, BRR, and clock select */
1978static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1979 unsigned int *brr, unsigned int *srr,
1980 unsigned int *cks)
1981{
1982 unsigned long freq = s->clk_rates[SCI_FCK];
1983 unsigned int sr, br, prediv, scrate, c;
1984 int err, min_err = INT_MAX;
1985
1986 if (s->port.type != PORT_HSCIF)
1987 freq *= 2;
1988
1989 /*
1990 * Find the combination of sample rate and clock select with the
1991 * smallest deviation from the desired baud rate.
1992 * Prefer high sample rates to maximise the receive margin.
1993 *
1994 * M: Receive margin (%)
1995 * N: Ratio of bit rate to clock (N = sampling rate)
1996 * D: Clock duty (D = 0 to 1.0)
1997 * L: Frame length (L = 9 to 12)
1998 * F: Absolute value of clock frequency deviation
1999 *
2000 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2001 * (|D - 0.5| / N * (1 + F))|
2002 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2003 */
2004 for_each_sr(sr, s) {
2005 for (c = 0; c <= 3; c++) {
2006 /* integerized formulas from HSCIF documentation */
2007 prediv = sr * (1 << (2 * c + 1));
2008
2009 /*
2010 * We need to calculate:
2011 *
2012 * br = freq / (prediv * bps) clamped to [1..256]
2013 * err = freq / (br * prediv) - bps
2014 *
2015 * Watch out for overflow when calculating the desired
2016 * sampling clock rate!
2017 */
2018 if (bps > UINT_MAX / prediv)
2019 break;
2020
2021 scrate = prediv * bps;
2022 br = DIV_ROUND_CLOSEST(freq, scrate);
2023 br = clamp(br, 1U, 256U);
2024
2025 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2026 if (abs(err) >= abs(min_err))
2027 continue;
2028
2029 min_err = err;
2030 *brr = br - 1;
2031 *srr = sr - 1;
2032 *cks = c;
2033
2034 if (!err)
2035 goto found;
2036 }
2037 }
2038
2039found:
2040 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2041 min_err, *brr, *srr + 1, *cks);
2042 return min_err;
2043}
2044
2045static void sci_reset(struct uart_port *port)
2046{
2047 const struct plat_sci_reg *reg;
2048 unsigned int status;
2049
2050 do {
2051 status = serial_port_in(port, SCxSR);
2052 } while (!(status & SCxSR_TEND(port)));
2053
2054 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2055
2056 reg = sci_getreg(port, SCFCR);
2057 if (reg->size)
2058 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2059}
2060
2061static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2062 struct ktermios *old)
2063{
2064 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2065 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2066 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2067 struct sci_port *s = to_sci_port(port);
2068 const struct plat_sci_reg *reg;
2069 int min_err = INT_MAX, err;
2070 unsigned long max_freq = 0;
2071 int best_clk = -1;
2072
2073 if ((termios->c_cflag & CSIZE) == CS7)
2074 smr_val |= SCSMR_CHR;
2075 if (termios->c_cflag & PARENB)
2076 smr_val |= SCSMR_PE;
2077 if (termios->c_cflag & PARODD)
2078 smr_val |= SCSMR_PE | SCSMR_ODD;
2079 if (termios->c_cflag & CSTOPB)
2080 smr_val |= SCSMR_STOP;
2081
2082 /*
2083 * earlyprintk comes here early on with port->uartclk set to zero.
2084 * the clock framework is not up and running at this point so here
2085 * we assume that 115200 is the maximum baud rate. please note that
2086 * the baud rate is not programmed during earlyprintk - it is assumed
2087 * that the previous boot loader has enabled required clocks and
2088 * setup the baud rate generator hardware for us already.
2089 */
2090 if (!port->uartclk) {
2091 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2092 goto done;
2093 }
2094
2095 for (i = 0; i < SCI_NUM_CLKS; i++)
2096 max_freq = max(max_freq, s->clk_rates[i]);
2097
2098 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2099 if (!baud)
2100 goto done;
2101
2102 /*
2103 * There can be multiple sources for the sampling clock. Find the one
2104 * that gives us the smallest deviation from the desired baud rate.
2105 */
2106
2107 /* Optional Undivided External Clock */
2108 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2109 port->type != PORT_SCIFB) {
2110 err = sci_sck_calc(s, baud, &srr1);
2111 if (abs(err) < abs(min_err)) {
2112 best_clk = SCI_SCK;
2113 scr_val = SCSCR_CKE1;
2114 sccks = SCCKS_CKS;
2115 min_err = err;
2116 srr = srr1;
2117 if (!err)
2118 goto done;
2119 }
2120 }
2121
2122 /* Optional BRG Frequency Divided External Clock */
2123 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2124 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2125 &srr1);
2126 if (abs(err) < abs(min_err)) {
2127 best_clk = SCI_SCIF_CLK;
2128 scr_val = SCSCR_CKE1;
2129 sccks = 0;
2130 min_err = err;
2131 dl = dl1;
2132 srr = srr1;
2133 if (!err)
2134 goto done;
2135 }
2136 }
2137
2138 /* Optional BRG Frequency Divided Internal Clock */
2139 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2140 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2141 &srr1);
2142 if (abs(err) < abs(min_err)) {
2143 best_clk = SCI_BRG_INT;
2144 scr_val = SCSCR_CKE1;
2145 sccks = SCCKS_XIN;
2146 min_err = err;
2147 dl = dl1;
2148 srr = srr1;
2149 if (!min_err)
2150 goto done;
2151 }
2152 }
2153
2154 /* Divided Functional Clock using standard Bit Rate Register */
2155 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2156 if (abs(err) < abs(min_err)) {
2157 best_clk = SCI_FCK;
2158 scr_val = 0;
2159 min_err = err;
2160 brr = brr1;
2161 srr = srr1;
2162 cks = cks1;
2163 }
2164
2165done:
2166 if (best_clk >= 0)
2167 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2168 s->clks[best_clk], baud, min_err);
2169
2170 sci_port_enable(s);
2171
2172 /*
2173 * Program the optional External Baud Rate Generator (BRG) first.
2174 * It controls the mux to select (H)SCK or frequency divided clock.
2175 */
2176 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2177 serial_port_out(port, SCDL, dl);
2178 serial_port_out(port, SCCKS, sccks);
2179 }
2180
2181 sci_reset(port);
2182
2183 uart_update_timeout(port, termios->c_cflag, baud);
2184
2185 if (best_clk >= 0) {
2186 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2187 switch (srr + 1) {
2188 case 5: smr_val |= SCSMR_SRC_5; break;
2189 case 7: smr_val |= SCSMR_SRC_7; break;
2190 case 11: smr_val |= SCSMR_SRC_11; break;
2191 case 13: smr_val |= SCSMR_SRC_13; break;
2192 case 16: smr_val |= SCSMR_SRC_16; break;
2193 case 17: smr_val |= SCSMR_SRC_17; break;
2194 case 19: smr_val |= SCSMR_SRC_19; break;
2195 case 27: smr_val |= SCSMR_SRC_27; break;
2196 }
2197 smr_val |= cks;
2198 dev_dbg(port->dev,
2199 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2200 scr_val, smr_val, brr, sccks, dl, srr);
2201 serial_port_out(port, SCSCR, scr_val);
2202 serial_port_out(port, SCSMR, smr_val);
2203 serial_port_out(port, SCBRR, brr);
2204 if (sci_getreg(port, HSSRR)->size)
2205 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2206
2207 /* Wait one bit interval */
2208 udelay((1000000 + (baud - 1)) / baud);
2209 } else {
2210 /* Don't touch the bit rate configuration */
2211 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2212 smr_val |= serial_port_in(port, SCSMR) &
2213 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2214 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2215 serial_port_out(port, SCSCR, scr_val);
2216 serial_port_out(port, SCSMR, smr_val);
2217 }
2218
2219 sci_init_pins(port, termios->c_cflag);
2220
2221 reg = sci_getreg(port, SCFCR);
2222 if (reg->size) {
2223 unsigned short ctrl = serial_port_in(port, SCFCR);
2224
2225 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2226 if (termios->c_cflag & CRTSCTS)
2227 ctrl |= SCFCR_MCE;
2228 else
2229 ctrl &= ~SCFCR_MCE;
2230 }
2231
2232 /*
2233 * As we've done a sci_reset() above, ensure we don't
2234 * interfere with the FIFOs while toggling MCE. As the
2235 * reset values could still be set, simply mask them out.
2236 */
2237 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2238
2239 serial_port_out(port, SCFCR, ctrl);
2240 }
2241
2242 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2243 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2244 serial_port_out(port, SCSCR, scr_val);
2245 if ((srr + 1 == 5) &&
2246 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2247 /*
2248 * In asynchronous mode, when the sampling rate is 1/5, first
2249 * received data may become invalid on some SCIFA and SCIFB.
2250 * To avoid this problem wait more than 1 serial data time (1
2251 * bit time x serial data number) after setting SCSCR.RE = 1.
2252 */
2253 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2254 }
2255
2256#ifdef CONFIG_SERIAL_SH_SCI_DMA
2257 /*
2258 * Calculate delay for 2 DMA buffers (4 FIFO).
2259 * See serial_core.c::uart_update_timeout().
2260 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2261 * function calculates 1 jiffie for the data plus 5 jiffies for the
2262 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2263 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2264 * value obtained by this formula is too small. Therefore, if the value
2265 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2266 */
2267 if (s->chan_rx) {
2268 unsigned int bits;
2269
2270 /* byte size and parity */
2271 switch (termios->c_cflag & CSIZE) {
2272 case CS5:
2273 bits = 7;
2274 break;
2275 case CS6:
2276 bits = 8;
2277 break;
2278 case CS7:
2279 bits = 9;
2280 break;
2281 default:
2282 bits = 10;
2283 break;
2284 }
2285
2286 if (termios->c_cflag & CSTOPB)
2287 bits++;
2288 if (termios->c_cflag & PARENB)
2289 bits++;
2290 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2291 (baud / 10), 10);
2292 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2293 s->rx_timeout * 1000 / HZ, port->timeout);
2294 if (s->rx_timeout < msecs_to_jiffies(20))
2295 s->rx_timeout = msecs_to_jiffies(20);
2296 }
2297#endif
2298
2299 if ((termios->c_cflag & CREAD) != 0)
2300 sci_start_rx(port);
2301
2302 sci_port_disable(s);
2303}
2304
2305static void sci_pm(struct uart_port *port, unsigned int state,
2306 unsigned int oldstate)
2307{
2308 struct sci_port *sci_port = to_sci_port(port);
2309
2310 switch (state) {
2311 case UART_PM_STATE_OFF:
2312 sci_port_disable(sci_port);
2313 break;
2314 default:
2315 sci_port_enable(sci_port);
2316 break;
2317 }
2318}
2319
2320static const char *sci_type(struct uart_port *port)
2321{
2322 switch (port->type) {
2323 case PORT_IRDA:
2324 return "irda";
2325 case PORT_SCI:
2326 return "sci";
2327 case PORT_SCIF:
2328 return "scif";
2329 case PORT_SCIFA:
2330 return "scifa";
2331 case PORT_SCIFB:
2332 return "scifb";
2333 case PORT_HSCIF:
2334 return "hscif";
2335 }
2336
2337 return NULL;
2338}
2339
2340static int sci_remap_port(struct uart_port *port)
2341{
2342 struct sci_port *sport = to_sci_port(port);
2343
2344 /*
2345 * Nothing to do if there's already an established membase.
2346 */
2347 if (port->membase)
2348 return 0;
2349
2350 if (port->flags & UPF_IOREMAP) {
2351 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2352 if (unlikely(!port->membase)) {
2353 dev_err(port->dev, "can't remap port#%d\n", port->line);
2354 return -ENXIO;
2355 }
2356 } else {
2357 /*
2358 * For the simple (and majority of) cases where we don't
2359 * need to do any remapping, just cast the cookie
2360 * directly.
2361 */
2362 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2363 }
2364
2365 return 0;
2366}
2367
2368static void sci_release_port(struct uart_port *port)
2369{
2370 struct sci_port *sport = to_sci_port(port);
2371
2372 if (port->flags & UPF_IOREMAP) {
2373 iounmap(port->membase);
2374 port->membase = NULL;
2375 }
2376
2377 release_mem_region(port->mapbase, sport->reg_size);
2378}
2379
2380static int sci_request_port(struct uart_port *port)
2381{
2382 struct resource *res;
2383 struct sci_port *sport = to_sci_port(port);
2384 int ret;
2385
2386 res = request_mem_region(port->mapbase, sport->reg_size,
2387 dev_name(port->dev));
2388 if (unlikely(res == NULL)) {
2389 dev_err(port->dev, "request_mem_region failed.");
2390 return -EBUSY;
2391 }
2392
2393 ret = sci_remap_port(port);
2394 if (unlikely(ret != 0)) {
2395 release_resource(res);
2396 return ret;
2397 }
2398
2399 return 0;
2400}
2401
2402static void sci_config_port(struct uart_port *port, int flags)
2403{
2404 if (flags & UART_CONFIG_TYPE) {
2405 struct sci_port *sport = to_sci_port(port);
2406
2407 port->type = sport->cfg->type;
2408 sci_request_port(port);
2409 }
2410}
2411
2412static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2413{
2414 if (ser->baud_base < 2400)
2415 /* No paper tape reader for Mitch.. */
2416 return -EINVAL;
2417
2418 return 0;
2419}
2420
2421static struct uart_ops sci_uart_ops = {
2422 .tx_empty = sci_tx_empty,
2423 .set_mctrl = sci_set_mctrl,
2424 .get_mctrl = sci_get_mctrl,
2425 .start_tx = sci_start_tx,
2426 .stop_tx = sci_stop_tx,
2427 .stop_rx = sci_stop_rx,
2428 .break_ctl = sci_break_ctl,
2429 .startup = sci_startup,
2430 .shutdown = sci_shutdown,
2431 .set_termios = sci_set_termios,
2432 .pm = sci_pm,
2433 .type = sci_type,
2434 .release_port = sci_release_port,
2435 .request_port = sci_request_port,
2436 .config_port = sci_config_port,
2437 .verify_port = sci_verify_port,
2438#ifdef CONFIG_CONSOLE_POLL
2439 .poll_get_char = sci_poll_get_char,
2440 .poll_put_char = sci_poll_put_char,
2441#endif
2442};
2443
2444static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2445{
2446 const char *clk_names[] = {
2447 [SCI_FCK] = "fck",
2448 [SCI_SCK] = "sck",
2449 [SCI_BRG_INT] = "brg_int",
2450 [SCI_SCIF_CLK] = "scif_clk",
2451 };
2452 struct clk *clk;
2453 unsigned int i;
2454
2455 if (sci_port->cfg->type == PORT_HSCIF)
2456 clk_names[SCI_SCK] = "hsck";
2457
2458 for (i = 0; i < SCI_NUM_CLKS; i++) {
2459 clk = devm_clk_get(dev, clk_names[i]);
2460 if (PTR_ERR(clk) == -EPROBE_DEFER)
2461 return -EPROBE_DEFER;
2462
2463 if (IS_ERR(clk) && i == SCI_FCK) {
2464 /*
2465 * "fck" used to be called "sci_ick", and we need to
2466 * maintain DT backward compatibility.
2467 */
2468 clk = devm_clk_get(dev, "sci_ick");
2469 if (PTR_ERR(clk) == -EPROBE_DEFER)
2470 return -EPROBE_DEFER;
2471
2472 if (!IS_ERR(clk))
2473 goto found;
2474
2475 /*
2476 * Not all SH platforms declare a clock lookup entry
2477 * for SCI devices, in which case we need to get the
2478 * global "peripheral_clk" clock.
2479 */
2480 clk = devm_clk_get(dev, "peripheral_clk");
2481 if (!IS_ERR(clk))
2482 goto found;
2483
2484 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2485 PTR_ERR(clk));
2486 return PTR_ERR(clk);
2487 }
2488
2489found:
2490 if (IS_ERR(clk))
2491 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2492 PTR_ERR(clk));
2493 else
2494 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2495 clk, clk);
2496 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2497 }
2498 return 0;
2499}
2500
2501static int sci_init_single(struct platform_device *dev,
2502 struct sci_port *sci_port, unsigned int index,
2503 struct plat_sci_port *p, bool early)
2504{
2505 struct uart_port *port = &sci_port->port;
2506 const struct resource *res;
2507 unsigned int i;
2508 int ret;
2509
2510 sci_port->cfg = p;
2511
2512 port->ops = &sci_uart_ops;
2513 port->iotype = UPIO_MEM;
2514 port->line = index;
2515
2516 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2517 if (res == NULL)
2518 return -ENOMEM;
2519
2520 port->mapbase = res->start;
2521 sci_port->reg_size = resource_size(res);
2522
2523 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2524 sci_port->irqs[i] = platform_get_irq(dev, i);
2525
2526 /* The SCI generates several interrupts. They can be muxed together or
2527 * connected to different interrupt lines. In the muxed case only one
2528 * interrupt resource is specified. In the non-muxed case three or four
2529 * interrupt resources are specified, as the BRI interrupt is optional.
2530 */
2531 if (sci_port->irqs[0] < 0)
2532 return -ENXIO;
2533
2534 if (sci_port->irqs[1] < 0) {
2535 sci_port->irqs[1] = sci_port->irqs[0];
2536 sci_port->irqs[2] = sci_port->irqs[0];
2537 sci_port->irqs[3] = sci_port->irqs[0];
2538 }
2539
2540 if (p->regtype == SCIx_PROBE_REGTYPE) {
2541 ret = sci_probe_regmap(p);
2542 if (unlikely(ret))
2543 return ret;
2544 }
2545
2546 switch (p->type) {
2547 case PORT_SCIFB:
2548 port->fifosize = 256;
2549 sci_port->overrun_reg = SCxSR;
2550 sci_port->overrun_mask = SCIFA_ORER;
2551 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2552 break;
2553 case PORT_HSCIF:
2554 port->fifosize = 128;
2555 sci_port->overrun_reg = SCLSR;
2556 sci_port->overrun_mask = SCLSR_ORER;
2557 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
2558 break;
2559 case PORT_SCIFA:
2560 port->fifosize = 64;
2561 sci_port->overrun_reg = SCxSR;
2562 sci_port->overrun_mask = SCIFA_ORER;
2563 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
2564 break;
2565 case PORT_SCIF:
2566 port->fifosize = 16;
2567 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2568 sci_port->overrun_reg = SCxSR;
2569 sci_port->overrun_mask = SCIFA_ORER;
2570 sci_port->sampling_rate_mask = SCI_SR(16);
2571 } else {
2572 sci_port->overrun_reg = SCLSR;
2573 sci_port->overrun_mask = SCLSR_ORER;
2574 sci_port->sampling_rate_mask = SCI_SR(32);
2575 }
2576 break;
2577 default:
2578 port->fifosize = 1;
2579 sci_port->overrun_reg = SCxSR;
2580 sci_port->overrun_mask = SCI_ORER;
2581 sci_port->sampling_rate_mask = SCI_SR(32);
2582 break;
2583 }
2584
2585 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2586 * match the SoC datasheet, this should be investigated. Let platform
2587 * data override the sampling rate for now.
2588 */
2589 if (p->sampling_rate)
2590 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
2591
2592 if (!early) {
2593 ret = sci_init_clocks(sci_port, &dev->dev);
2594 if (ret < 0)
2595 return ret;
2596
2597 port->dev = &dev->dev;
2598
2599 pm_runtime_enable(&dev->dev);
2600 }
2601
2602 sci_port->break_timer.data = (unsigned long)sci_port;
2603 sci_port->break_timer.function = sci_break_timer;
2604 init_timer(&sci_port->break_timer);
2605
2606 /*
2607 * Establish some sensible defaults for the error detection.
2608 */
2609 if (p->type == PORT_SCI) {
2610 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2611 sci_port->error_clear = SCI_ERROR_CLEAR;
2612 } else {
2613 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2614 sci_port->error_clear = SCIF_ERROR_CLEAR;
2615 }
2616
2617 /*
2618 * Make the error mask inclusive of overrun detection, if
2619 * supported.
2620 */
2621 if (sci_port->overrun_reg == SCxSR) {
2622 sci_port->error_mask |= sci_port->overrun_mask;
2623 sci_port->error_clear &= ~sci_port->overrun_mask;
2624 }
2625
2626 port->type = p->type;
2627 port->flags = UPF_FIXED_PORT | p->flags;
2628 port->regshift = p->regshift;
2629
2630 /*
2631 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2632 * for the multi-IRQ ports, which is where we are primarily
2633 * concerned with the shutdown path synchronization.
2634 *
2635 * For the muxed case there's nothing more to do.
2636 */
2637 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2638 port->irqflags = 0;
2639
2640 port->serial_in = sci_serial_in;
2641 port->serial_out = sci_serial_out;
2642
2643 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2644 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2645 p->dma_slave_tx, p->dma_slave_rx);
2646
2647 return 0;
2648}
2649
2650static void sci_cleanup_single(struct sci_port *port)
2651{
2652 pm_runtime_disable(port->port.dev);
2653}
2654
2655#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2656 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2657static void serial_console_putchar(struct uart_port *port, int ch)
2658{
2659 sci_poll_put_char(port, ch);
2660}
2661
2662/*
2663 * Print a string to the serial port trying not to disturb
2664 * any possible real use of the port...
2665 */
2666static void serial_console_write(struct console *co, const char *s,
2667 unsigned count)
2668{
2669 struct sci_port *sci_port = &sci_ports[co->index];
2670 struct uart_port *port = &sci_port->port;
2671 unsigned short bits, ctrl, ctrl_temp;
2672 unsigned long flags;
2673 int locked = 1;
2674
2675 local_irq_save(flags);
2676#if defined(SUPPORT_SYSRQ)
2677 if (port->sysrq)
2678 locked = 0;
2679 else
2680#endif
2681 if (oops_in_progress)
2682 locked = spin_trylock(&port->lock);
2683 else
2684 spin_lock(&port->lock);
2685
2686 /* first save SCSCR then disable interrupts, keep clock source */
2687 ctrl = serial_port_in(port, SCSCR);
2688 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2689 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2690 serial_port_out(port, SCSCR, ctrl_temp);
2691
2692 uart_console_write(port, s, count, serial_console_putchar);
2693
2694 /* wait until fifo is empty and last bit has been transmitted */
2695 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2696 while ((serial_port_in(port, SCxSR) & bits) != bits)
2697 cpu_relax();
2698
2699 /* restore the SCSCR */
2700 serial_port_out(port, SCSCR, ctrl);
2701
2702 if (locked)
2703 spin_unlock(&port->lock);
2704 local_irq_restore(flags);
2705}
2706
2707static int serial_console_setup(struct console *co, char *options)
2708{
2709 struct sci_port *sci_port;
2710 struct uart_port *port;
2711 int baud = 115200;
2712 int bits = 8;
2713 int parity = 'n';
2714 int flow = 'n';
2715 int ret;
2716
2717 /*
2718 * Refuse to handle any bogus ports.
2719 */
2720 if (co->index < 0 || co->index >= SCI_NPORTS)
2721 return -ENODEV;
2722
2723 sci_port = &sci_ports[co->index];
2724 port = &sci_port->port;
2725
2726 /*
2727 * Refuse to handle uninitialized ports.
2728 */
2729 if (!port->ops)
2730 return -ENODEV;
2731
2732 ret = sci_remap_port(port);
2733 if (unlikely(ret != 0))
2734 return ret;
2735
2736 if (options)
2737 uart_parse_options(options, &baud, &parity, &bits, &flow);
2738
2739 return uart_set_options(port, co, baud, parity, bits, flow);
2740}
2741
2742static struct console serial_console = {
2743 .name = "ttySC",
2744 .device = uart_console_device,
2745 .write = serial_console_write,
2746 .setup = serial_console_setup,
2747 .flags = CON_PRINTBUFFER,
2748 .index = -1,
2749 .data = &sci_uart_driver,
2750};
2751
2752static struct console early_serial_console = {
2753 .name = "early_ttySC",
2754 .write = serial_console_write,
2755 .flags = CON_PRINTBUFFER,
2756 .index = -1,
2757};
2758
2759static char early_serial_buf[32];
2760
2761static int sci_probe_earlyprintk(struct platform_device *pdev)
2762{
2763 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2764
2765 if (early_serial_console.data)
2766 return -EEXIST;
2767
2768 early_serial_console.index = pdev->id;
2769
2770 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2771
2772 serial_console_setup(&early_serial_console, early_serial_buf);
2773
2774 if (!strstr(early_serial_buf, "keep"))
2775 early_serial_console.flags |= CON_BOOT;
2776
2777 register_console(&early_serial_console);
2778 return 0;
2779}
2780
2781#define SCI_CONSOLE (&serial_console)
2782
2783#else
2784static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2785{
2786 return -EINVAL;
2787}
2788
2789#define SCI_CONSOLE NULL
2790
2791#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2792
2793static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2794
2795static struct uart_driver sci_uart_driver = {
2796 .owner = THIS_MODULE,
2797 .driver_name = "sci",
2798 .dev_name = "ttySC",
2799 .major = SCI_MAJOR,
2800 .minor = SCI_MINOR_START,
2801 .nr = SCI_NPORTS,
2802 .cons = SCI_CONSOLE,
2803};
2804
2805static int sci_remove(struct platform_device *dev)
2806{
2807 struct sci_port *port = platform_get_drvdata(dev);
2808
2809 uart_remove_one_port(&sci_uart_driver, &port->port);
2810
2811 sci_cleanup_single(port);
2812
2813 return 0;
2814}
2815
2816
2817#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2818#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2819#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2820
2821static const struct of_device_id of_sci_match[] = {
2822 /* SoC-specific types */
2823 {
2824 .compatible = "renesas,scif-r7s72100",
2825 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2826 },
2827 /* Family-specific types */
2828 {
2829 .compatible = "renesas,rcar-gen1-scif",
2830 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2831 }, {
2832 .compatible = "renesas,rcar-gen2-scif",
2833 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2834 }, {
2835 .compatible = "renesas,rcar-gen3-scif",
2836 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2837 },
2838 /* Generic types */
2839 {
2840 .compatible = "renesas,scif",
2841 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2842 }, {
2843 .compatible = "renesas,scifa",
2844 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2845 }, {
2846 .compatible = "renesas,scifb",
2847 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2848 }, {
2849 .compatible = "renesas,hscif",
2850 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2851 }, {
2852 .compatible = "renesas,sci",
2853 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2854 }, {
2855 /* Terminator */
2856 },
2857};
2858MODULE_DEVICE_TABLE(of, of_sci_match);
2859
2860static struct plat_sci_port *
2861sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2862{
2863 struct device_node *np = pdev->dev.of_node;
2864 const struct of_device_id *match;
2865 struct plat_sci_port *p;
2866 int id;
2867
2868 if (!IS_ENABLED(CONFIG_OF) || !np)
2869 return NULL;
2870
2871 match = of_match_node(of_sci_match, np);
2872 if (!match)
2873 return NULL;
2874
2875 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2876 if (!p)
2877 return NULL;
2878
2879 /* Get the line number from the aliases node. */
2880 id = of_alias_get_id(np, "serial");
2881 if (id < 0) {
2882 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2883 return NULL;
2884 }
2885
2886 *dev_id = id;
2887
2888 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2889 p->type = SCI_OF_TYPE(match->data);
2890 p->regtype = SCI_OF_REGTYPE(match->data);
2891 p->scscr = SCSCR_RE | SCSCR_TE;
2892
2893 return p;
2894}
2895
2896static int sci_probe_single(struct platform_device *dev,
2897 unsigned int index,
2898 struct plat_sci_port *p,
2899 struct sci_port *sciport)
2900{
2901 int ret;
2902
2903 /* Sanity check */
2904 if (unlikely(index >= SCI_NPORTS)) {
2905 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2906 index+1, SCI_NPORTS);
2907 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2908 return -EINVAL;
2909 }
2910
2911 ret = sci_init_single(dev, sciport, index, p, false);
2912 if (ret)
2913 return ret;
2914
2915 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2916 if (ret) {
2917 sci_cleanup_single(sciport);
2918 return ret;
2919 }
2920
2921 return 0;
2922}
2923
2924static int sci_probe(struct platform_device *dev)
2925{
2926 struct plat_sci_port *p;
2927 struct sci_port *sp;
2928 unsigned int dev_id;
2929 int ret;
2930
2931 /*
2932 * If we've come here via earlyprintk initialization, head off to
2933 * the special early probe. We don't have sufficient device state
2934 * to make it beyond this yet.
2935 */
2936 if (is_early_platform_device(dev))
2937 return sci_probe_earlyprintk(dev);
2938
2939 if (dev->dev.of_node) {
2940 p = sci_parse_dt(dev, &dev_id);
2941 if (p == NULL)
2942 return -EINVAL;
2943 } else {
2944 p = dev->dev.platform_data;
2945 if (p == NULL) {
2946 dev_err(&dev->dev, "no platform data supplied\n");
2947 return -EINVAL;
2948 }
2949
2950 dev_id = dev->id;
2951 }
2952
2953 sp = &sci_ports[dev_id];
2954 platform_set_drvdata(dev, sp);
2955
2956 ret = sci_probe_single(dev, dev_id, p, sp);
2957 if (ret)
2958 return ret;
2959
2960#ifdef CONFIG_SH_STANDARD_BIOS
2961 sh_bios_gdb_detach();
2962#endif
2963
2964 return 0;
2965}
2966
2967static __maybe_unused int sci_suspend(struct device *dev)
2968{
2969 struct sci_port *sport = dev_get_drvdata(dev);
2970
2971 if (sport)
2972 uart_suspend_port(&sci_uart_driver, &sport->port);
2973
2974 return 0;
2975}
2976
2977static __maybe_unused int sci_resume(struct device *dev)
2978{
2979 struct sci_port *sport = dev_get_drvdata(dev);
2980
2981 if (sport)
2982 uart_resume_port(&sci_uart_driver, &sport->port);
2983
2984 return 0;
2985}
2986
2987static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2988
2989static struct platform_driver sci_driver = {
2990 .probe = sci_probe,
2991 .remove = sci_remove,
2992 .driver = {
2993 .name = "sh-sci",
2994 .pm = &sci_dev_pm_ops,
2995 .of_match_table = of_match_ptr(of_sci_match),
2996 },
2997};
2998
2999static int __init sci_init(void)
3000{
3001 int ret;
3002
3003 pr_info("%s\n", banner);
3004
3005 ret = uart_register_driver(&sci_uart_driver);
3006 if (likely(ret == 0)) {
3007 ret = platform_driver_register(&sci_driver);
3008 if (unlikely(ret))
3009 uart_unregister_driver(&sci_uart_driver);
3010 }
3011
3012 return ret;
3013}
3014
3015static void __exit sci_exit(void)
3016{
3017 platform_driver_unregister(&sci_driver);
3018 uart_unregister_driver(&sci_uart_driver);
3019}
3020
3021#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3022early_platform_init_buffer("earlyprintk", &sci_driver,
3023 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3024#endif
3025#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3026static struct __init plat_sci_port port_cfg;
3027
3028static int __init early_console_setup(struct earlycon_device *device,
3029 int type)
3030{
3031 if (!device->port.membase)
3032 return -ENODEV;
3033
3034 device->port.serial_in = sci_serial_in;
3035 device->port.serial_out = sci_serial_out;
3036 device->port.type = type;
3037 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3038 sci_ports[0].cfg = &port_cfg;
3039 sci_ports[0].cfg->type = type;
3040 sci_probe_regmap(sci_ports[0].cfg);
3041 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3042 SCSCR_RE | SCSCR_TE;
3043 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3044
3045 device->con->write = serial_console_write;
3046 return 0;
3047}
3048static int __init sci_early_console_setup(struct earlycon_device *device,
3049 const char *opt)
3050{
3051 return early_console_setup(device, PORT_SCI);
3052}
3053static int __init scif_early_console_setup(struct earlycon_device *device,
3054 const char *opt)
3055{
3056 return early_console_setup(device, PORT_SCIF);
3057}
3058static int __init scifa_early_console_setup(struct earlycon_device *device,
3059 const char *opt)
3060{
3061 return early_console_setup(device, PORT_SCIFA);
3062}
3063static int __init scifb_early_console_setup(struct earlycon_device *device,
3064 const char *opt)
3065{
3066 return early_console_setup(device, PORT_SCIFB);
3067}
3068static int __init hscif_early_console_setup(struct earlycon_device *device,
3069 const char *opt)
3070{
3071 return early_console_setup(device, PORT_HSCIF);
3072}
3073
3074OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3075OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3076OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3077OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3078OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3079#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3080
3081module_init(sci_init);
3082module_exit(sci_exit);
3083
3084MODULE_LICENSE("GPL");
3085MODULE_ALIAS("platform:sh-sci");
3086MODULE_AUTHOR("Paul Mundt");
3087MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#undef DEBUG
19
20#include <linux/clk.h>
21#include <linux/console.h>
22#include <linux/ctype.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/ktime.h>
33#include <linux/major.h>
34#include <linux/minmax.h>
35#include <linux/module.h>
36#include <linux/mm.h>
37#include <linux/of.h>
38#include <linux/platform_device.h>
39#include <linux/pm_runtime.h>
40#include <linux/reset.h>
41#include <linux/scatterlist.h>
42#include <linux/serial.h>
43#include <linux/serial_sci.h>
44#include <linux/sh_dma.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/sysrq.h>
48#include <linux/timer.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51
52#ifdef CONFIG_SUPERH
53#include <asm/sh_bios.h>
54#include <asm/platform_early.h>
55#endif
56
57#include "serial_mctrl_gpio.h"
58#include "sh-sci.h"
59
60/* Offsets into the sci_port->irqs array */
61enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
146 void *rx_buf[2];
147 size_t buf_len_rx;
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
151#endif
152 unsigned int rx_frame;
153 int rx_trigger;
154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
156 u16 hscif_tot;
157
158 bool has_rtscts;
159 bool autorts;
160};
161
162#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
163
164static struct sci_port sci_ports[SCI_NPORTS];
165static unsigned long sci_ports_in_use;
166static struct uart_driver sci_uart_driver;
167
168static inline struct sci_port *
169to_sci_port(struct uart_port *uart)
170{
171 return container_of(uart, struct sci_port, port);
172}
173
174static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
175 /*
176 * Common SCI definitions, dependent on the port's regshift
177 * value.
178 */
179 [SCIx_SCI_REGTYPE] = {
180 .regs = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 },
188 .fifosize = 1,
189 .overrun_reg = SCxSR,
190 .overrun_mask = SCI_ORER,
191 .sampling_rate_mask = SCI_SR(32),
192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
194 },
195
196 /*
197 * Common definitions for legacy IrDA ports.
198 */
199 [SCIx_IRDA_REGTYPE] = {
200 .regs = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x02, 8 },
203 [SCSCR] = { 0x04, 8 },
204 [SCxTDR] = { 0x06, 8 },
205 [SCxSR] = { 0x08, 16 },
206 [SCxRDR] = { 0x0a, 8 },
207 [SCFCR] = { 0x0c, 8 },
208 [SCFDR] = { 0x0e, 16 },
209 },
210 .fifosize = 1,
211 .overrun_reg = SCxSR,
212 .overrun_mask = SCI_ORER,
213 .sampling_rate_mask = SCI_SR(32),
214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
216 },
217
218 /*
219 * Common SCIFA definitions.
220 */
221 [SCIx_SCIFA_REGTYPE] = {
222 .regs = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
233 },
234 .fifosize = 64,
235 .overrun_reg = SCxSR,
236 .overrun_mask = SCIFA_ORER,
237 .sampling_rate_mask = SCI_SR_SCIFAB,
238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
240 },
241
242 /*
243 * Common SCIFB definitions.
244 */
245 [SCIx_SCIFB_REGTYPE] = {
246 .regs = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x40, 8 },
251 [SCxSR] = { 0x14, 16 },
252 [SCxRDR] = { 0x60, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCPCR] = { 0x30, 16 },
257 [SCPDR] = { 0x34, 16 },
258 },
259 .fifosize = 256,
260 .overrun_reg = SCxSR,
261 .overrun_mask = SCIFA_ORER,
262 .sampling_rate_mask = SCI_SR_SCIFAB,
263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
265 },
266
267 /*
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
269 * count registers.
270 */
271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
272 .regs = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCSPTR] = { 0x20, 16 },
282 [SCLSR] = { 0x24, 16 },
283 },
284 .fifosize = 16,
285 .overrun_reg = SCLSR,
286 .overrun_mask = SCLSR_ORER,
287 .sampling_rate_mask = SCI_SR(32),
288 .error_mask = SCIF_DEFAULT_ERROR_MASK,
289 .error_clear = SCIF_ERROR_CLEAR,
290 },
291
292 /*
293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
294 * It looks like a normal SCIF with FIFO data, but with a
295 * compressed address space. Also, the break out of interrupts
296 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
297 */
298 [SCIx_RZ_SCIFA_REGTYPE] = {
299 .regs = {
300 [SCSMR] = { 0x00, 16 },
301 [SCBRR] = { 0x02, 8 },
302 [SCSCR] = { 0x04, 16 },
303 [SCxTDR] = { 0x06, 8 },
304 [SCxSR] = { 0x08, 16 },
305 [SCxRDR] = { 0x0A, 8 },
306 [SCFCR] = { 0x0C, 16 },
307 [SCFDR] = { 0x0E, 16 },
308 [SCSPTR] = { 0x10, 16 },
309 [SCLSR] = { 0x12, 16 },
310 [SEMR] = { 0x14, 8 },
311 },
312 .fifosize = 16,
313 .overrun_reg = SCLSR,
314 .overrun_mask = SCLSR_ORER,
315 .sampling_rate_mask = SCI_SR(32),
316 .error_mask = SCIF_DEFAULT_ERROR_MASK,
317 .error_clear = SCIF_ERROR_CLEAR,
318 },
319
320 /*
321 * Common SH-3 SCIF definitions.
322 */
323 [SCIx_SH3_SCIF_REGTYPE] = {
324 .regs = {
325 [SCSMR] = { 0x00, 8 },
326 [SCBRR] = { 0x02, 8 },
327 [SCSCR] = { 0x04, 8 },
328 [SCxTDR] = { 0x06, 8 },
329 [SCxSR] = { 0x08, 16 },
330 [SCxRDR] = { 0x0a, 8 },
331 [SCFCR] = { 0x0c, 8 },
332 [SCFDR] = { 0x0e, 16 },
333 },
334 .fifosize = 16,
335 .overrun_reg = SCLSR,
336 .overrun_mask = SCLSR_ORER,
337 .sampling_rate_mask = SCI_SR(32),
338 .error_mask = SCIF_DEFAULT_ERROR_MASK,
339 .error_clear = SCIF_ERROR_CLEAR,
340 },
341
342 /*
343 * Common SH-4(A) SCIF(B) definitions.
344 */
345 [SCIx_SH4_SCIF_REGTYPE] = {
346 .regs = {
347 [SCSMR] = { 0x00, 16 },
348 [SCBRR] = { 0x04, 8 },
349 [SCSCR] = { 0x08, 16 },
350 [SCxTDR] = { 0x0c, 8 },
351 [SCxSR] = { 0x10, 16 },
352 [SCxRDR] = { 0x14, 8 },
353 [SCFCR] = { 0x18, 16 },
354 [SCFDR] = { 0x1c, 16 },
355 [SCSPTR] = { 0x20, 16 },
356 [SCLSR] = { 0x24, 16 },
357 },
358 .fifosize = 16,
359 .overrun_reg = SCLSR,
360 .overrun_mask = SCLSR_ORER,
361 .sampling_rate_mask = SCI_SR(32),
362 .error_mask = SCIF_DEFAULT_ERROR_MASK,
363 .error_clear = SCIF_ERROR_CLEAR,
364 },
365
366 /*
367 * Common SCIF definitions for ports with a Baud Rate Generator for
368 * External Clock (BRG).
369 */
370 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
371 .regs = {
372 [SCSMR] = { 0x00, 16 },
373 [SCBRR] = { 0x04, 8 },
374 [SCSCR] = { 0x08, 16 },
375 [SCxTDR] = { 0x0c, 8 },
376 [SCxSR] = { 0x10, 16 },
377 [SCxRDR] = { 0x14, 8 },
378 [SCFCR] = { 0x18, 16 },
379 [SCFDR] = { 0x1c, 16 },
380 [SCSPTR] = { 0x20, 16 },
381 [SCLSR] = { 0x24, 16 },
382 [SCDL] = { 0x30, 16 },
383 [SCCKS] = { 0x34, 16 },
384 },
385 .fifosize = 16,
386 .overrun_reg = SCLSR,
387 .overrun_mask = SCLSR_ORER,
388 .sampling_rate_mask = SCI_SR(32),
389 .error_mask = SCIF_DEFAULT_ERROR_MASK,
390 .error_clear = SCIF_ERROR_CLEAR,
391 },
392
393 /*
394 * Common HSCIF definitions.
395 */
396 [SCIx_HSCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 [HSSRR] = { 0x40, 16 },
409 [SCDL] = { 0x30, 16 },
410 [SCCKS] = { 0x34, 16 },
411 [HSRTRGR] = { 0x54, 16 },
412 [HSTTRGR] = { 0x58, 16 },
413 },
414 .fifosize = 128,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
420 },
421
422 /*
423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
424 * register.
425 */
426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
427 .regs = {
428 [SCSMR] = { 0x00, 16 },
429 [SCBRR] = { 0x04, 8 },
430 [SCSCR] = { 0x08, 16 },
431 [SCxTDR] = { 0x0c, 8 },
432 [SCxSR] = { 0x10, 16 },
433 [SCxRDR] = { 0x14, 8 },
434 [SCFCR] = { 0x18, 16 },
435 [SCFDR] = { 0x1c, 16 },
436 [SCLSR] = { 0x24, 16 },
437 },
438 .fifosize = 16,
439 .overrun_reg = SCLSR,
440 .overrun_mask = SCLSR_ORER,
441 .sampling_rate_mask = SCI_SR(32),
442 .error_mask = SCIF_DEFAULT_ERROR_MASK,
443 .error_clear = SCIF_ERROR_CLEAR,
444 },
445
446 /*
447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
448 * count registers.
449 */
450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
451 .regs = {
452 [SCSMR] = { 0x00, 16 },
453 [SCBRR] = { 0x04, 8 },
454 [SCSCR] = { 0x08, 16 },
455 [SCxTDR] = { 0x0c, 8 },
456 [SCxSR] = { 0x10, 16 },
457 [SCxRDR] = { 0x14, 8 },
458 [SCFCR] = { 0x18, 16 },
459 [SCFDR] = { 0x1c, 16 },
460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
461 [SCRFDR] = { 0x20, 16 },
462 [SCSPTR] = { 0x24, 16 },
463 [SCLSR] = { 0x28, 16 },
464 },
465 .fifosize = 16,
466 .overrun_reg = SCLSR,
467 .overrun_mask = SCLSR_ORER,
468 .sampling_rate_mask = SCI_SR(32),
469 .error_mask = SCIF_DEFAULT_ERROR_MASK,
470 .error_clear = SCIF_ERROR_CLEAR,
471 },
472
473 /*
474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
475 * registers.
476 */
477 [SCIx_SH7705_SCIF_REGTYPE] = {
478 .regs = {
479 [SCSMR] = { 0x00, 16 },
480 [SCBRR] = { 0x04, 8 },
481 [SCSCR] = { 0x08, 16 },
482 [SCxTDR] = { 0x20, 8 },
483 [SCxSR] = { 0x14, 16 },
484 [SCxRDR] = { 0x24, 8 },
485 [SCFCR] = { 0x18, 16 },
486 [SCFDR] = { 0x1c, 16 },
487 },
488 .fifosize = 64,
489 .overrun_reg = SCxSR,
490 .overrun_mask = SCIFA_ORER,
491 .sampling_rate_mask = SCI_SR(16),
492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
494 },
495};
496
497#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
498
499/*
500 * The "offset" here is rather misleading, in that it refers to an enum
501 * value relative to the port mapping rather than the fixed offset
502 * itself, which needs to be manually retrieved from the platform's
503 * register map for the given port.
504 */
505static unsigned int sci_serial_in(struct uart_port *p, int offset)
506{
507 const struct plat_sci_reg *reg = sci_getreg(p, offset);
508
509 if (reg->size == 8)
510 return ioread8(p->membase + (reg->offset << p->regshift));
511 else if (reg->size == 16)
512 return ioread16(p->membase + (reg->offset << p->regshift));
513 else
514 WARN(1, "Invalid register access\n");
515
516 return 0;
517}
518
519static void sci_serial_out(struct uart_port *p, int offset, int value)
520{
521 const struct plat_sci_reg *reg = sci_getreg(p, offset);
522
523 if (reg->size == 8)
524 iowrite8(value, p->membase + (reg->offset << p->regshift));
525 else if (reg->size == 16)
526 iowrite16(value, p->membase + (reg->offset << p->regshift));
527 else
528 WARN(1, "Invalid register access\n");
529}
530
531static void sci_port_enable(struct sci_port *sci_port)
532{
533 unsigned int i;
534
535 if (!sci_port->port.dev)
536 return;
537
538 pm_runtime_get_sync(sci_port->port.dev);
539
540 for (i = 0; i < SCI_NUM_CLKS; i++) {
541 clk_prepare_enable(sci_port->clks[i]);
542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
543 }
544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
545}
546
547static void sci_port_disable(struct sci_port *sci_port)
548{
549 unsigned int i;
550
551 if (!sci_port->port.dev)
552 return;
553
554 for (i = SCI_NUM_CLKS; i-- > 0; )
555 clk_disable_unprepare(sci_port->clks[i]);
556
557 pm_runtime_put_sync(sci_port->port.dev);
558}
559
560static inline unsigned long port_rx_irq_mask(struct uart_port *port)
561{
562 /*
563 * Not all ports (such as SCIFA) will support REIE. Rather than
564 * special-casing the port type, we check the port initialization
565 * IRQ enable mask to see whether the IRQ is desired at all. If
566 * it's unset, it's logically inferred that there's no point in
567 * testing for it.
568 */
569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
570}
571
572static void sci_start_tx(struct uart_port *port)
573{
574 struct sci_port *s = to_sci_port(port);
575 unsigned short ctrl;
576
577#ifdef CONFIG_SERIAL_SH_SCI_DMA
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
579 u16 new, scr = sci_serial_in(port, SCSCR);
580 if (s->chan_tx)
581 new = scr | SCSCR_TDRQE;
582 else
583 new = scr & ~SCSCR_TDRQE;
584 if (new != scr)
585 sci_serial_out(port, SCSCR, new);
586 }
587
588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
589 dma_submit_error(s->cookie_tx)) {
590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
591 /* Switch irq from SCIF to DMA */
592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
593
594 s->cookie_tx = 0;
595 schedule_work(&s->work_tx);
596 }
597#endif
598
599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
601 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
602 ctrl = sci_serial_in(port, SCSCR);
603
604 /*
605 * For SCI, TE (transmit enable) must be set after setting TIE
606 * (transmit interrupt enable) or in the same instruction to start
607 * the transmit process.
608 */
609 if (port->type == PORT_SCI)
610 ctrl |= SCSCR_TE;
611
612 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
613 }
614}
615
616static void sci_stop_tx(struct uart_port *port)
617{
618 unsigned short ctrl;
619
620 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
621 ctrl = sci_serial_in(port, SCSCR);
622
623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
624 ctrl &= ~SCSCR_TDRQE;
625
626 ctrl &= ~SCSCR_TIE;
627
628 sci_serial_out(port, SCSCR, ctrl);
629
630#ifdef CONFIG_SERIAL_SH_SCI_DMA
631 if (to_sci_port(port)->chan_tx &&
632 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
633 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
634 to_sci_port(port)->cookie_tx = -EINVAL;
635 }
636#endif
637}
638
639static void sci_start_rx(struct uart_port *port)
640{
641 unsigned short ctrl;
642
643 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
644
645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
646 ctrl &= ~SCSCR_RDRQE;
647
648 sci_serial_out(port, SCSCR, ctrl);
649}
650
651static void sci_stop_rx(struct uart_port *port)
652{
653 unsigned short ctrl;
654
655 ctrl = sci_serial_in(port, SCSCR);
656
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_RDRQE;
659
660 ctrl &= ~port_rx_irq_mask(port);
661
662 sci_serial_out(port, SCSCR, ctrl);
663}
664
665static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
666{
667 if (port->type == PORT_SCI) {
668 /* Just store the mask */
669 sci_serial_out(port, SCxSR, mask);
670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
671 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
672 /* Only clear the status bits we want to clear */
673 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
674 } else {
675 /* Store the mask, clear parity/framing errors */
676 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
677 }
678}
679
680#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
681 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
682
683#ifdef CONFIG_CONSOLE_POLL
684static int sci_poll_get_char(struct uart_port *port)
685{
686 unsigned short status;
687 int c;
688
689 do {
690 status = sci_serial_in(port, SCxSR);
691 if (status & SCxSR_ERRORS(port)) {
692 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
693 continue;
694 }
695 break;
696 } while (1);
697
698 if (!(status & SCxSR_RDxF(port)))
699 return NO_POLL_CHAR;
700
701 c = sci_serial_in(port, SCxRDR);
702
703 /* Dummy read */
704 sci_serial_in(port, SCxSR);
705 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
706
707 return c;
708}
709#endif
710
711static void sci_poll_put_char(struct uart_port *port, unsigned char c)
712{
713 unsigned short status;
714
715 do {
716 status = sci_serial_in(port, SCxSR);
717 } while (!(status & SCxSR_TDxE(port)));
718
719 sci_serial_out(port, SCxTDR, c);
720 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
721}
722#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
723 CONFIG_SERIAL_SH_SCI_EARLYCON */
724
725static void sci_init_pins(struct uart_port *port, unsigned int cflag)
726{
727 struct sci_port *s = to_sci_port(port);
728
729 /*
730 * Use port-specific handler if provided.
731 */
732 if (s->cfg->ops && s->cfg->ops->init_pins) {
733 s->cfg->ops->init_pins(port, cflag);
734 return;
735 }
736
737 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
738 u16 data = sci_serial_in(port, SCPDR);
739 u16 ctrl = sci_serial_in(port, SCPCR);
740
741 /* Enable RXD and TXD pin functions */
742 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
743 if (to_sci_port(port)->has_rtscts) {
744 /* RTS# is output, active low, unless autorts */
745 if (!(port->mctrl & TIOCM_RTS)) {
746 ctrl |= SCPCR_RTSC;
747 data |= SCPDR_RTSD;
748 } else if (!s->autorts) {
749 ctrl |= SCPCR_RTSC;
750 data &= ~SCPDR_RTSD;
751 } else {
752 /* Enable RTS# pin function */
753 ctrl &= ~SCPCR_RTSC;
754 }
755 /* Enable CTS# pin function */
756 ctrl &= ~SCPCR_CTSC;
757 }
758 sci_serial_out(port, SCPDR, data);
759 sci_serial_out(port, SCPCR, ctrl);
760 } else if (sci_getreg(port, SCSPTR)->size) {
761 u16 status = sci_serial_in(port, SCSPTR);
762
763 /* RTS# is always output; and active low, unless autorts */
764 status |= SCSPTR_RTSIO;
765 if (!(port->mctrl & TIOCM_RTS))
766 status |= SCSPTR_RTSDT;
767 else if (!s->autorts)
768 status &= ~SCSPTR_RTSDT;
769 /* CTS# and SCK are inputs */
770 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
771 sci_serial_out(port, SCSPTR, status);
772 }
773}
774
775static int sci_txfill(struct uart_port *port)
776{
777 struct sci_port *s = to_sci_port(port);
778 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
779 const struct plat_sci_reg *reg;
780
781 reg = sci_getreg(port, SCTFDR);
782 if (reg->size)
783 return sci_serial_in(port, SCTFDR) & fifo_mask;
784
785 reg = sci_getreg(port, SCFDR);
786 if (reg->size)
787 return sci_serial_in(port, SCFDR) >> 8;
788
789 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
790}
791
792static int sci_txroom(struct uart_port *port)
793{
794 return port->fifosize - sci_txfill(port);
795}
796
797static int sci_rxfill(struct uart_port *port)
798{
799 struct sci_port *s = to_sci_port(port);
800 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
801 const struct plat_sci_reg *reg;
802
803 reg = sci_getreg(port, SCRFDR);
804 if (reg->size)
805 return sci_serial_in(port, SCRFDR) & fifo_mask;
806
807 reg = sci_getreg(port, SCFDR);
808 if (reg->size)
809 return sci_serial_in(port, SCFDR) & fifo_mask;
810
811 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
812}
813
814/* ********************************************************************** *
815 * the interrupt related routines *
816 * ********************************************************************** */
817
818static void sci_transmit_chars(struct uart_port *port)
819{
820 struct circ_buf *xmit = &port->state->xmit;
821 unsigned int stopped = uart_tx_stopped(port);
822 unsigned short status;
823 unsigned short ctrl;
824 int count;
825
826 status = sci_serial_in(port, SCxSR);
827 if (!(status & SCxSR_TDxE(port))) {
828 ctrl = sci_serial_in(port, SCSCR);
829 if (uart_circ_empty(xmit))
830 ctrl &= ~SCSCR_TIE;
831 else
832 ctrl |= SCSCR_TIE;
833 sci_serial_out(port, SCSCR, ctrl);
834 return;
835 }
836
837 count = sci_txroom(port);
838
839 do {
840 unsigned char c;
841
842 if (port->x_char) {
843 c = port->x_char;
844 port->x_char = 0;
845 } else if (!uart_circ_empty(xmit) && !stopped) {
846 c = xmit->buf[xmit->tail];
847 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
848 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) {
849 ctrl = sci_serial_in(port, SCSCR);
850 ctrl &= ~SCSCR_TE;
851 sci_serial_out(port, SCSCR, ctrl);
852 return;
853 } else {
854 break;
855 }
856
857 sci_serial_out(port, SCxTDR, c);
858
859 port->icount.tx++;
860 } while (--count > 0);
861
862 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
863
864 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
865 uart_write_wakeup(port);
866 if (uart_circ_empty(xmit)) {
867 if (port->type == PORT_SCI) {
868 ctrl = sci_serial_in(port, SCSCR);
869 ctrl &= ~SCSCR_TIE;
870 ctrl |= SCSCR_TEIE;
871 sci_serial_out(port, SCSCR, ctrl);
872 }
873
874 sci_stop_tx(port);
875 }
876}
877
878static void sci_receive_chars(struct uart_port *port)
879{
880 struct tty_port *tport = &port->state->port;
881 int i, count, copied = 0;
882 unsigned short status;
883 unsigned char flag;
884
885 status = sci_serial_in(port, SCxSR);
886 if (!(status & SCxSR_RDxF(port)))
887 return;
888
889 while (1) {
890 /* Don't copy more bytes than there is room for in the buffer */
891 count = tty_buffer_request_room(tport, sci_rxfill(port));
892
893 /* If for any reason we can't copy more data, we're done! */
894 if (count == 0)
895 break;
896
897 if (port->type == PORT_SCI) {
898 char c = sci_serial_in(port, SCxRDR);
899 if (uart_handle_sysrq_char(port, c))
900 count = 0;
901 else
902 tty_insert_flip_char(tport, c, TTY_NORMAL);
903 } else {
904 for (i = 0; i < count; i++) {
905 char c;
906
907 if (port->type == PORT_SCIF ||
908 port->type == PORT_HSCIF) {
909 status = sci_serial_in(port, SCxSR);
910 c = sci_serial_in(port, SCxRDR);
911 } else {
912 c = sci_serial_in(port, SCxRDR);
913 status = sci_serial_in(port, SCxSR);
914 }
915 if (uart_handle_sysrq_char(port, c)) {
916 count--; i--;
917 continue;
918 }
919
920 /* Store data and status */
921 if (status & SCxSR_FER(port)) {
922 flag = TTY_FRAME;
923 port->icount.frame++;
924 } else if (status & SCxSR_PER(port)) {
925 flag = TTY_PARITY;
926 port->icount.parity++;
927 } else
928 flag = TTY_NORMAL;
929
930 tty_insert_flip_char(tport, c, flag);
931 }
932 }
933
934 sci_serial_in(port, SCxSR); /* dummy read */
935 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
936
937 copied += count;
938 port->icount.rx += count;
939 }
940
941 if (copied) {
942 /* Tell the rest of the system the news. New characters! */
943 tty_flip_buffer_push(tport);
944 } else {
945 /* TTY buffers full; read from RX reg to prevent lockup */
946 sci_serial_in(port, SCxRDR);
947 sci_serial_in(port, SCxSR); /* dummy read */
948 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
949 }
950}
951
952static int sci_handle_errors(struct uart_port *port)
953{
954 int copied = 0;
955 unsigned short status = sci_serial_in(port, SCxSR);
956 struct tty_port *tport = &port->state->port;
957 struct sci_port *s = to_sci_port(port);
958
959 /* Handle overruns */
960 if (status & s->params->overrun_mask) {
961 port->icount.overrun++;
962
963 /* overrun error */
964 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
965 copied++;
966 }
967
968 if (status & SCxSR_FER(port)) {
969 /* frame error */
970 port->icount.frame++;
971
972 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
973 copied++;
974 }
975
976 if (status & SCxSR_PER(port)) {
977 /* parity error */
978 port->icount.parity++;
979
980 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
981 copied++;
982 }
983
984 if (copied)
985 tty_flip_buffer_push(tport);
986
987 return copied;
988}
989
990static int sci_handle_fifo_overrun(struct uart_port *port)
991{
992 struct tty_port *tport = &port->state->port;
993 struct sci_port *s = to_sci_port(port);
994 const struct plat_sci_reg *reg;
995 int copied = 0;
996 u16 status;
997
998 reg = sci_getreg(port, s->params->overrun_reg);
999 if (!reg->size)
1000 return 0;
1001
1002 status = sci_serial_in(port, s->params->overrun_reg);
1003 if (status & s->params->overrun_mask) {
1004 status &= ~s->params->overrun_mask;
1005 sci_serial_out(port, s->params->overrun_reg, status);
1006
1007 port->icount.overrun++;
1008
1009 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1010 tty_flip_buffer_push(tport);
1011 copied++;
1012 }
1013
1014 return copied;
1015}
1016
1017static int sci_handle_breaks(struct uart_port *port)
1018{
1019 int copied = 0;
1020 unsigned short status = sci_serial_in(port, SCxSR);
1021 struct tty_port *tport = &port->state->port;
1022
1023 if (uart_handle_break(port))
1024 return 0;
1025
1026 if (status & SCxSR_BRK(port)) {
1027 port->icount.brk++;
1028
1029 /* Notify of BREAK */
1030 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1031 copied++;
1032 }
1033
1034 if (copied)
1035 tty_flip_buffer_push(tport);
1036
1037 copied += sci_handle_fifo_overrun(port);
1038
1039 return copied;
1040}
1041
1042static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1043{
1044 unsigned int bits;
1045
1046 if (rx_trig >= port->fifosize)
1047 rx_trig = port->fifosize - 1;
1048 if (rx_trig < 1)
1049 rx_trig = 1;
1050
1051 /* HSCIF can be set to an arbitrary level. */
1052 if (sci_getreg(port, HSRTRGR)->size) {
1053 sci_serial_out(port, HSRTRGR, rx_trig);
1054 return rx_trig;
1055 }
1056
1057 switch (port->type) {
1058 case PORT_SCIF:
1059 if (rx_trig < 4) {
1060 bits = 0;
1061 rx_trig = 1;
1062 } else if (rx_trig < 8) {
1063 bits = SCFCR_RTRG0;
1064 rx_trig = 4;
1065 } else if (rx_trig < 14) {
1066 bits = SCFCR_RTRG1;
1067 rx_trig = 8;
1068 } else {
1069 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1070 rx_trig = 14;
1071 }
1072 break;
1073 case PORT_SCIFA:
1074 case PORT_SCIFB:
1075 if (rx_trig < 16) {
1076 bits = 0;
1077 rx_trig = 1;
1078 } else if (rx_trig < 32) {
1079 bits = SCFCR_RTRG0;
1080 rx_trig = 16;
1081 } else if (rx_trig < 48) {
1082 bits = SCFCR_RTRG1;
1083 rx_trig = 32;
1084 } else {
1085 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1086 rx_trig = 48;
1087 }
1088 break;
1089 default:
1090 WARN(1, "unknown FIFO configuration");
1091 return 1;
1092 }
1093
1094 sci_serial_out(port, SCFCR,
1095 (sci_serial_in(port, SCFCR) &
1096 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1097
1098 return rx_trig;
1099}
1100
1101static int scif_rtrg_enabled(struct uart_port *port)
1102{
1103 if (sci_getreg(port, HSRTRGR)->size)
1104 return sci_serial_in(port, HSRTRGR) != 0;
1105 else
1106 return (sci_serial_in(port, SCFCR) &
1107 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1108}
1109
1110static void rx_fifo_timer_fn(struct timer_list *t)
1111{
1112 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1113 struct uart_port *port = &s->port;
1114
1115 dev_dbg(port->dev, "Rx timed out\n");
1116 scif_set_rtrg(port, 1);
1117}
1118
1119static ssize_t rx_fifo_trigger_show(struct device *dev,
1120 struct device_attribute *attr, char *buf)
1121{
1122 struct uart_port *port = dev_get_drvdata(dev);
1123 struct sci_port *sci = to_sci_port(port);
1124
1125 return sprintf(buf, "%d\n", sci->rx_trigger);
1126}
1127
1128static ssize_t rx_fifo_trigger_store(struct device *dev,
1129 struct device_attribute *attr,
1130 const char *buf, size_t count)
1131{
1132 struct uart_port *port = dev_get_drvdata(dev);
1133 struct sci_port *sci = to_sci_port(port);
1134 int ret;
1135 long r;
1136
1137 ret = kstrtol(buf, 0, &r);
1138 if (ret)
1139 return ret;
1140
1141 sci->rx_trigger = scif_set_rtrg(port, r);
1142 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1143 scif_set_rtrg(port, 1);
1144
1145 return count;
1146}
1147
1148static DEVICE_ATTR_RW(rx_fifo_trigger);
1149
1150static ssize_t rx_fifo_timeout_show(struct device *dev,
1151 struct device_attribute *attr,
1152 char *buf)
1153{
1154 struct uart_port *port = dev_get_drvdata(dev);
1155 struct sci_port *sci = to_sci_port(port);
1156 int v;
1157
1158 if (port->type == PORT_HSCIF)
1159 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1160 else
1161 v = sci->rx_fifo_timeout;
1162
1163 return sprintf(buf, "%d\n", v);
1164}
1165
1166static ssize_t rx_fifo_timeout_store(struct device *dev,
1167 struct device_attribute *attr,
1168 const char *buf,
1169 size_t count)
1170{
1171 struct uart_port *port = dev_get_drvdata(dev);
1172 struct sci_port *sci = to_sci_port(port);
1173 int ret;
1174 long r;
1175
1176 ret = kstrtol(buf, 0, &r);
1177 if (ret)
1178 return ret;
1179
1180 if (port->type == PORT_HSCIF) {
1181 if (r < 0 || r > 3)
1182 return -EINVAL;
1183 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1184 } else {
1185 sci->rx_fifo_timeout = r;
1186 scif_set_rtrg(port, 1);
1187 if (r > 0)
1188 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1189 }
1190
1191 return count;
1192}
1193
1194static DEVICE_ATTR_RW(rx_fifo_timeout);
1195
1196
1197#ifdef CONFIG_SERIAL_SH_SCI_DMA
1198static void sci_dma_tx_complete(void *arg)
1199{
1200 struct sci_port *s = arg;
1201 struct uart_port *port = &s->port;
1202 struct circ_buf *xmit = &port->state->xmit;
1203 unsigned long flags;
1204
1205 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1206
1207 uart_port_lock_irqsave(port, &flags);
1208
1209 uart_xmit_advance(port, s->tx_dma_len);
1210
1211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1212 uart_write_wakeup(port);
1213
1214 if (!uart_circ_empty(xmit)) {
1215 s->cookie_tx = 0;
1216 schedule_work(&s->work_tx);
1217 } else {
1218 s->cookie_tx = -EINVAL;
1219 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1220 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1221 u16 ctrl = sci_serial_in(port, SCSCR);
1222 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1223 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1224 /* Switch irq from DMA to SCIF */
1225 dmaengine_pause(s->chan_tx_saved);
1226 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1227 }
1228 }
1229 }
1230
1231 uart_port_unlock_irqrestore(port, flags);
1232}
1233
1234/* Locking: called with port lock held */
1235static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1236{
1237 struct uart_port *port = &s->port;
1238 struct tty_port *tport = &port->state->port;
1239 int copied;
1240
1241 copied = tty_insert_flip_string(tport, buf, count);
1242 if (copied < count)
1243 port->icount.buf_overrun++;
1244
1245 port->icount.rx += copied;
1246
1247 return copied;
1248}
1249
1250static int sci_dma_rx_find_active(struct sci_port *s)
1251{
1252 unsigned int i;
1253
1254 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1255 if (s->active_rx == s->cookie_rx[i])
1256 return i;
1257
1258 return -1;
1259}
1260
1261static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1262{
1263 unsigned int i;
1264
1265 s->chan_rx = NULL;
1266 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1267 s->cookie_rx[i] = -EINVAL;
1268 s->active_rx = 0;
1269}
1270
1271static void sci_dma_rx_release(struct sci_port *s)
1272{
1273 struct dma_chan *chan = s->chan_rx_saved;
1274 struct uart_port *port = &s->port;
1275 unsigned long flags;
1276
1277 uart_port_lock_irqsave(port, &flags);
1278 s->chan_rx_saved = NULL;
1279 sci_dma_rx_chan_invalidate(s);
1280 uart_port_unlock_irqrestore(port, flags);
1281
1282 dmaengine_terminate_sync(chan);
1283 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1284 sg_dma_address(&s->sg_rx[0]));
1285 dma_release_channel(chan);
1286}
1287
1288static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1289{
1290 long sec = usec / 1000000;
1291 long nsec = (usec % 1000000) * 1000;
1292 ktime_t t = ktime_set(sec, nsec);
1293
1294 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1295}
1296
1297static void sci_dma_rx_reenable_irq(struct sci_port *s)
1298{
1299 struct uart_port *port = &s->port;
1300 u16 scr;
1301
1302 /* Direct new serial port interrupts back to CPU */
1303 scr = sci_serial_in(port, SCSCR);
1304 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1305 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1306 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1307 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1308 scif_set_rtrg(port, s->rx_trigger);
1309 else
1310 scr &= ~SCSCR_RDRQE;
1311 }
1312 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1313}
1314
1315static void sci_dma_rx_complete(void *arg)
1316{
1317 struct sci_port *s = arg;
1318 struct dma_chan *chan = s->chan_rx;
1319 struct uart_port *port = &s->port;
1320 struct dma_async_tx_descriptor *desc;
1321 unsigned long flags;
1322 int active, count = 0;
1323
1324 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1325 s->active_rx);
1326
1327 uart_port_lock_irqsave(port, &flags);
1328
1329 active = sci_dma_rx_find_active(s);
1330 if (active >= 0)
1331 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1332
1333 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1334
1335 if (count)
1336 tty_flip_buffer_push(&port->state->port);
1337
1338 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1339 DMA_DEV_TO_MEM,
1340 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1341 if (!desc)
1342 goto fail;
1343
1344 desc->callback = sci_dma_rx_complete;
1345 desc->callback_param = s;
1346 s->cookie_rx[active] = dmaengine_submit(desc);
1347 if (dma_submit_error(s->cookie_rx[active]))
1348 goto fail;
1349
1350 s->active_rx = s->cookie_rx[!active];
1351
1352 dma_async_issue_pending(chan);
1353
1354 uart_port_unlock_irqrestore(port, flags);
1355 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1356 __func__, s->cookie_rx[active], active, s->active_rx);
1357 return;
1358
1359fail:
1360 uart_port_unlock_irqrestore(port, flags);
1361 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1362 /* Switch to PIO */
1363 uart_port_lock_irqsave(port, &flags);
1364 dmaengine_terminate_async(chan);
1365 sci_dma_rx_chan_invalidate(s);
1366 sci_dma_rx_reenable_irq(s);
1367 uart_port_unlock_irqrestore(port, flags);
1368}
1369
1370static void sci_dma_tx_release(struct sci_port *s)
1371{
1372 struct dma_chan *chan = s->chan_tx_saved;
1373
1374 cancel_work_sync(&s->work_tx);
1375 s->chan_tx_saved = s->chan_tx = NULL;
1376 s->cookie_tx = -EINVAL;
1377 dmaengine_terminate_sync(chan);
1378 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1379 DMA_TO_DEVICE);
1380 dma_release_channel(chan);
1381}
1382
1383static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1384{
1385 struct dma_chan *chan = s->chan_rx;
1386 struct uart_port *port = &s->port;
1387 unsigned long flags;
1388 int i;
1389
1390 for (i = 0; i < 2; i++) {
1391 struct scatterlist *sg = &s->sg_rx[i];
1392 struct dma_async_tx_descriptor *desc;
1393
1394 desc = dmaengine_prep_slave_sg(chan,
1395 sg, 1, DMA_DEV_TO_MEM,
1396 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1397 if (!desc)
1398 goto fail;
1399
1400 desc->callback = sci_dma_rx_complete;
1401 desc->callback_param = s;
1402 s->cookie_rx[i] = dmaengine_submit(desc);
1403 if (dma_submit_error(s->cookie_rx[i]))
1404 goto fail;
1405
1406 }
1407
1408 s->active_rx = s->cookie_rx[0];
1409
1410 dma_async_issue_pending(chan);
1411 return 0;
1412
1413fail:
1414 /* Switch to PIO */
1415 if (!port_lock_held)
1416 uart_port_lock_irqsave(port, &flags);
1417 if (i)
1418 dmaengine_terminate_async(chan);
1419 sci_dma_rx_chan_invalidate(s);
1420 sci_start_rx(port);
1421 if (!port_lock_held)
1422 uart_port_unlock_irqrestore(port, flags);
1423 return -EAGAIN;
1424}
1425
1426static void sci_dma_tx_work_fn(struct work_struct *work)
1427{
1428 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1429 struct dma_async_tx_descriptor *desc;
1430 struct dma_chan *chan = s->chan_tx;
1431 struct uart_port *port = &s->port;
1432 struct circ_buf *xmit = &port->state->xmit;
1433 unsigned long flags;
1434 dma_addr_t buf;
1435 int head, tail;
1436
1437 /*
1438 * DMA is idle now.
1439 * Port xmit buffer is already mapped, and it is one page... Just adjust
1440 * offsets and lengths. Since it is a circular buffer, we have to
1441 * transmit till the end, and then the rest. Take the port lock to get a
1442 * consistent xmit buffer state.
1443 */
1444 uart_port_lock_irq(port);
1445 head = xmit->head;
1446 tail = xmit->tail;
1447 buf = s->tx_dma_addr + tail;
1448 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
1449 if (!s->tx_dma_len) {
1450 /* Transmit buffer has been flushed */
1451 uart_port_unlock_irq(port);
1452 return;
1453 }
1454
1455 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1456 DMA_MEM_TO_DEV,
1457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1458 if (!desc) {
1459 uart_port_unlock_irq(port);
1460 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1461 goto switch_to_pio;
1462 }
1463
1464 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1465 DMA_TO_DEVICE);
1466
1467 desc->callback = sci_dma_tx_complete;
1468 desc->callback_param = s;
1469 s->cookie_tx = dmaengine_submit(desc);
1470 if (dma_submit_error(s->cookie_tx)) {
1471 uart_port_unlock_irq(port);
1472 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1473 goto switch_to_pio;
1474 }
1475
1476 uart_port_unlock_irq(port);
1477 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1478 __func__, xmit->buf, tail, head, s->cookie_tx);
1479
1480 dma_async_issue_pending(chan);
1481 return;
1482
1483switch_to_pio:
1484 uart_port_lock_irqsave(port, &flags);
1485 s->chan_tx = NULL;
1486 sci_start_tx(port);
1487 uart_port_unlock_irqrestore(port, flags);
1488 return;
1489}
1490
1491static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1492{
1493 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1494 struct dma_chan *chan = s->chan_rx;
1495 struct uart_port *port = &s->port;
1496 struct dma_tx_state state;
1497 enum dma_status status;
1498 unsigned long flags;
1499 unsigned int read;
1500 int active, count;
1501
1502 dev_dbg(port->dev, "DMA Rx timed out\n");
1503
1504 uart_port_lock_irqsave(port, &flags);
1505
1506 active = sci_dma_rx_find_active(s);
1507 if (active < 0) {
1508 uart_port_unlock_irqrestore(port, flags);
1509 return HRTIMER_NORESTART;
1510 }
1511
1512 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1513 if (status == DMA_COMPLETE) {
1514 uart_port_unlock_irqrestore(port, flags);
1515 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1516 s->active_rx, active);
1517
1518 /* Let packet complete handler take care of the packet */
1519 return HRTIMER_NORESTART;
1520 }
1521
1522 dmaengine_pause(chan);
1523
1524 /*
1525 * sometimes DMA transfer doesn't stop even if it is stopped and
1526 * data keeps on coming until transaction is complete so check
1527 * for DMA_COMPLETE again
1528 * Let packet complete handler take care of the packet
1529 */
1530 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1531 if (status == DMA_COMPLETE) {
1532 uart_port_unlock_irqrestore(port, flags);
1533 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1534 return HRTIMER_NORESTART;
1535 }
1536
1537 /* Handle incomplete DMA receive */
1538 dmaengine_terminate_async(s->chan_rx);
1539 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1540
1541 if (read) {
1542 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1543 if (count)
1544 tty_flip_buffer_push(&port->state->port);
1545 }
1546
1547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1548 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1549 sci_dma_rx_submit(s, true);
1550
1551 sci_dma_rx_reenable_irq(s);
1552
1553 uart_port_unlock_irqrestore(port, flags);
1554
1555 return HRTIMER_NORESTART;
1556}
1557
1558static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1559 enum dma_transfer_direction dir)
1560{
1561 struct dma_chan *chan;
1562 struct dma_slave_config cfg;
1563 int ret;
1564
1565 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1566 if (IS_ERR(chan)) {
1567 dev_dbg(port->dev, "dma_request_chan failed\n");
1568 return NULL;
1569 }
1570
1571 memset(&cfg, 0, sizeof(cfg));
1572 cfg.direction = dir;
1573 cfg.dst_addr = port->mapbase +
1574 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1575 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1576 cfg.src_addr = port->mapbase +
1577 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1578 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1579
1580 ret = dmaengine_slave_config(chan, &cfg);
1581 if (ret) {
1582 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1583 dma_release_channel(chan);
1584 return NULL;
1585 }
1586
1587 return chan;
1588}
1589
1590static void sci_request_dma(struct uart_port *port)
1591{
1592 struct sci_port *s = to_sci_port(port);
1593 struct dma_chan *chan;
1594
1595 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1596
1597 /*
1598 * DMA on console may interfere with Kernel log messages which use
1599 * plain putchar(). So, simply don't use it with a console.
1600 */
1601 if (uart_console(port))
1602 return;
1603
1604 if (!port->dev->of_node)
1605 return;
1606
1607 s->cookie_tx = -EINVAL;
1608
1609 /*
1610 * Don't request a dma channel if no channel was specified
1611 * in the device tree.
1612 */
1613 if (!of_property_present(port->dev->of_node, "dmas"))
1614 return;
1615
1616 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1617 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1618 if (chan) {
1619 /* UART circular tx buffer is an aligned page. */
1620 s->tx_dma_addr = dma_map_single(chan->device->dev,
1621 port->state->xmit.buf,
1622 UART_XMIT_SIZE,
1623 DMA_TO_DEVICE);
1624 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1625 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1626 dma_release_channel(chan);
1627 } else {
1628 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1629 __func__, UART_XMIT_SIZE,
1630 port->state->xmit.buf, &s->tx_dma_addr);
1631
1632 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1633 s->chan_tx_saved = s->chan_tx = chan;
1634 }
1635 }
1636
1637 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1638 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1639 if (chan) {
1640 unsigned int i;
1641 dma_addr_t dma;
1642 void *buf;
1643
1644 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1645 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1646 &dma, GFP_KERNEL);
1647 if (!buf) {
1648 dev_warn(port->dev,
1649 "Failed to allocate Rx dma buffer, using PIO\n");
1650 dma_release_channel(chan);
1651 return;
1652 }
1653
1654 for (i = 0; i < 2; i++) {
1655 struct scatterlist *sg = &s->sg_rx[i];
1656
1657 sg_init_table(sg, 1);
1658 s->rx_buf[i] = buf;
1659 sg_dma_address(sg) = dma;
1660 sg_dma_len(sg) = s->buf_len_rx;
1661
1662 buf += s->buf_len_rx;
1663 dma += s->buf_len_rx;
1664 }
1665
1666 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1667 s->rx_timer.function = sci_dma_rx_timer_fn;
1668
1669 s->chan_rx_saved = s->chan_rx = chan;
1670
1671 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1672 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1673 sci_dma_rx_submit(s, false);
1674 }
1675}
1676
1677static void sci_free_dma(struct uart_port *port)
1678{
1679 struct sci_port *s = to_sci_port(port);
1680
1681 if (s->chan_tx_saved)
1682 sci_dma_tx_release(s);
1683 if (s->chan_rx_saved)
1684 sci_dma_rx_release(s);
1685}
1686
1687static void sci_flush_buffer(struct uart_port *port)
1688{
1689 struct sci_port *s = to_sci_port(port);
1690
1691 /*
1692 * In uart_flush_buffer(), the xmit circular buffer has just been
1693 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1694 * pending transfers
1695 */
1696 s->tx_dma_len = 0;
1697 if (s->chan_tx) {
1698 dmaengine_terminate_async(s->chan_tx);
1699 s->cookie_tx = -EINVAL;
1700 }
1701}
1702#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1703static inline void sci_request_dma(struct uart_port *port)
1704{
1705}
1706
1707static inline void sci_free_dma(struct uart_port *port)
1708{
1709}
1710
1711#define sci_flush_buffer NULL
1712#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1713
1714static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1715{
1716 struct uart_port *port = ptr;
1717 struct sci_port *s = to_sci_port(port);
1718
1719#ifdef CONFIG_SERIAL_SH_SCI_DMA
1720 if (s->chan_rx) {
1721 u16 scr = sci_serial_in(port, SCSCR);
1722 u16 ssr = sci_serial_in(port, SCxSR);
1723
1724 /* Disable future Rx interrupts */
1725 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1726 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1727 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1728 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1729 scif_set_rtrg(port, 1);
1730 scr |= SCSCR_RIE;
1731 } else {
1732 scr |= SCSCR_RDRQE;
1733 }
1734 } else {
1735 if (sci_dma_rx_submit(s, false) < 0)
1736 goto handle_pio;
1737
1738 scr &= ~SCSCR_RIE;
1739 }
1740 sci_serial_out(port, SCSCR, scr);
1741 /* Clear current interrupt */
1742 sci_serial_out(port, SCxSR,
1743 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1744 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1745 jiffies, s->rx_timeout);
1746 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1747
1748 return IRQ_HANDLED;
1749 }
1750
1751handle_pio:
1752#endif
1753
1754 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1755 if (!scif_rtrg_enabled(port))
1756 scif_set_rtrg(port, s->rx_trigger);
1757
1758 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1759 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1760 }
1761
1762 /* I think sci_receive_chars has to be called irrespective
1763 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1764 * to be disabled?
1765 */
1766 sci_receive_chars(port);
1767
1768 return IRQ_HANDLED;
1769}
1770
1771static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1772{
1773 struct uart_port *port = ptr;
1774 unsigned long flags;
1775
1776 uart_port_lock_irqsave(port, &flags);
1777 sci_transmit_chars(port);
1778 uart_port_unlock_irqrestore(port, flags);
1779
1780 return IRQ_HANDLED;
1781}
1782
1783static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1784{
1785 struct uart_port *port = ptr;
1786 unsigned long flags;
1787 unsigned short ctrl;
1788
1789 if (port->type != PORT_SCI)
1790 return sci_tx_interrupt(irq, ptr);
1791
1792 uart_port_lock_irqsave(port, &flags);
1793 ctrl = sci_serial_in(port, SCSCR);
1794 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1795 sci_serial_out(port, SCSCR, ctrl);
1796 uart_port_unlock_irqrestore(port, flags);
1797
1798 return IRQ_HANDLED;
1799}
1800
1801static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1802{
1803 struct uart_port *port = ptr;
1804
1805 /* Handle BREAKs */
1806 sci_handle_breaks(port);
1807
1808 /* drop invalid character received before break was detected */
1809 sci_serial_in(port, SCxRDR);
1810
1811 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1812
1813 return IRQ_HANDLED;
1814}
1815
1816static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1817{
1818 struct uart_port *port = ptr;
1819 struct sci_port *s = to_sci_port(port);
1820
1821 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1822 /* Break and Error interrupts are muxed */
1823 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1824
1825 /* Break Interrupt */
1826 if (ssr_status & SCxSR_BRK(port))
1827 sci_br_interrupt(irq, ptr);
1828
1829 /* Break only? */
1830 if (!(ssr_status & SCxSR_ERRORS(port)))
1831 return IRQ_HANDLED;
1832 }
1833
1834 /* Handle errors */
1835 if (port->type == PORT_SCI) {
1836 if (sci_handle_errors(port)) {
1837 /* discard character in rx buffer */
1838 sci_serial_in(port, SCxSR);
1839 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1840 }
1841 } else {
1842 sci_handle_fifo_overrun(port);
1843 if (!s->chan_rx)
1844 sci_receive_chars(port);
1845 }
1846
1847 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1848
1849 /* Kick the transmission */
1850 if (!s->chan_tx)
1851 sci_tx_interrupt(irq, ptr);
1852
1853 return IRQ_HANDLED;
1854}
1855
1856static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1857{
1858 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1859 struct uart_port *port = ptr;
1860 struct sci_port *s = to_sci_port(port);
1861 irqreturn_t ret = IRQ_NONE;
1862
1863 ssr_status = sci_serial_in(port, SCxSR);
1864 scr_status = sci_serial_in(port, SCSCR);
1865 if (s->params->overrun_reg == SCxSR)
1866 orer_status = ssr_status;
1867 else if (sci_getreg(port, s->params->overrun_reg)->size)
1868 orer_status = sci_serial_in(port, s->params->overrun_reg);
1869
1870 err_enabled = scr_status & port_rx_irq_mask(port);
1871
1872 /* Tx Interrupt */
1873 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1874 !s->chan_tx)
1875 ret = sci_tx_interrupt(irq, ptr);
1876
1877 /*
1878 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1879 * DR flags
1880 */
1881 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1882 (scr_status & SCSCR_RIE))
1883 ret = sci_rx_interrupt(irq, ptr);
1884
1885 /* Error Interrupt */
1886 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1887 ret = sci_er_interrupt(irq, ptr);
1888
1889 /* Break Interrupt */
1890 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1891 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1892 ret = sci_br_interrupt(irq, ptr);
1893
1894 /* Overrun Interrupt */
1895 if (orer_status & s->params->overrun_mask) {
1896 sci_handle_fifo_overrun(port);
1897 ret = IRQ_HANDLED;
1898 }
1899
1900 return ret;
1901}
1902
1903static const struct sci_irq_desc {
1904 const char *desc;
1905 irq_handler_t handler;
1906} sci_irq_desc[] = {
1907 /*
1908 * Split out handlers, the default case.
1909 */
1910 [SCIx_ERI_IRQ] = {
1911 .desc = "rx err",
1912 .handler = sci_er_interrupt,
1913 },
1914
1915 [SCIx_RXI_IRQ] = {
1916 .desc = "rx full",
1917 .handler = sci_rx_interrupt,
1918 },
1919
1920 [SCIx_TXI_IRQ] = {
1921 .desc = "tx empty",
1922 .handler = sci_tx_interrupt,
1923 },
1924
1925 [SCIx_BRI_IRQ] = {
1926 .desc = "break",
1927 .handler = sci_br_interrupt,
1928 },
1929
1930 [SCIx_DRI_IRQ] = {
1931 .desc = "rx ready",
1932 .handler = sci_rx_interrupt,
1933 },
1934
1935 [SCIx_TEI_IRQ] = {
1936 .desc = "tx end",
1937 .handler = sci_tx_end_interrupt,
1938 },
1939
1940 /*
1941 * Special muxed handler.
1942 */
1943 [SCIx_MUX_IRQ] = {
1944 .desc = "mux",
1945 .handler = sci_mpxed_interrupt,
1946 },
1947};
1948
1949static int sci_request_irq(struct sci_port *port)
1950{
1951 struct uart_port *up = &port->port;
1952 int i, j, w, ret = 0;
1953
1954 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1955 const struct sci_irq_desc *desc;
1956 int irq;
1957
1958 /* Check if already registered (muxed) */
1959 for (w = 0; w < i; w++)
1960 if (port->irqs[w] == port->irqs[i])
1961 w = i + 1;
1962 if (w > i)
1963 continue;
1964
1965 if (SCIx_IRQ_IS_MUXED(port)) {
1966 i = SCIx_MUX_IRQ;
1967 irq = up->irq;
1968 } else {
1969 irq = port->irqs[i];
1970
1971 /*
1972 * Certain port types won't support all of the
1973 * available interrupt sources.
1974 */
1975 if (unlikely(irq < 0))
1976 continue;
1977 }
1978
1979 desc = sci_irq_desc + i;
1980 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1981 dev_name(up->dev), desc->desc);
1982 if (!port->irqstr[j]) {
1983 ret = -ENOMEM;
1984 goto out_nomem;
1985 }
1986
1987 ret = request_irq(irq, desc->handler, up->irqflags,
1988 port->irqstr[j], port);
1989 if (unlikely(ret)) {
1990 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1991 goto out_noirq;
1992 }
1993 }
1994
1995 return 0;
1996
1997out_noirq:
1998 while (--i >= 0)
1999 free_irq(port->irqs[i], port);
2000
2001out_nomem:
2002 while (--j >= 0)
2003 kfree(port->irqstr[j]);
2004
2005 return ret;
2006}
2007
2008static void sci_free_irq(struct sci_port *port)
2009{
2010 int i, j;
2011
2012 /*
2013 * Intentionally in reverse order so we iterate over the muxed
2014 * IRQ first.
2015 */
2016 for (i = 0; i < SCIx_NR_IRQS; i++) {
2017 int irq = port->irqs[i];
2018
2019 /*
2020 * Certain port types won't support all of the available
2021 * interrupt sources.
2022 */
2023 if (unlikely(irq < 0))
2024 continue;
2025
2026 /* Check if already freed (irq was muxed) */
2027 for (j = 0; j < i; j++)
2028 if (port->irqs[j] == irq)
2029 j = i + 1;
2030 if (j > i)
2031 continue;
2032
2033 free_irq(port->irqs[i], port);
2034 kfree(port->irqstr[i]);
2035
2036 if (SCIx_IRQ_IS_MUXED(port)) {
2037 /* If there's only one IRQ, we're done. */
2038 return;
2039 }
2040 }
2041}
2042
2043static unsigned int sci_tx_empty(struct uart_port *port)
2044{
2045 unsigned short status = sci_serial_in(port, SCxSR);
2046 unsigned short in_tx_fifo = sci_txfill(port);
2047
2048 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2049}
2050
2051static void sci_set_rts(struct uart_port *port, bool state)
2052{
2053 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2054 u16 data = sci_serial_in(port, SCPDR);
2055
2056 /* Active low */
2057 if (state)
2058 data &= ~SCPDR_RTSD;
2059 else
2060 data |= SCPDR_RTSD;
2061 sci_serial_out(port, SCPDR, data);
2062
2063 /* RTS# is output */
2064 sci_serial_out(port, SCPCR,
2065 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2066 } else if (sci_getreg(port, SCSPTR)->size) {
2067 u16 ctrl = sci_serial_in(port, SCSPTR);
2068
2069 /* Active low */
2070 if (state)
2071 ctrl &= ~SCSPTR_RTSDT;
2072 else
2073 ctrl |= SCSPTR_RTSDT;
2074 sci_serial_out(port, SCSPTR, ctrl);
2075 }
2076}
2077
2078static bool sci_get_cts(struct uart_port *port)
2079{
2080 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2081 /* Active low */
2082 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2083 } else if (sci_getreg(port, SCSPTR)->size) {
2084 /* Active low */
2085 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2086 }
2087
2088 return true;
2089}
2090
2091/*
2092 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2093 * CTS/RTS is supported in hardware by at least one port and controlled
2094 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2095 * handled via the ->init_pins() op, which is a bit of a one-way street,
2096 * lacking any ability to defer pin control -- this will later be
2097 * converted over to the GPIO framework).
2098 *
2099 * Other modes (such as loopback) are supported generically on certain
2100 * port types, but not others. For these it's sufficient to test for the
2101 * existence of the support register and simply ignore the port type.
2102 */
2103static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2104{
2105 struct sci_port *s = to_sci_port(port);
2106
2107 if (mctrl & TIOCM_LOOP) {
2108 const struct plat_sci_reg *reg;
2109
2110 /*
2111 * Standard loopback mode for SCFCR ports.
2112 */
2113 reg = sci_getreg(port, SCFCR);
2114 if (reg->size)
2115 sci_serial_out(port, SCFCR,
2116 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2117 }
2118
2119 mctrl_gpio_set(s->gpios, mctrl);
2120
2121 if (!s->has_rtscts)
2122 return;
2123
2124 if (!(mctrl & TIOCM_RTS)) {
2125 /* Disable Auto RTS */
2126 sci_serial_out(port, SCFCR,
2127 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2128
2129 /* Clear RTS */
2130 sci_set_rts(port, 0);
2131 } else if (s->autorts) {
2132 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2133 /* Enable RTS# pin function */
2134 sci_serial_out(port, SCPCR,
2135 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2136 }
2137
2138 /* Enable Auto RTS */
2139 sci_serial_out(port, SCFCR,
2140 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2141 } else {
2142 /* Set RTS */
2143 sci_set_rts(port, 1);
2144 }
2145}
2146
2147static unsigned int sci_get_mctrl(struct uart_port *port)
2148{
2149 struct sci_port *s = to_sci_port(port);
2150 struct mctrl_gpios *gpios = s->gpios;
2151 unsigned int mctrl = 0;
2152
2153 mctrl_gpio_get(gpios, &mctrl);
2154
2155 /*
2156 * CTS/RTS is handled in hardware when supported, while nothing
2157 * else is wired up.
2158 */
2159 if (s->autorts) {
2160 if (sci_get_cts(port))
2161 mctrl |= TIOCM_CTS;
2162 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2163 mctrl |= TIOCM_CTS;
2164 }
2165 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2166 mctrl |= TIOCM_DSR;
2167 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2168 mctrl |= TIOCM_CAR;
2169
2170 return mctrl;
2171}
2172
2173static void sci_enable_ms(struct uart_port *port)
2174{
2175 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2176}
2177
2178static void sci_break_ctl(struct uart_port *port, int break_state)
2179{
2180 unsigned short scscr, scsptr;
2181 unsigned long flags;
2182
2183 /* check whether the port has SCSPTR */
2184 if (!sci_getreg(port, SCSPTR)->size) {
2185 /*
2186 * Not supported by hardware. Most parts couple break and rx
2187 * interrupts together, with break detection always enabled.
2188 */
2189 return;
2190 }
2191
2192 uart_port_lock_irqsave(port, &flags);
2193 scsptr = sci_serial_in(port, SCSPTR);
2194 scscr = sci_serial_in(port, SCSCR);
2195
2196 if (break_state == -1) {
2197 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2198 scscr &= ~SCSCR_TE;
2199 } else {
2200 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2201 scscr |= SCSCR_TE;
2202 }
2203
2204 sci_serial_out(port, SCSPTR, scsptr);
2205 sci_serial_out(port, SCSCR, scscr);
2206 uart_port_unlock_irqrestore(port, flags);
2207}
2208
2209static int sci_startup(struct uart_port *port)
2210{
2211 struct sci_port *s = to_sci_port(port);
2212 int ret;
2213
2214 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2215
2216 sci_request_dma(port);
2217
2218 ret = sci_request_irq(s);
2219 if (unlikely(ret < 0)) {
2220 sci_free_dma(port);
2221 return ret;
2222 }
2223
2224 return 0;
2225}
2226
2227static void sci_shutdown(struct uart_port *port)
2228{
2229 struct sci_port *s = to_sci_port(port);
2230 unsigned long flags;
2231 u16 scr;
2232
2233 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2234
2235 s->autorts = false;
2236 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2237
2238 uart_port_lock_irqsave(port, &flags);
2239 sci_stop_rx(port);
2240 sci_stop_tx(port);
2241 /*
2242 * Stop RX and TX, disable related interrupts, keep clock source
2243 * and HSCIF TOT bits
2244 */
2245 scr = sci_serial_in(port, SCSCR);
2246 sci_serial_out(port, SCSCR,
2247 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2248 uart_port_unlock_irqrestore(port, flags);
2249
2250#ifdef CONFIG_SERIAL_SH_SCI_DMA
2251 if (s->chan_rx_saved) {
2252 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2253 port->line);
2254 hrtimer_cancel(&s->rx_timer);
2255 }
2256#endif
2257
2258 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2259 del_timer_sync(&s->rx_fifo_timer);
2260 sci_free_irq(s);
2261 sci_free_dma(port);
2262}
2263
2264static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2265 unsigned int *srr)
2266{
2267 unsigned long freq = s->clk_rates[SCI_SCK];
2268 int err, min_err = INT_MAX;
2269 unsigned int sr;
2270
2271 if (s->port.type != PORT_HSCIF)
2272 freq *= 2;
2273
2274 for_each_sr(sr, s) {
2275 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2276 if (abs(err) >= abs(min_err))
2277 continue;
2278
2279 min_err = err;
2280 *srr = sr - 1;
2281
2282 if (!err)
2283 break;
2284 }
2285
2286 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2287 *srr + 1);
2288 return min_err;
2289}
2290
2291static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2292 unsigned long freq, unsigned int *dlr,
2293 unsigned int *srr)
2294{
2295 int err, min_err = INT_MAX;
2296 unsigned int sr, dl;
2297
2298 if (s->port.type != PORT_HSCIF)
2299 freq *= 2;
2300
2301 for_each_sr(sr, s) {
2302 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2303 dl = clamp(dl, 1U, 65535U);
2304
2305 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2306 if (abs(err) >= abs(min_err))
2307 continue;
2308
2309 min_err = err;
2310 *dlr = dl;
2311 *srr = sr - 1;
2312
2313 if (!err)
2314 break;
2315 }
2316
2317 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2318 min_err, *dlr, *srr + 1);
2319 return min_err;
2320}
2321
2322/* calculate sample rate, BRR, and clock select */
2323static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2324 unsigned int *brr, unsigned int *srr,
2325 unsigned int *cks)
2326{
2327 unsigned long freq = s->clk_rates[SCI_FCK];
2328 unsigned int sr, br, prediv, scrate, c;
2329 int err, min_err = INT_MAX;
2330
2331 if (s->port.type != PORT_HSCIF)
2332 freq *= 2;
2333
2334 /*
2335 * Find the combination of sample rate and clock select with the
2336 * smallest deviation from the desired baud rate.
2337 * Prefer high sample rates to maximise the receive margin.
2338 *
2339 * M: Receive margin (%)
2340 * N: Ratio of bit rate to clock (N = sampling rate)
2341 * D: Clock duty (D = 0 to 1.0)
2342 * L: Frame length (L = 9 to 12)
2343 * F: Absolute value of clock frequency deviation
2344 *
2345 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2346 * (|D - 0.5| / N * (1 + F))|
2347 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2348 */
2349 for_each_sr(sr, s) {
2350 for (c = 0; c <= 3; c++) {
2351 /* integerized formulas from HSCIF documentation */
2352 prediv = sr << (2 * c + 1);
2353
2354 /*
2355 * We need to calculate:
2356 *
2357 * br = freq / (prediv * bps) clamped to [1..256]
2358 * err = freq / (br * prediv) - bps
2359 *
2360 * Watch out for overflow when calculating the desired
2361 * sampling clock rate!
2362 */
2363 if (bps > UINT_MAX / prediv)
2364 break;
2365
2366 scrate = prediv * bps;
2367 br = DIV_ROUND_CLOSEST(freq, scrate);
2368 br = clamp(br, 1U, 256U);
2369
2370 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2371 if (abs(err) >= abs(min_err))
2372 continue;
2373
2374 min_err = err;
2375 *brr = br - 1;
2376 *srr = sr - 1;
2377 *cks = c;
2378
2379 if (!err)
2380 goto found;
2381 }
2382 }
2383
2384found:
2385 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2386 min_err, *brr, *srr + 1, *cks);
2387 return min_err;
2388}
2389
2390static void sci_reset(struct uart_port *port)
2391{
2392 const struct plat_sci_reg *reg;
2393 unsigned int status;
2394 struct sci_port *s = to_sci_port(port);
2395
2396 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2397
2398 reg = sci_getreg(port, SCFCR);
2399 if (reg->size)
2400 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2401
2402 sci_clear_SCxSR(port,
2403 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2404 SCxSR_BREAK_CLEAR(port));
2405 if (sci_getreg(port, SCLSR)->size) {
2406 status = sci_serial_in(port, SCLSR);
2407 status &= ~(SCLSR_TO | SCLSR_ORER);
2408 sci_serial_out(port, SCLSR, status);
2409 }
2410
2411 if (s->rx_trigger > 1) {
2412 if (s->rx_fifo_timeout) {
2413 scif_set_rtrg(port, 1);
2414 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2415 } else {
2416 if (port->type == PORT_SCIFA ||
2417 port->type == PORT_SCIFB)
2418 scif_set_rtrg(port, 1);
2419 else
2420 scif_set_rtrg(port, s->rx_trigger);
2421 }
2422 }
2423}
2424
2425static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2426 const struct ktermios *old)
2427{
2428 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2429 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2430 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2431 struct sci_port *s = to_sci_port(port);
2432 const struct plat_sci_reg *reg;
2433 int min_err = INT_MAX, err;
2434 unsigned long max_freq = 0;
2435 int best_clk = -1;
2436 unsigned long flags;
2437
2438 if ((termios->c_cflag & CSIZE) == CS7) {
2439 smr_val |= SCSMR_CHR;
2440 } else {
2441 termios->c_cflag &= ~CSIZE;
2442 termios->c_cflag |= CS8;
2443 }
2444 if (termios->c_cflag & PARENB)
2445 smr_val |= SCSMR_PE;
2446 if (termios->c_cflag & PARODD)
2447 smr_val |= SCSMR_PE | SCSMR_ODD;
2448 if (termios->c_cflag & CSTOPB)
2449 smr_val |= SCSMR_STOP;
2450
2451 /*
2452 * earlyprintk comes here early on with port->uartclk set to zero.
2453 * the clock framework is not up and running at this point so here
2454 * we assume that 115200 is the maximum baud rate. please note that
2455 * the baud rate is not programmed during earlyprintk - it is assumed
2456 * that the previous boot loader has enabled required clocks and
2457 * setup the baud rate generator hardware for us already.
2458 */
2459 if (!port->uartclk) {
2460 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2461 goto done;
2462 }
2463
2464 for (i = 0; i < SCI_NUM_CLKS; i++)
2465 max_freq = max(max_freq, s->clk_rates[i]);
2466
2467 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2468 if (!baud)
2469 goto done;
2470
2471 /*
2472 * There can be multiple sources for the sampling clock. Find the one
2473 * that gives us the smallest deviation from the desired baud rate.
2474 */
2475
2476 /* Optional Undivided External Clock */
2477 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2478 port->type != PORT_SCIFB) {
2479 err = sci_sck_calc(s, baud, &srr1);
2480 if (abs(err) < abs(min_err)) {
2481 best_clk = SCI_SCK;
2482 scr_val = SCSCR_CKE1;
2483 sccks = SCCKS_CKS;
2484 min_err = err;
2485 srr = srr1;
2486 if (!err)
2487 goto done;
2488 }
2489 }
2490
2491 /* Optional BRG Frequency Divided External Clock */
2492 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2493 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2494 &srr1);
2495 if (abs(err) < abs(min_err)) {
2496 best_clk = SCI_SCIF_CLK;
2497 scr_val = SCSCR_CKE1;
2498 sccks = 0;
2499 min_err = err;
2500 dl = dl1;
2501 srr = srr1;
2502 if (!err)
2503 goto done;
2504 }
2505 }
2506
2507 /* Optional BRG Frequency Divided Internal Clock */
2508 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2509 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2510 &srr1);
2511 if (abs(err) < abs(min_err)) {
2512 best_clk = SCI_BRG_INT;
2513 scr_val = SCSCR_CKE1;
2514 sccks = SCCKS_XIN;
2515 min_err = err;
2516 dl = dl1;
2517 srr = srr1;
2518 if (!min_err)
2519 goto done;
2520 }
2521 }
2522
2523 /* Divided Functional Clock using standard Bit Rate Register */
2524 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2525 if (abs(err) < abs(min_err)) {
2526 best_clk = SCI_FCK;
2527 scr_val = 0;
2528 min_err = err;
2529 brr = brr1;
2530 srr = srr1;
2531 cks = cks1;
2532 }
2533
2534done:
2535 if (best_clk >= 0)
2536 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2537 s->clks[best_clk], baud, min_err);
2538
2539 sci_port_enable(s);
2540
2541 /*
2542 * Program the optional External Baud Rate Generator (BRG) first.
2543 * It controls the mux to select (H)SCK or frequency divided clock.
2544 */
2545 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2546 sci_serial_out(port, SCDL, dl);
2547 sci_serial_out(port, SCCKS, sccks);
2548 }
2549
2550 uart_port_lock_irqsave(port, &flags);
2551
2552 sci_reset(port);
2553
2554 uart_update_timeout(port, termios->c_cflag, baud);
2555
2556 /* byte size and parity */
2557 bits = tty_get_frame_size(termios->c_cflag);
2558
2559 if (sci_getreg(port, SEMR)->size)
2560 sci_serial_out(port, SEMR, 0);
2561
2562 if (best_clk >= 0) {
2563 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2564 switch (srr + 1) {
2565 case 5: smr_val |= SCSMR_SRC_5; break;
2566 case 7: smr_val |= SCSMR_SRC_7; break;
2567 case 11: smr_val |= SCSMR_SRC_11; break;
2568 case 13: smr_val |= SCSMR_SRC_13; break;
2569 case 16: smr_val |= SCSMR_SRC_16; break;
2570 case 17: smr_val |= SCSMR_SRC_17; break;
2571 case 19: smr_val |= SCSMR_SRC_19; break;
2572 case 27: smr_val |= SCSMR_SRC_27; break;
2573 }
2574 smr_val |= cks;
2575 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2576 sci_serial_out(port, SCSMR, smr_val);
2577 sci_serial_out(port, SCBRR, brr);
2578 if (sci_getreg(port, HSSRR)->size) {
2579 unsigned int hssrr = srr | HSCIF_SRE;
2580 /* Calculate deviation from intended rate at the
2581 * center of the last stop bit in sampling clocks.
2582 */
2583 int last_stop = bits * 2 - 1;
2584 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2585 (int)(srr + 1),
2586 2 * (int)baud);
2587
2588 if (abs(deviation) >= 2) {
2589 /* At least two sampling clocks off at the
2590 * last stop bit; we can increase the error
2591 * margin by shifting the sampling point.
2592 */
2593 int shift = clamp(deviation / 2, -8, 7);
2594
2595 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2596 HSCIF_SRHP_MASK;
2597 hssrr |= HSCIF_SRDE;
2598 }
2599 sci_serial_out(port, HSSRR, hssrr);
2600 }
2601
2602 /* Wait one bit interval */
2603 udelay((1000000 + (baud - 1)) / baud);
2604 } else {
2605 /* Don't touch the bit rate configuration */
2606 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2607 smr_val |= sci_serial_in(port, SCSMR) &
2608 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2609 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2610 sci_serial_out(port, SCSMR, smr_val);
2611 }
2612
2613 sci_init_pins(port, termios->c_cflag);
2614
2615 port->status &= ~UPSTAT_AUTOCTS;
2616 s->autorts = false;
2617 reg = sci_getreg(port, SCFCR);
2618 if (reg->size) {
2619 unsigned short ctrl = sci_serial_in(port, SCFCR);
2620
2621 if ((port->flags & UPF_HARD_FLOW) &&
2622 (termios->c_cflag & CRTSCTS)) {
2623 /* There is no CTS interrupt to restart the hardware */
2624 port->status |= UPSTAT_AUTOCTS;
2625 /* MCE is enabled when RTS is raised */
2626 s->autorts = true;
2627 }
2628
2629 /*
2630 * As we've done a sci_reset() above, ensure we don't
2631 * interfere with the FIFOs while toggling MCE. As the
2632 * reset values could still be set, simply mask them out.
2633 */
2634 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2635
2636 sci_serial_out(port, SCFCR, ctrl);
2637 }
2638 if (port->flags & UPF_HARD_FLOW) {
2639 /* Refresh (Auto) RTS */
2640 sci_set_mctrl(port, port->mctrl);
2641 }
2642
2643 /*
2644 * For SCI, TE (transmit enable) must be set after setting TIE
2645 * (transmit interrupt enable) or in the same instruction to
2646 * start the transmitting process. So skip setting TE here for SCI.
2647 */
2648 if (port->type != PORT_SCI)
2649 scr_val |= SCSCR_TE;
2650 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2651 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2652 if ((srr + 1 == 5) &&
2653 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2654 /*
2655 * In asynchronous mode, when the sampling rate is 1/5, first
2656 * received data may become invalid on some SCIFA and SCIFB.
2657 * To avoid this problem wait more than 1 serial data time (1
2658 * bit time x serial data number) after setting SCSCR.RE = 1.
2659 */
2660 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2661 }
2662
2663 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2664 s->rx_frame = (10000 * bits) / (baud / 100);
2665#ifdef CONFIG_SERIAL_SH_SCI_DMA
2666 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2667#endif
2668
2669 if ((termios->c_cflag & CREAD) != 0)
2670 sci_start_rx(port);
2671
2672 uart_port_unlock_irqrestore(port, flags);
2673
2674 sci_port_disable(s);
2675
2676 if (UART_ENABLE_MS(port, termios->c_cflag))
2677 sci_enable_ms(port);
2678}
2679
2680static void sci_pm(struct uart_port *port, unsigned int state,
2681 unsigned int oldstate)
2682{
2683 struct sci_port *sci_port = to_sci_port(port);
2684
2685 switch (state) {
2686 case UART_PM_STATE_OFF:
2687 sci_port_disable(sci_port);
2688 break;
2689 default:
2690 sci_port_enable(sci_port);
2691 break;
2692 }
2693}
2694
2695static const char *sci_type(struct uart_port *port)
2696{
2697 switch (port->type) {
2698 case PORT_IRDA:
2699 return "irda";
2700 case PORT_SCI:
2701 return "sci";
2702 case PORT_SCIF:
2703 return "scif";
2704 case PORT_SCIFA:
2705 return "scifa";
2706 case PORT_SCIFB:
2707 return "scifb";
2708 case PORT_HSCIF:
2709 return "hscif";
2710 }
2711
2712 return NULL;
2713}
2714
2715static int sci_remap_port(struct uart_port *port)
2716{
2717 struct sci_port *sport = to_sci_port(port);
2718
2719 /*
2720 * Nothing to do if there's already an established membase.
2721 */
2722 if (port->membase)
2723 return 0;
2724
2725 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2726 port->membase = ioremap(port->mapbase, sport->reg_size);
2727 if (unlikely(!port->membase)) {
2728 dev_err(port->dev, "can't remap port#%d\n", port->line);
2729 return -ENXIO;
2730 }
2731 } else {
2732 /*
2733 * For the simple (and majority of) cases where we don't
2734 * need to do any remapping, just cast the cookie
2735 * directly.
2736 */
2737 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2738 }
2739
2740 return 0;
2741}
2742
2743static void sci_release_port(struct uart_port *port)
2744{
2745 struct sci_port *sport = to_sci_port(port);
2746
2747 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2748 iounmap(port->membase);
2749 port->membase = NULL;
2750 }
2751
2752 release_mem_region(port->mapbase, sport->reg_size);
2753}
2754
2755static int sci_request_port(struct uart_port *port)
2756{
2757 struct resource *res;
2758 struct sci_port *sport = to_sci_port(port);
2759 int ret;
2760
2761 res = request_mem_region(port->mapbase, sport->reg_size,
2762 dev_name(port->dev));
2763 if (unlikely(res == NULL)) {
2764 dev_err(port->dev, "request_mem_region failed.");
2765 return -EBUSY;
2766 }
2767
2768 ret = sci_remap_port(port);
2769 if (unlikely(ret != 0)) {
2770 release_resource(res);
2771 return ret;
2772 }
2773
2774 return 0;
2775}
2776
2777static void sci_config_port(struct uart_port *port, int flags)
2778{
2779 if (flags & UART_CONFIG_TYPE) {
2780 struct sci_port *sport = to_sci_port(port);
2781
2782 port->type = sport->cfg->type;
2783 sci_request_port(port);
2784 }
2785}
2786
2787static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2788{
2789 if (ser->baud_base < 2400)
2790 /* No paper tape reader for Mitch.. */
2791 return -EINVAL;
2792
2793 return 0;
2794}
2795
2796static const struct uart_ops sci_uart_ops = {
2797 .tx_empty = sci_tx_empty,
2798 .set_mctrl = sci_set_mctrl,
2799 .get_mctrl = sci_get_mctrl,
2800 .start_tx = sci_start_tx,
2801 .stop_tx = sci_stop_tx,
2802 .stop_rx = sci_stop_rx,
2803 .enable_ms = sci_enable_ms,
2804 .break_ctl = sci_break_ctl,
2805 .startup = sci_startup,
2806 .shutdown = sci_shutdown,
2807 .flush_buffer = sci_flush_buffer,
2808 .set_termios = sci_set_termios,
2809 .pm = sci_pm,
2810 .type = sci_type,
2811 .release_port = sci_release_port,
2812 .request_port = sci_request_port,
2813 .config_port = sci_config_port,
2814 .verify_port = sci_verify_port,
2815#ifdef CONFIG_CONSOLE_POLL
2816 .poll_get_char = sci_poll_get_char,
2817 .poll_put_char = sci_poll_put_char,
2818#endif
2819};
2820
2821static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2822{
2823 const char *clk_names[] = {
2824 [SCI_FCK] = "fck",
2825 [SCI_SCK] = "sck",
2826 [SCI_BRG_INT] = "brg_int",
2827 [SCI_SCIF_CLK] = "scif_clk",
2828 };
2829 struct clk *clk;
2830 unsigned int i;
2831
2832 if (sci_port->cfg->type == PORT_HSCIF)
2833 clk_names[SCI_SCK] = "hsck";
2834
2835 for (i = 0; i < SCI_NUM_CLKS; i++) {
2836 clk = devm_clk_get_optional(dev, clk_names[i]);
2837 if (IS_ERR(clk))
2838 return PTR_ERR(clk);
2839
2840 if (!clk && i == SCI_FCK) {
2841 /*
2842 * Not all SH platforms declare a clock lookup entry
2843 * for SCI devices, in which case we need to get the
2844 * global "peripheral_clk" clock.
2845 */
2846 clk = devm_clk_get(dev, "peripheral_clk");
2847 if (IS_ERR(clk))
2848 return dev_err_probe(dev, PTR_ERR(clk),
2849 "failed to get %s\n",
2850 clk_names[i]);
2851 }
2852
2853 if (!clk)
2854 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2855 else
2856 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2857 clk, clk_get_rate(clk));
2858 sci_port->clks[i] = clk;
2859 }
2860 return 0;
2861}
2862
2863static const struct sci_port_params *
2864sci_probe_regmap(const struct plat_sci_port *cfg)
2865{
2866 unsigned int regtype;
2867
2868 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2869 return &sci_port_params[cfg->regtype];
2870
2871 switch (cfg->type) {
2872 case PORT_SCI:
2873 regtype = SCIx_SCI_REGTYPE;
2874 break;
2875 case PORT_IRDA:
2876 regtype = SCIx_IRDA_REGTYPE;
2877 break;
2878 case PORT_SCIFA:
2879 regtype = SCIx_SCIFA_REGTYPE;
2880 break;
2881 case PORT_SCIFB:
2882 regtype = SCIx_SCIFB_REGTYPE;
2883 break;
2884 case PORT_SCIF:
2885 /*
2886 * The SH-4 is a bit of a misnomer here, although that's
2887 * where this particular port layout originated. This
2888 * configuration (or some slight variation thereof)
2889 * remains the dominant model for all SCIFs.
2890 */
2891 regtype = SCIx_SH4_SCIF_REGTYPE;
2892 break;
2893 case PORT_HSCIF:
2894 regtype = SCIx_HSCIF_REGTYPE;
2895 break;
2896 default:
2897 pr_err("Can't probe register map for given port\n");
2898 return NULL;
2899 }
2900
2901 return &sci_port_params[regtype];
2902}
2903
2904static int sci_init_single(struct platform_device *dev,
2905 struct sci_port *sci_port, unsigned int index,
2906 const struct plat_sci_port *p, bool early)
2907{
2908 struct uart_port *port = &sci_port->port;
2909 const struct resource *res;
2910 unsigned int i;
2911 int ret;
2912
2913 sci_port->cfg = p;
2914
2915 port->ops = &sci_uart_ops;
2916 port->iotype = UPIO_MEM;
2917 port->line = index;
2918 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2919
2920 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2921 if (res == NULL)
2922 return -ENOMEM;
2923
2924 port->mapbase = res->start;
2925 sci_port->reg_size = resource_size(res);
2926
2927 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2928 if (i)
2929 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2930 else
2931 sci_port->irqs[i] = platform_get_irq(dev, i);
2932 }
2933
2934 /*
2935 * The fourth interrupt on SCI port is transmit end interrupt, so
2936 * shuffle the interrupts.
2937 */
2938 if (p->type == PORT_SCI)
2939 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
2940
2941 /* The SCI generates several interrupts. They can be muxed together or
2942 * connected to different interrupt lines. In the muxed case only one
2943 * interrupt resource is specified as there is only one interrupt ID.
2944 * In the non-muxed case, up to 6 interrupt signals might be generated
2945 * from the SCI, however those signals might have their own individual
2946 * interrupt ID numbers, or muxed together with another interrupt.
2947 */
2948 if (sci_port->irqs[0] < 0)
2949 return -ENXIO;
2950
2951 if (sci_port->irqs[1] < 0)
2952 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2953 sci_port->irqs[i] = sci_port->irqs[0];
2954
2955 sci_port->params = sci_probe_regmap(p);
2956 if (unlikely(sci_port->params == NULL))
2957 return -EINVAL;
2958
2959 switch (p->type) {
2960 case PORT_SCIFB:
2961 sci_port->rx_trigger = 48;
2962 break;
2963 case PORT_HSCIF:
2964 sci_port->rx_trigger = 64;
2965 break;
2966 case PORT_SCIFA:
2967 sci_port->rx_trigger = 32;
2968 break;
2969 case PORT_SCIF:
2970 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2971 /* RX triggering not implemented for this IP */
2972 sci_port->rx_trigger = 1;
2973 else
2974 sci_port->rx_trigger = 8;
2975 break;
2976 default:
2977 sci_port->rx_trigger = 1;
2978 break;
2979 }
2980
2981 sci_port->rx_fifo_timeout = 0;
2982 sci_port->hscif_tot = 0;
2983
2984 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2985 * match the SoC datasheet, this should be investigated. Let platform
2986 * data override the sampling rate for now.
2987 */
2988 sci_port->sampling_rate_mask = p->sampling_rate
2989 ? SCI_SR(p->sampling_rate)
2990 : sci_port->params->sampling_rate_mask;
2991
2992 if (!early) {
2993 ret = sci_init_clocks(sci_port, &dev->dev);
2994 if (ret < 0)
2995 return ret;
2996
2997 port->dev = &dev->dev;
2998
2999 pm_runtime_enable(&dev->dev);
3000 }
3001
3002 port->type = p->type;
3003 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3004 port->fifosize = sci_port->params->fifosize;
3005
3006 if (port->type == PORT_SCI && !dev->dev.of_node) {
3007 if (sci_port->reg_size >= 0x20)
3008 port->regshift = 2;
3009 else
3010 port->regshift = 1;
3011 }
3012
3013 /*
3014 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3015 * for the multi-IRQ ports, which is where we are primarily
3016 * concerned with the shutdown path synchronization.
3017 *
3018 * For the muxed case there's nothing more to do.
3019 */
3020 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3021 port->irqflags = 0;
3022
3023 return 0;
3024}
3025
3026static void sci_cleanup_single(struct sci_port *port)
3027{
3028 pm_runtime_disable(port->port.dev);
3029}
3030
3031#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3032 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3033static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3034{
3035 sci_poll_put_char(port, ch);
3036}
3037
3038/*
3039 * Print a string to the serial port trying not to disturb
3040 * any possible real use of the port...
3041 */
3042static void serial_console_write(struct console *co, const char *s,
3043 unsigned count)
3044{
3045 struct sci_port *sci_port = &sci_ports[co->index];
3046 struct uart_port *port = &sci_port->port;
3047 unsigned short bits, ctrl, ctrl_temp;
3048 unsigned long flags;
3049 int locked = 1;
3050
3051 if (port->sysrq)
3052 locked = 0;
3053 else if (oops_in_progress)
3054 locked = uart_port_trylock_irqsave(port, &flags);
3055 else
3056 uart_port_lock_irqsave(port, &flags);
3057
3058 /* first save SCSCR then disable interrupts, keep clock source */
3059 ctrl = sci_serial_in(port, SCSCR);
3060 ctrl_temp = SCSCR_RE | SCSCR_TE |
3061 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3062 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3063 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3064
3065 uart_console_write(port, s, count, serial_console_putchar);
3066
3067 /* wait until fifo is empty and last bit has been transmitted */
3068 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3069 while ((sci_serial_in(port, SCxSR) & bits) != bits)
3070 cpu_relax();
3071
3072 /* restore the SCSCR */
3073 sci_serial_out(port, SCSCR, ctrl);
3074
3075 if (locked)
3076 uart_port_unlock_irqrestore(port, flags);
3077}
3078
3079static int serial_console_setup(struct console *co, char *options)
3080{
3081 struct sci_port *sci_port;
3082 struct uart_port *port;
3083 int baud = 115200;
3084 int bits = 8;
3085 int parity = 'n';
3086 int flow = 'n';
3087 int ret;
3088
3089 /*
3090 * Refuse to handle any bogus ports.
3091 */
3092 if (co->index < 0 || co->index >= SCI_NPORTS)
3093 return -ENODEV;
3094
3095 sci_port = &sci_ports[co->index];
3096 port = &sci_port->port;
3097
3098 /*
3099 * Refuse to handle uninitialized ports.
3100 */
3101 if (!port->ops)
3102 return -ENODEV;
3103
3104 ret = sci_remap_port(port);
3105 if (unlikely(ret != 0))
3106 return ret;
3107
3108 if (options)
3109 uart_parse_options(options, &baud, &parity, &bits, &flow);
3110
3111 return uart_set_options(port, co, baud, parity, bits, flow);
3112}
3113
3114static struct console serial_console = {
3115 .name = "ttySC",
3116 .device = uart_console_device,
3117 .write = serial_console_write,
3118 .setup = serial_console_setup,
3119 .flags = CON_PRINTBUFFER,
3120 .index = -1,
3121 .data = &sci_uart_driver,
3122};
3123
3124#ifdef CONFIG_SUPERH
3125static char early_serial_buf[32];
3126
3127static int early_serial_console_setup(struct console *co, char *options)
3128{
3129 /*
3130 * This early console is always registered using the earlyprintk=
3131 * parameter, which does not call add_preferred_console(). Thus
3132 * @options is always NULL and the options for this early console
3133 * are passed using a custom buffer.
3134 */
3135 WARN_ON(options);
3136
3137 return serial_console_setup(co, early_serial_buf);
3138}
3139
3140static struct console early_serial_console = {
3141 .name = "early_ttySC",
3142 .write = serial_console_write,
3143 .setup = early_serial_console_setup,
3144 .flags = CON_PRINTBUFFER,
3145 .index = -1,
3146};
3147
3148static int sci_probe_earlyprintk(struct platform_device *pdev)
3149{
3150 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3151
3152 if (early_serial_console.data)
3153 return -EEXIST;
3154
3155 early_serial_console.index = pdev->id;
3156
3157 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3158
3159 if (!strstr(early_serial_buf, "keep"))
3160 early_serial_console.flags |= CON_BOOT;
3161
3162 register_console(&early_serial_console);
3163 return 0;
3164}
3165#endif
3166
3167#define SCI_CONSOLE (&serial_console)
3168
3169#else
3170static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3171{
3172 return -EINVAL;
3173}
3174
3175#define SCI_CONSOLE NULL
3176
3177#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3178
3179static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3180
3181static DEFINE_MUTEX(sci_uart_registration_lock);
3182static struct uart_driver sci_uart_driver = {
3183 .owner = THIS_MODULE,
3184 .driver_name = "sci",
3185 .dev_name = "ttySC",
3186 .major = SCI_MAJOR,
3187 .minor = SCI_MINOR_START,
3188 .nr = SCI_NPORTS,
3189 .cons = SCI_CONSOLE,
3190};
3191
3192static void sci_remove(struct platform_device *dev)
3193{
3194 struct sci_port *port = platform_get_drvdata(dev);
3195 unsigned int type = port->port.type; /* uart_remove_... clears it */
3196
3197 sci_ports_in_use &= ~BIT(port->port.line);
3198 uart_remove_one_port(&sci_uart_driver, &port->port);
3199
3200 sci_cleanup_single(port);
3201
3202 if (port->port.fifosize > 1)
3203 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3204 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3205 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3206}
3207
3208
3209#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3210#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3211#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3212
3213static const struct of_device_id of_sci_match[] __maybe_unused = {
3214 /* SoC-specific types */
3215 {
3216 .compatible = "renesas,scif-r7s72100",
3217 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3218 },
3219 {
3220 .compatible = "renesas,scif-r7s9210",
3221 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3222 },
3223 {
3224 .compatible = "renesas,scif-r9a07g044",
3225 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3226 },
3227 /* Family-specific types */
3228 {
3229 .compatible = "renesas,rcar-gen1-scif",
3230 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3231 }, {
3232 .compatible = "renesas,rcar-gen2-scif",
3233 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3234 }, {
3235 .compatible = "renesas,rcar-gen3-scif",
3236 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3237 }, {
3238 .compatible = "renesas,rcar-gen4-scif",
3239 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3240 },
3241 /* Generic types */
3242 {
3243 .compatible = "renesas,scif",
3244 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3245 }, {
3246 .compatible = "renesas,scifa",
3247 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3248 }, {
3249 .compatible = "renesas,scifb",
3250 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3251 }, {
3252 .compatible = "renesas,hscif",
3253 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3254 }, {
3255 .compatible = "renesas,sci",
3256 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3257 }, {
3258 /* Terminator */
3259 },
3260};
3261MODULE_DEVICE_TABLE(of, of_sci_match);
3262
3263static void sci_reset_control_assert(void *data)
3264{
3265 reset_control_assert(data);
3266}
3267
3268static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3269 unsigned int *dev_id)
3270{
3271 struct device_node *np = pdev->dev.of_node;
3272 struct reset_control *rstc;
3273 struct plat_sci_port *p;
3274 struct sci_port *sp;
3275 const void *data;
3276 int id, ret;
3277
3278 if (!IS_ENABLED(CONFIG_OF) || !np)
3279 return ERR_PTR(-EINVAL);
3280
3281 data = of_device_get_match_data(&pdev->dev);
3282
3283 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3284 if (IS_ERR(rstc))
3285 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3286 "failed to get reset ctrl\n"));
3287
3288 ret = reset_control_deassert(rstc);
3289 if (ret) {
3290 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3291 return ERR_PTR(ret);
3292 }
3293
3294 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3295 if (ret) {
3296 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3297 ret);
3298 return ERR_PTR(ret);
3299 }
3300
3301 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3302 if (!p)
3303 return ERR_PTR(-ENOMEM);
3304
3305 /* Get the line number from the aliases node. */
3306 id = of_alias_get_id(np, "serial");
3307 if (id < 0 && ~sci_ports_in_use)
3308 id = ffz(sci_ports_in_use);
3309 if (id < 0) {
3310 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3311 return ERR_PTR(-EINVAL);
3312 }
3313 if (id >= ARRAY_SIZE(sci_ports)) {
3314 dev_err(&pdev->dev, "serial%d out of range\n", id);
3315 return ERR_PTR(-EINVAL);
3316 }
3317
3318 sp = &sci_ports[id];
3319 *dev_id = id;
3320
3321 p->type = SCI_OF_TYPE(data);
3322 p->regtype = SCI_OF_REGTYPE(data);
3323
3324 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3325
3326 return p;
3327}
3328
3329static int sci_probe_single(struct platform_device *dev,
3330 unsigned int index,
3331 struct plat_sci_port *p,
3332 struct sci_port *sciport)
3333{
3334 int ret;
3335
3336 /* Sanity check */
3337 if (unlikely(index >= SCI_NPORTS)) {
3338 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3339 index+1, SCI_NPORTS);
3340 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3341 return -EINVAL;
3342 }
3343 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3344 if (sci_ports_in_use & BIT(index))
3345 return -EBUSY;
3346
3347 mutex_lock(&sci_uart_registration_lock);
3348 if (!sci_uart_driver.state) {
3349 ret = uart_register_driver(&sci_uart_driver);
3350 if (ret) {
3351 mutex_unlock(&sci_uart_registration_lock);
3352 return ret;
3353 }
3354 }
3355 mutex_unlock(&sci_uart_registration_lock);
3356
3357 ret = sci_init_single(dev, sciport, index, p, false);
3358 if (ret)
3359 return ret;
3360
3361 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3362 if (IS_ERR(sciport->gpios))
3363 return PTR_ERR(sciport->gpios);
3364
3365 if (sciport->has_rtscts) {
3366 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3367 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3368 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3369 return -EINVAL;
3370 }
3371 sciport->port.flags |= UPF_HARD_FLOW;
3372 }
3373
3374 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3375 if (ret) {
3376 sci_cleanup_single(sciport);
3377 return ret;
3378 }
3379
3380 return 0;
3381}
3382
3383static int sci_probe(struct platform_device *dev)
3384{
3385 struct plat_sci_port *p;
3386 struct sci_port *sp;
3387 unsigned int dev_id;
3388 int ret;
3389
3390 /*
3391 * If we've come here via earlyprintk initialization, head off to
3392 * the special early probe. We don't have sufficient device state
3393 * to make it beyond this yet.
3394 */
3395#ifdef CONFIG_SUPERH
3396 if (is_sh_early_platform_device(dev))
3397 return sci_probe_earlyprintk(dev);
3398#endif
3399
3400 if (dev->dev.of_node) {
3401 p = sci_parse_dt(dev, &dev_id);
3402 if (IS_ERR(p))
3403 return PTR_ERR(p);
3404 } else {
3405 p = dev->dev.platform_data;
3406 if (p == NULL) {
3407 dev_err(&dev->dev, "no platform data supplied\n");
3408 return -EINVAL;
3409 }
3410
3411 dev_id = dev->id;
3412 }
3413
3414 sp = &sci_ports[dev_id];
3415 platform_set_drvdata(dev, sp);
3416
3417 ret = sci_probe_single(dev, dev_id, p, sp);
3418 if (ret)
3419 return ret;
3420
3421 if (sp->port.fifosize > 1) {
3422 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3423 if (ret)
3424 return ret;
3425 }
3426 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3427 sp->port.type == PORT_HSCIF) {
3428 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3429 if (ret) {
3430 if (sp->port.fifosize > 1) {
3431 device_remove_file(&dev->dev,
3432 &dev_attr_rx_fifo_trigger);
3433 }
3434 return ret;
3435 }
3436 }
3437
3438#ifdef CONFIG_SH_STANDARD_BIOS
3439 sh_bios_gdb_detach();
3440#endif
3441
3442 sci_ports_in_use |= BIT(dev_id);
3443 return 0;
3444}
3445
3446static __maybe_unused int sci_suspend(struct device *dev)
3447{
3448 struct sci_port *sport = dev_get_drvdata(dev);
3449
3450 if (sport)
3451 uart_suspend_port(&sci_uart_driver, &sport->port);
3452
3453 return 0;
3454}
3455
3456static __maybe_unused int sci_resume(struct device *dev)
3457{
3458 struct sci_port *sport = dev_get_drvdata(dev);
3459
3460 if (sport)
3461 uart_resume_port(&sci_uart_driver, &sport->port);
3462
3463 return 0;
3464}
3465
3466static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3467
3468static struct platform_driver sci_driver = {
3469 .probe = sci_probe,
3470 .remove_new = sci_remove,
3471 .driver = {
3472 .name = "sh-sci",
3473 .pm = &sci_dev_pm_ops,
3474 .of_match_table = of_match_ptr(of_sci_match),
3475 },
3476};
3477
3478static int __init sci_init(void)
3479{
3480 pr_info("%s\n", banner);
3481
3482 return platform_driver_register(&sci_driver);
3483}
3484
3485static void __exit sci_exit(void)
3486{
3487 platform_driver_unregister(&sci_driver);
3488
3489 if (sci_uart_driver.state)
3490 uart_unregister_driver(&sci_uart_driver);
3491}
3492
3493#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3494sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3495 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3496#endif
3497#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3498static struct plat_sci_port port_cfg __initdata;
3499
3500static int __init early_console_setup(struct earlycon_device *device,
3501 int type)
3502{
3503 if (!device->port.membase)
3504 return -ENODEV;
3505
3506 device->port.type = type;
3507 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3508 port_cfg.type = type;
3509 sci_ports[0].cfg = &port_cfg;
3510 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3511 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3512 sci_serial_out(&sci_ports[0].port, SCSCR,
3513 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3514
3515 device->con->write = serial_console_write;
3516 return 0;
3517}
3518static int __init sci_early_console_setup(struct earlycon_device *device,
3519 const char *opt)
3520{
3521 return early_console_setup(device, PORT_SCI);
3522}
3523static int __init scif_early_console_setup(struct earlycon_device *device,
3524 const char *opt)
3525{
3526 return early_console_setup(device, PORT_SCIF);
3527}
3528static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3529 const char *opt)
3530{
3531 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3532 return early_console_setup(device, PORT_SCIF);
3533}
3534
3535static int __init scifa_early_console_setup(struct earlycon_device *device,
3536 const char *opt)
3537{
3538 return early_console_setup(device, PORT_SCIFA);
3539}
3540static int __init scifb_early_console_setup(struct earlycon_device *device,
3541 const char *opt)
3542{
3543 return early_console_setup(device, PORT_SCIFB);
3544}
3545static int __init hscif_early_console_setup(struct earlycon_device *device,
3546 const char *opt)
3547{
3548 return early_console_setup(device, PORT_HSCIF);
3549}
3550
3551OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3552OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3553OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3554OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3555OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3556OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3557OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3558#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3559
3560module_init(sci_init);
3561module_exit(sci_exit);
3562
3563MODULE_LICENSE("GPL");
3564MODULE_ALIAS("platform:sh-sci");
3565MODULE_AUTHOR("Paul Mundt");
3566MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");