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1/*
2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <asm/addrspace.h>
12#include <asm/asm.h>
13#include <asm/asm-offsets.h>
14#include <asm/asmmacro.h>
15#include <asm/cacheops.h>
16#include <asm/eva.h>
17#include <asm/mipsregs.h>
18#include <asm/mipsmtregs.h>
19#include <asm/pm.h>
20
21#define GCR_CL_COHERENCE_OFS 0x2008
22#define GCR_CL_ID_OFS 0x2028
23
24.extern mips_cm_base
25
26.set noreorder
27
28#ifdef CONFIG_64BIT
29# define STATUS_BITDEPS ST0_KX
30#else
31# define STATUS_BITDEPS 0
32#endif
33
34#ifdef CONFIG_MIPS_CPS_NS16550
35
36#define DUMP_EXCEP(name) \
37 PTR_LA a0, 8f; \
38 jal mips_cps_bev_dump; \
39 nop; \
40 TEXT(name)
41
42#else /* !CONFIG_MIPS_CPS_NS16550 */
43
44#define DUMP_EXCEP(name)
45
46#endif /* !CONFIG_MIPS_CPS_NS16550 */
47
48 /*
49 * Set dest to non-zero if the core supports the MT ASE, else zero. If
50 * MT is not supported then branch to nomt.
51 */
52 .macro has_mt dest, nomt
53 mfc0 \dest, CP0_CONFIG, 1
54 bgez \dest, \nomt
55 mfc0 \dest, CP0_CONFIG, 2
56 bgez \dest, \nomt
57 mfc0 \dest, CP0_CONFIG, 3
58 andi \dest, \dest, MIPS_CONF3_MT
59 beqz \dest, \nomt
60 nop
61 .endm
62
63.section .text.cps-vec
64.balign 0x1000
65
66LEAF(mips_cps_core_entry)
67 /*
68 * These first 4 bytes will be patched by cps_smp_setup to load the
69 * CCA to use into register s0.
70 */
71 .word 0
72
73 /* Check whether we're here due to an NMI */
74 mfc0 k0, CP0_STATUS
75 and k0, k0, ST0_NMI
76 beqz k0, not_nmi
77 nop
78
79 /* This is an NMI */
80 PTR_LA k0, nmi_handler
81 jr k0
82 nop
83
84not_nmi:
85 /* Setup Cause */
86 li t0, CAUSEF_IV
87 mtc0 t0, CP0_CAUSE
88
89 /* Setup Status */
90 li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
91 mtc0 t0, CP0_STATUS
92
93 /*
94 * Clear the bits used to index the caches. Note that the architecture
95 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
96 * be valid for all MIPS32 CPUs, even those for which said writes are
97 * unnecessary.
98 */
99 mtc0 zero, CP0_TAGLO, 0
100 mtc0 zero, CP0_TAGHI, 0
101 mtc0 zero, CP0_TAGLO, 2
102 mtc0 zero, CP0_TAGHI, 2
103 ehb
104
105 /* Primary cache configuration is indicated by Config1 */
106 mfc0 v0, CP0_CONFIG, 1
107
108 /* Detect I-cache line size */
109 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
110 beqz t0, icache_done
111 li t1, 2
112 sllv t0, t1, t0
113
114 /* Detect I-cache size */
115 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
116 xori t2, t1, 0x7
117 beqz t2, 1f
118 li t3, 32
119 addiu t1, t1, 1
120 sllv t1, t3, t1
1211: /* At this point t1 == I-cache sets per way */
122 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
123 addiu t2, t2, 1
124 mul t1, t1, t0
125 mul t1, t1, t2
126
127 li a0, CKSEG0
128 PTR_ADD a1, a0, t1
1291: cache Index_Store_Tag_I, 0(a0)
130 PTR_ADD a0, a0, t0
131 bne a0, a1, 1b
132 nop
133icache_done:
134
135 /* Detect D-cache line size */
136 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
137 beqz t0, dcache_done
138 li t1, 2
139 sllv t0, t1, t0
140
141 /* Detect D-cache size */
142 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
143 xori t2, t1, 0x7
144 beqz t2, 1f
145 li t3, 32
146 addiu t1, t1, 1
147 sllv t1, t3, t1
1481: /* At this point t1 == D-cache sets per way */
149 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
150 addiu t2, t2, 1
151 mul t1, t1, t0
152 mul t1, t1, t2
153
154 li a0, CKSEG0
155 PTR_ADDU a1, a0, t1
156 PTR_SUBU a1, a1, t0
1571: cache Index_Store_Tag_D, 0(a0)
158 bne a0, a1, 1b
159 PTR_ADD a0, a0, t0
160dcache_done:
161
162 /* Set Kseg0 CCA to that in s0 */
163 mfc0 t0, CP0_CONFIG
164 ori t0, 0x7
165 xori t0, 0x7
166 or t0, t0, s0
167 mtc0 t0, CP0_CONFIG
168 ehb
169
170 /* Calculate an uncached address for the CM GCRs */
171 MFC0 v1, CP0_CMGCRBASE
172 PTR_SLL v1, v1, 4
173 PTR_LI t0, UNCAC_BASE
174 PTR_ADDU v1, v1, t0
175
176 /* Enter the coherent domain */
177 li t0, 0xff
178 sw t0, GCR_CL_COHERENCE_OFS(v1)
179 ehb
180
181 /* Jump to kseg0 */
182 PTR_LA t0, 1f
183 jr t0
184 nop
185
186 /*
187 * We're up, cached & coherent. Perform any further required core-level
188 * initialisation.
189 */
1901: jal mips_cps_core_init
191 nop
192
193 /* Do any EVA initialization if necessary */
194 eva_init
195
196 /*
197 * Boot any other VPEs within this core that should be online, and
198 * deactivate this VPE if it should be offline.
199 */
200 jal mips_cps_boot_vpes
201 nop
202
203 /* Off we go! */
204 PTR_L t1, VPEBOOTCFG_PC(v0)
205 PTR_L gp, VPEBOOTCFG_GP(v0)
206 PTR_L sp, VPEBOOTCFG_SP(v0)
207 jr t1
208 nop
209 END(mips_cps_core_entry)
210
211.org 0x200
212LEAF(excep_tlbfill)
213 DUMP_EXCEP("TLB Fill")
214 b .
215 nop
216 END(excep_tlbfill)
217
218.org 0x280
219LEAF(excep_xtlbfill)
220 DUMP_EXCEP("XTLB Fill")
221 b .
222 nop
223 END(excep_xtlbfill)
224
225.org 0x300
226LEAF(excep_cache)
227 DUMP_EXCEP("Cache")
228 b .
229 nop
230 END(excep_cache)
231
232.org 0x380
233LEAF(excep_genex)
234 DUMP_EXCEP("General")
235 b .
236 nop
237 END(excep_genex)
238
239.org 0x400
240LEAF(excep_intex)
241 DUMP_EXCEP("Interrupt")
242 b .
243 nop
244 END(excep_intex)
245
246.org 0x480
247LEAF(excep_ejtag)
248 DUMP_EXCEP("EJTAG")
249 PTR_LA k0, ejtag_debug_handler
250 jr k0
251 nop
252 END(excep_ejtag)
253
254LEAF(mips_cps_core_init)
255#ifdef CONFIG_MIPS_MT_SMP
256 /* Check that the core implements the MT ASE */
257 has_mt t0, 3f
258
259 .set push
260 .set mt
261
262 /* Only allow 1 TC per VPE to execute... */
263 dmt
264
265 /* ...and for the moment only 1 VPE */
266 dvpe
267 PTR_LA t1, 1f
268 jr.hb t1
269 nop
270
271 /* Enter VPE configuration state */
2721: mfc0 t0, CP0_MVPCONTROL
273 ori t0, t0, MVPCONTROL_VPC
274 mtc0 t0, CP0_MVPCONTROL
275
276 /* Retrieve the number of VPEs within the core */
277 mfc0 t0, CP0_MVPCONF0
278 srl t0, t0, MVPCONF0_PVPE_SHIFT
279 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
280 addiu ta3, t0, 1
281
282 /* If there's only 1, we're done */
283 beqz t0, 2f
284 nop
285
286 /* Loop through each VPE within this core */
287 li ta1, 1
288
2891: /* Operate on the appropriate TC */
290 mtc0 ta1, CP0_VPECONTROL
291 ehb
292
293 /* Bind TC to VPE (1:1 TC:VPE mapping) */
294 mttc0 ta1, CP0_TCBIND
295
296 /* Set exclusive TC, non-active, master */
297 li t0, VPECONF0_MVP
298 sll t1, ta1, VPECONF0_XTC_SHIFT
299 or t0, t0, t1
300 mttc0 t0, CP0_VPECONF0
301
302 /* Set TC non-active, non-allocatable */
303 mttc0 zero, CP0_TCSTATUS
304
305 /* Set TC halted */
306 li t0, TCHALT_H
307 mttc0 t0, CP0_TCHALT
308
309 /* Next VPE */
310 addiu ta1, ta1, 1
311 slt t0, ta1, ta3
312 bnez t0, 1b
313 nop
314
315 /* Leave VPE configuration state */
3162: mfc0 t0, CP0_MVPCONTROL
317 xori t0, t0, MVPCONTROL_VPC
318 mtc0 t0, CP0_MVPCONTROL
319
3203: .set pop
321#endif
322 jr ra
323 nop
324 END(mips_cps_core_init)
325
326LEAF(mips_cps_boot_vpes)
327 /* Retrieve CM base address */
328 PTR_LA t0, mips_cm_base
329 PTR_L t0, 0(t0)
330
331 /* Calculate a pointer to this cores struct core_boot_config */
332 lw t0, GCR_CL_ID_OFS(t0)
333 li t1, COREBOOTCFG_SIZE
334 mul t0, t0, t1
335 PTR_LA t1, mips_cps_core_bootcfg
336 PTR_L t1, 0(t1)
337 PTR_ADDU t0, t0, t1
338
339 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
340 li t9, 0
341#ifdef CONFIG_MIPS_MT_SMP
342 has_mt ta2, 1f
343
344 /* Find the number of VPEs present in the core */
345 mfc0 t1, CP0_MVPCONF0
346 srl t1, t1, MVPCONF0_PVPE_SHIFT
347 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
348 addiu t1, t1, 1
349
350 /* Calculate a mask for the VPE ID from EBase.CPUNum */
351 clz t1, t1
352 li t2, 31
353 subu t1, t2, t1
354 li t2, 1
355 sll t1, t2, t1
356 addiu t1, t1, -1
357
358 /* Retrieve the VPE ID from EBase.CPUNum */
359 mfc0 t9, $15, 1
360 and t9, t9, t1
361#endif
362
3631: /* Calculate a pointer to this VPEs struct vpe_boot_config */
364 li t1, VPEBOOTCFG_SIZE
365 mul v0, t9, t1
366 PTR_L ta3, COREBOOTCFG_VPECONFIG(t0)
367 PTR_ADDU v0, v0, ta3
368
369#ifdef CONFIG_MIPS_MT_SMP
370
371 /* If the core doesn't support MT then return */
372 bnez ta2, 1f
373 nop
374 jr ra
375 nop
376
377 .set push
378 .set mt
379
3801: /* Enter VPE configuration state */
381 dvpe
382 PTR_LA t1, 1f
383 jr.hb t1
384 nop
3851: mfc0 t1, CP0_MVPCONTROL
386 ori t1, t1, MVPCONTROL_VPC
387 mtc0 t1, CP0_MVPCONTROL
388 ehb
389
390 /* Loop through each VPE */
391 PTR_L ta2, COREBOOTCFG_VPEMASK(t0)
392 move t8, ta2
393 li ta1, 0
394
395 /* Check whether the VPE should be running. If not, skip it */
3961: andi t0, ta2, 1
397 beqz t0, 2f
398 nop
399
400 /* Operate on the appropriate TC */
401 mfc0 t0, CP0_VPECONTROL
402 ori t0, t0, VPECONTROL_TARGTC
403 xori t0, t0, VPECONTROL_TARGTC
404 or t0, t0, ta1
405 mtc0 t0, CP0_VPECONTROL
406 ehb
407
408 /* Skip the VPE if its TC is not halted */
409 mftc0 t0, CP0_TCHALT
410 beqz t0, 2f
411 nop
412
413 /* Calculate a pointer to the VPEs struct vpe_boot_config */
414 li t0, VPEBOOTCFG_SIZE
415 mul t0, t0, ta1
416 addu t0, t0, ta3
417
418 /* Set the TC restart PC */
419 lw t1, VPEBOOTCFG_PC(t0)
420 mttc0 t1, CP0_TCRESTART
421
422 /* Set the TC stack pointer */
423 lw t1, VPEBOOTCFG_SP(t0)
424 mttgpr t1, sp
425
426 /* Set the TC global pointer */
427 lw t1, VPEBOOTCFG_GP(t0)
428 mttgpr t1, gp
429
430 /* Copy config from this VPE */
431 mfc0 t0, CP0_CONFIG
432 mttc0 t0, CP0_CONFIG
433
434 /* Ensure no software interrupts are pending */
435 mttc0 zero, CP0_CAUSE
436 mttc0 zero, CP0_STATUS
437
438 /* Set TC active, not interrupt exempt */
439 mftc0 t0, CP0_TCSTATUS
440 li t1, ~TCSTATUS_IXMT
441 and t0, t0, t1
442 ori t0, t0, TCSTATUS_A
443 mttc0 t0, CP0_TCSTATUS
444
445 /* Clear the TC halt bit */
446 mttc0 zero, CP0_TCHALT
447
448 /* Set VPE active */
449 mftc0 t0, CP0_VPECONF0
450 ori t0, t0, VPECONF0_VPA
451 mttc0 t0, CP0_VPECONF0
452
453 /* Next VPE */
4542: srl ta2, ta2, 1
455 addiu ta1, ta1, 1
456 bnez ta2, 1b
457 nop
458
459 /* Leave VPE configuration state */
460 mfc0 t1, CP0_MVPCONTROL
461 xori t1, t1, MVPCONTROL_VPC
462 mtc0 t1, CP0_MVPCONTROL
463 ehb
464 evpe
465
466 /* Check whether this VPE is meant to be running */
467 li t0, 1
468 sll t0, t0, t9
469 and t0, t0, t8
470 bnez t0, 2f
471 nop
472
473 /* This VPE should be offline, halt the TC */
474 li t0, TCHALT_H
475 mtc0 t0, CP0_TCHALT
476 PTR_LA t0, 1f
4771: jr.hb t0
478 nop
479
4802: .set pop
481
482#endif /* CONFIG_MIPS_MT_SMP */
483
484 /* Return */
485 jr ra
486 nop
487 END(mips_cps_boot_vpes)
488
489#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
490
491 /* Calculate a pointer to this CPUs struct mips_static_suspend_state */
492 .macro psstate dest
493 .set push
494 .set noat
495 lw $1, TI_CPU(gp)
496 sll $1, $1, LONGLOG
497 PTR_LA \dest, __per_cpu_offset
498 addu $1, $1, \dest
499 lw $1, 0($1)
500 PTR_LA \dest, cps_cpu_state
501 addu \dest, \dest, $1
502 .set pop
503 .endm
504
505LEAF(mips_cps_pm_save)
506 /* Save CPU state */
507 SUSPEND_SAVE_REGS
508 psstate t1
509 SUSPEND_SAVE_STATIC
510 jr v0
511 nop
512 END(mips_cps_pm_save)
513
514LEAF(mips_cps_pm_restore)
515 /* Restore CPU state */
516 psstate t1
517 RESUME_RESTORE_STATIC
518 RESUME_RESTORE_REGS_RETURN
519 END(mips_cps_pm_restore)
520
521#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7#include <linux/init.h>
8#include <asm/addrspace.h>
9#include <asm/asm.h>
10#include <asm/asm-offsets.h>
11#include <asm/asmmacro.h>
12#include <asm/cacheops.h>
13#include <asm/eva.h>
14#include <asm/mipsregs.h>
15#include <asm/mipsmtregs.h>
16#include <asm/pm.h>
17#include <asm/smp-cps.h>
18
19#define GCR_CPC_BASE_OFS 0x0088
20#define GCR_CL_COHERENCE_OFS 0x2008
21#define GCR_CL_ID_OFS 0x2028
22
23#define CPC_CL_VC_STOP_OFS 0x2020
24#define CPC_CL_VC_RUN_OFS 0x2028
25
26.extern mips_cm_base
27
28.set noreorder
29
30#ifdef CONFIG_64BIT
31# define STATUS_BITDEPS ST0_KX
32#else
33# define STATUS_BITDEPS 0
34#endif
35
36#ifdef CONFIG_MIPS_CPS_NS16550
37
38#define DUMP_EXCEP(name) \
39 PTR_LA a0, 8f; \
40 jal mips_cps_bev_dump; \
41 nop; \
42 TEXT(name)
43
44#else /* !CONFIG_MIPS_CPS_NS16550 */
45
46#define DUMP_EXCEP(name)
47
48#endif /* !CONFIG_MIPS_CPS_NS16550 */
49
50 /*
51 * Set dest to non-zero if the core supports the MT ASE, else zero. If
52 * MT is not supported then branch to nomt.
53 */
54 .macro has_mt dest, nomt
55 mfc0 \dest, CP0_CONFIG, 1
56 bgez \dest, \nomt
57 mfc0 \dest, CP0_CONFIG, 2
58 bgez \dest, \nomt
59 mfc0 \dest, CP0_CONFIG, 3
60 andi \dest, \dest, MIPS_CONF3_MT
61 beqz \dest, \nomt
62 nop
63 .endm
64
65 /*
66 * Set dest to non-zero if the core supports MIPSr6 multithreading
67 * (ie. VPs), else zero. If MIPSr6 multithreading is not supported then
68 * branch to nomt.
69 */
70 .macro has_vp dest, nomt
71 mfc0 \dest, CP0_CONFIG, 1
72 bgez \dest, \nomt
73 mfc0 \dest, CP0_CONFIG, 2
74 bgez \dest, \nomt
75 mfc0 \dest, CP0_CONFIG, 3
76 bgez \dest, \nomt
77 mfc0 \dest, CP0_CONFIG, 4
78 bgez \dest, \nomt
79 mfc0 \dest, CP0_CONFIG, 5
80 andi \dest, \dest, MIPS_CONF5_VP
81 beqz \dest, \nomt
82 nop
83 .endm
84
85
86LEAF(mips_cps_core_boot)
87 /* Save CCA and GCR base */
88 move s0, a0
89 move s1, a1
90
91 /* We don't know how to do coherence setup on earlier ISA */
92#if MIPS_ISA_REV > 0
93 /* Skip cache & coherence setup if we're already coherent */
94 lw s7, GCR_CL_COHERENCE_OFS(s1)
95 bnez s7, 1f
96 nop
97
98 /* Initialize the L1 caches */
99 jal mips_cps_cache_init
100 nop
101
102 /* Enter the coherent domain */
103 li t0, 0xff
104 sw t0, GCR_CL_COHERENCE_OFS(s1)
105 ehb
106#endif /* MIPS_ISA_REV > 0 */
107
108 /* Set Kseg0 CCA to that in s0 */
1091: mfc0 t0, CP0_CONFIG
110 ori t0, 0x7
111 xori t0, 0x7
112 or t0, t0, s0
113 mtc0 t0, CP0_CONFIG
114 ehb
115
116 /* Jump to kseg0 */
117 PTR_LA t0, 1f
118 jr t0
119 nop
120
121 /*
122 * We're up, cached & coherent. Perform any EVA initialization necessary
123 * before we access memory.
124 */
1251: eva_init
126
127 /* Retrieve boot configuration pointers */
128 jal mips_cps_get_bootcfg
129 nop
130
131 /* Skip core-level init if we started up coherent */
132 bnez s7, 1f
133 nop
134
135 /* Perform any further required core-level initialisation */
136 jal mips_cps_core_init
137 nop
138
139 /*
140 * Boot any other VPEs within this core that should be online, and
141 * deactivate this VPE if it should be offline.
142 */
143 move a1, t9
144 jal mips_cps_boot_vpes
145 move a0, v0
146
147 /* Off we go! */
1481: PTR_L t1, VPEBOOTCFG_PC(v1)
149 PTR_L gp, VPEBOOTCFG_GP(v1)
150 PTR_L sp, VPEBOOTCFG_SP(v1)
151 jr t1
152 nop
153 END(mips_cps_core_boot)
154
155 __INIT
156LEAF(excep_tlbfill)
157 DUMP_EXCEP("TLB Fill")
158 b .
159 nop
160 END(excep_tlbfill)
161
162LEAF(excep_xtlbfill)
163 DUMP_EXCEP("XTLB Fill")
164 b .
165 nop
166 END(excep_xtlbfill)
167
168LEAF(excep_cache)
169 DUMP_EXCEP("Cache")
170 b .
171 nop
172 END(excep_cache)
173
174LEAF(excep_genex)
175 DUMP_EXCEP("General")
176 b .
177 nop
178 END(excep_genex)
179
180LEAF(excep_intex)
181 DUMP_EXCEP("Interrupt")
182 b .
183 nop
184 END(excep_intex)
185
186LEAF(excep_ejtag)
187 PTR_LA k0, ejtag_debug_handler
188 jr k0
189 nop
190 END(excep_ejtag)
191 __FINIT
192
193LEAF(mips_cps_core_init)
194#ifdef CONFIG_MIPS_MT_SMP
195 /* Check that the core implements the MT ASE */
196 has_mt t0, 3f
197
198 .set push
199 .set MIPS_ISA_LEVEL_RAW
200 .set mt
201
202 /* Only allow 1 TC per VPE to execute... */
203 dmt
204
205 /* ...and for the moment only 1 VPE */
206 dvpe
207 PTR_LA t1, 1f
208 jr.hb t1
209 nop
210
211 /* Enter VPE configuration state */
2121: mfc0 t0, CP0_MVPCONTROL
213 ori t0, t0, MVPCONTROL_VPC
214 mtc0 t0, CP0_MVPCONTROL
215
216 /* Retrieve the number of VPEs within the core */
217 mfc0 t0, CP0_MVPCONF0
218 srl t0, t0, MVPCONF0_PVPE_SHIFT
219 andi t0, t0, (MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT)
220 addiu ta3, t0, 1
221
222 /* If there's only 1, we're done */
223 beqz t0, 2f
224 nop
225
226 /* Loop through each VPE within this core */
227 li ta1, 1
228
2291: /* Operate on the appropriate TC */
230 mtc0 ta1, CP0_VPECONTROL
231 ehb
232
233 /* Bind TC to VPE (1:1 TC:VPE mapping) */
234 mttc0 ta1, CP0_TCBIND
235
236 /* Set exclusive TC, non-active, master */
237 li t0, VPECONF0_MVP
238 sll t1, ta1, VPECONF0_XTC_SHIFT
239 or t0, t0, t1
240 mttc0 t0, CP0_VPECONF0
241
242 /* Set TC non-active, non-allocatable */
243 mttc0 zero, CP0_TCSTATUS
244
245 /* Set TC halted */
246 li t0, TCHALT_H
247 mttc0 t0, CP0_TCHALT
248
249 /* Next VPE */
250 addiu ta1, ta1, 1
251 slt t0, ta1, ta3
252 bnez t0, 1b
253 nop
254
255 /* Leave VPE configuration state */
2562: mfc0 t0, CP0_MVPCONTROL
257 xori t0, t0, MVPCONTROL_VPC
258 mtc0 t0, CP0_MVPCONTROL
259
2603: .set pop
261#endif
262 jr ra
263 nop
264 END(mips_cps_core_init)
265
266/**
267 * mips_cps_get_bootcfg() - retrieve boot configuration pointers
268 *
269 * Returns: pointer to struct core_boot_config in v0, pointer to
270 * struct vpe_boot_config in v1, VPE ID in t9
271 */
272LEAF(mips_cps_get_bootcfg)
273 /* Calculate a pointer to this cores struct core_boot_config */
274 lw t0, GCR_CL_ID_OFS(s1)
275 li t1, COREBOOTCFG_SIZE
276 mul t0, t0, t1
277 PTR_LA t1, mips_cps_core_bootcfg
278 PTR_L t1, 0(t1)
279 PTR_ADDU v0, t0, t1
280
281 /* Calculate this VPEs ID. If the core doesn't support MT use 0 */
282 li t9, 0
283#if defined(CONFIG_CPU_MIPSR6)
284 has_vp ta2, 1f
285
286 /*
287 * Assume non-contiguous numbering. Perhaps some day we'll need
288 * to handle contiguous VP numbering, but no such systems yet
289 * exist.
290 */
291 mfc0 t9, CP0_GLOBALNUMBER
292 andi t9, t9, MIPS_GLOBALNUMBER_VP
293#elif defined(CONFIG_MIPS_MT_SMP)
294 has_mt ta2, 1f
295
296 /* Find the number of VPEs present in the core */
297 mfc0 t1, CP0_MVPCONF0
298 srl t1, t1, MVPCONF0_PVPE_SHIFT
299 andi t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
300 addiu t1, t1, 1
301
302 /* Calculate a mask for the VPE ID from EBase.CPUNum */
303 clz t1, t1
304 li t2, 31
305 subu t1, t2, t1
306 li t2, 1
307 sll t1, t2, t1
308 addiu t1, t1, -1
309
310 /* Retrieve the VPE ID from EBase.CPUNum */
311 mfc0 t9, $15, 1
312 and t9, t9, t1
313#endif
314
3151: /* Calculate a pointer to this VPEs struct vpe_boot_config */
316 li t1, VPEBOOTCFG_SIZE
317 mul v1, t9, t1
318 PTR_L ta3, COREBOOTCFG_VPECONFIG(v0)
319 PTR_ADDU v1, v1, ta3
320
321 jr ra
322 nop
323 END(mips_cps_get_bootcfg)
324
325LEAF(mips_cps_boot_vpes)
326 lw ta2, COREBOOTCFG_VPEMASK(a0)
327 PTR_L ta3, COREBOOTCFG_VPECONFIG(a0)
328
329#if defined(CONFIG_CPU_MIPSR6)
330
331 has_vp t0, 5f
332
333 /* Find base address of CPC */
334 PTR_LA t1, mips_gcr_base
335 PTR_L t1, 0(t1)
336 PTR_L t1, GCR_CPC_BASE_OFS(t1)
337 PTR_LI t2, ~0x7fff
338 and t1, t1, t2
339 PTR_LI t2, UNCAC_BASE
340 PTR_ADD t1, t1, t2
341
342 /* Start any other VPs that ought to be running */
343 PTR_S ta2, CPC_CL_VC_RUN_OFS(t1)
344
345 /* Ensure this VP stops running if it shouldn't be */
346 not ta2
347 PTR_S ta2, CPC_CL_VC_STOP_OFS(t1)
348 ehb
349
350#elif defined(CONFIG_MIPS_MT)
351
352 /* If the core doesn't support MT then return */
353 has_mt t0, 5f
354
355 /* Enter VPE configuration state */
356 .set push
357 .set MIPS_ISA_LEVEL_RAW
358 .set mt
359 dvpe
360 .set pop
361
362 PTR_LA t1, 1f
363 jr.hb t1
364 nop
3651: mfc0 t1, CP0_MVPCONTROL
366 ori t1, t1, MVPCONTROL_VPC
367 mtc0 t1, CP0_MVPCONTROL
368 ehb
369
370 /* Loop through each VPE */
371 move t8, ta2
372 li ta1, 0
373
374 /* Check whether the VPE should be running. If not, skip it */
3751: andi t0, ta2, 1
376 beqz t0, 2f
377 nop
378
379 /* Operate on the appropriate TC */
380 mfc0 t0, CP0_VPECONTROL
381 ori t0, t0, VPECONTROL_TARGTC
382 xori t0, t0, VPECONTROL_TARGTC
383 or t0, t0, ta1
384 mtc0 t0, CP0_VPECONTROL
385 ehb
386
387 .set push
388 .set MIPS_ISA_LEVEL_RAW
389 .set mt
390
391 /* Skip the VPE if its TC is not halted */
392 mftc0 t0, CP0_TCHALT
393 beqz t0, 2f
394 nop
395
396 /* Calculate a pointer to the VPEs struct vpe_boot_config */
397 li t0, VPEBOOTCFG_SIZE
398 mul t0, t0, ta1
399 PTR_ADDU t0, t0, ta3
400
401 /* Set the TC restart PC */
402 lw t1, VPEBOOTCFG_PC(t0)
403 mttc0 t1, CP0_TCRESTART
404
405 /* Set the TC stack pointer */
406 lw t1, VPEBOOTCFG_SP(t0)
407 mttgpr t1, sp
408
409 /* Set the TC global pointer */
410 lw t1, VPEBOOTCFG_GP(t0)
411 mttgpr t1, gp
412
413 /* Copy config from this VPE */
414 mfc0 t0, CP0_CONFIG
415 mttc0 t0, CP0_CONFIG
416
417 /*
418 * Copy the EVA config from this VPE if the CPU supports it.
419 * CONFIG3 must exist to be running MT startup - just read it.
420 */
421 mfc0 t0, CP0_CONFIG, 3
422 and t0, t0, MIPS_CONF3_SC
423 beqz t0, 3f
424 nop
425 mfc0 t0, CP0_SEGCTL0
426 mttc0 t0, CP0_SEGCTL0
427 mfc0 t0, CP0_SEGCTL1
428 mttc0 t0, CP0_SEGCTL1
429 mfc0 t0, CP0_SEGCTL2
430 mttc0 t0, CP0_SEGCTL2
4313:
432 /* Ensure no software interrupts are pending */
433 mttc0 zero, CP0_CAUSE
434 mttc0 zero, CP0_STATUS
435
436 /* Set TC active, not interrupt exempt */
437 mftc0 t0, CP0_TCSTATUS
438 li t1, ~TCSTATUS_IXMT
439 and t0, t0, t1
440 ori t0, t0, TCSTATUS_A
441 mttc0 t0, CP0_TCSTATUS
442
443 /* Clear the TC halt bit */
444 mttc0 zero, CP0_TCHALT
445
446 /* Set VPE active */
447 mftc0 t0, CP0_VPECONF0
448 ori t0, t0, VPECONF0_VPA
449 mttc0 t0, CP0_VPECONF0
450
451 /* Next VPE */
4522: srl ta2, ta2, 1
453 addiu ta1, ta1, 1
454 bnez ta2, 1b
455 nop
456
457 /* Leave VPE configuration state */
458 mfc0 t1, CP0_MVPCONTROL
459 xori t1, t1, MVPCONTROL_VPC
460 mtc0 t1, CP0_MVPCONTROL
461 ehb
462 evpe
463
464 .set pop
465
466 /* Check whether this VPE is meant to be running */
467 li t0, 1
468 sll t0, t0, a1
469 and t0, t0, t8
470 bnez t0, 2f
471 nop
472
473 /* This VPE should be offline, halt the TC */
474 li t0, TCHALT_H
475 mtc0 t0, CP0_TCHALT
476 PTR_LA t0, 1f
4771: jr.hb t0
478 nop
479
4802:
481
482#endif /* CONFIG_MIPS_MT_SMP */
483
484 /* Return */
4855: jr ra
486 nop
487 END(mips_cps_boot_vpes)
488
489#if MIPS_ISA_REV > 0
490LEAF(mips_cps_cache_init)
491 /*
492 * Clear the bits used to index the caches. Note that the architecture
493 * dictates that writing to any of TagLo or TagHi selects 0 or 2 should
494 * be valid for all MIPS32 CPUs, even those for which said writes are
495 * unnecessary.
496 */
497 mtc0 zero, CP0_TAGLO, 0
498 mtc0 zero, CP0_TAGHI, 0
499 mtc0 zero, CP0_TAGLO, 2
500 mtc0 zero, CP0_TAGHI, 2
501 ehb
502
503 /* Primary cache configuration is indicated by Config1 */
504 mfc0 v0, CP0_CONFIG, 1
505
506 /* Detect I-cache line size */
507 _EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
508 beqz t0, icache_done
509 li t1, 2
510 sllv t0, t1, t0
511
512 /* Detect I-cache size */
513 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
514 xori t2, t1, 0x7
515 beqz t2, 1f
516 li t3, 32
517 addiu t1, t1, 1
518 sllv t1, t3, t1
5191: /* At this point t1 == I-cache sets per way */
520 _EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
521 addiu t2, t2, 1
522 mul t1, t1, t0
523 mul t1, t1, t2
524
525 li a0, CKSEG0
526 PTR_ADD a1, a0, t1
5271: cache Index_Store_Tag_I, 0(a0)
528 PTR_ADD a0, a0, t0
529 bne a0, a1, 1b
530 nop
531icache_done:
532
533 /* Detect D-cache line size */
534 _EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
535 beqz t0, dcache_done
536 li t1, 2
537 sllv t0, t1, t0
538
539 /* Detect D-cache size */
540 _EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
541 xori t2, t1, 0x7
542 beqz t2, 1f
543 li t3, 32
544 addiu t1, t1, 1
545 sllv t1, t3, t1
5461: /* At this point t1 == D-cache sets per way */
547 _EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
548 addiu t2, t2, 1
549 mul t1, t1, t0
550 mul t1, t1, t2
551
552 li a0, CKSEG0
553 PTR_ADDU a1, a0, t1
554 PTR_SUBU a1, a1, t0
5551: cache Index_Store_Tag_D, 0(a0)
556 bne a0, a1, 1b
557 PTR_ADD a0, a0, t0
558dcache_done:
559
560 jr ra
561 nop
562 END(mips_cps_cache_init)
563#endif /* MIPS_ISA_REV > 0 */
564
565#if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM)
566
567 /* Calculate a pointer to this CPUs struct mips_static_suspend_state */
568 .macro psstate dest
569 .set push
570 .set noat
571 lw $1, TI_CPU(gp)
572 sll $1, $1, LONGLOG
573 PTR_LA \dest, __per_cpu_offset
574 PTR_ADDU $1, $1, \dest
575 lw $1, 0($1)
576 PTR_LA \dest, cps_cpu_state
577 PTR_ADDU \dest, \dest, $1
578 .set pop
579 .endm
580
581LEAF(mips_cps_pm_save)
582 /* Save CPU state */
583 SUSPEND_SAVE_REGS
584 psstate t1
585 SUSPEND_SAVE_STATIC
586 jr v0
587 nop
588 END(mips_cps_pm_save)
589
590LEAF(mips_cps_pm_restore)
591 /* Restore CPU state */
592 psstate t1
593 RESUME_RESTORE_STATIC
594 RESUME_RESTORE_REGS_RETURN
595 END(mips_cps_pm_restore)
596
597#endif /* CONFIG_MIPS_CPS_PM && CONFIG_CPU_PM */