1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
 4 */
 5
 6#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
 7#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
 8
 9/* INFRACFG resets */
10#define MT2701_INFRA_EMI_REG_RST		0
11#define MT2701_INFRA_DRAMC0_A0_RST		1
12#define MT2701_INFRA_FHCTL_RST			2
13#define MT2701_INFRA_APCIRQ_EINT_RST		3
14#define MT2701_INFRA_APXGPT_RST			4
15#define MT2701_INFRA_SCPSYS_RST			5
16#define MT2701_INFRA_KP_RST			6
17#define MT2701_INFRA_PMIC_WRAP_RST		7
18#define MT2701_INFRA_MIPI_RST			8
19#define MT2701_INFRA_IRRX_RST			9
20#define MT2701_INFRA_CEC_RST			10
21#define MT2701_INFRA_EMI_RST			32
22#define MT2701_INFRA_DRAMC0_RST			34
23#define MT2701_INFRA_TRNG_RST			37
24#define MT2701_INFRA_SYSIRQ_RST			38
25
26/*  PERICFG resets */
27#define MT2701_PERI_UART0_SW_RST		0
28#define MT2701_PERI_UART1_SW_RST		1
29#define MT2701_PERI_UART2_SW_RST		2
30#define MT2701_PERI_UART3_SW_RST		3
31#define MT2701_PERI_GCPU_SW_RST			5
32#define MT2701_PERI_BTIF_SW_RST			6
33#define MT2701_PERI_PWM_SW_RST			8
34#define MT2701_PERI_AUXADC_SW_RST		10
35#define MT2701_PERI_DMA_SW_RST			11
36#define MT2701_PERI_NFI_SW_RST			14
37#define MT2701_PERI_NLI_SW_RST			15
38#define MT2701_PERI_THERM_SW_RST		16
39#define MT2701_PERI_MSDC2_SW_RST		17
40#define MT2701_PERI_MSDC0_SW_RST		19
41#define MT2701_PERI_MSDC1_SW_RST		20
42#define MT2701_PERI_I2C0_SW_RST			22
43#define MT2701_PERI_I2C1_SW_RST			23
44#define MT2701_PERI_I2C2_SW_RST			24
45#define MT2701_PERI_I2C3_SW_RST			25
46#define MT2701_PERI_USB_SW_RST			28
47#define MT2701_PERI_ETH_SW_RST			29
48#define MT2701_PERI_SPI0_SW_RST			33
49
50/* TOPRGU resets */
51#define MT2701_TOPRGU_INFRA_RST			0
52#define MT2701_TOPRGU_MM_RST			1
53#define MT2701_TOPRGU_MFG_RST			2
54#define MT2701_TOPRGU_ETHDMA_RST		3
55#define MT2701_TOPRGU_VDEC_RST			4
56#define MT2701_TOPRGU_VENC_IMG_RST		5
57#define MT2701_TOPRGU_DDRPHY_RST		6
58#define MT2701_TOPRGU_MD_RST			7
59#define MT2701_TOPRGU_INFRA_AO_RST		8
60#define MT2701_TOPRGU_CONN_RST			9
61#define MT2701_TOPRGU_APMIXED_RST		10
62#define MT2701_TOPRGU_HIFSYS_RST		11
63#define MT2701_TOPRGU_CONN_MCU_RST		12
64#define MT2701_TOPRGU_BDP_DISP_RST		13
65
66/* HIFSYS resets */
67#define MT2701_HIFSYS_UHOST0_RST		3
68#define MT2701_HIFSYS_UHOST1_RST		4
69#define MT2701_HIFSYS_UPHY0_RST			21
70#define MT2701_HIFSYS_UPHY1_RST			22
71#define MT2701_HIFSYS_PCIE0_RST			24
72#define MT2701_HIFSYS_PCIE1_RST			25
73#define MT2701_HIFSYS_PCIE2_RST			26
74
75/* ETHSYS resets */
76#define MT2701_ETHSYS_SYS_RST			0
77#define MT2701_ETHSYS_MCM_RST			2
78#define MT2701_ETHSYS_FE_RST			6
79#define MT2701_ETHSYS_GMAC_RST			23
80#define MT2701_ETHSYS_PPE_RST			31
81
82/* G3DSYS resets */
83#define MT2701_G3DSYS_CORE_RST			0
84
85#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */