1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#include <drm/drm_managed.h>
  7
  8#include "xe_device.h"
  9#include "xe_ggtt.h"
 10#include "xe_gt.h"
 11#include "xe_migrate.h"
 12#include "xe_sa.h"
 13#include "xe_tile.h"
 14#include "xe_tile_sysfs.h"
 15#include "xe_ttm_vram_mgr.h"
 16#include "xe_wa.h"
 17
 18/**
 19 * DOC: Multi-tile Design
 20 *
 21 * Different vendors use the term "tile" a bit differently, but in the Intel
 22 * world, a 'tile' is pretty close to what most people would think of as being
 23 * a complete GPU.  When multiple GPUs are placed behind a single PCI device,
 24 * that's what is referred to as a "multi-tile device."  In such cases, pretty
 25 * much all hardware is replicated per-tile, although certain responsibilities
 26 * like PCI communication, reporting of interrupts to the OS, etc. are handled
 27 * solely by the "root tile."  A multi-tile platform takes care of tying the
 28 * tiles together in a way such that interrupt notifications from remote tiles
 29 * are forwarded to the root tile, the per-tile vram is combined into a single
 30 * address space, etc.
 31 *
 32 * In contrast, a "GT" (which officially stands for "Graphics Technology") is
 33 * the subset of a GPU/tile that is responsible for implementing graphics
 34 * and/or media operations.  The GT is where a lot of the driver implementation
 35 * happens since it's where the hardware engines, the execution units, and the
 36 * GuC all reside.
 37 *
 38 * Historically most Intel devices were single-tile devices that contained a
 39 * single GT.  PVC is an example of an Intel platform built on a multi-tile
 40 * design (i.e., multiple GPUs behind a single PCI device); each PVC tile only
 41 * has a single GT.  In contrast, platforms like MTL that have separate chips
 42 * for render and media IP are still only a single logical GPU, but the
 43 * graphics and media IP blocks are each exposed as a separate GT within that
 44 * single GPU.  This is important from a software perspective because multi-GT
 45 * platforms like MTL only replicate a subset of the GPU hardware and behave
 46 * differently than multi-tile platforms like PVC where nearly everything is
 47 * replicated.
 48 *
 49 * Per-tile functionality (shared by all GTs within the tile):
 50 *  - Complete 4MB MMIO space (containing SGunit/SoC registers, GT
 51 *    registers, display registers, etc.)
 52 *  - Global GTT
 53 *  - VRAM (if discrete)
 54 *  - Interrupt flows
 55 *  - Migration context
 56 *  - kernel batchbuffer pool
 57 *  - Primary GT
 58 *  - Media GT (if media version >= 13)
 59 *
 60 * Per-GT functionality:
 61 *  - GuC
 62 *  - Hardware engines
 63 *  - Programmable hardware units (subslices, EUs)
 64 *  - GSI subset of registers (multiple copies of these registers reside
 65 *    within the complete MMIO space provided by the tile, but at different
 66 *    offsets --- 0 for render, 0x380000 for media)
 67 *  - Multicast register steering
 68 *  - TLBs to cache page table translations
 69 *  - Reset capability
 70 *  - Low-level power management (e.g., C6)
 71 *  - Clock frequency
 72 *  - MOCS and PAT programming
 73 */
 74
 75/**
 76 * xe_tile_alloc - Perform per-tile memory allocation
 77 * @tile: Tile to perform allocations for
 78 *
 79 * Allocates various per-tile data structures using DRM-managed allocations.
 80 * Does not touch the hardware.
 81 *
 82 * Returns -ENOMEM if allocations fail, otherwise 0.
 83 */
 84static int xe_tile_alloc(struct xe_tile *tile)
 85{
 86	struct drm_device *drm = &tile_to_xe(tile)->drm;
 87
 88	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),
 89				      GFP_KERNEL);
 90	if (!tile->mem.ggtt)
 91		return -ENOMEM;
 92	tile->mem.ggtt->tile = tile;
 93
 94	tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL);
 95	if (!tile->mem.vram_mgr)
 96		return -ENOMEM;
 97
 98	return 0;
 99}
100
101/**
102 * xe_tile_init_early - Initialize the tile and primary GT
103 * @tile: Tile to initialize
104 * @xe: Parent Xe device
105 * @id: Tile ID
106 *
107 * Initializes per-tile resources that don't require any interactions with the
108 * hardware or any knowledge about the Graphics/Media IP version.
109 *
110 * Returns: 0 on success, negative error code on error.
111 */
112int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id)
113{
114	int err;
115
116	tile->xe = xe;
117	tile->id = id;
118
119	err = xe_tile_alloc(tile);
120	if (err)
121		return err;
122
123	tile->primary_gt = xe_gt_alloc(tile);
124	if (IS_ERR(tile->primary_gt))
125		return PTR_ERR(tile->primary_gt);
126
127	return 0;
128}
129
130static int tile_ttm_mgr_init(struct xe_tile *tile)
131{
132	struct xe_device *xe = tile_to_xe(tile);
133	int err;
134
135	if (tile->mem.vram.usable_size) {
136		err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr);
137		if (err)
138			return err;
139		xe->info.mem_region_mask |= BIT(tile->id) << 1;
140	}
141
142	return 0;
143}
144
145/**
146 * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
147 * @tile: The tile to initialize.
148 *
149 * This function prepares the tile to allow memory allocations to VRAM, but is
150 * not allowed to allocate memory itself. This state is useful for display
151 * readout, because the inherited display framebuffer will otherwise be
152 * overwritten as it is usually put at the start of VRAM.
153 *
154 * Note that since this is tile initialization, it should not perform any
155 * GT-specific operations, and thus does not need to hold GT forcewake.
156 *
157 * Returns: 0 on success, negative error code on error.
158 */
159int xe_tile_init_noalloc(struct xe_tile *tile)
160{
161	int err;
162
163	xe_device_mem_access_get(tile_to_xe(tile));
164
165	err = tile_ttm_mgr_init(tile);
166	if (err)
167		goto err_mem_access;
168
169	tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);
170	if (IS_ERR(tile->mem.kernel_bb_pool)) {
171		err = PTR_ERR(tile->mem.kernel_bb_pool);
172		goto err_mem_access;
173	}
174	xe_wa_apply_tile_workarounds(tile);
175
176	xe_tile_sysfs_init(tile);
177
178err_mem_access:
179	xe_device_mem_access_put(tile_to_xe(tile));
180	return err;
181}
182
183void xe_tile_migrate_wait(struct xe_tile *tile)
184{
185	xe_migrate_wait(tile->migrate);
186}