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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33
34#include <linux/vga_switcheroo.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
37#include "amdgpu_amdkfd.h"
38
39#if defined(CONFIG_VGA_SWITCHEROO)
40bool amdgpu_has_atpx(void);
41#else
42static inline bool amdgpu_has_atpx(void) { return false; }
43#endif
44
45/**
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
52 */
53int amdgpu_driver_unload_kms(struct drm_device *dev)
54{
55 struct amdgpu_device *adev = dev->dev_private;
56
57 if (adev == NULL)
58 return 0;
59
60 if (adev->rmmio == NULL)
61 goto done_free;
62
63 pm_runtime_get_sync(dev->dev);
64
65 amdgpu_amdkfd_device_fini(adev);
66
67 amdgpu_acpi_fini(adev);
68
69 amdgpu_device_fini(adev);
70
71done_free:
72 kfree(adev);
73 dev->dev_private = NULL;
74 return 0;
75}
76
77/**
78 * amdgpu_driver_load_kms - Main load function for KMS.
79 *
80 * @dev: drm dev pointer
81 * @flags: device flags
82 *
83 * This is the main load function for KMS (all asics).
84 * Returns 0 on success, error on failure.
85 */
86int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
87{
88 struct amdgpu_device *adev;
89 int r, acpi_status;
90
91 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
92 if (adev == NULL) {
93 return -ENOMEM;
94 }
95 dev->dev_private = (void *)adev;
96
97 if ((amdgpu_runtime_pm != 0) &&
98 amdgpu_has_atpx() &&
99 ((flags & AMD_IS_APU) == 0))
100 flags |= AMD_IS_PX;
101
102 /* amdgpu_device_init should report only fatal error
103 * like memory allocation failure or iomapping failure,
104 * or memory manager initialization failure, it must
105 * properly initialize the GPU MC controller and permit
106 * VRAM allocation
107 */
108 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
109 if (r) {
110 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
111 goto out;
112 }
113
114 /* Call ACPI methods: require modeset init
115 * but failure is not fatal
116 */
117 if (!r) {
118 acpi_status = amdgpu_acpi_init(adev);
119 if (acpi_status)
120 dev_dbg(&dev->pdev->dev,
121 "Error during ACPI methods call\n");
122 }
123
124 amdgpu_amdkfd_load_interface(adev);
125 amdgpu_amdkfd_device_probe(adev);
126 amdgpu_amdkfd_device_init(adev);
127
128 if (amdgpu_device_is_px(dev)) {
129 pm_runtime_use_autosuspend(dev->dev);
130 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
131 pm_runtime_set_active(dev->dev);
132 pm_runtime_allow(dev->dev);
133 pm_runtime_mark_last_busy(dev->dev);
134 pm_runtime_put_autosuspend(dev->dev);
135 }
136
137out:
138 if (r)
139 amdgpu_driver_unload_kms(dev);
140
141
142 return r;
143}
144
145/*
146 * Userspace get information ioctl
147 */
148/**
149 * amdgpu_info_ioctl - answer a device specific request.
150 *
151 * @adev: amdgpu device pointer
152 * @data: request object
153 * @filp: drm filp
154 *
155 * This function is used to pass device specific parameters to the userspace
156 * drivers. Examples include: pci device id, pipeline parms, tiling params,
157 * etc. (all asics).
158 * Returns 0 on success, -EINVAL on failure.
159 */
160static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
161{
162 struct amdgpu_device *adev = dev->dev_private;
163 struct drm_amdgpu_info *info = data;
164 struct amdgpu_mode_info *minfo = &adev->mode_info;
165 void __user *out = (void __user *)(long)info->return_pointer;
166 uint32_t size = info->return_size;
167 struct drm_crtc *crtc;
168 uint32_t ui32 = 0;
169 uint64_t ui64 = 0;
170 int i, found;
171
172 if (!info->return_size || !info->return_pointer)
173 return -EINVAL;
174
175 switch (info->query) {
176 case AMDGPU_INFO_ACCEL_WORKING:
177 ui32 = adev->accel_working;
178 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
179 case AMDGPU_INFO_CRTC_FROM_ID:
180 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
181 crtc = (struct drm_crtc *)minfo->crtcs[i];
182 if (crtc && crtc->base.id == info->mode_crtc.id) {
183 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
184 ui32 = amdgpu_crtc->crtc_id;
185 found = 1;
186 break;
187 }
188 }
189 if (!found) {
190 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
191 return -EINVAL;
192 }
193 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
194 case AMDGPU_INFO_HW_IP_INFO: {
195 struct drm_amdgpu_info_hw_ip ip = {};
196 enum amd_ip_block_type type;
197 uint32_t ring_mask = 0;
198 uint32_t ib_start_alignment = 0;
199 uint32_t ib_size_alignment = 0;
200
201 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
202 return -EINVAL;
203
204 switch (info->query_hw_ip.type) {
205 case AMDGPU_HW_IP_GFX:
206 type = AMD_IP_BLOCK_TYPE_GFX;
207 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
208 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
209 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
210 ib_size_alignment = 8;
211 break;
212 case AMDGPU_HW_IP_COMPUTE:
213 type = AMD_IP_BLOCK_TYPE_GFX;
214 for (i = 0; i < adev->gfx.num_compute_rings; i++)
215 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
216 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
217 ib_size_alignment = 8;
218 break;
219 case AMDGPU_HW_IP_DMA:
220 type = AMD_IP_BLOCK_TYPE_SDMA;
221 for (i = 0; i < adev->sdma.num_instances; i++)
222 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
223 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
224 ib_size_alignment = 1;
225 break;
226 case AMDGPU_HW_IP_UVD:
227 type = AMD_IP_BLOCK_TYPE_UVD;
228 ring_mask = adev->uvd.ring.ready ? 1 : 0;
229 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
230 ib_size_alignment = 8;
231 break;
232 case AMDGPU_HW_IP_VCE:
233 type = AMD_IP_BLOCK_TYPE_VCE;
234 for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
235 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
236 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
237 ib_size_alignment = 8;
238 break;
239 default:
240 return -EINVAL;
241 }
242
243 for (i = 0; i < adev->num_ip_blocks; i++) {
244 if (adev->ip_blocks[i].type == type &&
245 adev->ip_block_status[i].valid) {
246 ip.hw_ip_version_major = adev->ip_blocks[i].major;
247 ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
248 ip.capabilities_flags = 0;
249 ip.available_rings = ring_mask;
250 ip.ib_start_alignment = ib_start_alignment;
251 ip.ib_size_alignment = ib_size_alignment;
252 break;
253 }
254 }
255 return copy_to_user(out, &ip,
256 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
257 }
258 case AMDGPU_INFO_HW_IP_COUNT: {
259 enum amd_ip_block_type type;
260 uint32_t count = 0;
261
262 switch (info->query_hw_ip.type) {
263 case AMDGPU_HW_IP_GFX:
264 type = AMD_IP_BLOCK_TYPE_GFX;
265 break;
266 case AMDGPU_HW_IP_COMPUTE:
267 type = AMD_IP_BLOCK_TYPE_GFX;
268 break;
269 case AMDGPU_HW_IP_DMA:
270 type = AMD_IP_BLOCK_TYPE_SDMA;
271 break;
272 case AMDGPU_HW_IP_UVD:
273 type = AMD_IP_BLOCK_TYPE_UVD;
274 break;
275 case AMDGPU_HW_IP_VCE:
276 type = AMD_IP_BLOCK_TYPE_VCE;
277 break;
278 default:
279 return -EINVAL;
280 }
281
282 for (i = 0; i < adev->num_ip_blocks; i++)
283 if (adev->ip_blocks[i].type == type &&
284 adev->ip_block_status[i].valid &&
285 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
286 count++;
287
288 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
289 }
290 case AMDGPU_INFO_TIMESTAMP:
291 ui64 = amdgpu_asic_get_gpu_clock_counter(adev);
292 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
293 case AMDGPU_INFO_FW_VERSION: {
294 struct drm_amdgpu_info_firmware fw_info;
295
296 /* We only support one instance of each IP block right now. */
297 if (info->query_fw.ip_instance != 0)
298 return -EINVAL;
299
300 switch (info->query_fw.fw_type) {
301 case AMDGPU_INFO_FW_VCE:
302 fw_info.ver = adev->vce.fw_version;
303 fw_info.feature = adev->vce.fb_version;
304 break;
305 case AMDGPU_INFO_FW_UVD:
306 fw_info.ver = adev->uvd.fw_version;
307 fw_info.feature = 0;
308 break;
309 case AMDGPU_INFO_FW_GMC:
310 fw_info.ver = adev->mc.fw_version;
311 fw_info.feature = 0;
312 break;
313 case AMDGPU_INFO_FW_GFX_ME:
314 fw_info.ver = adev->gfx.me_fw_version;
315 fw_info.feature = adev->gfx.me_feature_version;
316 break;
317 case AMDGPU_INFO_FW_GFX_PFP:
318 fw_info.ver = adev->gfx.pfp_fw_version;
319 fw_info.feature = adev->gfx.pfp_feature_version;
320 break;
321 case AMDGPU_INFO_FW_GFX_CE:
322 fw_info.ver = adev->gfx.ce_fw_version;
323 fw_info.feature = adev->gfx.ce_feature_version;
324 break;
325 case AMDGPU_INFO_FW_GFX_RLC:
326 fw_info.ver = adev->gfx.rlc_fw_version;
327 fw_info.feature = adev->gfx.rlc_feature_version;
328 break;
329 case AMDGPU_INFO_FW_GFX_MEC:
330 if (info->query_fw.index == 0) {
331 fw_info.ver = adev->gfx.mec_fw_version;
332 fw_info.feature = adev->gfx.mec_feature_version;
333 } else if (info->query_fw.index == 1) {
334 fw_info.ver = adev->gfx.mec2_fw_version;
335 fw_info.feature = adev->gfx.mec2_feature_version;
336 } else
337 return -EINVAL;
338 break;
339 case AMDGPU_INFO_FW_SMC:
340 fw_info.ver = adev->pm.fw_version;
341 fw_info.feature = 0;
342 break;
343 case AMDGPU_INFO_FW_SDMA:
344 if (info->query_fw.index >= adev->sdma.num_instances)
345 return -EINVAL;
346 fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version;
347 fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version;
348 break;
349 default:
350 return -EINVAL;
351 }
352 return copy_to_user(out, &fw_info,
353 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
354 }
355 case AMDGPU_INFO_NUM_BYTES_MOVED:
356 ui64 = atomic64_read(&adev->num_bytes_moved);
357 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
358 case AMDGPU_INFO_VRAM_USAGE:
359 ui64 = atomic64_read(&adev->vram_usage);
360 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
361 case AMDGPU_INFO_VIS_VRAM_USAGE:
362 ui64 = atomic64_read(&adev->vram_vis_usage);
363 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
364 case AMDGPU_INFO_GTT_USAGE:
365 ui64 = atomic64_read(&adev->gtt_usage);
366 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
367 case AMDGPU_INFO_GDS_CONFIG: {
368 struct drm_amdgpu_info_gds gds_info;
369
370 memset(&gds_info, 0, sizeof(gds_info));
371 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
372 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
373 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
374 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
375 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
376 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
377 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
378 return copy_to_user(out, &gds_info,
379 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
380 }
381 case AMDGPU_INFO_VRAM_GTT: {
382 struct drm_amdgpu_info_vram_gtt vram_gtt;
383
384 vram_gtt.vram_size = adev->mc.real_vram_size;
385 vram_gtt.vram_size -= adev->vram_pin_size;
386 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
387 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
388 vram_gtt.gtt_size = adev->mc.gtt_size;
389 vram_gtt.gtt_size -= adev->gart_pin_size;
390 return copy_to_user(out, &vram_gtt,
391 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
392 }
393 case AMDGPU_INFO_READ_MMR_REG: {
394 unsigned n, alloc_size;
395 uint32_t *regs;
396 unsigned se_num = (info->read_mmr_reg.instance >>
397 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
398 AMDGPU_INFO_MMR_SE_INDEX_MASK;
399 unsigned sh_num = (info->read_mmr_reg.instance >>
400 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
401 AMDGPU_INFO_MMR_SH_INDEX_MASK;
402
403 /* set full masks if the userspace set all bits
404 * in the bitfields */
405 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
406 se_num = 0xffffffff;
407 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
408 sh_num = 0xffffffff;
409
410 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
411 if (!regs)
412 return -ENOMEM;
413 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
414
415 for (i = 0; i < info->read_mmr_reg.count; i++)
416 if (amdgpu_asic_read_register(adev, se_num, sh_num,
417 info->read_mmr_reg.dword_offset + i,
418 ®s[i])) {
419 DRM_DEBUG_KMS("unallowed offset %#x\n",
420 info->read_mmr_reg.dword_offset + i);
421 kfree(regs);
422 return -EFAULT;
423 }
424 n = copy_to_user(out, regs, min(size, alloc_size));
425 kfree(regs);
426 return n ? -EFAULT : 0;
427 }
428 case AMDGPU_INFO_DEV_INFO: {
429 struct drm_amdgpu_info_device dev_info = {};
430 struct amdgpu_cu_info cu_info;
431
432 dev_info.device_id = dev->pdev->device;
433 dev_info.chip_rev = adev->rev_id;
434 dev_info.external_rev = adev->external_rev_id;
435 dev_info.pci_rev = dev->pdev->revision;
436 dev_info.family = adev->family;
437 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
438 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
439 /* return all clocks in KHz */
440 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
441 if (adev->pm.dpm_enabled) {
442 dev_info.max_engine_clock =
443 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
444 dev_info.max_memory_clock =
445 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10;
446 } else {
447 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
448 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
449 }
450 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
451 dev_info.num_rb_pipes = adev->gfx.config.num_rbs;
452 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
453 dev_info._pad = 0;
454 dev_info.ids_flags = 0;
455 if (adev->flags & AMD_IS_APU)
456 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
457 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
458 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
459 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
460 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
461 AMDGPU_GPU_PAGE_SIZE;
462 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
463
464 amdgpu_asic_get_cu_info(adev, &cu_info);
465 dev_info.cu_active_number = cu_info.number;
466 dev_info.cu_ao_mask = cu_info.ao_cu_mask;
467 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
468 memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
469 dev_info.vram_type = adev->mc.vram_type;
470 dev_info.vram_bit_width = adev->mc.vram_width;
471 dev_info.vce_harvest_config = adev->vce.harvest_config;
472
473 return copy_to_user(out, &dev_info,
474 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
475 }
476 default:
477 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
478 return -EINVAL;
479 }
480 return 0;
481}
482
483
484/*
485 * Outdated mess for old drm with Xorg being in charge (void function now).
486 */
487/**
488 * amdgpu_driver_lastclose_kms - drm callback for last close
489 *
490 * @dev: drm dev pointer
491 *
492 * Switch vga_switcheroo state after last close (all asics).
493 */
494void amdgpu_driver_lastclose_kms(struct drm_device *dev)
495{
496 struct amdgpu_device *adev = dev->dev_private;
497
498 amdgpu_fbdev_restore_mode(adev);
499 vga_switcheroo_process_delayed_switch();
500}
501
502/**
503 * amdgpu_driver_open_kms - drm callback for open
504 *
505 * @dev: drm dev pointer
506 * @file_priv: drm file
507 *
508 * On device open, init vm on cayman+ (all asics).
509 * Returns 0 on success, error on failure.
510 */
511int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
512{
513 struct amdgpu_device *adev = dev->dev_private;
514 struct amdgpu_fpriv *fpriv;
515 int r;
516
517 file_priv->driver_priv = NULL;
518
519 r = pm_runtime_get_sync(dev->dev);
520 if (r < 0)
521 return r;
522
523 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
524 if (unlikely(!fpriv))
525 return -ENOMEM;
526
527 r = amdgpu_vm_init(adev, &fpriv->vm);
528 if (r)
529 goto error_free;
530
531 mutex_init(&fpriv->bo_list_lock);
532 idr_init(&fpriv->bo_list_handles);
533
534 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
535
536 file_priv->driver_priv = fpriv;
537
538 pm_runtime_mark_last_busy(dev->dev);
539 pm_runtime_put_autosuspend(dev->dev);
540 return 0;
541
542error_free:
543 kfree(fpriv);
544
545 return r;
546}
547
548/**
549 * amdgpu_driver_postclose_kms - drm callback for post close
550 *
551 * @dev: drm dev pointer
552 * @file_priv: drm file
553 *
554 * On device post close, tear down vm on cayman+ (all asics).
555 */
556void amdgpu_driver_postclose_kms(struct drm_device *dev,
557 struct drm_file *file_priv)
558{
559 struct amdgpu_device *adev = dev->dev_private;
560 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
561 struct amdgpu_bo_list *list;
562 int handle;
563
564 if (!fpriv)
565 return;
566
567 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
568
569 amdgpu_vm_fini(adev, &fpriv->vm);
570
571 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
572 amdgpu_bo_list_free(list);
573
574 idr_destroy(&fpriv->bo_list_handles);
575 mutex_destroy(&fpriv->bo_list_lock);
576
577 kfree(fpriv);
578 file_priv->driver_priv = NULL;
579}
580
581/**
582 * amdgpu_driver_preclose_kms - drm callback for pre close
583 *
584 * @dev: drm dev pointer
585 * @file_priv: drm file
586 *
587 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
588 * (all asics).
589 */
590void amdgpu_driver_preclose_kms(struct drm_device *dev,
591 struct drm_file *file_priv)
592{
593 struct amdgpu_device *adev = dev->dev_private;
594
595 amdgpu_uvd_free_handles(adev, file_priv);
596 amdgpu_vce_free_handles(adev, file_priv);
597}
598
599/*
600 * VBlank related functions.
601 */
602/**
603 * amdgpu_get_vblank_counter_kms - get frame count
604 *
605 * @dev: drm dev pointer
606 * @pipe: crtc to get the frame count from
607 *
608 * Gets the frame count on the requested crtc (all asics).
609 * Returns frame count on success, -EINVAL on failure.
610 */
611u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
612{
613 struct amdgpu_device *adev = dev->dev_private;
614 int vpos, hpos, stat;
615 u32 count;
616
617 if (pipe >= adev->mode_info.num_crtc) {
618 DRM_ERROR("Invalid crtc %u\n", pipe);
619 return -EINVAL;
620 }
621
622 /* The hw increments its frame counter at start of vsync, not at start
623 * of vblank, as is required by DRM core vblank counter handling.
624 * Cook the hw count here to make it appear to the caller as if it
625 * incremented at start of vblank. We measure distance to start of
626 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
627 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
628 * result by 1 to give the proper appearance to caller.
629 */
630 if (adev->mode_info.crtcs[pipe]) {
631 /* Repeat readout if needed to provide stable result if
632 * we cross start of vsync during the queries.
633 */
634 do {
635 count = amdgpu_display_vblank_get_counter(adev, pipe);
636 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
637 * distance to start of vblank, instead of regular
638 * vertical scanout pos.
639 */
640 stat = amdgpu_get_crtc_scanoutpos(
641 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
642 &vpos, &hpos, NULL, NULL,
643 &adev->mode_info.crtcs[pipe]->base.hwmode);
644 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
645
646 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
647 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
648 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
649 } else {
650 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
651 pipe, vpos);
652
653 /* Bump counter if we are at >= leading edge of vblank,
654 * but before vsync where vpos would turn negative and
655 * the hw counter really increments.
656 */
657 if (vpos >= 0)
658 count++;
659 }
660 } else {
661 /* Fallback to use value as is. */
662 count = amdgpu_display_vblank_get_counter(adev, pipe);
663 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
664 }
665
666 return count;
667}
668
669/**
670 * amdgpu_enable_vblank_kms - enable vblank interrupt
671 *
672 * @dev: drm dev pointer
673 * @pipe: crtc to enable vblank interrupt for
674 *
675 * Enable the interrupt on the requested crtc (all asics).
676 * Returns 0 on success, -EINVAL on failure.
677 */
678int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
679{
680 struct amdgpu_device *adev = dev->dev_private;
681 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
682
683 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
684}
685
686/**
687 * amdgpu_disable_vblank_kms - disable vblank interrupt
688 *
689 * @dev: drm dev pointer
690 * @pipe: crtc to disable vblank interrupt for
691 *
692 * Disable the interrupt on the requested crtc (all asics).
693 */
694void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
695{
696 struct amdgpu_device *adev = dev->dev_private;
697 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
698
699 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
700}
701
702/**
703 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
704 *
705 * @dev: drm dev pointer
706 * @crtc: crtc to get the timestamp for
707 * @max_error: max error
708 * @vblank_time: time value
709 * @flags: flags passed to the driver
710 *
711 * Gets the timestamp on the requested crtc based on the
712 * scanout position. (all asics).
713 * Returns postive status flags on success, negative error on failure.
714 */
715int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
716 int *max_error,
717 struct timeval *vblank_time,
718 unsigned flags)
719{
720 struct drm_crtc *crtc;
721 struct amdgpu_device *adev = dev->dev_private;
722
723 if (pipe >= dev->num_crtcs) {
724 DRM_ERROR("Invalid crtc %u\n", pipe);
725 return -EINVAL;
726 }
727
728 /* Get associated drm_crtc: */
729 crtc = &adev->mode_info.crtcs[pipe]->base;
730 if (!crtc) {
731 /* This can occur on driver load if some component fails to
732 * initialize completely and driver is unloaded */
733 DRM_ERROR("Uninitialized crtc %d\n", pipe);
734 return -EINVAL;
735 }
736
737 /* Helper routine in DRM core does all the work: */
738 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
739 vblank_time, flags,
740 &crtc->hwmode);
741}
742
743const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
744 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
745 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
746 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
747 /* KMS */
748 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
749 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
750 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
751 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
752 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
753 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
754 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
755 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
756 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
757};
758int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include <drm/drm_drv.h>
32#include <drm/drm_fb_helper.h>
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "atom.h"
36
37#include <linux/vga_switcheroo.h>
38#include <linux/slab.h>
39#include <linux/uaccess.h>
40#include <linux/pci.h>
41#include <linux/pm_runtime.h>
42#include "amdgpu_amdkfd.h"
43#include "amdgpu_gem.h"
44#include "amdgpu_display.h"
45#include "amdgpu_ras.h"
46#include "amd_pcie.h"
47
48void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
49{
50 struct amdgpu_gpu_instance *gpu_instance;
51 int i;
52
53 mutex_lock(&mgpu_info.mutex);
54
55 for (i = 0; i < mgpu_info.num_gpu; i++) {
56 gpu_instance = &(mgpu_info.gpu_ins[i]);
57 if (gpu_instance->adev == adev) {
58 mgpu_info.gpu_ins[i] =
59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
60 mgpu_info.num_gpu--;
61 if (adev->flags & AMD_IS_APU)
62 mgpu_info.num_apu--;
63 else
64 mgpu_info.num_dgpu--;
65 break;
66 }
67 }
68
69 mutex_unlock(&mgpu_info.mutex);
70}
71
72/**
73 * amdgpu_driver_unload_kms - Main unload function for KMS.
74 *
75 * @dev: drm dev pointer
76 *
77 * This is the main unload function for KMS (all asics).
78 * Returns 0 on success.
79 */
80void amdgpu_driver_unload_kms(struct drm_device *dev)
81{
82 struct amdgpu_device *adev = drm_to_adev(dev);
83
84 if (adev == NULL)
85 return;
86
87 amdgpu_unregister_gpu_instance(adev);
88
89 if (adev->rmmio == NULL)
90 return;
91
92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
93 DRM_WARN("smart shift update failed\n");
94
95 amdgpu_acpi_fini(adev);
96 amdgpu_device_fini_hw(adev);
97}
98
99void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
100{
101 struct amdgpu_gpu_instance *gpu_instance;
102
103 mutex_lock(&mgpu_info.mutex);
104
105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
106 DRM_ERROR("Cannot register more gpu instance\n");
107 mutex_unlock(&mgpu_info.mutex);
108 return;
109 }
110
111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
112 gpu_instance->adev = adev;
113 gpu_instance->mgpu_fan_enabled = 0;
114
115 mgpu_info.num_gpu++;
116 if (adev->flags & AMD_IS_APU)
117 mgpu_info.num_apu++;
118 else
119 mgpu_info.num_dgpu++;
120
121 mutex_unlock(&mgpu_info.mutex);
122}
123
124/**
125 * amdgpu_driver_load_kms - Main load function for KMS.
126 *
127 * @adev: pointer to struct amdgpu_device
128 * @flags: device flags
129 *
130 * This is the main load function for KMS (all asics).
131 * Returns 0 on success, error on failure.
132 */
133int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
134{
135 struct drm_device *dev;
136 int r, acpi_status;
137
138 dev = adev_to_drm(adev);
139
140 /* amdgpu_device_init should report only fatal error
141 * like memory allocation failure or iomapping failure,
142 * or memory manager initialization failure, it must
143 * properly initialize the GPU MC controller and permit
144 * VRAM allocation
145 */
146 r = amdgpu_device_init(adev, flags);
147 if (r) {
148 dev_err(dev->dev, "Fatal error during GPU init\n");
149 goto out;
150 }
151
152 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
153 if (amdgpu_device_supports_px(dev) &&
154 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
155 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
156 dev_info(adev->dev, "Using ATPX for runtime pm\n");
157 } else if (amdgpu_device_supports_boco(dev) &&
158 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
159 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
160 dev_info(adev->dev, "Using BOCO for runtime pm\n");
161 } else if (amdgpu_device_supports_baco(dev) &&
162 (amdgpu_runtime_pm != 0)) {
163 switch (adev->asic_type) {
164 case CHIP_VEGA20:
165 case CHIP_ARCTURUS:
166 /* enable BACO as runpm mode if runpm=1 */
167 if (amdgpu_runtime_pm > 0)
168 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
169 break;
170 case CHIP_VEGA10:
171 /* enable BACO as runpm mode if noretry=0 */
172 if (!adev->gmc.noretry)
173 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
174 break;
175 default:
176 /* enable BACO as runpm mode on CI+ */
177 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
178 break;
179 }
180
181 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
182 dev_info(adev->dev, "Using BACO for runtime pm\n");
183 }
184
185 /* Call ACPI methods: require modeset init
186 * but failure is not fatal
187 */
188
189 acpi_status = amdgpu_acpi_init(adev);
190 if (acpi_status)
191 dev_dbg(dev->dev, "Error during ACPI methods call\n");
192
193 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
194 DRM_WARN("smart shift update failed\n");
195
196out:
197 if (r)
198 amdgpu_driver_unload_kms(dev);
199
200 return r;
201}
202
203static enum amd_ip_block_type
204 amdgpu_ip_get_block_type(struct amdgpu_device *adev, uint32_t ip)
205{
206 enum amd_ip_block_type type;
207
208 switch (ip) {
209 case AMDGPU_HW_IP_GFX:
210 type = AMD_IP_BLOCK_TYPE_GFX;
211 break;
212 case AMDGPU_HW_IP_COMPUTE:
213 type = AMD_IP_BLOCK_TYPE_GFX;
214 break;
215 case AMDGPU_HW_IP_DMA:
216 type = AMD_IP_BLOCK_TYPE_SDMA;
217 break;
218 case AMDGPU_HW_IP_UVD:
219 case AMDGPU_HW_IP_UVD_ENC:
220 type = AMD_IP_BLOCK_TYPE_UVD;
221 break;
222 case AMDGPU_HW_IP_VCE:
223 type = AMD_IP_BLOCK_TYPE_VCE;
224 break;
225 case AMDGPU_HW_IP_VCN_DEC:
226 case AMDGPU_HW_IP_VCN_ENC:
227 type = AMD_IP_BLOCK_TYPE_VCN;
228 break;
229 case AMDGPU_HW_IP_VCN_JPEG:
230 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
231 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
232 break;
233 default:
234 type = AMD_IP_BLOCK_TYPE_NUM;
235 break;
236 }
237
238 return type;
239}
240
241static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
242 struct drm_amdgpu_query_fw *query_fw,
243 struct amdgpu_device *adev)
244{
245 switch (query_fw->fw_type) {
246 case AMDGPU_INFO_FW_VCE:
247 fw_info->ver = adev->vce.fw_version;
248 fw_info->feature = adev->vce.fb_version;
249 break;
250 case AMDGPU_INFO_FW_UVD:
251 fw_info->ver = adev->uvd.fw_version;
252 fw_info->feature = 0;
253 break;
254 case AMDGPU_INFO_FW_VCN:
255 fw_info->ver = adev->vcn.fw_version;
256 fw_info->feature = 0;
257 break;
258 case AMDGPU_INFO_FW_GMC:
259 fw_info->ver = adev->gmc.fw_version;
260 fw_info->feature = 0;
261 break;
262 case AMDGPU_INFO_FW_GFX_ME:
263 fw_info->ver = adev->gfx.me_fw_version;
264 fw_info->feature = adev->gfx.me_feature_version;
265 break;
266 case AMDGPU_INFO_FW_GFX_PFP:
267 fw_info->ver = adev->gfx.pfp_fw_version;
268 fw_info->feature = adev->gfx.pfp_feature_version;
269 break;
270 case AMDGPU_INFO_FW_GFX_CE:
271 fw_info->ver = adev->gfx.ce_fw_version;
272 fw_info->feature = adev->gfx.ce_feature_version;
273 break;
274 case AMDGPU_INFO_FW_GFX_RLC:
275 fw_info->ver = adev->gfx.rlc_fw_version;
276 fw_info->feature = adev->gfx.rlc_feature_version;
277 break;
278 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
279 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
280 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
281 break;
282 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
283 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
284 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
285 break;
286 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
287 fw_info->ver = adev->gfx.rlc_srls_fw_version;
288 fw_info->feature = adev->gfx.rlc_srls_feature_version;
289 break;
290 case AMDGPU_INFO_FW_GFX_RLCP:
291 fw_info->ver = adev->gfx.rlcp_ucode_version;
292 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
293 break;
294 case AMDGPU_INFO_FW_GFX_RLCV:
295 fw_info->ver = adev->gfx.rlcv_ucode_version;
296 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
297 break;
298 case AMDGPU_INFO_FW_GFX_MEC:
299 if (query_fw->index == 0) {
300 fw_info->ver = adev->gfx.mec_fw_version;
301 fw_info->feature = adev->gfx.mec_feature_version;
302 } else if (query_fw->index == 1) {
303 fw_info->ver = adev->gfx.mec2_fw_version;
304 fw_info->feature = adev->gfx.mec2_feature_version;
305 } else
306 return -EINVAL;
307 break;
308 case AMDGPU_INFO_FW_SMC:
309 fw_info->ver = adev->pm.fw_version;
310 fw_info->feature = 0;
311 break;
312 case AMDGPU_INFO_FW_TA:
313 switch (query_fw->index) {
314 case TA_FW_TYPE_PSP_XGMI:
315 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
316 fw_info->feature = adev->psp.xgmi_context.context
317 .bin_desc.feature_version;
318 break;
319 case TA_FW_TYPE_PSP_RAS:
320 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
321 fw_info->feature = adev->psp.ras_context.context
322 .bin_desc.feature_version;
323 break;
324 case TA_FW_TYPE_PSP_HDCP:
325 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
326 fw_info->feature = adev->psp.hdcp_context.context
327 .bin_desc.feature_version;
328 break;
329 case TA_FW_TYPE_PSP_DTM:
330 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
331 fw_info->feature = adev->psp.dtm_context.context
332 .bin_desc.feature_version;
333 break;
334 case TA_FW_TYPE_PSP_RAP:
335 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
336 fw_info->feature = adev->psp.rap_context.context
337 .bin_desc.feature_version;
338 break;
339 case TA_FW_TYPE_PSP_SECUREDISPLAY:
340 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
341 fw_info->feature =
342 adev->psp.securedisplay_context.context.bin_desc
343 .feature_version;
344 break;
345 default:
346 return -EINVAL;
347 }
348 break;
349 case AMDGPU_INFO_FW_SDMA:
350 if (query_fw->index >= adev->sdma.num_instances)
351 return -EINVAL;
352 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
353 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
354 break;
355 case AMDGPU_INFO_FW_SOS:
356 fw_info->ver = adev->psp.sos.fw_version;
357 fw_info->feature = adev->psp.sos.feature_version;
358 break;
359 case AMDGPU_INFO_FW_ASD:
360 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
361 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
362 break;
363 case AMDGPU_INFO_FW_DMCU:
364 fw_info->ver = adev->dm.dmcu_fw_version;
365 fw_info->feature = 0;
366 break;
367 case AMDGPU_INFO_FW_DMCUB:
368 fw_info->ver = adev->dm.dmcub_fw_version;
369 fw_info->feature = 0;
370 break;
371 case AMDGPU_INFO_FW_TOC:
372 fw_info->ver = adev->psp.toc.fw_version;
373 fw_info->feature = adev->psp.toc.feature_version;
374 break;
375 case AMDGPU_INFO_FW_CAP:
376 fw_info->ver = adev->psp.cap_fw_version;
377 fw_info->feature = adev->psp.cap_feature_version;
378 break;
379 case AMDGPU_INFO_FW_MES_KIQ:
380 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
381 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
382 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
383 break;
384 case AMDGPU_INFO_FW_MES:
385 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
386 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
387 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
388 break;
389 case AMDGPU_INFO_FW_IMU:
390 fw_info->ver = adev->gfx.imu_fw_version;
391 fw_info->feature = 0;
392 break;
393 case AMDGPU_INFO_FW_VPE:
394 fw_info->ver = adev->vpe.fw_version;
395 fw_info->feature = adev->vpe.feature_version;
396 break;
397 default:
398 return -EINVAL;
399 }
400 return 0;
401}
402
403static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
404 struct drm_amdgpu_info *info,
405 struct drm_amdgpu_info_hw_ip *result)
406{
407 uint32_t ib_start_alignment = 0;
408 uint32_t ib_size_alignment = 0;
409 enum amd_ip_block_type type;
410 unsigned int num_rings = 0;
411 unsigned int i, j;
412
413 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
414 return -EINVAL;
415
416 switch (info->query_hw_ip.type) {
417 case AMDGPU_HW_IP_GFX:
418 type = AMD_IP_BLOCK_TYPE_GFX;
419 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
420 if (adev->gfx.gfx_ring[i].sched.ready)
421 ++num_rings;
422 ib_start_alignment = 32;
423 ib_size_alignment = 32;
424 break;
425 case AMDGPU_HW_IP_COMPUTE:
426 type = AMD_IP_BLOCK_TYPE_GFX;
427 for (i = 0; i < adev->gfx.num_compute_rings; i++)
428 if (adev->gfx.compute_ring[i].sched.ready)
429 ++num_rings;
430 ib_start_alignment = 32;
431 ib_size_alignment = 32;
432 break;
433 case AMDGPU_HW_IP_DMA:
434 type = AMD_IP_BLOCK_TYPE_SDMA;
435 for (i = 0; i < adev->sdma.num_instances; i++)
436 if (adev->sdma.instance[i].ring.sched.ready)
437 ++num_rings;
438 ib_start_alignment = 256;
439 ib_size_alignment = 4;
440 break;
441 case AMDGPU_HW_IP_UVD:
442 type = AMD_IP_BLOCK_TYPE_UVD;
443 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
444 if (adev->uvd.harvest_config & (1 << i))
445 continue;
446
447 if (adev->uvd.inst[i].ring.sched.ready)
448 ++num_rings;
449 }
450 ib_start_alignment = 256;
451 ib_size_alignment = 64;
452 break;
453 case AMDGPU_HW_IP_VCE:
454 type = AMD_IP_BLOCK_TYPE_VCE;
455 for (i = 0; i < adev->vce.num_rings; i++)
456 if (adev->vce.ring[i].sched.ready)
457 ++num_rings;
458 ib_start_alignment = 256;
459 ib_size_alignment = 4;
460 break;
461 case AMDGPU_HW_IP_UVD_ENC:
462 type = AMD_IP_BLOCK_TYPE_UVD;
463 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
464 if (adev->uvd.harvest_config & (1 << i))
465 continue;
466
467 for (j = 0; j < adev->uvd.num_enc_rings; j++)
468 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
469 ++num_rings;
470 }
471 ib_start_alignment = 256;
472 ib_size_alignment = 4;
473 break;
474 case AMDGPU_HW_IP_VCN_DEC:
475 type = AMD_IP_BLOCK_TYPE_VCN;
476 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
477 if (adev->vcn.harvest_config & (1 << i))
478 continue;
479
480 if (adev->vcn.inst[i].ring_dec.sched.ready)
481 ++num_rings;
482 }
483 ib_start_alignment = 256;
484 ib_size_alignment = 64;
485 break;
486 case AMDGPU_HW_IP_VCN_ENC:
487 type = AMD_IP_BLOCK_TYPE_VCN;
488 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
489 if (adev->vcn.harvest_config & (1 << i))
490 continue;
491
492 for (j = 0; j < adev->vcn.num_enc_rings; j++)
493 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
494 ++num_rings;
495 }
496 ib_start_alignment = 256;
497 ib_size_alignment = 4;
498 break;
499 case AMDGPU_HW_IP_VCN_JPEG:
500 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
501 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
502
503 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
504 if (adev->jpeg.harvest_config & (1 << i))
505 continue;
506
507 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++)
508 if (adev->jpeg.inst[i].ring_dec[j].sched.ready)
509 ++num_rings;
510 }
511 ib_start_alignment = 256;
512 ib_size_alignment = 64;
513 break;
514 case AMDGPU_HW_IP_VPE:
515 type = AMD_IP_BLOCK_TYPE_VPE;
516 if (adev->vpe.ring.sched.ready)
517 ++num_rings;
518 ib_start_alignment = 256;
519 ib_size_alignment = 4;
520 break;
521 default:
522 return -EINVAL;
523 }
524
525 for (i = 0; i < adev->num_ip_blocks; i++)
526 if (adev->ip_blocks[i].version->type == type &&
527 adev->ip_blocks[i].status.valid)
528 break;
529
530 if (i == adev->num_ip_blocks)
531 return 0;
532
533 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
534 num_rings);
535
536 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
537 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
538
539 if (adev->asic_type >= CHIP_VEGA10) {
540 switch (type) {
541 case AMD_IP_BLOCK_TYPE_GFX:
542 result->ip_discovery_version =
543 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, GC_HWIP, 0));
544 break;
545 case AMD_IP_BLOCK_TYPE_SDMA:
546 result->ip_discovery_version =
547 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0));
548 break;
549 case AMD_IP_BLOCK_TYPE_UVD:
550 case AMD_IP_BLOCK_TYPE_VCN:
551 case AMD_IP_BLOCK_TYPE_JPEG:
552 result->ip_discovery_version =
553 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, UVD_HWIP, 0));
554 break;
555 case AMD_IP_BLOCK_TYPE_VCE:
556 result->ip_discovery_version =
557 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VCE_HWIP, 0));
558 break;
559 case AMD_IP_BLOCK_TYPE_VPE:
560 result->ip_discovery_version =
561 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, VPE_HWIP, 0));
562 break;
563 default:
564 result->ip_discovery_version = 0;
565 break;
566 }
567 } else {
568 result->ip_discovery_version = 0;
569 }
570 result->capabilities_flags = 0;
571 result->available_rings = (1 << num_rings) - 1;
572 result->ib_start_alignment = ib_start_alignment;
573 result->ib_size_alignment = ib_size_alignment;
574 return 0;
575}
576
577/*
578 * Userspace get information ioctl
579 */
580/**
581 * amdgpu_info_ioctl - answer a device specific request.
582 *
583 * @dev: drm device pointer
584 * @data: request object
585 * @filp: drm filp
586 *
587 * This function is used to pass device specific parameters to the userspace
588 * drivers. Examples include: pci device id, pipeline parms, tiling params,
589 * etc. (all asics).
590 * Returns 0 on success, -EINVAL on failure.
591 */
592int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
593{
594 struct amdgpu_device *adev = drm_to_adev(dev);
595 struct drm_amdgpu_info *info = data;
596 struct amdgpu_mode_info *minfo = &adev->mode_info;
597 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
598 struct amdgpu_fpriv *fpriv;
599 struct amdgpu_ip_block *ip_block;
600 enum amd_ip_block_type type;
601 struct amdgpu_xcp *xcp;
602 u32 count, inst_mask;
603 uint32_t size = info->return_size;
604 struct drm_crtc *crtc;
605 uint32_t ui32 = 0;
606 uint64_t ui64 = 0;
607 int i, found, ret;
608 int ui32_size = sizeof(ui32);
609
610 if (!info->return_size || !info->return_pointer)
611 return -EINVAL;
612
613 switch (info->query) {
614 case AMDGPU_INFO_ACCEL_WORKING:
615 ui32 = adev->accel_working;
616 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
617 case AMDGPU_INFO_CRTC_FROM_ID:
618 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
619 crtc = (struct drm_crtc *)minfo->crtcs[i];
620 if (crtc && crtc->base.id == info->mode_crtc.id) {
621 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
622
623 ui32 = amdgpu_crtc->crtc_id;
624 found = 1;
625 break;
626 }
627 }
628 if (!found) {
629 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
630 return -EINVAL;
631 }
632 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
633 case AMDGPU_INFO_HW_IP_INFO: {
634 struct drm_amdgpu_info_hw_ip ip = {};
635
636 ret = amdgpu_hw_ip_info(adev, info, &ip);
637 if (ret)
638 return ret;
639
640 ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
641 return ret ? -EFAULT : 0;
642 }
643 case AMDGPU_INFO_HW_IP_COUNT: {
644 fpriv = (struct amdgpu_fpriv *)filp->driver_priv;
645 type = amdgpu_ip_get_block_type(adev, info->query_hw_ip.type);
646 ip_block = amdgpu_device_ip_get_ip_block(adev, type);
647
648 if (!ip_block || !ip_block->status.valid)
649 return -EINVAL;
650
651 if (adev->xcp_mgr && adev->xcp_mgr->num_xcps > 0 &&
652 fpriv->xcp_id >= 0 && fpriv->xcp_id < adev->xcp_mgr->num_xcps) {
653 xcp = &adev->xcp_mgr->xcp[fpriv->xcp_id];
654 switch (type) {
655 case AMD_IP_BLOCK_TYPE_GFX:
656 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
657 count = hweight32(inst_mask);
658 break;
659 case AMD_IP_BLOCK_TYPE_SDMA:
660 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_SDMA, &inst_mask);
661 count = hweight32(inst_mask);
662 break;
663 case AMD_IP_BLOCK_TYPE_JPEG:
664 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
665 count = hweight32(inst_mask) * adev->jpeg.num_jpeg_rings;
666 break;
667 case AMD_IP_BLOCK_TYPE_VCN:
668 ret = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
669 count = hweight32(inst_mask);
670 break;
671 default:
672 return -EINVAL;
673 }
674 if (ret)
675 return ret;
676 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
677 }
678
679 switch (type) {
680 case AMD_IP_BLOCK_TYPE_GFX:
681 case AMD_IP_BLOCK_TYPE_VCE:
682 count = 1;
683 break;
684 case AMD_IP_BLOCK_TYPE_SDMA:
685 count = adev->sdma.num_instances;
686 break;
687 case AMD_IP_BLOCK_TYPE_JPEG:
688 count = adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings;
689 break;
690 case AMD_IP_BLOCK_TYPE_VCN:
691 count = adev->vcn.num_vcn_inst;
692 break;
693 case AMD_IP_BLOCK_TYPE_UVD:
694 count = adev->uvd.num_uvd_inst;
695 break;
696 /* For all other IP block types not listed in the switch statement
697 * the ip status is valid here and the instance count is one.
698 */
699 default:
700 count = 1;
701 break;
702 }
703
704 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
705 }
706 case AMDGPU_INFO_TIMESTAMP:
707 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
708 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
709 case AMDGPU_INFO_FW_VERSION: {
710 struct drm_amdgpu_info_firmware fw_info;
711
712 /* We only support one instance of each IP block right now. */
713 if (info->query_fw.ip_instance != 0)
714 return -EINVAL;
715
716 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
717 if (ret)
718 return ret;
719
720 return copy_to_user(out, &fw_info,
721 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
722 }
723 case AMDGPU_INFO_NUM_BYTES_MOVED:
724 ui64 = atomic64_read(&adev->num_bytes_moved);
725 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
726 case AMDGPU_INFO_NUM_EVICTIONS:
727 ui64 = atomic64_read(&adev->num_evictions);
728 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
729 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
730 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
731 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
732 case AMDGPU_INFO_VRAM_USAGE:
733 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
734 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
735 case AMDGPU_INFO_VIS_VRAM_USAGE:
736 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
737 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
738 case AMDGPU_INFO_GTT_USAGE:
739 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
740 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
741 case AMDGPU_INFO_GDS_CONFIG: {
742 struct drm_amdgpu_info_gds gds_info;
743
744 memset(&gds_info, 0, sizeof(gds_info));
745 gds_info.compute_partition_size = adev->gds.gds_size;
746 gds_info.gds_total_size = adev->gds.gds_size;
747 gds_info.gws_per_compute_partition = adev->gds.gws_size;
748 gds_info.oa_per_compute_partition = adev->gds.oa_size;
749 return copy_to_user(out, &gds_info,
750 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
751 }
752 case AMDGPU_INFO_VRAM_GTT: {
753 struct drm_amdgpu_info_vram_gtt vram_gtt;
754
755 vram_gtt.vram_size = adev->gmc.real_vram_size -
756 atomic64_read(&adev->vram_pin_size) -
757 AMDGPU_VM_RESERVED_VRAM;
758 vram_gtt.vram_cpu_accessible_size =
759 min(adev->gmc.visible_vram_size -
760 atomic64_read(&adev->visible_pin_size),
761 vram_gtt.vram_size);
762 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
763 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
764 return copy_to_user(out, &vram_gtt,
765 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
766 }
767 case AMDGPU_INFO_MEMORY: {
768 struct drm_amdgpu_memory_info mem;
769 struct ttm_resource_manager *gtt_man =
770 &adev->mman.gtt_mgr.manager;
771 struct ttm_resource_manager *vram_man =
772 &adev->mman.vram_mgr.manager;
773
774 memset(&mem, 0, sizeof(mem));
775 mem.vram.total_heap_size = adev->gmc.real_vram_size;
776 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
777 atomic64_read(&adev->vram_pin_size) -
778 AMDGPU_VM_RESERVED_VRAM;
779 mem.vram.heap_usage =
780 ttm_resource_manager_usage(vram_man);
781 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
782
783 mem.cpu_accessible_vram.total_heap_size =
784 adev->gmc.visible_vram_size;
785 mem.cpu_accessible_vram.usable_heap_size =
786 min(adev->gmc.visible_vram_size -
787 atomic64_read(&adev->visible_pin_size),
788 mem.vram.usable_heap_size);
789 mem.cpu_accessible_vram.heap_usage =
790 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
791 mem.cpu_accessible_vram.max_allocation =
792 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
793
794 mem.gtt.total_heap_size = gtt_man->size;
795 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
796 atomic64_read(&adev->gart_pin_size);
797 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
798 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
799
800 return copy_to_user(out, &mem,
801 min((size_t)size, sizeof(mem)))
802 ? -EFAULT : 0;
803 }
804 case AMDGPU_INFO_READ_MMR_REG: {
805 unsigned int n, alloc_size;
806 uint32_t *regs;
807 unsigned int se_num = (info->read_mmr_reg.instance >>
808 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
809 AMDGPU_INFO_MMR_SE_INDEX_MASK;
810 unsigned int sh_num = (info->read_mmr_reg.instance >>
811 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
812 AMDGPU_INFO_MMR_SH_INDEX_MASK;
813
814 /* set full masks if the userspace set all bits
815 * in the bitfields
816 */
817 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
818 se_num = 0xffffffff;
819 else if (se_num >= AMDGPU_GFX_MAX_SE)
820 return -EINVAL;
821 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
822 sh_num = 0xffffffff;
823 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
824 return -EINVAL;
825
826 if (info->read_mmr_reg.count > 128)
827 return -EINVAL;
828
829 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
830 if (!regs)
831 return -ENOMEM;
832 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
833
834 amdgpu_gfx_off_ctrl(adev, false);
835 for (i = 0; i < info->read_mmr_reg.count; i++) {
836 if (amdgpu_asic_read_register(adev, se_num, sh_num,
837 info->read_mmr_reg.dword_offset + i,
838 ®s[i])) {
839 DRM_DEBUG_KMS("unallowed offset %#x\n",
840 info->read_mmr_reg.dword_offset + i);
841 kfree(regs);
842 amdgpu_gfx_off_ctrl(adev, true);
843 return -EFAULT;
844 }
845 }
846 amdgpu_gfx_off_ctrl(adev, true);
847 n = copy_to_user(out, regs, min(size, alloc_size));
848 kfree(regs);
849 return n ? -EFAULT : 0;
850 }
851 case AMDGPU_INFO_DEV_INFO: {
852 struct drm_amdgpu_info_device *dev_info;
853 uint64_t vm_size;
854 uint32_t pcie_gen_mask;
855
856 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
857 if (!dev_info)
858 return -ENOMEM;
859
860 dev_info->device_id = adev->pdev->device;
861 dev_info->chip_rev = adev->rev_id;
862 dev_info->external_rev = adev->external_rev_id;
863 dev_info->pci_rev = adev->pdev->revision;
864 dev_info->family = adev->family;
865 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
866 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
867 /* return all clocks in KHz */
868 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
869 if (adev->pm.dpm_enabled) {
870 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
871 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
872 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
873 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
874 } else {
875 dev_info->max_engine_clock =
876 dev_info->min_engine_clock =
877 adev->clock.default_sclk * 10;
878 dev_info->max_memory_clock =
879 dev_info->min_memory_clock =
880 adev->clock.default_mclk * 10;
881 }
882 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
883 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
884 adev->gfx.config.max_shader_engines;
885 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
886 dev_info->ids_flags = 0;
887 if (adev->flags & AMD_IS_APU)
888 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
889 if (adev->gfx.mcbp)
890 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
891 if (amdgpu_is_tmz(adev))
892 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
893 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
894 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
895
896 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
897 vm_size -= AMDGPU_VA_RESERVED_SIZE;
898
899 /* Older VCE FW versions are buggy and can handle only 40bits */
900 if (adev->vce.fw_version &&
901 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
902 vm_size = min(vm_size, 1ULL << 40);
903
904 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
905 dev_info->virtual_address_max =
906 min(vm_size, AMDGPU_GMC_HOLE_START);
907
908 if (vm_size > AMDGPU_GMC_HOLE_START) {
909 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
910 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
911 }
912 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
913 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
914 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
915 dev_info->cu_active_number = adev->gfx.cu_info.number;
916 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
917 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
918 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
919 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
920 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
921 sizeof(dev_info->cu_bitmap));
922 dev_info->vram_type = adev->gmc.vram_type;
923 dev_info->vram_bit_width = adev->gmc.vram_width;
924 dev_info->vce_harvest_config = adev->vce.harvest_config;
925 dev_info->gc_double_offchip_lds_buf =
926 adev->gfx.config.double_offchip_lds_buf;
927 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
928 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
929 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
930 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
931 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
932 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
933 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
934
935 if (adev->family >= AMDGPU_FAMILY_NV)
936 dev_info->pa_sc_tile_steering_override =
937 adev->gfx.config.pa_sc_tile_steering_override;
938
939 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
940
941 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
942 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
943 dev_info->pcie_gen = fls(pcie_gen_mask);
944 dev_info->pcie_num_lanes =
945 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
946 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
947 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
948 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
949 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
950 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
951
952 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
953 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
954 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
955 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
956 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
957 adev->gfx.config.gc_gl1c_per_sa;
958 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
959 dev_info->mall_size = adev->gmc.mall_size;
960
961
962 if (adev->gfx.funcs->get_gfx_shadow_info) {
963 struct amdgpu_gfx_shadow_info shadow_info;
964
965 ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info);
966 if (!ret) {
967 dev_info->shadow_size = shadow_info.shadow_size;
968 dev_info->shadow_alignment = shadow_info.shadow_alignment;
969 dev_info->csa_size = shadow_info.csa_size;
970 dev_info->csa_alignment = shadow_info.csa_alignment;
971 }
972 }
973
974 ret = copy_to_user(out, dev_info,
975 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
976 kfree(dev_info);
977 return ret;
978 }
979 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
980 unsigned int i;
981 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
982 struct amd_vce_state *vce_state;
983
984 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
985 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
986 if (vce_state) {
987 vce_clk_table.entries[i].sclk = vce_state->sclk;
988 vce_clk_table.entries[i].mclk = vce_state->mclk;
989 vce_clk_table.entries[i].eclk = vce_state->evclk;
990 vce_clk_table.num_valid_entries++;
991 }
992 }
993
994 return copy_to_user(out, &vce_clk_table,
995 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
996 }
997 case AMDGPU_INFO_VBIOS: {
998 uint32_t bios_size = adev->bios_size;
999
1000 switch (info->vbios_info.type) {
1001 case AMDGPU_INFO_VBIOS_SIZE:
1002 return copy_to_user(out, &bios_size,
1003 min((size_t)size, sizeof(bios_size)))
1004 ? -EFAULT : 0;
1005 case AMDGPU_INFO_VBIOS_IMAGE: {
1006 uint8_t *bios;
1007 uint32_t bios_offset = info->vbios_info.offset;
1008
1009 if (bios_offset >= bios_size)
1010 return -EINVAL;
1011
1012 bios = adev->bios + bios_offset;
1013 return copy_to_user(out, bios,
1014 min((size_t)size, (size_t)(bios_size - bios_offset)))
1015 ? -EFAULT : 0;
1016 }
1017 case AMDGPU_INFO_VBIOS_INFO: {
1018 struct drm_amdgpu_info_vbios vbios_info = {};
1019 struct atom_context *atom_context;
1020
1021 atom_context = adev->mode_info.atom_context;
1022 if (atom_context) {
1023 memcpy(vbios_info.name, atom_context->name,
1024 sizeof(atom_context->name));
1025 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn,
1026 sizeof(atom_context->vbios_pn));
1027 vbios_info.version = atom_context->version;
1028 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
1029 sizeof(atom_context->vbios_ver_str));
1030 memcpy(vbios_info.date, atom_context->date,
1031 sizeof(atom_context->date));
1032 }
1033
1034 return copy_to_user(out, &vbios_info,
1035 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
1036 }
1037 default:
1038 DRM_DEBUG_KMS("Invalid request %d\n",
1039 info->vbios_info.type);
1040 return -EINVAL;
1041 }
1042 }
1043 case AMDGPU_INFO_NUM_HANDLES: {
1044 struct drm_amdgpu_info_num_handles handle;
1045
1046 switch (info->query_hw_ip.type) {
1047 case AMDGPU_HW_IP_UVD:
1048 /* Starting Polaris, we support unlimited UVD handles */
1049 if (adev->asic_type < CHIP_POLARIS10) {
1050 handle.uvd_max_handles = adev->uvd.max_handles;
1051 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
1052
1053 return copy_to_user(out, &handle,
1054 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
1055 } else {
1056 return -ENODATA;
1057 }
1058
1059 break;
1060 default:
1061 return -EINVAL;
1062 }
1063 }
1064 case AMDGPU_INFO_SENSOR: {
1065 if (!adev->pm.dpm_enabled)
1066 return -ENOENT;
1067
1068 switch (info->sensor_info.type) {
1069 case AMDGPU_INFO_SENSOR_GFX_SCLK:
1070 /* get sclk in Mhz */
1071 if (amdgpu_dpm_read_sensor(adev,
1072 AMDGPU_PP_SENSOR_GFX_SCLK,
1073 (void *)&ui32, &ui32_size)) {
1074 return -EINVAL;
1075 }
1076 ui32 /= 100;
1077 break;
1078 case AMDGPU_INFO_SENSOR_GFX_MCLK:
1079 /* get mclk in Mhz */
1080 if (amdgpu_dpm_read_sensor(adev,
1081 AMDGPU_PP_SENSOR_GFX_MCLK,
1082 (void *)&ui32, &ui32_size)) {
1083 return -EINVAL;
1084 }
1085 ui32 /= 100;
1086 break;
1087 case AMDGPU_INFO_SENSOR_GPU_TEMP:
1088 /* get temperature in millidegrees C */
1089 if (amdgpu_dpm_read_sensor(adev,
1090 AMDGPU_PP_SENSOR_GPU_TEMP,
1091 (void *)&ui32, &ui32_size)) {
1092 return -EINVAL;
1093 }
1094 break;
1095 case AMDGPU_INFO_SENSOR_GPU_LOAD:
1096 /* get GPU load */
1097 if (amdgpu_dpm_read_sensor(adev,
1098 AMDGPU_PP_SENSOR_GPU_LOAD,
1099 (void *)&ui32, &ui32_size)) {
1100 return -EINVAL;
1101 }
1102 break;
1103 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1104 /* get average GPU power */
1105 if (amdgpu_dpm_read_sensor(adev,
1106 AMDGPU_PP_SENSOR_GPU_AVG_POWER,
1107 (void *)&ui32, &ui32_size)) {
1108 /* fall back to input power for backwards compat */
1109 if (amdgpu_dpm_read_sensor(adev,
1110 AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
1111 (void *)&ui32, &ui32_size)) {
1112 return -EINVAL;
1113 }
1114 }
1115 ui32 >>= 8;
1116 break;
1117 case AMDGPU_INFO_SENSOR_VDDNB:
1118 /* get VDDNB in millivolts */
1119 if (amdgpu_dpm_read_sensor(adev,
1120 AMDGPU_PP_SENSOR_VDDNB,
1121 (void *)&ui32, &ui32_size)) {
1122 return -EINVAL;
1123 }
1124 break;
1125 case AMDGPU_INFO_SENSOR_VDDGFX:
1126 /* get VDDGFX in millivolts */
1127 if (amdgpu_dpm_read_sensor(adev,
1128 AMDGPU_PP_SENSOR_VDDGFX,
1129 (void *)&ui32, &ui32_size)) {
1130 return -EINVAL;
1131 }
1132 break;
1133 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1134 /* get stable pstate sclk in Mhz */
1135 if (amdgpu_dpm_read_sensor(adev,
1136 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1137 (void *)&ui32, &ui32_size)) {
1138 return -EINVAL;
1139 }
1140 ui32 /= 100;
1141 break;
1142 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1143 /* get stable pstate mclk in Mhz */
1144 if (amdgpu_dpm_read_sensor(adev,
1145 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1146 (void *)&ui32, &ui32_size)) {
1147 return -EINVAL;
1148 }
1149 ui32 /= 100;
1150 break;
1151 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1152 /* get peak pstate sclk in Mhz */
1153 if (amdgpu_dpm_read_sensor(adev,
1154 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1155 (void *)&ui32, &ui32_size)) {
1156 return -EINVAL;
1157 }
1158 ui32 /= 100;
1159 break;
1160 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1161 /* get peak pstate mclk in Mhz */
1162 if (amdgpu_dpm_read_sensor(adev,
1163 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1164 (void *)&ui32, &ui32_size)) {
1165 return -EINVAL;
1166 }
1167 ui32 /= 100;
1168 break;
1169 default:
1170 DRM_DEBUG_KMS("Invalid request %d\n",
1171 info->sensor_info.type);
1172 return -EINVAL;
1173 }
1174 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1175 }
1176 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1177 ui32 = atomic_read(&adev->vram_lost_counter);
1178 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1179 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1180 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1181 uint64_t ras_mask;
1182
1183 if (!ras)
1184 return -EINVAL;
1185 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1186
1187 return copy_to_user(out, &ras_mask,
1188 min_t(u64, size, sizeof(ras_mask))) ?
1189 -EFAULT : 0;
1190 }
1191 case AMDGPU_INFO_VIDEO_CAPS: {
1192 const struct amdgpu_video_codecs *codecs;
1193 struct drm_amdgpu_info_video_caps *caps;
1194 int r;
1195
1196 if (!adev->asic_funcs->query_video_codecs)
1197 return -EINVAL;
1198
1199 switch (info->video_cap.type) {
1200 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1201 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1202 if (r)
1203 return -EINVAL;
1204 break;
1205 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1206 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1207 if (r)
1208 return -EINVAL;
1209 break;
1210 default:
1211 DRM_DEBUG_KMS("Invalid request %d\n",
1212 info->video_cap.type);
1213 return -EINVAL;
1214 }
1215
1216 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1217 if (!caps)
1218 return -ENOMEM;
1219
1220 for (i = 0; i < codecs->codec_count; i++) {
1221 int idx = codecs->codec_array[i].codec_type;
1222
1223 switch (idx) {
1224 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1225 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1226 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1227 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1228 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1229 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1230 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1231 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1232 caps->codec_info[idx].valid = 1;
1233 caps->codec_info[idx].max_width =
1234 codecs->codec_array[i].max_width;
1235 caps->codec_info[idx].max_height =
1236 codecs->codec_array[i].max_height;
1237 caps->codec_info[idx].max_pixels_per_frame =
1238 codecs->codec_array[i].max_pixels_per_frame;
1239 caps->codec_info[idx].max_level =
1240 codecs->codec_array[i].max_level;
1241 break;
1242 default:
1243 break;
1244 }
1245 }
1246 r = copy_to_user(out, caps,
1247 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1248 kfree(caps);
1249 return r;
1250 }
1251 case AMDGPU_INFO_MAX_IBS: {
1252 uint32_t max_ibs[AMDGPU_HW_IP_NUM];
1253
1254 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i)
1255 max_ibs[i] = amdgpu_ring_max_ibs(i);
1256
1257 return copy_to_user(out, max_ibs,
1258 min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0;
1259 }
1260 case AMDGPU_INFO_GPUVM_FAULT: {
1261 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1262 struct amdgpu_vm *vm = &fpriv->vm;
1263 struct drm_amdgpu_info_gpuvm_fault gpuvm_fault;
1264 unsigned long flags;
1265
1266 if (!vm)
1267 return -EINVAL;
1268
1269 memset(&gpuvm_fault, 0, sizeof(gpuvm_fault));
1270
1271 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
1272 gpuvm_fault.addr = vm->fault_info.addr;
1273 gpuvm_fault.status = vm->fault_info.status;
1274 gpuvm_fault.vmhub = vm->fault_info.vmhub;
1275 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
1276
1277 return copy_to_user(out, &gpuvm_fault,
1278 min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0;
1279 }
1280 default:
1281 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1282 return -EINVAL;
1283 }
1284 return 0;
1285}
1286
1287
1288/*
1289 * Outdated mess for old drm with Xorg being in charge (void function now).
1290 */
1291/**
1292 * amdgpu_driver_lastclose_kms - drm callback for last close
1293 *
1294 * @dev: drm dev pointer
1295 *
1296 * Switch vga_switcheroo state after last close (all asics).
1297 */
1298void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1299{
1300 drm_fb_helper_lastclose(dev);
1301 vga_switcheroo_process_delayed_switch();
1302}
1303
1304/**
1305 * amdgpu_driver_open_kms - drm callback for open
1306 *
1307 * @dev: drm dev pointer
1308 * @file_priv: drm file
1309 *
1310 * On device open, init vm on cayman+ (all asics).
1311 * Returns 0 on success, error on failure.
1312 */
1313int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1314{
1315 struct amdgpu_device *adev = drm_to_adev(dev);
1316 struct amdgpu_fpriv *fpriv;
1317 int r, pasid;
1318
1319 /* Ensure IB tests are run on ring */
1320 flush_delayed_work(&adev->delayed_init_work);
1321
1322
1323 if (amdgpu_ras_intr_triggered()) {
1324 DRM_ERROR("RAS Intr triggered, device disabled!!");
1325 return -EHWPOISON;
1326 }
1327
1328 file_priv->driver_priv = NULL;
1329
1330 r = pm_runtime_get_sync(dev->dev);
1331 if (r < 0)
1332 goto pm_put;
1333
1334 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1335 if (unlikely(!fpriv)) {
1336 r = -ENOMEM;
1337 goto out_suspend;
1338 }
1339
1340 pasid = amdgpu_pasid_alloc(16);
1341 if (pasid < 0) {
1342 dev_warn(adev->dev, "No more PASIDs available!");
1343 pasid = 0;
1344 }
1345
1346 r = amdgpu_xcp_open_device(adev, fpriv, file_priv);
1347 if (r)
1348 goto error_pasid;
1349
1350 r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id);
1351 if (r)
1352 goto error_pasid;
1353
1354 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1355 if (r)
1356 goto error_vm;
1357
1358 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1359 if (!fpriv->prt_va) {
1360 r = -ENOMEM;
1361 goto error_vm;
1362 }
1363
1364 if (adev->gfx.mcbp) {
1365 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1366
1367 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1368 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1369 if (r)
1370 goto error_vm;
1371 }
1372
1373 mutex_init(&fpriv->bo_list_lock);
1374 idr_init_base(&fpriv->bo_list_handles, 1);
1375
1376 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1377
1378 file_priv->driver_priv = fpriv;
1379 goto out_suspend;
1380
1381error_vm:
1382 amdgpu_vm_fini(adev, &fpriv->vm);
1383
1384error_pasid:
1385 if (pasid) {
1386 amdgpu_pasid_free(pasid);
1387 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1388 }
1389
1390 kfree(fpriv);
1391
1392out_suspend:
1393 pm_runtime_mark_last_busy(dev->dev);
1394pm_put:
1395 pm_runtime_put_autosuspend(dev->dev);
1396
1397 return r;
1398}
1399
1400/**
1401 * amdgpu_driver_postclose_kms - drm callback for post close
1402 *
1403 * @dev: drm dev pointer
1404 * @file_priv: drm file
1405 *
1406 * On device post close, tear down vm on cayman+ (all asics).
1407 */
1408void amdgpu_driver_postclose_kms(struct drm_device *dev,
1409 struct drm_file *file_priv)
1410{
1411 struct amdgpu_device *adev = drm_to_adev(dev);
1412 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1413 struct amdgpu_bo_list *list;
1414 struct amdgpu_bo *pd;
1415 u32 pasid;
1416 int handle;
1417
1418 if (!fpriv)
1419 return;
1420
1421 pm_runtime_get_sync(dev->dev);
1422
1423 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1424 amdgpu_uvd_free_handles(adev, file_priv);
1425 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1426 amdgpu_vce_free_handles(adev, file_priv);
1427
1428 if (fpriv->csa_va) {
1429 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1430
1431 WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1432 fpriv->csa_va, csa_addr));
1433 fpriv->csa_va = NULL;
1434 }
1435
1436 amdgpu_seq64_unmap(adev, fpriv);
1437
1438 pasid = fpriv->vm.pasid;
1439 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1440 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1441 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1442 amdgpu_bo_unreserve(pd);
1443 }
1444
1445 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1446 amdgpu_vm_fini(adev, &fpriv->vm);
1447
1448 if (pasid)
1449 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1450 amdgpu_bo_unref(&pd);
1451
1452 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1453 amdgpu_bo_list_put(list);
1454
1455 idr_destroy(&fpriv->bo_list_handles);
1456 mutex_destroy(&fpriv->bo_list_lock);
1457
1458 kfree(fpriv);
1459 file_priv->driver_priv = NULL;
1460
1461 pm_runtime_mark_last_busy(dev->dev);
1462 pm_runtime_put_autosuspend(dev->dev);
1463}
1464
1465
1466void amdgpu_driver_release_kms(struct drm_device *dev)
1467{
1468 struct amdgpu_device *adev = drm_to_adev(dev);
1469
1470 amdgpu_device_fini_sw(adev);
1471 pci_set_drvdata(adev->pdev, NULL);
1472}
1473
1474/*
1475 * VBlank related functions.
1476 */
1477/**
1478 * amdgpu_get_vblank_counter_kms - get frame count
1479 *
1480 * @crtc: crtc to get the frame count from
1481 *
1482 * Gets the frame count on the requested crtc (all asics).
1483 * Returns frame count on success, -EINVAL on failure.
1484 */
1485u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1486{
1487 struct drm_device *dev = crtc->dev;
1488 unsigned int pipe = crtc->index;
1489 struct amdgpu_device *adev = drm_to_adev(dev);
1490 int vpos, hpos, stat;
1491 u32 count;
1492
1493 if (pipe >= adev->mode_info.num_crtc) {
1494 DRM_ERROR("Invalid crtc %u\n", pipe);
1495 return -EINVAL;
1496 }
1497
1498 /* The hw increments its frame counter at start of vsync, not at start
1499 * of vblank, as is required by DRM core vblank counter handling.
1500 * Cook the hw count here to make it appear to the caller as if it
1501 * incremented at start of vblank. We measure distance to start of
1502 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1503 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1504 * result by 1 to give the proper appearance to caller.
1505 */
1506 if (adev->mode_info.crtcs[pipe]) {
1507 /* Repeat readout if needed to provide stable result if
1508 * we cross start of vsync during the queries.
1509 */
1510 do {
1511 count = amdgpu_display_vblank_get_counter(adev, pipe);
1512 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1513 * vpos as distance to start of vblank, instead of
1514 * regular vertical scanout pos.
1515 */
1516 stat = amdgpu_display_get_crtc_scanoutpos(
1517 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1518 &vpos, &hpos, NULL, NULL,
1519 &adev->mode_info.crtcs[pipe]->base.hwmode);
1520 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1521
1522 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1523 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1524 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1525 } else {
1526 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1527 pipe, vpos);
1528
1529 /* Bump counter if we are at >= leading edge of vblank,
1530 * but before vsync where vpos would turn negative and
1531 * the hw counter really increments.
1532 */
1533 if (vpos >= 0)
1534 count++;
1535 }
1536 } else {
1537 /* Fallback to use value as is. */
1538 count = amdgpu_display_vblank_get_counter(adev, pipe);
1539 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1540 }
1541
1542 return count;
1543}
1544
1545/**
1546 * amdgpu_enable_vblank_kms - enable vblank interrupt
1547 *
1548 * @crtc: crtc to enable vblank interrupt for
1549 *
1550 * Enable the interrupt on the requested crtc (all asics).
1551 * Returns 0 on success, -EINVAL on failure.
1552 */
1553int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1554{
1555 struct drm_device *dev = crtc->dev;
1556 unsigned int pipe = crtc->index;
1557 struct amdgpu_device *adev = drm_to_adev(dev);
1558 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1559
1560 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1561}
1562
1563/**
1564 * amdgpu_disable_vblank_kms - disable vblank interrupt
1565 *
1566 * @crtc: crtc to disable vblank interrupt for
1567 *
1568 * Disable the interrupt on the requested crtc (all asics).
1569 */
1570void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1571{
1572 struct drm_device *dev = crtc->dev;
1573 unsigned int pipe = crtc->index;
1574 struct amdgpu_device *adev = drm_to_adev(dev);
1575 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1576
1577 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1578}
1579
1580/*
1581 * Debugfs info
1582 */
1583#if defined(CONFIG_DEBUG_FS)
1584
1585static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1586{
1587 struct amdgpu_device *adev = m->private;
1588 struct drm_amdgpu_info_firmware fw_info;
1589 struct drm_amdgpu_query_fw query_fw;
1590 struct atom_context *ctx = adev->mode_info.atom_context;
1591 uint8_t smu_program, smu_major, smu_minor, smu_debug;
1592 int ret, i;
1593
1594 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1595#define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type
1596 TA_FW_NAME(XGMI),
1597 TA_FW_NAME(RAS),
1598 TA_FW_NAME(HDCP),
1599 TA_FW_NAME(DTM),
1600 TA_FW_NAME(RAP),
1601 TA_FW_NAME(SECUREDISPLAY),
1602#undef TA_FW_NAME
1603 };
1604
1605 /* VCE */
1606 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1607 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1608 if (ret)
1609 return ret;
1610 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1611 fw_info.feature, fw_info.ver);
1612
1613 /* UVD */
1614 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1615 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1616 if (ret)
1617 return ret;
1618 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1619 fw_info.feature, fw_info.ver);
1620
1621 /* GMC */
1622 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1623 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1624 if (ret)
1625 return ret;
1626 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1627 fw_info.feature, fw_info.ver);
1628
1629 /* ME */
1630 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1631 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1632 if (ret)
1633 return ret;
1634 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1635 fw_info.feature, fw_info.ver);
1636
1637 /* PFP */
1638 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1639 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1640 if (ret)
1641 return ret;
1642 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1643 fw_info.feature, fw_info.ver);
1644
1645 /* CE */
1646 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1647 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1648 if (ret)
1649 return ret;
1650 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1651 fw_info.feature, fw_info.ver);
1652
1653 /* RLC */
1654 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1655 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1656 if (ret)
1657 return ret;
1658 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1659 fw_info.feature, fw_info.ver);
1660
1661 /* RLC SAVE RESTORE LIST CNTL */
1662 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1663 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1664 if (ret)
1665 return ret;
1666 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1667 fw_info.feature, fw_info.ver);
1668
1669 /* RLC SAVE RESTORE LIST GPM MEM */
1670 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1671 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1672 if (ret)
1673 return ret;
1674 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1675 fw_info.feature, fw_info.ver);
1676
1677 /* RLC SAVE RESTORE LIST SRM MEM */
1678 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1679 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1680 if (ret)
1681 return ret;
1682 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1683 fw_info.feature, fw_info.ver);
1684
1685 /* RLCP */
1686 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1687 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1688 if (ret)
1689 return ret;
1690 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1691 fw_info.feature, fw_info.ver);
1692
1693 /* RLCV */
1694 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1695 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1696 if (ret)
1697 return ret;
1698 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1699 fw_info.feature, fw_info.ver);
1700
1701 /* MEC */
1702 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1703 query_fw.index = 0;
1704 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1705 if (ret)
1706 return ret;
1707 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1708 fw_info.feature, fw_info.ver);
1709
1710 /* MEC2 */
1711 if (adev->gfx.mec2_fw) {
1712 query_fw.index = 1;
1713 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1714 if (ret)
1715 return ret;
1716 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1717 fw_info.feature, fw_info.ver);
1718 }
1719
1720 /* IMU */
1721 query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1722 query_fw.index = 0;
1723 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1724 if (ret)
1725 return ret;
1726 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1727 fw_info.feature, fw_info.ver);
1728
1729 /* PSP SOS */
1730 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1731 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1732 if (ret)
1733 return ret;
1734 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1735 fw_info.feature, fw_info.ver);
1736
1737
1738 /* PSP ASD */
1739 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1740 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1741 if (ret)
1742 return ret;
1743 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1744 fw_info.feature, fw_info.ver);
1745
1746 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1747 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1748 query_fw.index = i;
1749 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1750 if (ret)
1751 continue;
1752
1753 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1754 ta_fw_name[i], fw_info.feature, fw_info.ver);
1755 }
1756
1757 /* SMC */
1758 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1759 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1760 if (ret)
1761 return ret;
1762 smu_program = (fw_info.ver >> 24) & 0xff;
1763 smu_major = (fw_info.ver >> 16) & 0xff;
1764 smu_minor = (fw_info.ver >> 8) & 0xff;
1765 smu_debug = (fw_info.ver >> 0) & 0xff;
1766 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1767 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1768
1769 /* SDMA */
1770 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1771 for (i = 0; i < adev->sdma.num_instances; i++) {
1772 query_fw.index = i;
1773 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1774 if (ret)
1775 return ret;
1776 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1777 i, fw_info.feature, fw_info.ver);
1778 }
1779
1780 /* VCN */
1781 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1782 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1783 if (ret)
1784 return ret;
1785 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1786 fw_info.feature, fw_info.ver);
1787
1788 /* DMCU */
1789 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1790 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1791 if (ret)
1792 return ret;
1793 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1794 fw_info.feature, fw_info.ver);
1795
1796 /* DMCUB */
1797 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1798 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1799 if (ret)
1800 return ret;
1801 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1802 fw_info.feature, fw_info.ver);
1803
1804 /* TOC */
1805 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1806 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1807 if (ret)
1808 return ret;
1809 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1810 fw_info.feature, fw_info.ver);
1811
1812 /* CAP */
1813 if (adev->psp.cap_fw) {
1814 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1815 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1816 if (ret)
1817 return ret;
1818 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1819 fw_info.feature, fw_info.ver);
1820 }
1821
1822 /* MES_KIQ */
1823 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1824 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1825 if (ret)
1826 return ret;
1827 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1828 fw_info.feature, fw_info.ver);
1829
1830 /* MES */
1831 query_fw.fw_type = AMDGPU_INFO_FW_MES;
1832 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1833 if (ret)
1834 return ret;
1835 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1836 fw_info.feature, fw_info.ver);
1837
1838 /* VPE */
1839 query_fw.fw_type = AMDGPU_INFO_FW_VPE;
1840 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1841 if (ret)
1842 return ret;
1843 seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n",
1844 fw_info.feature, fw_info.ver);
1845
1846 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn);
1847
1848 return 0;
1849}
1850
1851DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1852
1853#endif
1854
1855void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1856{
1857#if defined(CONFIG_DEBUG_FS)
1858 struct drm_minor *minor = adev_to_drm(adev)->primary;
1859 struct dentry *root = minor->debugfs_root;
1860
1861 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1862 adev, &amdgpu_debugfs_firmware_info_fops);
1863
1864#endif
1865}