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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include "amdgpu_uvd.h"
32#include "amdgpu_vce.h"
33
34#include <linux/vga_switcheroo.h>
35#include <linux/slab.h>
36#include <linux/pm_runtime.h>
37#include "amdgpu_amdkfd.h"
38
39#if defined(CONFIG_VGA_SWITCHEROO)
40bool amdgpu_has_atpx(void);
41#else
42static inline bool amdgpu_has_atpx(void) { return false; }
43#endif
44
45/**
46 * amdgpu_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * Returns 0 on success.
52 */
53int amdgpu_driver_unload_kms(struct drm_device *dev)
54{
55 struct amdgpu_device *adev = dev->dev_private;
56
57 if (adev == NULL)
58 return 0;
59
60 if (adev->rmmio == NULL)
61 goto done_free;
62
63 pm_runtime_get_sync(dev->dev);
64
65 amdgpu_amdkfd_device_fini(adev);
66
67 amdgpu_acpi_fini(adev);
68
69 amdgpu_device_fini(adev);
70
71done_free:
72 kfree(adev);
73 dev->dev_private = NULL;
74 return 0;
75}
76
77/**
78 * amdgpu_driver_load_kms - Main load function for KMS.
79 *
80 * @dev: drm dev pointer
81 * @flags: device flags
82 *
83 * This is the main load function for KMS (all asics).
84 * Returns 0 on success, error on failure.
85 */
86int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
87{
88 struct amdgpu_device *adev;
89 int r, acpi_status;
90
91 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
92 if (adev == NULL) {
93 return -ENOMEM;
94 }
95 dev->dev_private = (void *)adev;
96
97 if ((amdgpu_runtime_pm != 0) &&
98 amdgpu_has_atpx() &&
99 ((flags & AMD_IS_APU) == 0))
100 flags |= AMD_IS_PX;
101
102 /* amdgpu_device_init should report only fatal error
103 * like memory allocation failure or iomapping failure,
104 * or memory manager initialization failure, it must
105 * properly initialize the GPU MC controller and permit
106 * VRAM allocation
107 */
108 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
109 if (r) {
110 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
111 goto out;
112 }
113
114 /* Call ACPI methods: require modeset init
115 * but failure is not fatal
116 */
117 if (!r) {
118 acpi_status = amdgpu_acpi_init(adev);
119 if (acpi_status)
120 dev_dbg(&dev->pdev->dev,
121 "Error during ACPI methods call\n");
122 }
123
124 amdgpu_amdkfd_load_interface(adev);
125 amdgpu_amdkfd_device_probe(adev);
126 amdgpu_amdkfd_device_init(adev);
127
128 if (amdgpu_device_is_px(dev)) {
129 pm_runtime_use_autosuspend(dev->dev);
130 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
131 pm_runtime_set_active(dev->dev);
132 pm_runtime_allow(dev->dev);
133 pm_runtime_mark_last_busy(dev->dev);
134 pm_runtime_put_autosuspend(dev->dev);
135 }
136
137out:
138 if (r)
139 amdgpu_driver_unload_kms(dev);
140
141
142 return r;
143}
144
145/*
146 * Userspace get information ioctl
147 */
148/**
149 * amdgpu_info_ioctl - answer a device specific request.
150 *
151 * @adev: amdgpu device pointer
152 * @data: request object
153 * @filp: drm filp
154 *
155 * This function is used to pass device specific parameters to the userspace
156 * drivers. Examples include: pci device id, pipeline parms, tiling params,
157 * etc. (all asics).
158 * Returns 0 on success, -EINVAL on failure.
159 */
160static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
161{
162 struct amdgpu_device *adev = dev->dev_private;
163 struct drm_amdgpu_info *info = data;
164 struct amdgpu_mode_info *minfo = &adev->mode_info;
165 void __user *out = (void __user *)(long)info->return_pointer;
166 uint32_t size = info->return_size;
167 struct drm_crtc *crtc;
168 uint32_t ui32 = 0;
169 uint64_t ui64 = 0;
170 int i, found;
171
172 if (!info->return_size || !info->return_pointer)
173 return -EINVAL;
174
175 switch (info->query) {
176 case AMDGPU_INFO_ACCEL_WORKING:
177 ui32 = adev->accel_working;
178 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
179 case AMDGPU_INFO_CRTC_FROM_ID:
180 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
181 crtc = (struct drm_crtc *)minfo->crtcs[i];
182 if (crtc && crtc->base.id == info->mode_crtc.id) {
183 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
184 ui32 = amdgpu_crtc->crtc_id;
185 found = 1;
186 break;
187 }
188 }
189 if (!found) {
190 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
191 return -EINVAL;
192 }
193 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
194 case AMDGPU_INFO_HW_IP_INFO: {
195 struct drm_amdgpu_info_hw_ip ip = {};
196 enum amd_ip_block_type type;
197 uint32_t ring_mask = 0;
198 uint32_t ib_start_alignment = 0;
199 uint32_t ib_size_alignment = 0;
200
201 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
202 return -EINVAL;
203
204 switch (info->query_hw_ip.type) {
205 case AMDGPU_HW_IP_GFX:
206 type = AMD_IP_BLOCK_TYPE_GFX;
207 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
208 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
209 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
210 ib_size_alignment = 8;
211 break;
212 case AMDGPU_HW_IP_COMPUTE:
213 type = AMD_IP_BLOCK_TYPE_GFX;
214 for (i = 0; i < adev->gfx.num_compute_rings; i++)
215 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
216 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
217 ib_size_alignment = 8;
218 break;
219 case AMDGPU_HW_IP_DMA:
220 type = AMD_IP_BLOCK_TYPE_SDMA;
221 for (i = 0; i < adev->sdma.num_instances; i++)
222 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
223 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
224 ib_size_alignment = 1;
225 break;
226 case AMDGPU_HW_IP_UVD:
227 type = AMD_IP_BLOCK_TYPE_UVD;
228 ring_mask = adev->uvd.ring.ready ? 1 : 0;
229 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
230 ib_size_alignment = 8;
231 break;
232 case AMDGPU_HW_IP_VCE:
233 type = AMD_IP_BLOCK_TYPE_VCE;
234 for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++)
235 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
236 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
237 ib_size_alignment = 8;
238 break;
239 default:
240 return -EINVAL;
241 }
242
243 for (i = 0; i < adev->num_ip_blocks; i++) {
244 if (adev->ip_blocks[i].type == type &&
245 adev->ip_block_status[i].valid) {
246 ip.hw_ip_version_major = adev->ip_blocks[i].major;
247 ip.hw_ip_version_minor = adev->ip_blocks[i].minor;
248 ip.capabilities_flags = 0;
249 ip.available_rings = ring_mask;
250 ip.ib_start_alignment = ib_start_alignment;
251 ip.ib_size_alignment = ib_size_alignment;
252 break;
253 }
254 }
255 return copy_to_user(out, &ip,
256 min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
257 }
258 case AMDGPU_INFO_HW_IP_COUNT: {
259 enum amd_ip_block_type type;
260 uint32_t count = 0;
261
262 switch (info->query_hw_ip.type) {
263 case AMDGPU_HW_IP_GFX:
264 type = AMD_IP_BLOCK_TYPE_GFX;
265 break;
266 case AMDGPU_HW_IP_COMPUTE:
267 type = AMD_IP_BLOCK_TYPE_GFX;
268 break;
269 case AMDGPU_HW_IP_DMA:
270 type = AMD_IP_BLOCK_TYPE_SDMA;
271 break;
272 case AMDGPU_HW_IP_UVD:
273 type = AMD_IP_BLOCK_TYPE_UVD;
274 break;
275 case AMDGPU_HW_IP_VCE:
276 type = AMD_IP_BLOCK_TYPE_VCE;
277 break;
278 default:
279 return -EINVAL;
280 }
281
282 for (i = 0; i < adev->num_ip_blocks; i++)
283 if (adev->ip_blocks[i].type == type &&
284 adev->ip_block_status[i].valid &&
285 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
286 count++;
287
288 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
289 }
290 case AMDGPU_INFO_TIMESTAMP:
291 ui64 = amdgpu_asic_get_gpu_clock_counter(adev);
292 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
293 case AMDGPU_INFO_FW_VERSION: {
294 struct drm_amdgpu_info_firmware fw_info;
295
296 /* We only support one instance of each IP block right now. */
297 if (info->query_fw.ip_instance != 0)
298 return -EINVAL;
299
300 switch (info->query_fw.fw_type) {
301 case AMDGPU_INFO_FW_VCE:
302 fw_info.ver = adev->vce.fw_version;
303 fw_info.feature = adev->vce.fb_version;
304 break;
305 case AMDGPU_INFO_FW_UVD:
306 fw_info.ver = adev->uvd.fw_version;
307 fw_info.feature = 0;
308 break;
309 case AMDGPU_INFO_FW_GMC:
310 fw_info.ver = adev->mc.fw_version;
311 fw_info.feature = 0;
312 break;
313 case AMDGPU_INFO_FW_GFX_ME:
314 fw_info.ver = adev->gfx.me_fw_version;
315 fw_info.feature = adev->gfx.me_feature_version;
316 break;
317 case AMDGPU_INFO_FW_GFX_PFP:
318 fw_info.ver = adev->gfx.pfp_fw_version;
319 fw_info.feature = adev->gfx.pfp_feature_version;
320 break;
321 case AMDGPU_INFO_FW_GFX_CE:
322 fw_info.ver = adev->gfx.ce_fw_version;
323 fw_info.feature = adev->gfx.ce_feature_version;
324 break;
325 case AMDGPU_INFO_FW_GFX_RLC:
326 fw_info.ver = adev->gfx.rlc_fw_version;
327 fw_info.feature = adev->gfx.rlc_feature_version;
328 break;
329 case AMDGPU_INFO_FW_GFX_MEC:
330 if (info->query_fw.index == 0) {
331 fw_info.ver = adev->gfx.mec_fw_version;
332 fw_info.feature = adev->gfx.mec_feature_version;
333 } else if (info->query_fw.index == 1) {
334 fw_info.ver = adev->gfx.mec2_fw_version;
335 fw_info.feature = adev->gfx.mec2_feature_version;
336 } else
337 return -EINVAL;
338 break;
339 case AMDGPU_INFO_FW_SMC:
340 fw_info.ver = adev->pm.fw_version;
341 fw_info.feature = 0;
342 break;
343 case AMDGPU_INFO_FW_SDMA:
344 if (info->query_fw.index >= adev->sdma.num_instances)
345 return -EINVAL;
346 fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version;
347 fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version;
348 break;
349 default:
350 return -EINVAL;
351 }
352 return copy_to_user(out, &fw_info,
353 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
354 }
355 case AMDGPU_INFO_NUM_BYTES_MOVED:
356 ui64 = atomic64_read(&adev->num_bytes_moved);
357 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
358 case AMDGPU_INFO_VRAM_USAGE:
359 ui64 = atomic64_read(&adev->vram_usage);
360 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
361 case AMDGPU_INFO_VIS_VRAM_USAGE:
362 ui64 = atomic64_read(&adev->vram_vis_usage);
363 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
364 case AMDGPU_INFO_GTT_USAGE:
365 ui64 = atomic64_read(&adev->gtt_usage);
366 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
367 case AMDGPU_INFO_GDS_CONFIG: {
368 struct drm_amdgpu_info_gds gds_info;
369
370 memset(&gds_info, 0, sizeof(gds_info));
371 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
372 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
373 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
374 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
375 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
376 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
377 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
378 return copy_to_user(out, &gds_info,
379 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
380 }
381 case AMDGPU_INFO_VRAM_GTT: {
382 struct drm_amdgpu_info_vram_gtt vram_gtt;
383
384 vram_gtt.vram_size = adev->mc.real_vram_size;
385 vram_gtt.vram_size -= adev->vram_pin_size;
386 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
387 vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
388 vram_gtt.gtt_size = adev->mc.gtt_size;
389 vram_gtt.gtt_size -= adev->gart_pin_size;
390 return copy_to_user(out, &vram_gtt,
391 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
392 }
393 case AMDGPU_INFO_READ_MMR_REG: {
394 unsigned n, alloc_size;
395 uint32_t *regs;
396 unsigned se_num = (info->read_mmr_reg.instance >>
397 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
398 AMDGPU_INFO_MMR_SE_INDEX_MASK;
399 unsigned sh_num = (info->read_mmr_reg.instance >>
400 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
401 AMDGPU_INFO_MMR_SH_INDEX_MASK;
402
403 /* set full masks if the userspace set all bits
404 * in the bitfields */
405 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
406 se_num = 0xffffffff;
407 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
408 sh_num = 0xffffffff;
409
410 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
411 if (!regs)
412 return -ENOMEM;
413 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
414
415 for (i = 0; i < info->read_mmr_reg.count; i++)
416 if (amdgpu_asic_read_register(adev, se_num, sh_num,
417 info->read_mmr_reg.dword_offset + i,
418 ®s[i])) {
419 DRM_DEBUG_KMS("unallowed offset %#x\n",
420 info->read_mmr_reg.dword_offset + i);
421 kfree(regs);
422 return -EFAULT;
423 }
424 n = copy_to_user(out, regs, min(size, alloc_size));
425 kfree(regs);
426 return n ? -EFAULT : 0;
427 }
428 case AMDGPU_INFO_DEV_INFO: {
429 struct drm_amdgpu_info_device dev_info = {};
430 struct amdgpu_cu_info cu_info;
431
432 dev_info.device_id = dev->pdev->device;
433 dev_info.chip_rev = adev->rev_id;
434 dev_info.external_rev = adev->external_rev_id;
435 dev_info.pci_rev = dev->pdev->revision;
436 dev_info.family = adev->family;
437 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
438 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
439 /* return all clocks in KHz */
440 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
441 if (adev->pm.dpm_enabled) {
442 dev_info.max_engine_clock =
443 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
444 dev_info.max_memory_clock =
445 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10;
446 } else {
447 dev_info.max_engine_clock = adev->pm.default_sclk * 10;
448 dev_info.max_memory_clock = adev->pm.default_mclk * 10;
449 }
450 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
451 dev_info.num_rb_pipes = adev->gfx.config.num_rbs;
452 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
453 dev_info._pad = 0;
454 dev_info.ids_flags = 0;
455 if (adev->flags & AMD_IS_APU)
456 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
457 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
458 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
459 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
460 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) *
461 AMDGPU_GPU_PAGE_SIZE;
462 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
463
464 amdgpu_asic_get_cu_info(adev, &cu_info);
465 dev_info.cu_active_number = cu_info.number;
466 dev_info.cu_ao_mask = cu_info.ao_cu_mask;
467 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
468 memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));
469 dev_info.vram_type = adev->mc.vram_type;
470 dev_info.vram_bit_width = adev->mc.vram_width;
471 dev_info.vce_harvest_config = adev->vce.harvest_config;
472
473 return copy_to_user(out, &dev_info,
474 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
475 }
476 default:
477 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
478 return -EINVAL;
479 }
480 return 0;
481}
482
483
484/*
485 * Outdated mess for old drm with Xorg being in charge (void function now).
486 */
487/**
488 * amdgpu_driver_lastclose_kms - drm callback for last close
489 *
490 * @dev: drm dev pointer
491 *
492 * Switch vga_switcheroo state after last close (all asics).
493 */
494void amdgpu_driver_lastclose_kms(struct drm_device *dev)
495{
496 struct amdgpu_device *adev = dev->dev_private;
497
498 amdgpu_fbdev_restore_mode(adev);
499 vga_switcheroo_process_delayed_switch();
500}
501
502/**
503 * amdgpu_driver_open_kms - drm callback for open
504 *
505 * @dev: drm dev pointer
506 * @file_priv: drm file
507 *
508 * On device open, init vm on cayman+ (all asics).
509 * Returns 0 on success, error on failure.
510 */
511int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
512{
513 struct amdgpu_device *adev = dev->dev_private;
514 struct amdgpu_fpriv *fpriv;
515 int r;
516
517 file_priv->driver_priv = NULL;
518
519 r = pm_runtime_get_sync(dev->dev);
520 if (r < 0)
521 return r;
522
523 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
524 if (unlikely(!fpriv))
525 return -ENOMEM;
526
527 r = amdgpu_vm_init(adev, &fpriv->vm);
528 if (r)
529 goto error_free;
530
531 mutex_init(&fpriv->bo_list_lock);
532 idr_init(&fpriv->bo_list_handles);
533
534 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
535
536 file_priv->driver_priv = fpriv;
537
538 pm_runtime_mark_last_busy(dev->dev);
539 pm_runtime_put_autosuspend(dev->dev);
540 return 0;
541
542error_free:
543 kfree(fpriv);
544
545 return r;
546}
547
548/**
549 * amdgpu_driver_postclose_kms - drm callback for post close
550 *
551 * @dev: drm dev pointer
552 * @file_priv: drm file
553 *
554 * On device post close, tear down vm on cayman+ (all asics).
555 */
556void amdgpu_driver_postclose_kms(struct drm_device *dev,
557 struct drm_file *file_priv)
558{
559 struct amdgpu_device *adev = dev->dev_private;
560 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
561 struct amdgpu_bo_list *list;
562 int handle;
563
564 if (!fpriv)
565 return;
566
567 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
568
569 amdgpu_vm_fini(adev, &fpriv->vm);
570
571 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
572 amdgpu_bo_list_free(list);
573
574 idr_destroy(&fpriv->bo_list_handles);
575 mutex_destroy(&fpriv->bo_list_lock);
576
577 kfree(fpriv);
578 file_priv->driver_priv = NULL;
579}
580
581/**
582 * amdgpu_driver_preclose_kms - drm callback for pre close
583 *
584 * @dev: drm dev pointer
585 * @file_priv: drm file
586 *
587 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
588 * (all asics).
589 */
590void amdgpu_driver_preclose_kms(struct drm_device *dev,
591 struct drm_file *file_priv)
592{
593 struct amdgpu_device *adev = dev->dev_private;
594
595 amdgpu_uvd_free_handles(adev, file_priv);
596 amdgpu_vce_free_handles(adev, file_priv);
597}
598
599/*
600 * VBlank related functions.
601 */
602/**
603 * amdgpu_get_vblank_counter_kms - get frame count
604 *
605 * @dev: drm dev pointer
606 * @pipe: crtc to get the frame count from
607 *
608 * Gets the frame count on the requested crtc (all asics).
609 * Returns frame count on success, -EINVAL on failure.
610 */
611u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
612{
613 struct amdgpu_device *adev = dev->dev_private;
614 int vpos, hpos, stat;
615 u32 count;
616
617 if (pipe >= adev->mode_info.num_crtc) {
618 DRM_ERROR("Invalid crtc %u\n", pipe);
619 return -EINVAL;
620 }
621
622 /* The hw increments its frame counter at start of vsync, not at start
623 * of vblank, as is required by DRM core vblank counter handling.
624 * Cook the hw count here to make it appear to the caller as if it
625 * incremented at start of vblank. We measure distance to start of
626 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
627 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
628 * result by 1 to give the proper appearance to caller.
629 */
630 if (adev->mode_info.crtcs[pipe]) {
631 /* Repeat readout if needed to provide stable result if
632 * we cross start of vsync during the queries.
633 */
634 do {
635 count = amdgpu_display_vblank_get_counter(adev, pipe);
636 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as
637 * distance to start of vblank, instead of regular
638 * vertical scanout pos.
639 */
640 stat = amdgpu_get_crtc_scanoutpos(
641 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
642 &vpos, &hpos, NULL, NULL,
643 &adev->mode_info.crtcs[pipe]->base.hwmode);
644 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
645
646 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
647 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
648 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
649 } else {
650 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
651 pipe, vpos);
652
653 /* Bump counter if we are at >= leading edge of vblank,
654 * but before vsync where vpos would turn negative and
655 * the hw counter really increments.
656 */
657 if (vpos >= 0)
658 count++;
659 }
660 } else {
661 /* Fallback to use value as is. */
662 count = amdgpu_display_vblank_get_counter(adev, pipe);
663 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
664 }
665
666 return count;
667}
668
669/**
670 * amdgpu_enable_vblank_kms - enable vblank interrupt
671 *
672 * @dev: drm dev pointer
673 * @pipe: crtc to enable vblank interrupt for
674 *
675 * Enable the interrupt on the requested crtc (all asics).
676 * Returns 0 on success, -EINVAL on failure.
677 */
678int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
679{
680 struct amdgpu_device *adev = dev->dev_private;
681 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
682
683 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
684}
685
686/**
687 * amdgpu_disable_vblank_kms - disable vblank interrupt
688 *
689 * @dev: drm dev pointer
690 * @pipe: crtc to disable vblank interrupt for
691 *
692 * Disable the interrupt on the requested crtc (all asics).
693 */
694void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
695{
696 struct amdgpu_device *adev = dev->dev_private;
697 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
698
699 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
700}
701
702/**
703 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
704 *
705 * @dev: drm dev pointer
706 * @crtc: crtc to get the timestamp for
707 * @max_error: max error
708 * @vblank_time: time value
709 * @flags: flags passed to the driver
710 *
711 * Gets the timestamp on the requested crtc based on the
712 * scanout position. (all asics).
713 * Returns postive status flags on success, negative error on failure.
714 */
715int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
716 int *max_error,
717 struct timeval *vblank_time,
718 unsigned flags)
719{
720 struct drm_crtc *crtc;
721 struct amdgpu_device *adev = dev->dev_private;
722
723 if (pipe >= dev->num_crtcs) {
724 DRM_ERROR("Invalid crtc %u\n", pipe);
725 return -EINVAL;
726 }
727
728 /* Get associated drm_crtc: */
729 crtc = &adev->mode_info.crtcs[pipe]->base;
730 if (!crtc) {
731 /* This can occur on driver load if some component fails to
732 * initialize completely and driver is unloaded */
733 DRM_ERROR("Uninitialized crtc %d\n", pipe);
734 return -EINVAL;
735 }
736
737 /* Helper routine in DRM core does all the work: */
738 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
739 vblank_time, flags,
740 &crtc->hwmode);
741}
742
743const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
744 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
745 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
746 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
747 /* KMS */
748 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
749 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
750 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
751 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
752 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
753 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
754 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
755 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
756 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
757};
758int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);