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1/*
2 * libata-sff.c - helper library for PCI IDE BMDMA
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/gfp.h>
37#include <linux/pci.h>
38#include <linux/module.h>
39#include <linux/libata.h>
40#include <linux/highmem.h>
41
42#include "libata.h"
43
44static struct workqueue_struct *ata_sff_wq;
45
46const struct ata_port_operations ata_sff_port_ops = {
47 .inherits = &ata_base_port_ops,
48
49 .qc_prep = ata_noop_qc_prep,
50 .qc_issue = ata_sff_qc_issue,
51 .qc_fill_rtf = ata_sff_qc_fill_rtf,
52
53 .freeze = ata_sff_freeze,
54 .thaw = ata_sff_thaw,
55 .prereset = ata_sff_prereset,
56 .softreset = ata_sff_softreset,
57 .hardreset = sata_sff_hardreset,
58 .postreset = ata_sff_postreset,
59 .error_handler = ata_sff_error_handler,
60
61 .sff_dev_select = ata_sff_dev_select,
62 .sff_check_status = ata_sff_check_status,
63 .sff_tf_load = ata_sff_tf_load,
64 .sff_tf_read = ata_sff_tf_read,
65 .sff_exec_command = ata_sff_exec_command,
66 .sff_data_xfer = ata_sff_data_xfer,
67 .sff_drain_fifo = ata_sff_drain_fifo,
68
69 .lost_interrupt = ata_sff_lost_interrupt,
70};
71EXPORT_SYMBOL_GPL(ata_sff_port_ops);
72
73/**
74 * ata_sff_check_status - Read device status reg & clear interrupt
75 * @ap: port where the device is
76 *
77 * Reads ATA taskfile status register for currently-selected device
78 * and return its value. This also clears pending interrupts
79 * from this device
80 *
81 * LOCKING:
82 * Inherited from caller.
83 */
84u8 ata_sff_check_status(struct ata_port *ap)
85{
86 return ioread8(ap->ioaddr.status_addr);
87}
88EXPORT_SYMBOL_GPL(ata_sff_check_status);
89
90/**
91 * ata_sff_altstatus - Read device alternate status reg
92 * @ap: port where the device is
93 *
94 * Reads ATA taskfile alternate status register for
95 * currently-selected device and return its value.
96 *
97 * Note: may NOT be used as the check_altstatus() entry in
98 * ata_port_operations.
99 *
100 * LOCKING:
101 * Inherited from caller.
102 */
103static u8 ata_sff_altstatus(struct ata_port *ap)
104{
105 if (ap->ops->sff_check_altstatus)
106 return ap->ops->sff_check_altstatus(ap);
107
108 return ioread8(ap->ioaddr.altstatus_addr);
109}
110
111/**
112 * ata_sff_irq_status - Check if the device is busy
113 * @ap: port where the device is
114 *
115 * Determine if the port is currently busy. Uses altstatus
116 * if available in order to avoid clearing shared IRQ status
117 * when finding an IRQ source. Non ctl capable devices don't
118 * share interrupt lines fortunately for us.
119 *
120 * LOCKING:
121 * Inherited from caller.
122 */
123static u8 ata_sff_irq_status(struct ata_port *ap)
124{
125 u8 status;
126
127 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
128 status = ata_sff_altstatus(ap);
129 /* Not us: We are busy */
130 if (status & ATA_BUSY)
131 return status;
132 }
133 /* Clear INTRQ latch */
134 status = ap->ops->sff_check_status(ap);
135 return status;
136}
137
138/**
139 * ata_sff_sync - Flush writes
140 * @ap: Port to wait for.
141 *
142 * CAUTION:
143 * If we have an mmio device with no ctl and no altstatus
144 * method this will fail. No such devices are known to exist.
145 *
146 * LOCKING:
147 * Inherited from caller.
148 */
149
150static void ata_sff_sync(struct ata_port *ap)
151{
152 if (ap->ops->sff_check_altstatus)
153 ap->ops->sff_check_altstatus(ap);
154 else if (ap->ioaddr.altstatus_addr)
155 ioread8(ap->ioaddr.altstatus_addr);
156}
157
158/**
159 * ata_sff_pause - Flush writes and wait 400nS
160 * @ap: Port to pause for.
161 *
162 * CAUTION:
163 * If we have an mmio device with no ctl and no altstatus
164 * method this will fail. No such devices are known to exist.
165 *
166 * LOCKING:
167 * Inherited from caller.
168 */
169
170void ata_sff_pause(struct ata_port *ap)
171{
172 ata_sff_sync(ap);
173 ndelay(400);
174}
175EXPORT_SYMBOL_GPL(ata_sff_pause);
176
177/**
178 * ata_sff_dma_pause - Pause before commencing DMA
179 * @ap: Port to pause for.
180 *
181 * Perform I/O fencing and ensure sufficient cycle delays occur
182 * for the HDMA1:0 transition
183 */
184
185void ata_sff_dma_pause(struct ata_port *ap)
186{
187 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
188 /* An altstatus read will cause the needed delay without
189 messing up the IRQ status */
190 ata_sff_altstatus(ap);
191 return;
192 }
193 /* There are no DMA controllers without ctl. BUG here to ensure
194 we never violate the HDMA1:0 transition timing and risk
195 corruption. */
196 BUG();
197}
198EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
199
200/**
201 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
202 * @ap: port containing status register to be polled
203 * @tmout_pat: impatience timeout in msecs
204 * @tmout: overall timeout in msecs
205 *
206 * Sleep until ATA Status register bit BSY clears,
207 * or a timeout occurs.
208 *
209 * LOCKING:
210 * Kernel thread context (may sleep).
211 *
212 * RETURNS:
213 * 0 on success, -errno otherwise.
214 */
215int ata_sff_busy_sleep(struct ata_port *ap,
216 unsigned long tmout_pat, unsigned long tmout)
217{
218 unsigned long timer_start, timeout;
219 u8 status;
220
221 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
222 timer_start = jiffies;
223 timeout = ata_deadline(timer_start, tmout_pat);
224 while (status != 0xff && (status & ATA_BUSY) &&
225 time_before(jiffies, timeout)) {
226 ata_msleep(ap, 50);
227 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
228 }
229
230 if (status != 0xff && (status & ATA_BUSY))
231 ata_port_warn(ap,
232 "port is slow to respond, please be patient (Status 0x%x)\n",
233 status);
234
235 timeout = ata_deadline(timer_start, tmout);
236 while (status != 0xff && (status & ATA_BUSY) &&
237 time_before(jiffies, timeout)) {
238 ata_msleep(ap, 50);
239 status = ap->ops->sff_check_status(ap);
240 }
241
242 if (status == 0xff)
243 return -ENODEV;
244
245 if (status & ATA_BUSY) {
246 ata_port_err(ap,
247 "port failed to respond (%lu secs, Status 0x%x)\n",
248 DIV_ROUND_UP(tmout, 1000), status);
249 return -EBUSY;
250 }
251
252 return 0;
253}
254EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
255
256static int ata_sff_check_ready(struct ata_link *link)
257{
258 u8 status = link->ap->ops->sff_check_status(link->ap);
259
260 return ata_check_ready(status);
261}
262
263/**
264 * ata_sff_wait_ready - sleep until BSY clears, or timeout
265 * @link: SFF link to wait ready status for
266 * @deadline: deadline jiffies for the operation
267 *
268 * Sleep until ATA Status register bit BSY clears, or timeout
269 * occurs.
270 *
271 * LOCKING:
272 * Kernel thread context (may sleep).
273 *
274 * RETURNS:
275 * 0 on success, -errno otherwise.
276 */
277int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
278{
279 return ata_wait_ready(link, deadline, ata_sff_check_ready);
280}
281EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
282
283/**
284 * ata_sff_set_devctl - Write device control reg
285 * @ap: port where the device is
286 * @ctl: value to write
287 *
288 * Writes ATA taskfile device control register.
289 *
290 * Note: may NOT be used as the sff_set_devctl() entry in
291 * ata_port_operations.
292 *
293 * LOCKING:
294 * Inherited from caller.
295 */
296static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
297{
298 if (ap->ops->sff_set_devctl)
299 ap->ops->sff_set_devctl(ap, ctl);
300 else
301 iowrite8(ctl, ap->ioaddr.ctl_addr);
302}
303
304/**
305 * ata_sff_dev_select - Select device 0/1 on ATA bus
306 * @ap: ATA channel to manipulate
307 * @device: ATA device (numbered from zero) to select
308 *
309 * Use the method defined in the ATA specification to
310 * make either device 0, or device 1, active on the
311 * ATA channel. Works with both PIO and MMIO.
312 *
313 * May be used as the dev_select() entry in ata_port_operations.
314 *
315 * LOCKING:
316 * caller.
317 */
318void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
319{
320 u8 tmp;
321
322 if (device == 0)
323 tmp = ATA_DEVICE_OBS;
324 else
325 tmp = ATA_DEVICE_OBS | ATA_DEV1;
326
327 iowrite8(tmp, ap->ioaddr.device_addr);
328 ata_sff_pause(ap); /* needed; also flushes, for mmio */
329}
330EXPORT_SYMBOL_GPL(ata_sff_dev_select);
331
332/**
333 * ata_dev_select - Select device 0/1 on ATA bus
334 * @ap: ATA channel to manipulate
335 * @device: ATA device (numbered from zero) to select
336 * @wait: non-zero to wait for Status register BSY bit to clear
337 * @can_sleep: non-zero if context allows sleeping
338 *
339 * Use the method defined in the ATA specification to
340 * make either device 0, or device 1, active on the
341 * ATA channel.
342 *
343 * This is a high-level version of ata_sff_dev_select(), which
344 * additionally provides the services of inserting the proper
345 * pauses and status polling, where needed.
346 *
347 * LOCKING:
348 * caller.
349 */
350static void ata_dev_select(struct ata_port *ap, unsigned int device,
351 unsigned int wait, unsigned int can_sleep)
352{
353 if (ata_msg_probe(ap))
354 ata_port_info(ap, "ata_dev_select: ENTER, device %u, wait %u\n",
355 device, wait);
356
357 if (wait)
358 ata_wait_idle(ap);
359
360 ap->ops->sff_dev_select(ap, device);
361
362 if (wait) {
363 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
364 ata_msleep(ap, 150);
365 ata_wait_idle(ap);
366 }
367}
368
369/**
370 * ata_sff_irq_on - Enable interrupts on a port.
371 * @ap: Port on which interrupts are enabled.
372 *
373 * Enable interrupts on a legacy IDE device using MMIO or PIO,
374 * wait for idle, clear any pending interrupts.
375 *
376 * Note: may NOT be used as the sff_irq_on() entry in
377 * ata_port_operations.
378 *
379 * LOCKING:
380 * Inherited from caller.
381 */
382void ata_sff_irq_on(struct ata_port *ap)
383{
384 struct ata_ioports *ioaddr = &ap->ioaddr;
385
386 if (ap->ops->sff_irq_on) {
387 ap->ops->sff_irq_on(ap);
388 return;
389 }
390
391 ap->ctl &= ~ATA_NIEN;
392 ap->last_ctl = ap->ctl;
393
394 if (ap->ops->sff_set_devctl || ioaddr->ctl_addr)
395 ata_sff_set_devctl(ap, ap->ctl);
396 ata_wait_idle(ap);
397
398 if (ap->ops->sff_irq_clear)
399 ap->ops->sff_irq_clear(ap);
400}
401EXPORT_SYMBOL_GPL(ata_sff_irq_on);
402
403/**
404 * ata_sff_tf_load - send taskfile registers to host controller
405 * @ap: Port to which output is sent
406 * @tf: ATA taskfile register set
407 *
408 * Outputs ATA taskfile to standard ATA host controller.
409 *
410 * LOCKING:
411 * Inherited from caller.
412 */
413void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
414{
415 struct ata_ioports *ioaddr = &ap->ioaddr;
416 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
417
418 if (tf->ctl != ap->last_ctl) {
419 if (ioaddr->ctl_addr)
420 iowrite8(tf->ctl, ioaddr->ctl_addr);
421 ap->last_ctl = tf->ctl;
422 ata_wait_idle(ap);
423 }
424
425 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
426 WARN_ON_ONCE(!ioaddr->ctl_addr);
427 iowrite8(tf->hob_feature, ioaddr->feature_addr);
428 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
429 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
430 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
431 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
432 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
433 tf->hob_feature,
434 tf->hob_nsect,
435 tf->hob_lbal,
436 tf->hob_lbam,
437 tf->hob_lbah);
438 }
439
440 if (is_addr) {
441 iowrite8(tf->feature, ioaddr->feature_addr);
442 iowrite8(tf->nsect, ioaddr->nsect_addr);
443 iowrite8(tf->lbal, ioaddr->lbal_addr);
444 iowrite8(tf->lbam, ioaddr->lbam_addr);
445 iowrite8(tf->lbah, ioaddr->lbah_addr);
446 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
447 tf->feature,
448 tf->nsect,
449 tf->lbal,
450 tf->lbam,
451 tf->lbah);
452 }
453
454 if (tf->flags & ATA_TFLAG_DEVICE) {
455 iowrite8(tf->device, ioaddr->device_addr);
456 VPRINTK("device 0x%X\n", tf->device);
457 }
458
459 ata_wait_idle(ap);
460}
461EXPORT_SYMBOL_GPL(ata_sff_tf_load);
462
463/**
464 * ata_sff_tf_read - input device's ATA taskfile shadow registers
465 * @ap: Port from which input is read
466 * @tf: ATA taskfile register set for storing input
467 *
468 * Reads ATA taskfile registers for currently-selected device
469 * into @tf. Assumes the device has a fully SFF compliant task file
470 * layout and behaviour. If you device does not (eg has a different
471 * status method) then you will need to provide a replacement tf_read
472 *
473 * LOCKING:
474 * Inherited from caller.
475 */
476void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
477{
478 struct ata_ioports *ioaddr = &ap->ioaddr;
479
480 tf->command = ata_sff_check_status(ap);
481 tf->feature = ioread8(ioaddr->error_addr);
482 tf->nsect = ioread8(ioaddr->nsect_addr);
483 tf->lbal = ioread8(ioaddr->lbal_addr);
484 tf->lbam = ioread8(ioaddr->lbam_addr);
485 tf->lbah = ioread8(ioaddr->lbah_addr);
486 tf->device = ioread8(ioaddr->device_addr);
487
488 if (tf->flags & ATA_TFLAG_LBA48) {
489 if (likely(ioaddr->ctl_addr)) {
490 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
491 tf->hob_feature = ioread8(ioaddr->error_addr);
492 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
493 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
494 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
495 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
496 iowrite8(tf->ctl, ioaddr->ctl_addr);
497 ap->last_ctl = tf->ctl;
498 } else
499 WARN_ON_ONCE(1);
500 }
501}
502EXPORT_SYMBOL_GPL(ata_sff_tf_read);
503
504/**
505 * ata_sff_exec_command - issue ATA command to host controller
506 * @ap: port to which command is being issued
507 * @tf: ATA taskfile register set
508 *
509 * Issues ATA command, with proper synchronization with interrupt
510 * handler / other threads.
511 *
512 * LOCKING:
513 * spin_lock_irqsave(host lock)
514 */
515void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
516{
517 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
518
519 iowrite8(tf->command, ap->ioaddr.command_addr);
520 ata_sff_pause(ap);
521}
522EXPORT_SYMBOL_GPL(ata_sff_exec_command);
523
524/**
525 * ata_tf_to_host - issue ATA taskfile to host controller
526 * @ap: port to which command is being issued
527 * @tf: ATA taskfile register set
528 *
529 * Issues ATA taskfile register set to ATA host controller,
530 * with proper synchronization with interrupt handler and
531 * other threads.
532 *
533 * LOCKING:
534 * spin_lock_irqsave(host lock)
535 */
536static inline void ata_tf_to_host(struct ata_port *ap,
537 const struct ata_taskfile *tf)
538{
539 ap->ops->sff_tf_load(ap, tf);
540 ap->ops->sff_exec_command(ap, tf);
541}
542
543/**
544 * ata_sff_data_xfer - Transfer data by PIO
545 * @dev: device to target
546 * @buf: data buffer
547 * @buflen: buffer length
548 * @rw: read/write
549 *
550 * Transfer data from/to the device data register by PIO.
551 *
552 * LOCKING:
553 * Inherited from caller.
554 *
555 * RETURNS:
556 * Bytes consumed.
557 */
558unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
559 unsigned int buflen, int rw)
560{
561 struct ata_port *ap = dev->link->ap;
562 void __iomem *data_addr = ap->ioaddr.data_addr;
563 unsigned int words = buflen >> 1;
564
565 /* Transfer multiple of 2 bytes */
566 if (rw == READ)
567 ioread16_rep(data_addr, buf, words);
568 else
569 iowrite16_rep(data_addr, buf, words);
570
571 /* Transfer trailing byte, if any. */
572 if (unlikely(buflen & 0x01)) {
573 unsigned char pad[2] = { };
574
575 /* Point buf to the tail of buffer */
576 buf += buflen - 1;
577
578 /*
579 * Use io*16_rep() accessors here as well to avoid pointlessly
580 * swapping bytes to and from on the big endian machines...
581 */
582 if (rw == READ) {
583 ioread16_rep(data_addr, pad, 1);
584 *buf = pad[0];
585 } else {
586 pad[0] = *buf;
587 iowrite16_rep(data_addr, pad, 1);
588 }
589 words++;
590 }
591
592 return words << 1;
593}
594EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
595
596/**
597 * ata_sff_data_xfer32 - Transfer data by PIO
598 * @dev: device to target
599 * @buf: data buffer
600 * @buflen: buffer length
601 * @rw: read/write
602 *
603 * Transfer data from/to the device data register by PIO using 32bit
604 * I/O operations.
605 *
606 * LOCKING:
607 * Inherited from caller.
608 *
609 * RETURNS:
610 * Bytes consumed.
611 */
612
613unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
614 unsigned int buflen, int rw)
615{
616 struct ata_port *ap = dev->link->ap;
617 void __iomem *data_addr = ap->ioaddr.data_addr;
618 unsigned int words = buflen >> 2;
619 int slop = buflen & 3;
620
621 if (!(ap->pflags & ATA_PFLAG_PIO32))
622 return ata_sff_data_xfer(dev, buf, buflen, rw);
623
624 /* Transfer multiple of 4 bytes */
625 if (rw == READ)
626 ioread32_rep(data_addr, buf, words);
627 else
628 iowrite32_rep(data_addr, buf, words);
629
630 /* Transfer trailing bytes, if any */
631 if (unlikely(slop)) {
632 unsigned char pad[4] = { };
633
634 /* Point buf to the tail of buffer */
635 buf += buflen - slop;
636
637 /*
638 * Use io*_rep() accessors here as well to avoid pointlessly
639 * swapping bytes to and from on the big endian machines...
640 */
641 if (rw == READ) {
642 if (slop < 3)
643 ioread16_rep(data_addr, pad, 1);
644 else
645 ioread32_rep(data_addr, pad, 1);
646 memcpy(buf, pad, slop);
647 } else {
648 memcpy(pad, buf, slop);
649 if (slop < 3)
650 iowrite16_rep(data_addr, pad, 1);
651 else
652 iowrite32_rep(data_addr, pad, 1);
653 }
654 }
655 return (buflen + 1) & ~1;
656}
657EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
658
659/**
660 * ata_sff_data_xfer_noirq - Transfer data by PIO
661 * @dev: device to target
662 * @buf: data buffer
663 * @buflen: buffer length
664 * @rw: read/write
665 *
666 * Transfer data from/to the device data register by PIO. Do the
667 * transfer with interrupts disabled.
668 *
669 * LOCKING:
670 * Inherited from caller.
671 *
672 * RETURNS:
673 * Bytes consumed.
674 */
675unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
676 unsigned int buflen, int rw)
677{
678 unsigned long flags;
679 unsigned int consumed;
680
681 local_irq_save(flags);
682 consumed = ata_sff_data_xfer32(dev, buf, buflen, rw);
683 local_irq_restore(flags);
684
685 return consumed;
686}
687EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
688
689/**
690 * ata_pio_sector - Transfer a sector of data.
691 * @qc: Command on going
692 *
693 * Transfer qc->sect_size bytes of data from/to the ATA device.
694 *
695 * LOCKING:
696 * Inherited from caller.
697 */
698static void ata_pio_sector(struct ata_queued_cmd *qc)
699{
700 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
701 struct ata_port *ap = qc->ap;
702 struct page *page;
703 unsigned int offset;
704 unsigned char *buf;
705
706 if (qc->curbytes == qc->nbytes - qc->sect_size)
707 ap->hsm_task_state = HSM_ST_LAST;
708
709 page = sg_page(qc->cursg);
710 offset = qc->cursg->offset + qc->cursg_ofs;
711
712 /* get the current page and offset */
713 page = nth_page(page, (offset >> PAGE_SHIFT));
714 offset %= PAGE_SIZE;
715
716 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
717
718 if (PageHighMem(page)) {
719 unsigned long flags;
720
721 /* FIXME: use a bounce buffer */
722 local_irq_save(flags);
723 buf = kmap_atomic(page);
724
725 /* do the actual data transfer */
726 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
727 do_write);
728
729 kunmap_atomic(buf);
730 local_irq_restore(flags);
731 } else {
732 buf = page_address(page);
733 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
734 do_write);
735 }
736
737 if (!do_write && !PageSlab(page))
738 flush_dcache_page(page);
739
740 qc->curbytes += qc->sect_size;
741 qc->cursg_ofs += qc->sect_size;
742
743 if (qc->cursg_ofs == qc->cursg->length) {
744 qc->cursg = sg_next(qc->cursg);
745 qc->cursg_ofs = 0;
746 }
747}
748
749/**
750 * ata_pio_sectors - Transfer one or many sectors.
751 * @qc: Command on going
752 *
753 * Transfer one or many sectors of data from/to the
754 * ATA device for the DRQ request.
755 *
756 * LOCKING:
757 * Inherited from caller.
758 */
759static void ata_pio_sectors(struct ata_queued_cmd *qc)
760{
761 if (is_multi_taskfile(&qc->tf)) {
762 /* READ/WRITE MULTIPLE */
763 unsigned int nsect;
764
765 WARN_ON_ONCE(qc->dev->multi_count == 0);
766
767 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
768 qc->dev->multi_count);
769 while (nsect--)
770 ata_pio_sector(qc);
771 } else
772 ata_pio_sector(qc);
773
774 ata_sff_sync(qc->ap); /* flush */
775}
776
777/**
778 * atapi_send_cdb - Write CDB bytes to hardware
779 * @ap: Port to which ATAPI device is attached.
780 * @qc: Taskfile currently active
781 *
782 * When device has indicated its readiness to accept
783 * a CDB, this function is called. Send the CDB.
784 *
785 * LOCKING:
786 * caller.
787 */
788static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
789{
790 /* send SCSI cdb */
791 DPRINTK("send cdb\n");
792 WARN_ON_ONCE(qc->dev->cdb_len < 12);
793
794 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
795 ata_sff_sync(ap);
796 /* FIXME: If the CDB is for DMA do we need to do the transition delay
797 or is bmdma_start guaranteed to do it ? */
798 switch (qc->tf.protocol) {
799 case ATAPI_PROT_PIO:
800 ap->hsm_task_state = HSM_ST;
801 break;
802 case ATAPI_PROT_NODATA:
803 ap->hsm_task_state = HSM_ST_LAST;
804 break;
805#ifdef CONFIG_ATA_BMDMA
806 case ATAPI_PROT_DMA:
807 ap->hsm_task_state = HSM_ST_LAST;
808 /* initiate bmdma */
809 ap->ops->bmdma_start(qc);
810 break;
811#endif /* CONFIG_ATA_BMDMA */
812 default:
813 BUG();
814 }
815}
816
817/**
818 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
819 * @qc: Command on going
820 * @bytes: number of bytes
821 *
822 * Transfer Transfer data from/to the ATAPI device.
823 *
824 * LOCKING:
825 * Inherited from caller.
826 *
827 */
828static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
829{
830 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
831 struct ata_port *ap = qc->ap;
832 struct ata_device *dev = qc->dev;
833 struct ata_eh_info *ehi = &dev->link->eh_info;
834 struct scatterlist *sg;
835 struct page *page;
836 unsigned char *buf;
837 unsigned int offset, count, consumed;
838
839next_sg:
840 sg = qc->cursg;
841 if (unlikely(!sg)) {
842 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
843 "buf=%u cur=%u bytes=%u",
844 qc->nbytes, qc->curbytes, bytes);
845 return -1;
846 }
847
848 page = sg_page(sg);
849 offset = sg->offset + qc->cursg_ofs;
850
851 /* get the current page and offset */
852 page = nth_page(page, (offset >> PAGE_SHIFT));
853 offset %= PAGE_SIZE;
854
855 /* don't overrun current sg */
856 count = min(sg->length - qc->cursg_ofs, bytes);
857
858 /* don't cross page boundaries */
859 count = min(count, (unsigned int)PAGE_SIZE - offset);
860
861 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
862
863 if (PageHighMem(page)) {
864 unsigned long flags;
865
866 /* FIXME: use bounce buffer */
867 local_irq_save(flags);
868 buf = kmap_atomic(page);
869
870 /* do the actual data transfer */
871 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
872 count, rw);
873
874 kunmap_atomic(buf);
875 local_irq_restore(flags);
876 } else {
877 buf = page_address(page);
878 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
879 count, rw);
880 }
881
882 bytes -= min(bytes, consumed);
883 qc->curbytes += count;
884 qc->cursg_ofs += count;
885
886 if (qc->cursg_ofs == sg->length) {
887 qc->cursg = sg_next(qc->cursg);
888 qc->cursg_ofs = 0;
889 }
890
891 /*
892 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
893 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
894 * check correctly as it doesn't know if it is the last request being
895 * made. Somebody should implement a proper sanity check.
896 */
897 if (bytes)
898 goto next_sg;
899 return 0;
900}
901
902/**
903 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
904 * @qc: Command on going
905 *
906 * Transfer Transfer data from/to the ATAPI device.
907 *
908 * LOCKING:
909 * Inherited from caller.
910 */
911static void atapi_pio_bytes(struct ata_queued_cmd *qc)
912{
913 struct ata_port *ap = qc->ap;
914 struct ata_device *dev = qc->dev;
915 struct ata_eh_info *ehi = &dev->link->eh_info;
916 unsigned int ireason, bc_lo, bc_hi, bytes;
917 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
918
919 /* Abuse qc->result_tf for temp storage of intermediate TF
920 * here to save some kernel stack usage.
921 * For normal completion, qc->result_tf is not relevant. For
922 * error, qc->result_tf is later overwritten by ata_qc_complete().
923 * So, the correctness of qc->result_tf is not affected.
924 */
925 ap->ops->sff_tf_read(ap, &qc->result_tf);
926 ireason = qc->result_tf.nsect;
927 bc_lo = qc->result_tf.lbam;
928 bc_hi = qc->result_tf.lbah;
929 bytes = (bc_hi << 8) | bc_lo;
930
931 /* shall be cleared to zero, indicating xfer of data */
932 if (unlikely(ireason & ATAPI_COD))
933 goto atapi_check;
934
935 /* make sure transfer direction matches expected */
936 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
937 if (unlikely(do_write != i_write))
938 goto atapi_check;
939
940 if (unlikely(!bytes))
941 goto atapi_check;
942
943 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
944
945 if (unlikely(__atapi_pio_bytes(qc, bytes)))
946 goto err_out;
947 ata_sff_sync(ap); /* flush */
948
949 return;
950
951 atapi_check:
952 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
953 ireason, bytes);
954 err_out:
955 qc->err_mask |= AC_ERR_HSM;
956 ap->hsm_task_state = HSM_ST_ERR;
957}
958
959/**
960 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
961 * @ap: the target ata_port
962 * @qc: qc on going
963 *
964 * RETURNS:
965 * 1 if ok in workqueue, 0 otherwise.
966 */
967static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
968 struct ata_queued_cmd *qc)
969{
970 if (qc->tf.flags & ATA_TFLAG_POLLING)
971 return 1;
972
973 if (ap->hsm_task_state == HSM_ST_FIRST) {
974 if (qc->tf.protocol == ATA_PROT_PIO &&
975 (qc->tf.flags & ATA_TFLAG_WRITE))
976 return 1;
977
978 if (ata_is_atapi(qc->tf.protocol) &&
979 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
980 return 1;
981 }
982
983 return 0;
984}
985
986/**
987 * ata_hsm_qc_complete - finish a qc running on standard HSM
988 * @qc: Command to complete
989 * @in_wq: 1 if called from workqueue, 0 otherwise
990 *
991 * Finish @qc which is running on standard HSM.
992 *
993 * LOCKING:
994 * If @in_wq is zero, spin_lock_irqsave(host lock).
995 * Otherwise, none on entry and grabs host lock.
996 */
997static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
998{
999 struct ata_port *ap = qc->ap;
1000
1001 if (ap->ops->error_handler) {
1002 if (in_wq) {
1003 /* EH might have kicked in while host lock is
1004 * released.
1005 */
1006 qc = ata_qc_from_tag(ap, qc->tag);
1007 if (qc) {
1008 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1009 ata_sff_irq_on(ap);
1010 ata_qc_complete(qc);
1011 } else
1012 ata_port_freeze(ap);
1013 }
1014 } else {
1015 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1016 ata_qc_complete(qc);
1017 else
1018 ata_port_freeze(ap);
1019 }
1020 } else {
1021 if (in_wq) {
1022 ata_sff_irq_on(ap);
1023 ata_qc_complete(qc);
1024 } else
1025 ata_qc_complete(qc);
1026 }
1027}
1028
1029/**
1030 * ata_sff_hsm_move - move the HSM to the next state.
1031 * @ap: the target ata_port
1032 * @qc: qc on going
1033 * @status: current device status
1034 * @in_wq: 1 if called from workqueue, 0 otherwise
1035 *
1036 * RETURNS:
1037 * 1 when poll next status needed, 0 otherwise.
1038 */
1039int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1040 u8 status, int in_wq)
1041{
1042 struct ata_link *link = qc->dev->link;
1043 struct ata_eh_info *ehi = &link->eh_info;
1044 int poll_next;
1045
1046 lockdep_assert_held(ap->lock);
1047
1048 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1049
1050 /* Make sure ata_sff_qc_issue() does not throw things
1051 * like DMA polling into the workqueue. Notice that
1052 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1053 */
1054 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1055
1056fsm_start:
1057 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1058 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1059
1060 switch (ap->hsm_task_state) {
1061 case HSM_ST_FIRST:
1062 /* Send first data block or PACKET CDB */
1063
1064 /* If polling, we will stay in the work queue after
1065 * sending the data. Otherwise, interrupt handler
1066 * takes over after sending the data.
1067 */
1068 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1069
1070 /* check device status */
1071 if (unlikely((status & ATA_DRQ) == 0)) {
1072 /* handle BSY=0, DRQ=0 as error */
1073 if (likely(status & (ATA_ERR | ATA_DF)))
1074 /* device stops HSM for abort/error */
1075 qc->err_mask |= AC_ERR_DEV;
1076 else {
1077 /* HSM violation. Let EH handle this */
1078 ata_ehi_push_desc(ehi,
1079 "ST_FIRST: !(DRQ|ERR|DF)");
1080 qc->err_mask |= AC_ERR_HSM;
1081 }
1082
1083 ap->hsm_task_state = HSM_ST_ERR;
1084 goto fsm_start;
1085 }
1086
1087 /* Device should not ask for data transfer (DRQ=1)
1088 * when it finds something wrong.
1089 * We ignore DRQ here and stop the HSM by
1090 * changing hsm_task_state to HSM_ST_ERR and
1091 * let the EH abort the command or reset the device.
1092 */
1093 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1094 /* Some ATAPI tape drives forget to clear the ERR bit
1095 * when doing the next command (mostly request sense).
1096 * We ignore ERR here to workaround and proceed sending
1097 * the CDB.
1098 */
1099 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1100 ata_ehi_push_desc(ehi, "ST_FIRST: "
1101 "DRQ=1 with device error, "
1102 "dev_stat 0x%X", status);
1103 qc->err_mask |= AC_ERR_HSM;
1104 ap->hsm_task_state = HSM_ST_ERR;
1105 goto fsm_start;
1106 }
1107 }
1108
1109 if (qc->tf.protocol == ATA_PROT_PIO) {
1110 /* PIO data out protocol.
1111 * send first data block.
1112 */
1113
1114 /* ata_pio_sectors() might change the state
1115 * to HSM_ST_LAST. so, the state is changed here
1116 * before ata_pio_sectors().
1117 */
1118 ap->hsm_task_state = HSM_ST;
1119 ata_pio_sectors(qc);
1120 } else
1121 /* send CDB */
1122 atapi_send_cdb(ap, qc);
1123
1124 /* if polling, ata_sff_pio_task() handles the rest.
1125 * otherwise, interrupt handler takes over from here.
1126 */
1127 break;
1128
1129 case HSM_ST:
1130 /* complete command or read/write the data register */
1131 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1132 /* ATAPI PIO protocol */
1133 if ((status & ATA_DRQ) == 0) {
1134 /* No more data to transfer or device error.
1135 * Device error will be tagged in HSM_ST_LAST.
1136 */
1137 ap->hsm_task_state = HSM_ST_LAST;
1138 goto fsm_start;
1139 }
1140
1141 /* Device should not ask for data transfer (DRQ=1)
1142 * when it finds something wrong.
1143 * We ignore DRQ here and stop the HSM by
1144 * changing hsm_task_state to HSM_ST_ERR and
1145 * let the EH abort the command or reset the device.
1146 */
1147 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1148 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1149 "DRQ=1 with device error, "
1150 "dev_stat 0x%X", status);
1151 qc->err_mask |= AC_ERR_HSM;
1152 ap->hsm_task_state = HSM_ST_ERR;
1153 goto fsm_start;
1154 }
1155
1156 atapi_pio_bytes(qc);
1157
1158 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1159 /* bad ireason reported by device */
1160 goto fsm_start;
1161
1162 } else {
1163 /* ATA PIO protocol */
1164 if (unlikely((status & ATA_DRQ) == 0)) {
1165 /* handle BSY=0, DRQ=0 as error */
1166 if (likely(status & (ATA_ERR | ATA_DF))) {
1167 /* device stops HSM for abort/error */
1168 qc->err_mask |= AC_ERR_DEV;
1169
1170 /* If diagnostic failed and this is
1171 * IDENTIFY, it's likely a phantom
1172 * device. Mark hint.
1173 */
1174 if (qc->dev->horkage &
1175 ATA_HORKAGE_DIAGNOSTIC)
1176 qc->err_mask |=
1177 AC_ERR_NODEV_HINT;
1178 } else {
1179 /* HSM violation. Let EH handle this.
1180 * Phantom devices also trigger this
1181 * condition. Mark hint.
1182 */
1183 ata_ehi_push_desc(ehi, "ST-ATA: "
1184 "DRQ=0 without device error, "
1185 "dev_stat 0x%X", status);
1186 qc->err_mask |= AC_ERR_HSM |
1187 AC_ERR_NODEV_HINT;
1188 }
1189
1190 ap->hsm_task_state = HSM_ST_ERR;
1191 goto fsm_start;
1192 }
1193
1194 /* For PIO reads, some devices may ask for
1195 * data transfer (DRQ=1) alone with ERR=1.
1196 * We respect DRQ here and transfer one
1197 * block of junk data before changing the
1198 * hsm_task_state to HSM_ST_ERR.
1199 *
1200 * For PIO writes, ERR=1 DRQ=1 doesn't make
1201 * sense since the data block has been
1202 * transferred to the device.
1203 */
1204 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1205 /* data might be corrputed */
1206 qc->err_mask |= AC_ERR_DEV;
1207
1208 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1209 ata_pio_sectors(qc);
1210 status = ata_wait_idle(ap);
1211 }
1212
1213 if (status & (ATA_BUSY | ATA_DRQ)) {
1214 ata_ehi_push_desc(ehi, "ST-ATA: "
1215 "BUSY|DRQ persists on ERR|DF, "
1216 "dev_stat 0x%X", status);
1217 qc->err_mask |= AC_ERR_HSM;
1218 }
1219
1220 /* There are oddball controllers with
1221 * status register stuck at 0x7f and
1222 * lbal/m/h at zero which makes it
1223 * pass all other presence detection
1224 * mechanisms we have. Set NODEV_HINT
1225 * for it. Kernel bz#7241.
1226 */
1227 if (status == 0x7f)
1228 qc->err_mask |= AC_ERR_NODEV_HINT;
1229
1230 /* ata_pio_sectors() might change the
1231 * state to HSM_ST_LAST. so, the state
1232 * is changed after ata_pio_sectors().
1233 */
1234 ap->hsm_task_state = HSM_ST_ERR;
1235 goto fsm_start;
1236 }
1237
1238 ata_pio_sectors(qc);
1239
1240 if (ap->hsm_task_state == HSM_ST_LAST &&
1241 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1242 /* all data read */
1243 status = ata_wait_idle(ap);
1244 goto fsm_start;
1245 }
1246 }
1247
1248 poll_next = 1;
1249 break;
1250
1251 case HSM_ST_LAST:
1252 if (unlikely(!ata_ok(status))) {
1253 qc->err_mask |= __ac_err_mask(status);
1254 ap->hsm_task_state = HSM_ST_ERR;
1255 goto fsm_start;
1256 }
1257
1258 /* no more data to transfer */
1259 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1260 ap->print_id, qc->dev->devno, status);
1261
1262 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1263
1264 ap->hsm_task_state = HSM_ST_IDLE;
1265
1266 /* complete taskfile transaction */
1267 ata_hsm_qc_complete(qc, in_wq);
1268
1269 poll_next = 0;
1270 break;
1271
1272 case HSM_ST_ERR:
1273 ap->hsm_task_state = HSM_ST_IDLE;
1274
1275 /* complete taskfile transaction */
1276 ata_hsm_qc_complete(qc, in_wq);
1277
1278 poll_next = 0;
1279 break;
1280 default:
1281 poll_next = 0;
1282 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1283 ap->print_id, ap->hsm_task_state);
1284 }
1285
1286 return poll_next;
1287}
1288EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1289
1290void ata_sff_queue_work(struct work_struct *work)
1291{
1292 queue_work(ata_sff_wq, work);
1293}
1294EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1295
1296void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1297{
1298 queue_delayed_work(ata_sff_wq, dwork, delay);
1299}
1300EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1301
1302void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1303{
1304 struct ata_port *ap = link->ap;
1305
1306 WARN_ON((ap->sff_pio_task_link != NULL) &&
1307 (ap->sff_pio_task_link != link));
1308 ap->sff_pio_task_link = link;
1309
1310 /* may fail if ata_sff_flush_pio_task() in progress */
1311 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1312}
1313EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1314
1315void ata_sff_flush_pio_task(struct ata_port *ap)
1316{
1317 DPRINTK("ENTER\n");
1318
1319 cancel_delayed_work_sync(&ap->sff_pio_task);
1320
1321 /*
1322 * We wanna reset the HSM state to IDLE. If we do so without
1323 * grabbing the port lock, critical sections protected by it which
1324 * expect the HSM state to stay stable may get surprised. For
1325 * example, we may set IDLE in between the time
1326 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1327 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1328 */
1329 spin_lock_irq(ap->lock);
1330 ap->hsm_task_state = HSM_ST_IDLE;
1331 spin_unlock_irq(ap->lock);
1332
1333 ap->sff_pio_task_link = NULL;
1334
1335 if (ata_msg_ctl(ap))
1336 ata_port_dbg(ap, "%s: EXIT\n", __func__);
1337}
1338
1339static void ata_sff_pio_task(struct work_struct *work)
1340{
1341 struct ata_port *ap =
1342 container_of(work, struct ata_port, sff_pio_task.work);
1343 struct ata_link *link = ap->sff_pio_task_link;
1344 struct ata_queued_cmd *qc;
1345 u8 status;
1346 int poll_next;
1347
1348 spin_lock_irq(ap->lock);
1349
1350 BUG_ON(ap->sff_pio_task_link == NULL);
1351 /* qc can be NULL if timeout occurred */
1352 qc = ata_qc_from_tag(ap, link->active_tag);
1353 if (!qc) {
1354 ap->sff_pio_task_link = NULL;
1355 goto out_unlock;
1356 }
1357
1358fsm_start:
1359 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1360
1361 /*
1362 * This is purely heuristic. This is a fast path.
1363 * Sometimes when we enter, BSY will be cleared in
1364 * a chk-status or two. If not, the drive is probably seeking
1365 * or something. Snooze for a couple msecs, then
1366 * chk-status again. If still busy, queue delayed work.
1367 */
1368 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1369 if (status & ATA_BUSY) {
1370 spin_unlock_irq(ap->lock);
1371 ata_msleep(ap, 2);
1372 spin_lock_irq(ap->lock);
1373
1374 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1375 if (status & ATA_BUSY) {
1376 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1377 goto out_unlock;
1378 }
1379 }
1380
1381 /*
1382 * hsm_move() may trigger another command to be processed.
1383 * clean the link beforehand.
1384 */
1385 ap->sff_pio_task_link = NULL;
1386 /* move the HSM */
1387 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1388
1389 /* another command or interrupt handler
1390 * may be running at this point.
1391 */
1392 if (poll_next)
1393 goto fsm_start;
1394out_unlock:
1395 spin_unlock_irq(ap->lock);
1396}
1397
1398/**
1399 * ata_sff_qc_issue - issue taskfile to a SFF controller
1400 * @qc: command to issue to device
1401 *
1402 * This function issues a PIO or NODATA command to a SFF
1403 * controller.
1404 *
1405 * LOCKING:
1406 * spin_lock_irqsave(host lock)
1407 *
1408 * RETURNS:
1409 * Zero on success, AC_ERR_* mask on failure
1410 */
1411unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1412{
1413 struct ata_port *ap = qc->ap;
1414 struct ata_link *link = qc->dev->link;
1415
1416 /* Use polling pio if the LLD doesn't handle
1417 * interrupt driven pio and atapi CDB interrupt.
1418 */
1419 if (ap->flags & ATA_FLAG_PIO_POLLING)
1420 qc->tf.flags |= ATA_TFLAG_POLLING;
1421
1422 /* select the device */
1423 ata_dev_select(ap, qc->dev->devno, 1, 0);
1424
1425 /* start the command */
1426 switch (qc->tf.protocol) {
1427 case ATA_PROT_NODATA:
1428 if (qc->tf.flags & ATA_TFLAG_POLLING)
1429 ata_qc_set_polling(qc);
1430
1431 ata_tf_to_host(ap, &qc->tf);
1432 ap->hsm_task_state = HSM_ST_LAST;
1433
1434 if (qc->tf.flags & ATA_TFLAG_POLLING)
1435 ata_sff_queue_pio_task(link, 0);
1436
1437 break;
1438
1439 case ATA_PROT_PIO:
1440 if (qc->tf.flags & ATA_TFLAG_POLLING)
1441 ata_qc_set_polling(qc);
1442
1443 ata_tf_to_host(ap, &qc->tf);
1444
1445 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1446 /* PIO data out protocol */
1447 ap->hsm_task_state = HSM_ST_FIRST;
1448 ata_sff_queue_pio_task(link, 0);
1449
1450 /* always send first data block using the
1451 * ata_sff_pio_task() codepath.
1452 */
1453 } else {
1454 /* PIO data in protocol */
1455 ap->hsm_task_state = HSM_ST;
1456
1457 if (qc->tf.flags & ATA_TFLAG_POLLING)
1458 ata_sff_queue_pio_task(link, 0);
1459
1460 /* if polling, ata_sff_pio_task() handles the
1461 * rest. otherwise, interrupt handler takes
1462 * over from here.
1463 */
1464 }
1465
1466 break;
1467
1468 case ATAPI_PROT_PIO:
1469 case ATAPI_PROT_NODATA:
1470 if (qc->tf.flags & ATA_TFLAG_POLLING)
1471 ata_qc_set_polling(qc);
1472
1473 ata_tf_to_host(ap, &qc->tf);
1474
1475 ap->hsm_task_state = HSM_ST_FIRST;
1476
1477 /* send cdb by polling if no cdb interrupt */
1478 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1479 (qc->tf.flags & ATA_TFLAG_POLLING))
1480 ata_sff_queue_pio_task(link, 0);
1481 break;
1482
1483 default:
1484 WARN_ON_ONCE(1);
1485 return AC_ERR_SYSTEM;
1486 }
1487
1488 return 0;
1489}
1490EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1491
1492/**
1493 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1494 * @qc: qc to fill result TF for
1495 *
1496 * @qc is finished and result TF needs to be filled. Fill it
1497 * using ->sff_tf_read.
1498 *
1499 * LOCKING:
1500 * spin_lock_irqsave(host lock)
1501 *
1502 * RETURNS:
1503 * true indicating that result TF is successfully filled.
1504 */
1505bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1506{
1507 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1508 return true;
1509}
1510EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1511
1512static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1513{
1514 ap->stats.idle_irq++;
1515
1516#ifdef ATA_IRQ_TRAP
1517 if ((ap->stats.idle_irq % 1000) == 0) {
1518 ap->ops->sff_check_status(ap);
1519 if (ap->ops->sff_irq_clear)
1520 ap->ops->sff_irq_clear(ap);
1521 ata_port_warn(ap, "irq trap\n");
1522 return 1;
1523 }
1524#endif
1525 return 0; /* irq not handled */
1526}
1527
1528static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1529 struct ata_queued_cmd *qc,
1530 bool hsmv_on_idle)
1531{
1532 u8 status;
1533
1534 VPRINTK("ata%u: protocol %d task_state %d\n",
1535 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1536
1537 /* Check whether we are expecting interrupt in this state */
1538 switch (ap->hsm_task_state) {
1539 case HSM_ST_FIRST:
1540 /* Some pre-ATAPI-4 devices assert INTRQ
1541 * at this state when ready to receive CDB.
1542 */
1543
1544 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1545 * The flag was turned on only for atapi devices. No
1546 * need to check ata_is_atapi(qc->tf.protocol) again.
1547 */
1548 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1549 return ata_sff_idle_irq(ap);
1550 break;
1551 case HSM_ST_IDLE:
1552 return ata_sff_idle_irq(ap);
1553 default:
1554 break;
1555 }
1556
1557 /* check main status, clearing INTRQ if needed */
1558 status = ata_sff_irq_status(ap);
1559 if (status & ATA_BUSY) {
1560 if (hsmv_on_idle) {
1561 /* BMDMA engine is already stopped, we're screwed */
1562 qc->err_mask |= AC_ERR_HSM;
1563 ap->hsm_task_state = HSM_ST_ERR;
1564 } else
1565 return ata_sff_idle_irq(ap);
1566 }
1567
1568 /* clear irq events */
1569 if (ap->ops->sff_irq_clear)
1570 ap->ops->sff_irq_clear(ap);
1571
1572 ata_sff_hsm_move(ap, qc, status, 0);
1573
1574 return 1; /* irq handled */
1575}
1576
1577/**
1578 * ata_sff_port_intr - Handle SFF port interrupt
1579 * @ap: Port on which interrupt arrived (possibly...)
1580 * @qc: Taskfile currently active in engine
1581 *
1582 * Handle port interrupt for given queued command.
1583 *
1584 * LOCKING:
1585 * spin_lock_irqsave(host lock)
1586 *
1587 * RETURNS:
1588 * One if interrupt was handled, zero if not (shared irq).
1589 */
1590unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1591{
1592 return __ata_sff_port_intr(ap, qc, false);
1593}
1594EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1595
1596static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1597 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1598{
1599 struct ata_host *host = dev_instance;
1600 bool retried = false;
1601 unsigned int i;
1602 unsigned int handled, idle, polling;
1603 unsigned long flags;
1604
1605 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1606 spin_lock_irqsave(&host->lock, flags);
1607
1608retry:
1609 handled = idle = polling = 0;
1610 for (i = 0; i < host->n_ports; i++) {
1611 struct ata_port *ap = host->ports[i];
1612 struct ata_queued_cmd *qc;
1613
1614 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1615 if (qc) {
1616 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1617 handled |= port_intr(ap, qc);
1618 else
1619 polling |= 1 << i;
1620 } else
1621 idle |= 1 << i;
1622 }
1623
1624 /*
1625 * If no port was expecting IRQ but the controller is actually
1626 * asserting IRQ line, nobody cared will ensue. Check IRQ
1627 * pending status if available and clear spurious IRQ.
1628 */
1629 if (!handled && !retried) {
1630 bool retry = false;
1631
1632 for (i = 0; i < host->n_ports; i++) {
1633 struct ata_port *ap = host->ports[i];
1634
1635 if (polling & (1 << i))
1636 continue;
1637
1638 if (!ap->ops->sff_irq_check ||
1639 !ap->ops->sff_irq_check(ap))
1640 continue;
1641
1642 if (idle & (1 << i)) {
1643 ap->ops->sff_check_status(ap);
1644 if (ap->ops->sff_irq_clear)
1645 ap->ops->sff_irq_clear(ap);
1646 } else {
1647 /* clear INTRQ and check if BUSY cleared */
1648 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1649 retry |= true;
1650 /*
1651 * With command in flight, we can't do
1652 * sff_irq_clear() w/o racing with completion.
1653 */
1654 }
1655 }
1656
1657 if (retry) {
1658 retried = true;
1659 goto retry;
1660 }
1661 }
1662
1663 spin_unlock_irqrestore(&host->lock, flags);
1664
1665 return IRQ_RETVAL(handled);
1666}
1667
1668/**
1669 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1670 * @irq: irq line (unused)
1671 * @dev_instance: pointer to our ata_host information structure
1672 *
1673 * Default interrupt handler for PCI IDE devices. Calls
1674 * ata_sff_port_intr() for each port that is not disabled.
1675 *
1676 * LOCKING:
1677 * Obtains host lock during operation.
1678 *
1679 * RETURNS:
1680 * IRQ_NONE or IRQ_HANDLED.
1681 */
1682irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1683{
1684 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1685}
1686EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1687
1688/**
1689 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1690 * @ap: port that appears to have timed out
1691 *
1692 * Called from the libata error handlers when the core code suspects
1693 * an interrupt has been lost. If it has complete anything we can and
1694 * then return. Interface must support altstatus for this faster
1695 * recovery to occur.
1696 *
1697 * Locking:
1698 * Caller holds host lock
1699 */
1700
1701void ata_sff_lost_interrupt(struct ata_port *ap)
1702{
1703 u8 status;
1704 struct ata_queued_cmd *qc;
1705
1706 /* Only one outstanding command per SFF channel */
1707 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1708 /* We cannot lose an interrupt on a non-existent or polled command */
1709 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1710 return;
1711 /* See if the controller thinks it is still busy - if so the command
1712 isn't a lost IRQ but is still in progress */
1713 status = ata_sff_altstatus(ap);
1714 if (status & ATA_BUSY)
1715 return;
1716
1717 /* There was a command running, we are no longer busy and we have
1718 no interrupt. */
1719 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n",
1720 status);
1721 /* Run the host interrupt logic as if the interrupt had not been
1722 lost */
1723 ata_sff_port_intr(ap, qc);
1724}
1725EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1726
1727/**
1728 * ata_sff_freeze - Freeze SFF controller port
1729 * @ap: port to freeze
1730 *
1731 * Freeze SFF controller port.
1732 *
1733 * LOCKING:
1734 * Inherited from caller.
1735 */
1736void ata_sff_freeze(struct ata_port *ap)
1737{
1738 ap->ctl |= ATA_NIEN;
1739 ap->last_ctl = ap->ctl;
1740
1741 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr)
1742 ata_sff_set_devctl(ap, ap->ctl);
1743
1744 /* Under certain circumstances, some controllers raise IRQ on
1745 * ATA_NIEN manipulation. Also, many controllers fail to mask
1746 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1747 */
1748 ap->ops->sff_check_status(ap);
1749
1750 if (ap->ops->sff_irq_clear)
1751 ap->ops->sff_irq_clear(ap);
1752}
1753EXPORT_SYMBOL_GPL(ata_sff_freeze);
1754
1755/**
1756 * ata_sff_thaw - Thaw SFF controller port
1757 * @ap: port to thaw
1758 *
1759 * Thaw SFF controller port.
1760 *
1761 * LOCKING:
1762 * Inherited from caller.
1763 */
1764void ata_sff_thaw(struct ata_port *ap)
1765{
1766 /* clear & re-enable interrupts */
1767 ap->ops->sff_check_status(ap);
1768 if (ap->ops->sff_irq_clear)
1769 ap->ops->sff_irq_clear(ap);
1770 ata_sff_irq_on(ap);
1771}
1772EXPORT_SYMBOL_GPL(ata_sff_thaw);
1773
1774/**
1775 * ata_sff_prereset - prepare SFF link for reset
1776 * @link: SFF link to be reset
1777 * @deadline: deadline jiffies for the operation
1778 *
1779 * SFF link @link is about to be reset. Initialize it. It first
1780 * calls ata_std_prereset() and wait for !BSY if the port is
1781 * being softreset.
1782 *
1783 * LOCKING:
1784 * Kernel thread context (may sleep)
1785 *
1786 * RETURNS:
1787 * 0 on success, -errno otherwise.
1788 */
1789int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1790{
1791 struct ata_eh_context *ehc = &link->eh_context;
1792 int rc;
1793
1794 rc = ata_std_prereset(link, deadline);
1795 if (rc)
1796 return rc;
1797
1798 /* if we're about to do hardreset, nothing more to do */
1799 if (ehc->i.action & ATA_EH_HARDRESET)
1800 return 0;
1801
1802 /* wait for !BSY if we don't know that no device is attached */
1803 if (!ata_link_offline(link)) {
1804 rc = ata_sff_wait_ready(link, deadline);
1805 if (rc && rc != -ENODEV) {
1806 ata_link_warn(link,
1807 "device not ready (errno=%d), forcing hardreset\n",
1808 rc);
1809 ehc->i.action |= ATA_EH_HARDRESET;
1810 }
1811 }
1812
1813 return 0;
1814}
1815EXPORT_SYMBOL_GPL(ata_sff_prereset);
1816
1817/**
1818 * ata_devchk - PATA device presence detection
1819 * @ap: ATA channel to examine
1820 * @device: Device to examine (starting at zero)
1821 *
1822 * This technique was originally described in
1823 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1824 * later found its way into the ATA/ATAPI spec.
1825 *
1826 * Write a pattern to the ATA shadow registers,
1827 * and if a device is present, it will respond by
1828 * correctly storing and echoing back the
1829 * ATA shadow register contents.
1830 *
1831 * LOCKING:
1832 * caller.
1833 */
1834static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1835{
1836 struct ata_ioports *ioaddr = &ap->ioaddr;
1837 u8 nsect, lbal;
1838
1839 ap->ops->sff_dev_select(ap, device);
1840
1841 iowrite8(0x55, ioaddr->nsect_addr);
1842 iowrite8(0xaa, ioaddr->lbal_addr);
1843
1844 iowrite8(0xaa, ioaddr->nsect_addr);
1845 iowrite8(0x55, ioaddr->lbal_addr);
1846
1847 iowrite8(0x55, ioaddr->nsect_addr);
1848 iowrite8(0xaa, ioaddr->lbal_addr);
1849
1850 nsect = ioread8(ioaddr->nsect_addr);
1851 lbal = ioread8(ioaddr->lbal_addr);
1852
1853 if ((nsect == 0x55) && (lbal == 0xaa))
1854 return 1; /* we found a device */
1855
1856 return 0; /* nothing found */
1857}
1858
1859/**
1860 * ata_sff_dev_classify - Parse returned ATA device signature
1861 * @dev: ATA device to classify (starting at zero)
1862 * @present: device seems present
1863 * @r_err: Value of error register on completion
1864 *
1865 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1866 * an ATA/ATAPI-defined set of values is placed in the ATA
1867 * shadow registers, indicating the results of device detection
1868 * and diagnostics.
1869 *
1870 * Select the ATA device, and read the values from the ATA shadow
1871 * registers. Then parse according to the Error register value,
1872 * and the spec-defined values examined by ata_dev_classify().
1873 *
1874 * LOCKING:
1875 * caller.
1876 *
1877 * RETURNS:
1878 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1879 */
1880unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1881 u8 *r_err)
1882{
1883 struct ata_port *ap = dev->link->ap;
1884 struct ata_taskfile tf;
1885 unsigned int class;
1886 u8 err;
1887
1888 ap->ops->sff_dev_select(ap, dev->devno);
1889
1890 memset(&tf, 0, sizeof(tf));
1891
1892 ap->ops->sff_tf_read(ap, &tf);
1893 err = tf.feature;
1894 if (r_err)
1895 *r_err = err;
1896
1897 /* see if device passed diags: continue and warn later */
1898 if (err == 0)
1899 /* diagnostic fail : do nothing _YET_ */
1900 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1901 else if (err == 1)
1902 /* do nothing */ ;
1903 else if ((dev->devno == 0) && (err == 0x81))
1904 /* do nothing */ ;
1905 else
1906 return ATA_DEV_NONE;
1907
1908 /* determine if device is ATA or ATAPI */
1909 class = ata_dev_classify(&tf);
1910
1911 if (class == ATA_DEV_UNKNOWN) {
1912 /* If the device failed diagnostic, it's likely to
1913 * have reported incorrect device signature too.
1914 * Assume ATA device if the device seems present but
1915 * device signature is invalid with diagnostic
1916 * failure.
1917 */
1918 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1919 class = ATA_DEV_ATA;
1920 else
1921 class = ATA_DEV_NONE;
1922 } else if ((class == ATA_DEV_ATA) &&
1923 (ap->ops->sff_check_status(ap) == 0))
1924 class = ATA_DEV_NONE;
1925
1926 return class;
1927}
1928EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1929
1930/**
1931 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1932 * @link: SFF link which is just reset
1933 * @devmask: mask of present devices
1934 * @deadline: deadline jiffies for the operation
1935 *
1936 * Wait devices attached to SFF @link to become ready after
1937 * reset. It contains preceding 150ms wait to avoid accessing TF
1938 * status register too early.
1939 *
1940 * LOCKING:
1941 * Kernel thread context (may sleep).
1942 *
1943 * RETURNS:
1944 * 0 on success, -ENODEV if some or all of devices in @devmask
1945 * don't seem to exist. -errno on other errors.
1946 */
1947int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1948 unsigned long deadline)
1949{
1950 struct ata_port *ap = link->ap;
1951 struct ata_ioports *ioaddr = &ap->ioaddr;
1952 unsigned int dev0 = devmask & (1 << 0);
1953 unsigned int dev1 = devmask & (1 << 1);
1954 int rc, ret = 0;
1955
1956 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1957
1958 /* always check readiness of the master device */
1959 rc = ata_sff_wait_ready(link, deadline);
1960 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1961 * and TF status is 0xff, bail out on it too.
1962 */
1963 if (rc)
1964 return rc;
1965
1966 /* if device 1 was found in ata_devchk, wait for register
1967 * access briefly, then wait for BSY to clear.
1968 */
1969 if (dev1) {
1970 int i;
1971
1972 ap->ops->sff_dev_select(ap, 1);
1973
1974 /* Wait for register access. Some ATAPI devices fail
1975 * to set nsect/lbal after reset, so don't waste too
1976 * much time on it. We're gonna wait for !BSY anyway.
1977 */
1978 for (i = 0; i < 2; i++) {
1979 u8 nsect, lbal;
1980
1981 nsect = ioread8(ioaddr->nsect_addr);
1982 lbal = ioread8(ioaddr->lbal_addr);
1983 if ((nsect == 1) && (lbal == 1))
1984 break;
1985 ata_msleep(ap, 50); /* give drive a breather */
1986 }
1987
1988 rc = ata_sff_wait_ready(link, deadline);
1989 if (rc) {
1990 if (rc != -ENODEV)
1991 return rc;
1992 ret = rc;
1993 }
1994 }
1995
1996 /* is all this really necessary? */
1997 ap->ops->sff_dev_select(ap, 0);
1998 if (dev1)
1999 ap->ops->sff_dev_select(ap, 1);
2000 if (dev0)
2001 ap->ops->sff_dev_select(ap, 0);
2002
2003 return ret;
2004}
2005EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2006
2007static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2008 unsigned long deadline)
2009{
2010 struct ata_ioports *ioaddr = &ap->ioaddr;
2011
2012 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2013
2014 if (ap->ioaddr.ctl_addr) {
2015 /* software reset. causes dev0 to be selected */
2016 iowrite8(ap->ctl, ioaddr->ctl_addr);
2017 udelay(20); /* FIXME: flush */
2018 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2019 udelay(20); /* FIXME: flush */
2020 iowrite8(ap->ctl, ioaddr->ctl_addr);
2021 ap->last_ctl = ap->ctl;
2022 }
2023
2024 /* wait the port to become ready */
2025 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2026}
2027
2028/**
2029 * ata_sff_softreset - reset host port via ATA SRST
2030 * @link: ATA link to reset
2031 * @classes: resulting classes of attached devices
2032 * @deadline: deadline jiffies for the operation
2033 *
2034 * Reset host port using ATA SRST.
2035 *
2036 * LOCKING:
2037 * Kernel thread context (may sleep)
2038 *
2039 * RETURNS:
2040 * 0 on success, -errno otherwise.
2041 */
2042int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2043 unsigned long deadline)
2044{
2045 struct ata_port *ap = link->ap;
2046 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2047 unsigned int devmask = 0;
2048 int rc;
2049 u8 err;
2050
2051 DPRINTK("ENTER\n");
2052
2053 /* determine if device 0/1 are present */
2054 if (ata_devchk(ap, 0))
2055 devmask |= (1 << 0);
2056 if (slave_possible && ata_devchk(ap, 1))
2057 devmask |= (1 << 1);
2058
2059 /* select device 0 again */
2060 ap->ops->sff_dev_select(ap, 0);
2061
2062 /* issue bus reset */
2063 DPRINTK("about to softreset, devmask=%x\n", devmask);
2064 rc = ata_bus_softreset(ap, devmask, deadline);
2065 /* if link is occupied, -ENODEV too is an error */
2066 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2067 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
2068 return rc;
2069 }
2070
2071 /* determine by signature whether we have ATA or ATAPI devices */
2072 classes[0] = ata_sff_dev_classify(&link->device[0],
2073 devmask & (1 << 0), &err);
2074 if (slave_possible && err != 0x81)
2075 classes[1] = ata_sff_dev_classify(&link->device[1],
2076 devmask & (1 << 1), &err);
2077
2078 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2079 return 0;
2080}
2081EXPORT_SYMBOL_GPL(ata_sff_softreset);
2082
2083/**
2084 * sata_sff_hardreset - reset host port via SATA phy reset
2085 * @link: link to reset
2086 * @class: resulting class of attached device
2087 * @deadline: deadline jiffies for the operation
2088 *
2089 * SATA phy-reset host port using DET bits of SControl register,
2090 * wait for !BSY and classify the attached device.
2091 *
2092 * LOCKING:
2093 * Kernel thread context (may sleep)
2094 *
2095 * RETURNS:
2096 * 0 on success, -errno otherwise.
2097 */
2098int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2099 unsigned long deadline)
2100{
2101 struct ata_eh_context *ehc = &link->eh_context;
2102 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2103 bool online;
2104 int rc;
2105
2106 rc = sata_link_hardreset(link, timing, deadline, &online,
2107 ata_sff_check_ready);
2108 if (online)
2109 *class = ata_sff_dev_classify(link->device, 1, NULL);
2110
2111 DPRINTK("EXIT, class=%u\n", *class);
2112 return rc;
2113}
2114EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2115
2116/**
2117 * ata_sff_postreset - SFF postreset callback
2118 * @link: the target SFF ata_link
2119 * @classes: classes of attached devices
2120 *
2121 * This function is invoked after a successful reset. It first
2122 * calls ata_std_postreset() and performs SFF specific postreset
2123 * processing.
2124 *
2125 * LOCKING:
2126 * Kernel thread context (may sleep)
2127 */
2128void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2129{
2130 struct ata_port *ap = link->ap;
2131
2132 ata_std_postreset(link, classes);
2133
2134 /* is double-select really necessary? */
2135 if (classes[0] != ATA_DEV_NONE)
2136 ap->ops->sff_dev_select(ap, 1);
2137 if (classes[1] != ATA_DEV_NONE)
2138 ap->ops->sff_dev_select(ap, 0);
2139
2140 /* bail out if no device is present */
2141 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2142 DPRINTK("EXIT, no device\n");
2143 return;
2144 }
2145
2146 /* set up device control */
2147 if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) {
2148 ata_sff_set_devctl(ap, ap->ctl);
2149 ap->last_ctl = ap->ctl;
2150 }
2151}
2152EXPORT_SYMBOL_GPL(ata_sff_postreset);
2153
2154/**
2155 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2156 * @qc: command
2157 *
2158 * Drain the FIFO and device of any stuck data following a command
2159 * failing to complete. In some cases this is necessary before a
2160 * reset will recover the device.
2161 *
2162 */
2163
2164void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2165{
2166 int count;
2167 struct ata_port *ap;
2168
2169 /* We only need to flush incoming data when a command was running */
2170 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2171 return;
2172
2173 ap = qc->ap;
2174 /* Drain up to 64K of data before we give up this recovery method */
2175 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2176 && count < 65536; count += 2)
2177 ioread16(ap->ioaddr.data_addr);
2178
2179 /* Can become DEBUG later */
2180 if (count)
2181 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2182
2183}
2184EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2185
2186/**
2187 * ata_sff_error_handler - Stock error handler for SFF controller
2188 * @ap: port to handle error for
2189 *
2190 * Stock error handler for SFF controller. It can handle both
2191 * PATA and SATA controllers. Many controllers should be able to
2192 * use this EH as-is or with some added handling before and
2193 * after.
2194 *
2195 * LOCKING:
2196 * Kernel thread context (may sleep)
2197 */
2198void ata_sff_error_handler(struct ata_port *ap)
2199{
2200 ata_reset_fn_t softreset = ap->ops->softreset;
2201 ata_reset_fn_t hardreset = ap->ops->hardreset;
2202 struct ata_queued_cmd *qc;
2203 unsigned long flags;
2204
2205 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2206 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2207 qc = NULL;
2208
2209 spin_lock_irqsave(ap->lock, flags);
2210
2211 /*
2212 * We *MUST* do FIFO draining before we issue a reset as
2213 * several devices helpfully clear their internal state and
2214 * will lock solid if we touch the data port post reset. Pass
2215 * qc in case anyone wants to do different PIO/DMA recovery or
2216 * has per command fixups
2217 */
2218 if (ap->ops->sff_drain_fifo)
2219 ap->ops->sff_drain_fifo(qc);
2220
2221 spin_unlock_irqrestore(ap->lock, flags);
2222
2223 /* ignore built-in hardresets if SCR access is not available */
2224 if ((hardreset == sata_std_hardreset ||
2225 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2226 hardreset = NULL;
2227
2228 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2229 ap->ops->postreset);
2230}
2231EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2232
2233/**
2234 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2235 * @ioaddr: IO address structure to be initialized
2236 *
2237 * Utility function which initializes data_addr, error_addr,
2238 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2239 * device_addr, status_addr, and command_addr to standard offsets
2240 * relative to cmd_addr.
2241 *
2242 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2243 */
2244void ata_sff_std_ports(struct ata_ioports *ioaddr)
2245{
2246 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2247 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2248 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2249 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2250 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2251 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2252 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2253 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2254 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2255 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2256}
2257EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2258
2259#ifdef CONFIG_PCI
2260
2261static int ata_resources_present(struct pci_dev *pdev, int port)
2262{
2263 int i;
2264
2265 /* Check the PCI resources for this channel are enabled */
2266 port = port * 2;
2267 for (i = 0; i < 2; i++) {
2268 if (pci_resource_start(pdev, port + i) == 0 ||
2269 pci_resource_len(pdev, port + i) == 0)
2270 return 0;
2271 }
2272 return 1;
2273}
2274
2275/**
2276 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2277 * @host: target ATA host
2278 *
2279 * Acquire native PCI ATA resources for @host and initialize the
2280 * first two ports of @host accordingly. Ports marked dummy are
2281 * skipped and allocation failure makes the port dummy.
2282 *
2283 * Note that native PCI resources are valid even for legacy hosts
2284 * as we fix up pdev resources array early in boot, so this
2285 * function can be used for both native and legacy SFF hosts.
2286 *
2287 * LOCKING:
2288 * Inherited from calling layer (may sleep).
2289 *
2290 * RETURNS:
2291 * 0 if at least one port is initialized, -ENODEV if no port is
2292 * available.
2293 */
2294int ata_pci_sff_init_host(struct ata_host *host)
2295{
2296 struct device *gdev = host->dev;
2297 struct pci_dev *pdev = to_pci_dev(gdev);
2298 unsigned int mask = 0;
2299 int i, rc;
2300
2301 /* request, iomap BARs and init port addresses accordingly */
2302 for (i = 0; i < 2; i++) {
2303 struct ata_port *ap = host->ports[i];
2304 int base = i * 2;
2305 void __iomem * const *iomap;
2306
2307 if (ata_port_is_dummy(ap))
2308 continue;
2309
2310 /* Discard disabled ports. Some controllers show
2311 * their unused channels this way. Disabled ports are
2312 * made dummy.
2313 */
2314 if (!ata_resources_present(pdev, i)) {
2315 ap->ops = &ata_dummy_port_ops;
2316 continue;
2317 }
2318
2319 rc = pcim_iomap_regions(pdev, 0x3 << base,
2320 dev_driver_string(gdev));
2321 if (rc) {
2322 dev_warn(gdev,
2323 "failed to request/iomap BARs for port %d (errno=%d)\n",
2324 i, rc);
2325 if (rc == -EBUSY)
2326 pcim_pin_device(pdev);
2327 ap->ops = &ata_dummy_port_ops;
2328 continue;
2329 }
2330 host->iomap = iomap = pcim_iomap_table(pdev);
2331
2332 ap->ioaddr.cmd_addr = iomap[base];
2333 ap->ioaddr.altstatus_addr =
2334 ap->ioaddr.ctl_addr = (void __iomem *)
2335 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2336 ata_sff_std_ports(&ap->ioaddr);
2337
2338 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2339 (unsigned long long)pci_resource_start(pdev, base),
2340 (unsigned long long)pci_resource_start(pdev, base + 1));
2341
2342 mask |= 1 << i;
2343 }
2344
2345 if (!mask) {
2346 dev_err(gdev, "no available native port\n");
2347 return -ENODEV;
2348 }
2349
2350 return 0;
2351}
2352EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2353
2354/**
2355 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2356 * @pdev: target PCI device
2357 * @ppi: array of port_info, must be enough for two ports
2358 * @r_host: out argument for the initialized ATA host
2359 *
2360 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2361 * all PCI resources and initialize it accordingly in one go.
2362 *
2363 * LOCKING:
2364 * Inherited from calling layer (may sleep).
2365 *
2366 * RETURNS:
2367 * 0 on success, -errno otherwise.
2368 */
2369int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2370 const struct ata_port_info * const *ppi,
2371 struct ata_host **r_host)
2372{
2373 struct ata_host *host;
2374 int rc;
2375
2376 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2377 return -ENOMEM;
2378
2379 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2380 if (!host) {
2381 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2382 rc = -ENOMEM;
2383 goto err_out;
2384 }
2385
2386 rc = ata_pci_sff_init_host(host);
2387 if (rc)
2388 goto err_out;
2389
2390 devres_remove_group(&pdev->dev, NULL);
2391 *r_host = host;
2392 return 0;
2393
2394err_out:
2395 devres_release_group(&pdev->dev, NULL);
2396 return rc;
2397}
2398EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2399
2400/**
2401 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2402 * @host: target SFF ATA host
2403 * @irq_handler: irq_handler used when requesting IRQ(s)
2404 * @sht: scsi_host_template to use when registering the host
2405 *
2406 * This is the counterpart of ata_host_activate() for SFF ATA
2407 * hosts. This separate helper is necessary because SFF hosts
2408 * use two separate interrupts in legacy mode.
2409 *
2410 * LOCKING:
2411 * Inherited from calling layer (may sleep).
2412 *
2413 * RETURNS:
2414 * 0 on success, -errno otherwise.
2415 */
2416int ata_pci_sff_activate_host(struct ata_host *host,
2417 irq_handler_t irq_handler,
2418 struct scsi_host_template *sht)
2419{
2420 struct device *dev = host->dev;
2421 struct pci_dev *pdev = to_pci_dev(dev);
2422 const char *drv_name = dev_driver_string(host->dev);
2423 int legacy_mode = 0, rc;
2424
2425 rc = ata_host_start(host);
2426 if (rc)
2427 return rc;
2428
2429 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2430 u8 tmp8, mask;
2431
2432 /* TODO: What if one channel is in native mode ... */
2433 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2434 mask = (1 << 2) | (1 << 0);
2435 if ((tmp8 & mask) != mask)
2436 legacy_mode = 1;
2437 }
2438
2439 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2440 return -ENOMEM;
2441
2442 if (!legacy_mode && pdev->irq) {
2443 int i;
2444
2445 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2446 IRQF_SHARED, drv_name, host);
2447 if (rc)
2448 goto out;
2449
2450 for (i = 0; i < 2; i++) {
2451 if (ata_port_is_dummy(host->ports[i]))
2452 continue;
2453 ata_port_desc(host->ports[i], "irq %d", pdev->irq);
2454 }
2455 } else if (legacy_mode) {
2456 if (!ata_port_is_dummy(host->ports[0])) {
2457 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2458 irq_handler, IRQF_SHARED,
2459 drv_name, host);
2460 if (rc)
2461 goto out;
2462
2463 ata_port_desc(host->ports[0], "irq %d",
2464 ATA_PRIMARY_IRQ(pdev));
2465 }
2466
2467 if (!ata_port_is_dummy(host->ports[1])) {
2468 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2469 irq_handler, IRQF_SHARED,
2470 drv_name, host);
2471 if (rc)
2472 goto out;
2473
2474 ata_port_desc(host->ports[1], "irq %d",
2475 ATA_SECONDARY_IRQ(pdev));
2476 }
2477 }
2478
2479 rc = ata_host_register(host, sht);
2480out:
2481 if (rc == 0)
2482 devres_remove_group(dev, NULL);
2483 else
2484 devres_release_group(dev, NULL);
2485
2486 return rc;
2487}
2488EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2489
2490static const struct ata_port_info *ata_sff_find_valid_pi(
2491 const struct ata_port_info * const *ppi)
2492{
2493 int i;
2494
2495 /* look up the first valid port_info */
2496 for (i = 0; i < 2 && ppi[i]; i++)
2497 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2498 return ppi[i];
2499
2500 return NULL;
2501}
2502
2503static int ata_pci_init_one(struct pci_dev *pdev,
2504 const struct ata_port_info * const *ppi,
2505 struct scsi_host_template *sht, void *host_priv,
2506 int hflags, bool bmdma)
2507{
2508 struct device *dev = &pdev->dev;
2509 const struct ata_port_info *pi;
2510 struct ata_host *host = NULL;
2511 int rc;
2512
2513 DPRINTK("ENTER\n");
2514
2515 pi = ata_sff_find_valid_pi(ppi);
2516 if (!pi) {
2517 dev_err(&pdev->dev, "no valid port_info specified\n");
2518 return -EINVAL;
2519 }
2520
2521 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2522 return -ENOMEM;
2523
2524 rc = pcim_enable_device(pdev);
2525 if (rc)
2526 goto out;
2527
2528#ifdef CONFIG_ATA_BMDMA
2529 if (bmdma)
2530 /* prepare and activate BMDMA host */
2531 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2532 else
2533#endif
2534 /* prepare and activate SFF host */
2535 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2536 if (rc)
2537 goto out;
2538 host->private_data = host_priv;
2539 host->flags |= hflags;
2540
2541#ifdef CONFIG_ATA_BMDMA
2542 if (bmdma) {
2543 pci_set_master(pdev);
2544 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2545 } else
2546#endif
2547 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2548out:
2549 if (rc == 0)
2550 devres_remove_group(&pdev->dev, NULL);
2551 else
2552 devres_release_group(&pdev->dev, NULL);
2553
2554 return rc;
2555}
2556
2557/**
2558 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2559 * @pdev: Controller to be initialized
2560 * @ppi: array of port_info, must be enough for two ports
2561 * @sht: scsi_host_template to use when registering the host
2562 * @host_priv: host private_data
2563 * @hflag: host flags
2564 *
2565 * This is a helper function which can be called from a driver's
2566 * xxx_init_one() probe function if the hardware uses traditional
2567 * IDE taskfile registers and is PIO only.
2568 *
2569 * ASSUMPTION:
2570 * Nobody makes a single channel controller that appears solely as
2571 * the secondary legacy port on PCI.
2572 *
2573 * LOCKING:
2574 * Inherited from PCI layer (may sleep).
2575 *
2576 * RETURNS:
2577 * Zero on success, negative on errno-based value on error.
2578 */
2579int ata_pci_sff_init_one(struct pci_dev *pdev,
2580 const struct ata_port_info * const *ppi,
2581 struct scsi_host_template *sht, void *host_priv, int hflag)
2582{
2583 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2584}
2585EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2586
2587#endif /* CONFIG_PCI */
2588
2589/*
2590 * BMDMA support
2591 */
2592
2593#ifdef CONFIG_ATA_BMDMA
2594
2595const struct ata_port_operations ata_bmdma_port_ops = {
2596 .inherits = &ata_sff_port_ops,
2597
2598 .error_handler = ata_bmdma_error_handler,
2599 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2600
2601 .qc_prep = ata_bmdma_qc_prep,
2602 .qc_issue = ata_bmdma_qc_issue,
2603
2604 .sff_irq_clear = ata_bmdma_irq_clear,
2605 .bmdma_setup = ata_bmdma_setup,
2606 .bmdma_start = ata_bmdma_start,
2607 .bmdma_stop = ata_bmdma_stop,
2608 .bmdma_status = ata_bmdma_status,
2609
2610 .port_start = ata_bmdma_port_start,
2611};
2612EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2613
2614const struct ata_port_operations ata_bmdma32_port_ops = {
2615 .inherits = &ata_bmdma_port_ops,
2616
2617 .sff_data_xfer = ata_sff_data_xfer32,
2618 .port_start = ata_bmdma_port_start32,
2619};
2620EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2621
2622/**
2623 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2624 * @qc: Metadata associated with taskfile to be transferred
2625 *
2626 * Fill PCI IDE PRD (scatter-gather) table with segments
2627 * associated with the current disk command.
2628 *
2629 * LOCKING:
2630 * spin_lock_irqsave(host lock)
2631 *
2632 */
2633static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2634{
2635 struct ata_port *ap = qc->ap;
2636 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2637 struct scatterlist *sg;
2638 unsigned int si, pi;
2639
2640 pi = 0;
2641 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2642 u32 addr, offset;
2643 u32 sg_len, len;
2644
2645 /* determine if physical DMA addr spans 64K boundary.
2646 * Note h/w doesn't support 64-bit, so we unconditionally
2647 * truncate dma_addr_t to u32.
2648 */
2649 addr = (u32) sg_dma_address(sg);
2650 sg_len = sg_dma_len(sg);
2651
2652 while (sg_len) {
2653 offset = addr & 0xffff;
2654 len = sg_len;
2655 if ((offset + sg_len) > 0x10000)
2656 len = 0x10000 - offset;
2657
2658 prd[pi].addr = cpu_to_le32(addr);
2659 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2660 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2661
2662 pi++;
2663 sg_len -= len;
2664 addr += len;
2665 }
2666 }
2667
2668 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2669}
2670
2671/**
2672 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2673 * @qc: Metadata associated with taskfile to be transferred
2674 *
2675 * Fill PCI IDE PRD (scatter-gather) table with segments
2676 * associated with the current disk command. Perform the fill
2677 * so that we avoid writing any length 64K records for
2678 * controllers that don't follow the spec.
2679 *
2680 * LOCKING:
2681 * spin_lock_irqsave(host lock)
2682 *
2683 */
2684static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2685{
2686 struct ata_port *ap = qc->ap;
2687 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2688 struct scatterlist *sg;
2689 unsigned int si, pi;
2690
2691 pi = 0;
2692 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2693 u32 addr, offset;
2694 u32 sg_len, len, blen;
2695
2696 /* determine if physical DMA addr spans 64K boundary.
2697 * Note h/w doesn't support 64-bit, so we unconditionally
2698 * truncate dma_addr_t to u32.
2699 */
2700 addr = (u32) sg_dma_address(sg);
2701 sg_len = sg_dma_len(sg);
2702
2703 while (sg_len) {
2704 offset = addr & 0xffff;
2705 len = sg_len;
2706 if ((offset + sg_len) > 0x10000)
2707 len = 0x10000 - offset;
2708
2709 blen = len & 0xffff;
2710 prd[pi].addr = cpu_to_le32(addr);
2711 if (blen == 0) {
2712 /* Some PATA chipsets like the CS5530 can't
2713 cope with 0x0000 meaning 64K as the spec
2714 says */
2715 prd[pi].flags_len = cpu_to_le32(0x8000);
2716 blen = 0x8000;
2717 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2718 }
2719 prd[pi].flags_len = cpu_to_le32(blen);
2720 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
2721
2722 pi++;
2723 sg_len -= len;
2724 addr += len;
2725 }
2726 }
2727
2728 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2729}
2730
2731/**
2732 * ata_bmdma_qc_prep - Prepare taskfile for submission
2733 * @qc: Metadata associated with taskfile to be prepared
2734 *
2735 * Prepare ATA taskfile for submission.
2736 *
2737 * LOCKING:
2738 * spin_lock_irqsave(host lock)
2739 */
2740void ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2741{
2742 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2743 return;
2744
2745 ata_bmdma_fill_sg(qc);
2746}
2747EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2748
2749/**
2750 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2751 * @qc: Metadata associated with taskfile to be prepared
2752 *
2753 * Prepare ATA taskfile for submission.
2754 *
2755 * LOCKING:
2756 * spin_lock_irqsave(host lock)
2757 */
2758void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2759{
2760 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2761 return;
2762
2763 ata_bmdma_fill_sg_dumb(qc);
2764}
2765EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2766
2767/**
2768 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2769 * @qc: command to issue to device
2770 *
2771 * This function issues a PIO, NODATA or DMA command to a
2772 * SFF/BMDMA controller. PIO and NODATA are handled by
2773 * ata_sff_qc_issue().
2774 *
2775 * LOCKING:
2776 * spin_lock_irqsave(host lock)
2777 *
2778 * RETURNS:
2779 * Zero on success, AC_ERR_* mask on failure
2780 */
2781unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2782{
2783 struct ata_port *ap = qc->ap;
2784 struct ata_link *link = qc->dev->link;
2785
2786 /* defer PIO handling to sff_qc_issue */
2787 if (!ata_is_dma(qc->tf.protocol))
2788 return ata_sff_qc_issue(qc);
2789
2790 /* select the device */
2791 ata_dev_select(ap, qc->dev->devno, 1, 0);
2792
2793 /* start the command */
2794 switch (qc->tf.protocol) {
2795 case ATA_PROT_DMA:
2796 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2797
2798 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2799 ap->ops->bmdma_setup(qc); /* set up bmdma */
2800 ap->ops->bmdma_start(qc); /* initiate bmdma */
2801 ap->hsm_task_state = HSM_ST_LAST;
2802 break;
2803
2804 case ATAPI_PROT_DMA:
2805 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2806
2807 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2808 ap->ops->bmdma_setup(qc); /* set up bmdma */
2809 ap->hsm_task_state = HSM_ST_FIRST;
2810
2811 /* send cdb by polling if no cdb interrupt */
2812 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2813 ata_sff_queue_pio_task(link, 0);
2814 break;
2815
2816 default:
2817 WARN_ON(1);
2818 return AC_ERR_SYSTEM;
2819 }
2820
2821 return 0;
2822}
2823EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2824
2825/**
2826 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2827 * @ap: Port on which interrupt arrived (possibly...)
2828 * @qc: Taskfile currently active in engine
2829 *
2830 * Handle port interrupt for given queued command.
2831 *
2832 * LOCKING:
2833 * spin_lock_irqsave(host lock)
2834 *
2835 * RETURNS:
2836 * One if interrupt was handled, zero if not (shared irq).
2837 */
2838unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2839{
2840 struct ata_eh_info *ehi = &ap->link.eh_info;
2841 u8 host_stat = 0;
2842 bool bmdma_stopped = false;
2843 unsigned int handled;
2844
2845 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2846 /* check status of DMA engine */
2847 host_stat = ap->ops->bmdma_status(ap);
2848 VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat);
2849
2850 /* if it's not our irq... */
2851 if (!(host_stat & ATA_DMA_INTR))
2852 return ata_sff_idle_irq(ap);
2853
2854 /* before we do anything else, clear DMA-Start bit */
2855 ap->ops->bmdma_stop(qc);
2856 bmdma_stopped = true;
2857
2858 if (unlikely(host_stat & ATA_DMA_ERR)) {
2859 /* error when transferring data to/from memory */
2860 qc->err_mask |= AC_ERR_HOST_BUS;
2861 ap->hsm_task_state = HSM_ST_ERR;
2862 }
2863 }
2864
2865 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2866
2867 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2868 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2869
2870 return handled;
2871}
2872EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2873
2874/**
2875 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2876 * @irq: irq line (unused)
2877 * @dev_instance: pointer to our ata_host information structure
2878 *
2879 * Default interrupt handler for PCI IDE devices. Calls
2880 * ata_bmdma_port_intr() for each port that is not disabled.
2881 *
2882 * LOCKING:
2883 * Obtains host lock during operation.
2884 *
2885 * RETURNS:
2886 * IRQ_NONE or IRQ_HANDLED.
2887 */
2888irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2889{
2890 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2891}
2892EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2893
2894/**
2895 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2896 * @ap: port to handle error for
2897 *
2898 * Stock error handler for BMDMA controller. It can handle both
2899 * PATA and SATA controllers. Most BMDMA controllers should be
2900 * able to use this EH as-is or with some added handling before
2901 * and after.
2902 *
2903 * LOCKING:
2904 * Kernel thread context (may sleep)
2905 */
2906void ata_bmdma_error_handler(struct ata_port *ap)
2907{
2908 struct ata_queued_cmd *qc;
2909 unsigned long flags;
2910 bool thaw = false;
2911
2912 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2913 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2914 qc = NULL;
2915
2916 /* reset PIO HSM and stop DMA engine */
2917 spin_lock_irqsave(ap->lock, flags);
2918
2919 if (qc && ata_is_dma(qc->tf.protocol)) {
2920 u8 host_stat;
2921
2922 host_stat = ap->ops->bmdma_status(ap);
2923
2924 /* BMDMA controllers indicate host bus error by
2925 * setting DMA_ERR bit and timing out. As it wasn't
2926 * really a timeout event, adjust error mask and
2927 * cancel frozen state.
2928 */
2929 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2930 qc->err_mask = AC_ERR_HOST_BUS;
2931 thaw = true;
2932 }
2933
2934 ap->ops->bmdma_stop(qc);
2935
2936 /* if we're gonna thaw, make sure IRQ is clear */
2937 if (thaw) {
2938 ap->ops->sff_check_status(ap);
2939 if (ap->ops->sff_irq_clear)
2940 ap->ops->sff_irq_clear(ap);
2941 }
2942 }
2943
2944 spin_unlock_irqrestore(ap->lock, flags);
2945
2946 if (thaw)
2947 ata_eh_thaw_port(ap);
2948
2949 ata_sff_error_handler(ap);
2950}
2951EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2952
2953/**
2954 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2955 * @qc: internal command to clean up
2956 *
2957 * LOCKING:
2958 * Kernel thread context (may sleep)
2959 */
2960void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2961{
2962 struct ata_port *ap = qc->ap;
2963 unsigned long flags;
2964
2965 if (ata_is_dma(qc->tf.protocol)) {
2966 spin_lock_irqsave(ap->lock, flags);
2967 ap->ops->bmdma_stop(qc);
2968 spin_unlock_irqrestore(ap->lock, flags);
2969 }
2970}
2971EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2972
2973/**
2974 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2975 * @ap: Port associated with this ATA transaction.
2976 *
2977 * Clear interrupt and error flags in DMA status register.
2978 *
2979 * May be used as the irq_clear() entry in ata_port_operations.
2980 *
2981 * LOCKING:
2982 * spin_lock_irqsave(host lock)
2983 */
2984void ata_bmdma_irq_clear(struct ata_port *ap)
2985{
2986 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2987
2988 if (!mmio)
2989 return;
2990
2991 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2992}
2993EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2994
2995/**
2996 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2997 * @qc: Info associated with this ATA transaction.
2998 *
2999 * LOCKING:
3000 * spin_lock_irqsave(host lock)
3001 */
3002void ata_bmdma_setup(struct ata_queued_cmd *qc)
3003{
3004 struct ata_port *ap = qc->ap;
3005 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3006 u8 dmactl;
3007
3008 /* load PRD table addr. */
3009 mb(); /* make sure PRD table writes are visible to controller */
3010 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3011
3012 /* specify data direction, triple-check start bit is clear */
3013 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3014 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3015 if (!rw)
3016 dmactl |= ATA_DMA_WR;
3017 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3018
3019 /* issue r/w command */
3020 ap->ops->sff_exec_command(ap, &qc->tf);
3021}
3022EXPORT_SYMBOL_GPL(ata_bmdma_setup);
3023
3024/**
3025 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3026 * @qc: Info associated with this ATA transaction.
3027 *
3028 * LOCKING:
3029 * spin_lock_irqsave(host lock)
3030 */
3031void ata_bmdma_start(struct ata_queued_cmd *qc)
3032{
3033 struct ata_port *ap = qc->ap;
3034 u8 dmactl;
3035
3036 /* start host DMA transaction */
3037 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3038 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3039
3040 /* Strictly, one may wish to issue an ioread8() here, to
3041 * flush the mmio write. However, control also passes
3042 * to the hardware at this point, and it will interrupt
3043 * us when we are to resume control. So, in effect,
3044 * we don't care when the mmio write flushes.
3045 * Further, a read of the DMA status register _immediately_
3046 * following the write may not be what certain flaky hardware
3047 * is expected, so I think it is best to not add a readb()
3048 * without first all the MMIO ATA cards/mobos.
3049 * Or maybe I'm just being paranoid.
3050 *
3051 * FIXME: The posting of this write means I/O starts are
3052 * unnecessarily delayed for MMIO
3053 */
3054}
3055EXPORT_SYMBOL_GPL(ata_bmdma_start);
3056
3057/**
3058 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
3059 * @qc: Command we are ending DMA for
3060 *
3061 * Clears the ATA_DMA_START flag in the dma control register
3062 *
3063 * May be used as the bmdma_stop() entry in ata_port_operations.
3064 *
3065 * LOCKING:
3066 * spin_lock_irqsave(host lock)
3067 */
3068void ata_bmdma_stop(struct ata_queued_cmd *qc)
3069{
3070 struct ata_port *ap = qc->ap;
3071 void __iomem *mmio = ap->ioaddr.bmdma_addr;
3072
3073 /* clear start/stop bit */
3074 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3075 mmio + ATA_DMA_CMD);
3076
3077 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3078 ata_sff_dma_pause(ap);
3079}
3080EXPORT_SYMBOL_GPL(ata_bmdma_stop);
3081
3082/**
3083 * ata_bmdma_status - Read PCI IDE BMDMA status
3084 * @ap: Port associated with this ATA transaction.
3085 *
3086 * Read and return BMDMA status register.
3087 *
3088 * May be used as the bmdma_status() entry in ata_port_operations.
3089 *
3090 * LOCKING:
3091 * spin_lock_irqsave(host lock)
3092 */
3093u8 ata_bmdma_status(struct ata_port *ap)
3094{
3095 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
3096}
3097EXPORT_SYMBOL_GPL(ata_bmdma_status);
3098
3099
3100/**
3101 * ata_bmdma_port_start - Set port up for bmdma.
3102 * @ap: Port to initialize
3103 *
3104 * Called just after data structures for each port are
3105 * initialized. Allocates space for PRD table.
3106 *
3107 * May be used as the port_start() entry in ata_port_operations.
3108 *
3109 * LOCKING:
3110 * Inherited from caller.
3111 */
3112int ata_bmdma_port_start(struct ata_port *ap)
3113{
3114 if (ap->mwdma_mask || ap->udma_mask) {
3115 ap->bmdma_prd =
3116 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
3117 &ap->bmdma_prd_dma, GFP_KERNEL);
3118 if (!ap->bmdma_prd)
3119 return -ENOMEM;
3120 }
3121
3122 return 0;
3123}
3124EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3125
3126/**
3127 * ata_bmdma_port_start32 - Set port up for dma.
3128 * @ap: Port to initialize
3129 *
3130 * Called just after data structures for each port are
3131 * initialized. Enables 32bit PIO and allocates space for PRD
3132 * table.
3133 *
3134 * May be used as the port_start() entry in ata_port_operations for
3135 * devices that are capable of 32bit PIO.
3136 *
3137 * LOCKING:
3138 * Inherited from caller.
3139 */
3140int ata_bmdma_port_start32(struct ata_port *ap)
3141{
3142 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3143 return ata_bmdma_port_start(ap);
3144}
3145EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3146
3147#ifdef CONFIG_PCI
3148
3149/**
3150 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3151 * @pdev: PCI device
3152 *
3153 * Some PCI ATA devices report simplex mode but in fact can be told to
3154 * enter non simplex mode. This implements the necessary logic to
3155 * perform the task on such devices. Calling it on other devices will
3156 * have -undefined- behaviour.
3157 */
3158int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3159{
3160 unsigned long bmdma = pci_resource_start(pdev, 4);
3161 u8 simplex;
3162
3163 if (bmdma == 0)
3164 return -ENOENT;
3165
3166 simplex = inb(bmdma + 0x02);
3167 outb(simplex & 0x60, bmdma + 0x02);
3168 simplex = inb(bmdma + 0x02);
3169 if (simplex & 0x80)
3170 return -EOPNOTSUPP;
3171 return 0;
3172}
3173EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3174
3175static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3176{
3177 int i;
3178
3179 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3180
3181 for (i = 0; i < 2; i++) {
3182 host->ports[i]->mwdma_mask = 0;
3183 host->ports[i]->udma_mask = 0;
3184 }
3185}
3186
3187/**
3188 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3189 * @host: target ATA host
3190 *
3191 * Acquire PCI BMDMA resources and initialize @host accordingly.
3192 *
3193 * LOCKING:
3194 * Inherited from calling layer (may sleep).
3195 */
3196void ata_pci_bmdma_init(struct ata_host *host)
3197{
3198 struct device *gdev = host->dev;
3199 struct pci_dev *pdev = to_pci_dev(gdev);
3200 int i, rc;
3201
3202 /* No BAR4 allocation: No DMA */
3203 if (pci_resource_start(pdev, 4) == 0) {
3204 ata_bmdma_nodma(host, "BAR4 is zero");
3205 return;
3206 }
3207
3208 /*
3209 * Some controllers require BMDMA region to be initialized
3210 * even if DMA is not in use to clear IRQ status via
3211 * ->sff_irq_clear method. Try to initialize bmdma_addr
3212 * regardless of dma masks.
3213 */
3214 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK);
3215 if (rc)
3216 ata_bmdma_nodma(host, "failed to set dma mask");
3217 if (!rc) {
3218 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK);
3219 if (rc)
3220 ata_bmdma_nodma(host,
3221 "failed to set consistent dma mask");
3222 }
3223
3224 /* request and iomap DMA region */
3225 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3226 if (rc) {
3227 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3228 return;
3229 }
3230 host->iomap = pcim_iomap_table(pdev);
3231
3232 for (i = 0; i < 2; i++) {
3233 struct ata_port *ap = host->ports[i];
3234 void __iomem *bmdma = host->iomap[4] + 8 * i;
3235
3236 if (ata_port_is_dummy(ap))
3237 continue;
3238
3239 ap->ioaddr.bmdma_addr = bmdma;
3240 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3241 (ioread8(bmdma + 2) & 0x80))
3242 host->flags |= ATA_HOST_SIMPLEX;
3243
3244 ata_port_desc(ap, "bmdma 0x%llx",
3245 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3246 }
3247}
3248EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3249
3250/**
3251 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3252 * @pdev: target PCI device
3253 * @ppi: array of port_info, must be enough for two ports
3254 * @r_host: out argument for the initialized ATA host
3255 *
3256 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3257 * resources and initialize it accordingly in one go.
3258 *
3259 * LOCKING:
3260 * Inherited from calling layer (may sleep).
3261 *
3262 * RETURNS:
3263 * 0 on success, -errno otherwise.
3264 */
3265int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3266 const struct ata_port_info * const * ppi,
3267 struct ata_host **r_host)
3268{
3269 int rc;
3270
3271 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3272 if (rc)
3273 return rc;
3274
3275 ata_pci_bmdma_init(*r_host);
3276 return 0;
3277}
3278EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3279
3280/**
3281 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3282 * @pdev: Controller to be initialized
3283 * @ppi: array of port_info, must be enough for two ports
3284 * @sht: scsi_host_template to use when registering the host
3285 * @host_priv: host private_data
3286 * @hflags: host flags
3287 *
3288 * This function is similar to ata_pci_sff_init_one() but also
3289 * takes care of BMDMA initialization.
3290 *
3291 * LOCKING:
3292 * Inherited from PCI layer (may sleep).
3293 *
3294 * RETURNS:
3295 * Zero on success, negative on errno-based value on error.
3296 */
3297int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3298 const struct ata_port_info * const * ppi,
3299 struct scsi_host_template *sht, void *host_priv,
3300 int hflags)
3301{
3302 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3303}
3304EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3305
3306#endif /* CONFIG_PCI */
3307#endif /* CONFIG_ATA_BMDMA */
3308
3309/**
3310 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3311 * @ap: Port to initialize
3312 *
3313 * Called on port allocation to initialize SFF/BMDMA specific
3314 * fields.
3315 *
3316 * LOCKING:
3317 * None.
3318 */
3319void ata_sff_port_init(struct ata_port *ap)
3320{
3321 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3322 ap->ctl = ATA_DEVCTL_OBS;
3323 ap->last_ctl = 0xFF;
3324}
3325
3326int __init ata_sff_init(void)
3327{
3328 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3329 if (!ata_sff_wq)
3330 return -ENOMEM;
3331
3332 return 0;
3333}
3334
3335void ata_sff_exit(void)
3336{
3337 destroy_workqueue(ata_sff_wq);
3338}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * libata-sff.c - helper library for PCI IDE BMDMA
4 *
5 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2006 Jeff Garzik
7 *
8 * libata documentation is available via 'make {ps|pdf}docs',
9 * as Documentation/driver-api/libata.rst
10 *
11 * Hardware documentation available from http://www.t13.org/ and
12 * http://www.sata-io.org/
13 */
14
15#include <linux/kernel.h>
16#include <linux/gfp.h>
17#include <linux/pci.h>
18#include <linux/module.h>
19#include <linux/libata.h>
20#include <linux/highmem.h>
21#include <trace/events/libata.h>
22#include "libata.h"
23
24static struct workqueue_struct *ata_sff_wq;
25
26const struct ata_port_operations ata_sff_port_ops = {
27 .inherits = &ata_base_port_ops,
28
29 .qc_prep = ata_noop_qc_prep,
30 .qc_issue = ata_sff_qc_issue,
31 .qc_fill_rtf = ata_sff_qc_fill_rtf,
32
33 .freeze = ata_sff_freeze,
34 .thaw = ata_sff_thaw,
35 .prereset = ata_sff_prereset,
36 .softreset = ata_sff_softreset,
37 .hardreset = sata_sff_hardreset,
38 .postreset = ata_sff_postreset,
39 .error_handler = ata_sff_error_handler,
40
41 .sff_dev_select = ata_sff_dev_select,
42 .sff_check_status = ata_sff_check_status,
43 .sff_tf_load = ata_sff_tf_load,
44 .sff_tf_read = ata_sff_tf_read,
45 .sff_exec_command = ata_sff_exec_command,
46 .sff_data_xfer = ata_sff_data_xfer,
47 .sff_drain_fifo = ata_sff_drain_fifo,
48
49 .lost_interrupt = ata_sff_lost_interrupt,
50};
51EXPORT_SYMBOL_GPL(ata_sff_port_ops);
52
53/**
54 * ata_sff_check_status - Read device status reg & clear interrupt
55 * @ap: port where the device is
56 *
57 * Reads ATA taskfile status register for currently-selected device
58 * and return its value. This also clears pending interrupts
59 * from this device
60 *
61 * LOCKING:
62 * Inherited from caller.
63 */
64u8 ata_sff_check_status(struct ata_port *ap)
65{
66 return ioread8(ap->ioaddr.status_addr);
67}
68EXPORT_SYMBOL_GPL(ata_sff_check_status);
69
70/**
71 * ata_sff_altstatus - Read device alternate status reg
72 * @ap: port where the device is
73 * @status: pointer to a status value
74 *
75 * Reads ATA alternate status register for currently-selected device
76 * and return its value.
77 *
78 * RETURN:
79 * true if the register exists, false if not.
80 *
81 * LOCKING:
82 * Inherited from caller.
83 */
84static bool ata_sff_altstatus(struct ata_port *ap, u8 *status)
85{
86 u8 tmp;
87
88 if (ap->ops->sff_check_altstatus) {
89 tmp = ap->ops->sff_check_altstatus(ap);
90 goto read;
91 }
92 if (ap->ioaddr.altstatus_addr) {
93 tmp = ioread8(ap->ioaddr.altstatus_addr);
94 goto read;
95 }
96 return false;
97
98read:
99 if (status)
100 *status = tmp;
101 return true;
102}
103
104/**
105 * ata_sff_irq_status - Check if the device is busy
106 * @ap: port where the device is
107 *
108 * Determine if the port is currently busy. Uses altstatus
109 * if available in order to avoid clearing shared IRQ status
110 * when finding an IRQ source. Non ctl capable devices don't
111 * share interrupt lines fortunately for us.
112 *
113 * LOCKING:
114 * Inherited from caller.
115 */
116static u8 ata_sff_irq_status(struct ata_port *ap)
117{
118 u8 status;
119
120 /* Not us: We are busy */
121 if (ata_sff_altstatus(ap, &status) && (status & ATA_BUSY))
122 return status;
123 /* Clear INTRQ latch */
124 status = ap->ops->sff_check_status(ap);
125 return status;
126}
127
128/**
129 * ata_sff_sync - Flush writes
130 * @ap: Port to wait for.
131 *
132 * CAUTION:
133 * If we have an mmio device with no ctl and no altstatus
134 * method this will fail. No such devices are known to exist.
135 *
136 * LOCKING:
137 * Inherited from caller.
138 */
139
140static void ata_sff_sync(struct ata_port *ap)
141{
142 ata_sff_altstatus(ap, NULL);
143}
144
145/**
146 * ata_sff_pause - Flush writes and wait 400nS
147 * @ap: Port to pause for.
148 *
149 * CAUTION:
150 * If we have an mmio device with no ctl and no altstatus
151 * method this will fail. No such devices are known to exist.
152 *
153 * LOCKING:
154 * Inherited from caller.
155 */
156
157void ata_sff_pause(struct ata_port *ap)
158{
159 ata_sff_sync(ap);
160 ndelay(400);
161}
162EXPORT_SYMBOL_GPL(ata_sff_pause);
163
164/**
165 * ata_sff_dma_pause - Pause before commencing DMA
166 * @ap: Port to pause for.
167 *
168 * Perform I/O fencing and ensure sufficient cycle delays occur
169 * for the HDMA1:0 transition
170 */
171
172void ata_sff_dma_pause(struct ata_port *ap)
173{
174 /*
175 * An altstatus read will cause the needed delay without
176 * messing up the IRQ status
177 */
178 if (ata_sff_altstatus(ap, NULL))
179 return;
180 /* There are no DMA controllers without ctl. BUG here to ensure
181 we never violate the HDMA1:0 transition timing and risk
182 corruption. */
183 BUG();
184}
185EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
186
187static int ata_sff_check_ready(struct ata_link *link)
188{
189 u8 status = link->ap->ops->sff_check_status(link->ap);
190
191 return ata_check_ready(status);
192}
193
194/**
195 * ata_sff_wait_ready - sleep until BSY clears, or timeout
196 * @link: SFF link to wait ready status for
197 * @deadline: deadline jiffies for the operation
198 *
199 * Sleep until ATA Status register bit BSY clears, or timeout
200 * occurs.
201 *
202 * LOCKING:
203 * Kernel thread context (may sleep).
204 *
205 * RETURNS:
206 * 0 on success, -errno otherwise.
207 */
208int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
209{
210 return ata_wait_ready(link, deadline, ata_sff_check_ready);
211}
212EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
213
214/**
215 * ata_sff_set_devctl - Write device control reg
216 * @ap: port where the device is
217 * @ctl: value to write
218 *
219 * Writes ATA device control register.
220 *
221 * RETURN:
222 * true if the register exists, false if not.
223 *
224 * LOCKING:
225 * Inherited from caller.
226 */
227static bool ata_sff_set_devctl(struct ata_port *ap, u8 ctl)
228{
229 if (ap->ops->sff_set_devctl) {
230 ap->ops->sff_set_devctl(ap, ctl);
231 return true;
232 }
233 if (ap->ioaddr.ctl_addr) {
234 iowrite8(ctl, ap->ioaddr.ctl_addr);
235 return true;
236 }
237
238 return false;
239}
240
241/**
242 * ata_sff_dev_select - Select device 0/1 on ATA bus
243 * @ap: ATA channel to manipulate
244 * @device: ATA device (numbered from zero) to select
245 *
246 * Use the method defined in the ATA specification to
247 * make either device 0, or device 1, active on the
248 * ATA channel. Works with both PIO and MMIO.
249 *
250 * May be used as the dev_select() entry in ata_port_operations.
251 *
252 * LOCKING:
253 * caller.
254 */
255void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
256{
257 u8 tmp;
258
259 if (device == 0)
260 tmp = ATA_DEVICE_OBS;
261 else
262 tmp = ATA_DEVICE_OBS | ATA_DEV1;
263
264 iowrite8(tmp, ap->ioaddr.device_addr);
265 ata_sff_pause(ap); /* needed; also flushes, for mmio */
266}
267EXPORT_SYMBOL_GPL(ata_sff_dev_select);
268
269/**
270 * ata_dev_select - Select device 0/1 on ATA bus
271 * @ap: ATA channel to manipulate
272 * @device: ATA device (numbered from zero) to select
273 * @wait: non-zero to wait for Status register BSY bit to clear
274 * @can_sleep: non-zero if context allows sleeping
275 *
276 * Use the method defined in the ATA specification to
277 * make either device 0, or device 1, active on the
278 * ATA channel.
279 *
280 * This is a high-level version of ata_sff_dev_select(), which
281 * additionally provides the services of inserting the proper
282 * pauses and status polling, where needed.
283 *
284 * LOCKING:
285 * caller.
286 */
287static void ata_dev_select(struct ata_port *ap, unsigned int device,
288 unsigned int wait, unsigned int can_sleep)
289{
290 if (wait)
291 ata_wait_idle(ap);
292
293 ap->ops->sff_dev_select(ap, device);
294
295 if (wait) {
296 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
297 ata_msleep(ap, 150);
298 ata_wait_idle(ap);
299 }
300}
301
302/**
303 * ata_sff_irq_on - Enable interrupts on a port.
304 * @ap: Port on which interrupts are enabled.
305 *
306 * Enable interrupts on a legacy IDE device using MMIO or PIO,
307 * wait for idle, clear any pending interrupts.
308 *
309 * Note: may NOT be used as the sff_irq_on() entry in
310 * ata_port_operations.
311 *
312 * LOCKING:
313 * Inherited from caller.
314 */
315void ata_sff_irq_on(struct ata_port *ap)
316{
317 if (ap->ops->sff_irq_on) {
318 ap->ops->sff_irq_on(ap);
319 return;
320 }
321
322 ap->ctl &= ~ATA_NIEN;
323 ap->last_ctl = ap->ctl;
324
325 ata_sff_set_devctl(ap, ap->ctl);
326 ata_wait_idle(ap);
327
328 if (ap->ops->sff_irq_clear)
329 ap->ops->sff_irq_clear(ap);
330}
331EXPORT_SYMBOL_GPL(ata_sff_irq_on);
332
333/**
334 * ata_sff_tf_load - send taskfile registers to host controller
335 * @ap: Port to which output is sent
336 * @tf: ATA taskfile register set
337 *
338 * Outputs ATA taskfile to standard ATA host controller.
339 *
340 * LOCKING:
341 * Inherited from caller.
342 */
343void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
344{
345 struct ata_ioports *ioaddr = &ap->ioaddr;
346 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
347
348 if (tf->ctl != ap->last_ctl) {
349 if (ioaddr->ctl_addr)
350 iowrite8(tf->ctl, ioaddr->ctl_addr);
351 ap->last_ctl = tf->ctl;
352 ata_wait_idle(ap);
353 }
354
355 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
356 WARN_ON_ONCE(!ioaddr->ctl_addr);
357 iowrite8(tf->hob_feature, ioaddr->feature_addr);
358 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
359 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
360 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
361 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
362 }
363
364 if (is_addr) {
365 iowrite8(tf->feature, ioaddr->feature_addr);
366 iowrite8(tf->nsect, ioaddr->nsect_addr);
367 iowrite8(tf->lbal, ioaddr->lbal_addr);
368 iowrite8(tf->lbam, ioaddr->lbam_addr);
369 iowrite8(tf->lbah, ioaddr->lbah_addr);
370 }
371
372 if (tf->flags & ATA_TFLAG_DEVICE)
373 iowrite8(tf->device, ioaddr->device_addr);
374
375 ata_wait_idle(ap);
376}
377EXPORT_SYMBOL_GPL(ata_sff_tf_load);
378
379/**
380 * ata_sff_tf_read - input device's ATA taskfile shadow registers
381 * @ap: Port from which input is read
382 * @tf: ATA taskfile register set for storing input
383 *
384 * Reads ATA taskfile registers for currently-selected device
385 * into @tf. Assumes the device has a fully SFF compliant task file
386 * layout and behaviour. If you device does not (eg has a different
387 * status method) then you will need to provide a replacement tf_read
388 *
389 * LOCKING:
390 * Inherited from caller.
391 */
392void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
393{
394 struct ata_ioports *ioaddr = &ap->ioaddr;
395
396 tf->status = ata_sff_check_status(ap);
397 tf->error = ioread8(ioaddr->error_addr);
398 tf->nsect = ioread8(ioaddr->nsect_addr);
399 tf->lbal = ioread8(ioaddr->lbal_addr);
400 tf->lbam = ioread8(ioaddr->lbam_addr);
401 tf->lbah = ioread8(ioaddr->lbah_addr);
402 tf->device = ioread8(ioaddr->device_addr);
403
404 if (tf->flags & ATA_TFLAG_LBA48) {
405 if (likely(ioaddr->ctl_addr)) {
406 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
407 tf->hob_feature = ioread8(ioaddr->error_addr);
408 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
409 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
410 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
411 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
412 iowrite8(tf->ctl, ioaddr->ctl_addr);
413 ap->last_ctl = tf->ctl;
414 } else
415 WARN_ON_ONCE(1);
416 }
417}
418EXPORT_SYMBOL_GPL(ata_sff_tf_read);
419
420/**
421 * ata_sff_exec_command - issue ATA command to host controller
422 * @ap: port to which command is being issued
423 * @tf: ATA taskfile register set
424 *
425 * Issues ATA command, with proper synchronization with interrupt
426 * handler / other threads.
427 *
428 * LOCKING:
429 * spin_lock_irqsave(host lock)
430 */
431void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
432{
433 iowrite8(tf->command, ap->ioaddr.command_addr);
434 ata_sff_pause(ap);
435}
436EXPORT_SYMBOL_GPL(ata_sff_exec_command);
437
438/**
439 * ata_tf_to_host - issue ATA taskfile to host controller
440 * @ap: port to which command is being issued
441 * @tf: ATA taskfile register set
442 * @tag: tag of the associated command
443 *
444 * Issues ATA taskfile register set to ATA host controller,
445 * with proper synchronization with interrupt handler and
446 * other threads.
447 *
448 * LOCKING:
449 * spin_lock_irqsave(host lock)
450 */
451static inline void ata_tf_to_host(struct ata_port *ap,
452 const struct ata_taskfile *tf,
453 unsigned int tag)
454{
455 trace_ata_tf_load(ap, tf);
456 ap->ops->sff_tf_load(ap, tf);
457 trace_ata_exec_command(ap, tf, tag);
458 ap->ops->sff_exec_command(ap, tf);
459}
460
461/**
462 * ata_sff_data_xfer - Transfer data by PIO
463 * @qc: queued command
464 * @buf: data buffer
465 * @buflen: buffer length
466 * @rw: read/write
467 *
468 * Transfer data from/to the device data register by PIO.
469 *
470 * LOCKING:
471 * Inherited from caller.
472 *
473 * RETURNS:
474 * Bytes consumed.
475 */
476unsigned int ata_sff_data_xfer(struct ata_queued_cmd *qc, unsigned char *buf,
477 unsigned int buflen, int rw)
478{
479 struct ata_port *ap = qc->dev->link->ap;
480 void __iomem *data_addr = ap->ioaddr.data_addr;
481 unsigned int words = buflen >> 1;
482
483 /* Transfer multiple of 2 bytes */
484 if (rw == READ)
485 ioread16_rep(data_addr, buf, words);
486 else
487 iowrite16_rep(data_addr, buf, words);
488
489 /* Transfer trailing byte, if any. */
490 if (unlikely(buflen & 0x01)) {
491 unsigned char pad[2] = { };
492
493 /* Point buf to the tail of buffer */
494 buf += buflen - 1;
495
496 /*
497 * Use io*16_rep() accessors here as well to avoid pointlessly
498 * swapping bytes to and from on the big endian machines...
499 */
500 if (rw == READ) {
501 ioread16_rep(data_addr, pad, 1);
502 *buf = pad[0];
503 } else {
504 pad[0] = *buf;
505 iowrite16_rep(data_addr, pad, 1);
506 }
507 words++;
508 }
509
510 return words << 1;
511}
512EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
513
514/**
515 * ata_sff_data_xfer32 - Transfer data by PIO
516 * @qc: queued command
517 * @buf: data buffer
518 * @buflen: buffer length
519 * @rw: read/write
520 *
521 * Transfer data from/to the device data register by PIO using 32bit
522 * I/O operations.
523 *
524 * LOCKING:
525 * Inherited from caller.
526 *
527 * RETURNS:
528 * Bytes consumed.
529 */
530
531unsigned int ata_sff_data_xfer32(struct ata_queued_cmd *qc, unsigned char *buf,
532 unsigned int buflen, int rw)
533{
534 struct ata_device *dev = qc->dev;
535 struct ata_port *ap = dev->link->ap;
536 void __iomem *data_addr = ap->ioaddr.data_addr;
537 unsigned int words = buflen >> 2;
538 int slop = buflen & 3;
539
540 if (!(ap->pflags & ATA_PFLAG_PIO32))
541 return ata_sff_data_xfer(qc, buf, buflen, rw);
542
543 /* Transfer multiple of 4 bytes */
544 if (rw == READ)
545 ioread32_rep(data_addr, buf, words);
546 else
547 iowrite32_rep(data_addr, buf, words);
548
549 /* Transfer trailing bytes, if any */
550 if (unlikely(slop)) {
551 unsigned char pad[4] = { };
552
553 /* Point buf to the tail of buffer */
554 buf += buflen - slop;
555
556 /*
557 * Use io*_rep() accessors here as well to avoid pointlessly
558 * swapping bytes to and from on the big endian machines...
559 */
560 if (rw == READ) {
561 if (slop < 3)
562 ioread16_rep(data_addr, pad, 1);
563 else
564 ioread32_rep(data_addr, pad, 1);
565 memcpy(buf, pad, slop);
566 } else {
567 memcpy(pad, buf, slop);
568 if (slop < 3)
569 iowrite16_rep(data_addr, pad, 1);
570 else
571 iowrite32_rep(data_addr, pad, 1);
572 }
573 }
574 return (buflen + 1) & ~1;
575}
576EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
577
578static void ata_pio_xfer(struct ata_queued_cmd *qc, struct page *page,
579 unsigned int offset, size_t xfer_size)
580{
581 bool do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
582 unsigned char *buf;
583
584 buf = kmap_atomic(page);
585 qc->ap->ops->sff_data_xfer(qc, buf + offset, xfer_size, do_write);
586 kunmap_atomic(buf);
587
588 if (!do_write && !PageSlab(page))
589 flush_dcache_page(page);
590}
591
592/**
593 * ata_pio_sector - Transfer a sector of data.
594 * @qc: Command on going
595 *
596 * Transfer qc->sect_size bytes of data from/to the ATA device.
597 *
598 * LOCKING:
599 * Inherited from caller.
600 */
601static void ata_pio_sector(struct ata_queued_cmd *qc)
602{
603 struct ata_port *ap = qc->ap;
604 struct page *page;
605 unsigned int offset;
606
607 if (!qc->cursg) {
608 qc->curbytes = qc->nbytes;
609 return;
610 }
611 if (qc->curbytes == qc->nbytes - qc->sect_size)
612 ap->hsm_task_state = HSM_ST_LAST;
613
614 page = sg_page(qc->cursg);
615 offset = qc->cursg->offset + qc->cursg_ofs;
616
617 /* get the current page and offset */
618 page = nth_page(page, (offset >> PAGE_SHIFT));
619 offset %= PAGE_SIZE;
620
621 trace_ata_sff_pio_transfer_data(qc, offset, qc->sect_size);
622
623 /*
624 * Split the transfer when it splits a page boundary. Note that the
625 * split still has to be dword aligned like all ATA data transfers.
626 */
627 WARN_ON_ONCE(offset % 4);
628 if (offset + qc->sect_size > PAGE_SIZE) {
629 unsigned int split_len = PAGE_SIZE - offset;
630
631 ata_pio_xfer(qc, page, offset, split_len);
632 ata_pio_xfer(qc, nth_page(page, 1), 0,
633 qc->sect_size - split_len);
634 } else {
635 ata_pio_xfer(qc, page, offset, qc->sect_size);
636 }
637
638 qc->curbytes += qc->sect_size;
639 qc->cursg_ofs += qc->sect_size;
640
641 if (qc->cursg_ofs == qc->cursg->length) {
642 qc->cursg = sg_next(qc->cursg);
643 if (!qc->cursg)
644 ap->hsm_task_state = HSM_ST_LAST;
645 qc->cursg_ofs = 0;
646 }
647}
648
649/**
650 * ata_pio_sectors - Transfer one or many sectors.
651 * @qc: Command on going
652 *
653 * Transfer one or many sectors of data from/to the
654 * ATA device for the DRQ request.
655 *
656 * LOCKING:
657 * Inherited from caller.
658 */
659static void ata_pio_sectors(struct ata_queued_cmd *qc)
660{
661 if (is_multi_taskfile(&qc->tf)) {
662 /* READ/WRITE MULTIPLE */
663 unsigned int nsect;
664
665 WARN_ON_ONCE(qc->dev->multi_count == 0);
666
667 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
668 qc->dev->multi_count);
669 while (nsect--)
670 ata_pio_sector(qc);
671 } else
672 ata_pio_sector(qc);
673
674 ata_sff_sync(qc->ap); /* flush */
675}
676
677/**
678 * atapi_send_cdb - Write CDB bytes to hardware
679 * @ap: Port to which ATAPI device is attached.
680 * @qc: Taskfile currently active
681 *
682 * When device has indicated its readiness to accept
683 * a CDB, this function is called. Send the CDB.
684 *
685 * LOCKING:
686 * caller.
687 */
688static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
689{
690 /* send SCSI cdb */
691 trace_atapi_send_cdb(qc, 0, qc->dev->cdb_len);
692 WARN_ON_ONCE(qc->dev->cdb_len < 12);
693
694 ap->ops->sff_data_xfer(qc, qc->cdb, qc->dev->cdb_len, 1);
695 ata_sff_sync(ap);
696 /* FIXME: If the CDB is for DMA do we need to do the transition delay
697 or is bmdma_start guaranteed to do it ? */
698 switch (qc->tf.protocol) {
699 case ATAPI_PROT_PIO:
700 ap->hsm_task_state = HSM_ST;
701 break;
702 case ATAPI_PROT_NODATA:
703 ap->hsm_task_state = HSM_ST_LAST;
704 break;
705#ifdef CONFIG_ATA_BMDMA
706 case ATAPI_PROT_DMA:
707 ap->hsm_task_state = HSM_ST_LAST;
708 /* initiate bmdma */
709 trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
710 ap->ops->bmdma_start(qc);
711 break;
712#endif /* CONFIG_ATA_BMDMA */
713 default:
714 BUG();
715 }
716}
717
718/**
719 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
720 * @qc: Command on going
721 * @bytes: number of bytes
722 *
723 * Transfer data from/to the ATAPI device.
724 *
725 * LOCKING:
726 * Inherited from caller.
727 *
728 */
729static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
730{
731 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
732 struct ata_port *ap = qc->ap;
733 struct ata_device *dev = qc->dev;
734 struct ata_eh_info *ehi = &dev->link->eh_info;
735 struct scatterlist *sg;
736 struct page *page;
737 unsigned char *buf;
738 unsigned int offset, count, consumed;
739
740next_sg:
741 sg = qc->cursg;
742 if (unlikely(!sg)) {
743 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
744 "buf=%u cur=%u bytes=%u",
745 qc->nbytes, qc->curbytes, bytes);
746 return -1;
747 }
748
749 page = sg_page(sg);
750 offset = sg->offset + qc->cursg_ofs;
751
752 /* get the current page and offset */
753 page = nth_page(page, (offset >> PAGE_SHIFT));
754 offset %= PAGE_SIZE;
755
756 /* don't overrun current sg */
757 count = min(sg->length - qc->cursg_ofs, bytes);
758
759 /* don't cross page boundaries */
760 count = min(count, (unsigned int)PAGE_SIZE - offset);
761
762 trace_atapi_pio_transfer_data(qc, offset, count);
763
764 /* do the actual data transfer */
765 buf = kmap_atomic(page);
766 consumed = ap->ops->sff_data_xfer(qc, buf + offset, count, rw);
767 kunmap_atomic(buf);
768
769 bytes -= min(bytes, consumed);
770 qc->curbytes += count;
771 qc->cursg_ofs += count;
772
773 if (qc->cursg_ofs == sg->length) {
774 qc->cursg = sg_next(qc->cursg);
775 qc->cursg_ofs = 0;
776 }
777
778 /*
779 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
780 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
781 * check correctly as it doesn't know if it is the last request being
782 * made. Somebody should implement a proper sanity check.
783 */
784 if (bytes)
785 goto next_sg;
786 return 0;
787}
788
789/**
790 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
791 * @qc: Command on going
792 *
793 * Transfer Transfer data from/to the ATAPI device.
794 *
795 * LOCKING:
796 * Inherited from caller.
797 */
798static void atapi_pio_bytes(struct ata_queued_cmd *qc)
799{
800 struct ata_port *ap = qc->ap;
801 struct ata_device *dev = qc->dev;
802 struct ata_eh_info *ehi = &dev->link->eh_info;
803 unsigned int ireason, bc_lo, bc_hi, bytes;
804 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
805
806 /* Abuse qc->result_tf for temp storage of intermediate TF
807 * here to save some kernel stack usage.
808 * For normal completion, qc->result_tf is not relevant. For
809 * error, qc->result_tf is later overwritten by ata_qc_complete().
810 * So, the correctness of qc->result_tf is not affected.
811 */
812 ap->ops->sff_tf_read(ap, &qc->result_tf);
813 ireason = qc->result_tf.nsect;
814 bc_lo = qc->result_tf.lbam;
815 bc_hi = qc->result_tf.lbah;
816 bytes = (bc_hi << 8) | bc_lo;
817
818 /* shall be cleared to zero, indicating xfer of data */
819 if (unlikely(ireason & ATAPI_COD))
820 goto atapi_check;
821
822 /* make sure transfer direction matches expected */
823 i_write = ((ireason & ATAPI_IO) == 0) ? 1 : 0;
824 if (unlikely(do_write != i_write))
825 goto atapi_check;
826
827 if (unlikely(!bytes))
828 goto atapi_check;
829
830 if (unlikely(__atapi_pio_bytes(qc, bytes)))
831 goto err_out;
832 ata_sff_sync(ap); /* flush */
833
834 return;
835
836 atapi_check:
837 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
838 ireason, bytes);
839 err_out:
840 qc->err_mask |= AC_ERR_HSM;
841 ap->hsm_task_state = HSM_ST_ERR;
842}
843
844/**
845 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
846 * @ap: the target ata_port
847 * @qc: qc on going
848 *
849 * RETURNS:
850 * 1 if ok in workqueue, 0 otherwise.
851 */
852static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
853 struct ata_queued_cmd *qc)
854{
855 if (qc->tf.flags & ATA_TFLAG_POLLING)
856 return 1;
857
858 if (ap->hsm_task_state == HSM_ST_FIRST) {
859 if (qc->tf.protocol == ATA_PROT_PIO &&
860 (qc->tf.flags & ATA_TFLAG_WRITE))
861 return 1;
862
863 if (ata_is_atapi(qc->tf.protocol) &&
864 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
865 return 1;
866 }
867
868 return 0;
869}
870
871/**
872 * ata_hsm_qc_complete - finish a qc running on standard HSM
873 * @qc: Command to complete
874 * @in_wq: 1 if called from workqueue, 0 otherwise
875 *
876 * Finish @qc which is running on standard HSM.
877 *
878 * LOCKING:
879 * If @in_wq is zero, spin_lock_irqsave(host lock).
880 * Otherwise, none on entry and grabs host lock.
881 */
882static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
883{
884 struct ata_port *ap = qc->ap;
885
886 if (in_wq) {
887 /* EH might have kicked in while host lock is released. */
888 qc = ata_qc_from_tag(ap, qc->tag);
889 if (qc) {
890 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
891 ata_sff_irq_on(ap);
892 ata_qc_complete(qc);
893 } else
894 ata_port_freeze(ap);
895 }
896 } else {
897 if (likely(!(qc->err_mask & AC_ERR_HSM)))
898 ata_qc_complete(qc);
899 else
900 ata_port_freeze(ap);
901 }
902}
903
904/**
905 * ata_sff_hsm_move - move the HSM to the next state.
906 * @ap: the target ata_port
907 * @qc: qc on going
908 * @status: current device status
909 * @in_wq: 1 if called from workqueue, 0 otherwise
910 *
911 * RETURNS:
912 * 1 when poll next status needed, 0 otherwise.
913 */
914int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
915 u8 status, int in_wq)
916{
917 struct ata_link *link = qc->dev->link;
918 struct ata_eh_info *ehi = &link->eh_info;
919 int poll_next;
920
921 lockdep_assert_held(ap->lock);
922
923 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
924
925 /* Make sure ata_sff_qc_issue() does not throw things
926 * like DMA polling into the workqueue. Notice that
927 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
928 */
929 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
930
931fsm_start:
932 trace_ata_sff_hsm_state(qc, status);
933
934 switch (ap->hsm_task_state) {
935 case HSM_ST_FIRST:
936 /* Send first data block or PACKET CDB */
937
938 /* If polling, we will stay in the work queue after
939 * sending the data. Otherwise, interrupt handler
940 * takes over after sending the data.
941 */
942 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
943
944 /* check device status */
945 if (unlikely((status & ATA_DRQ) == 0)) {
946 /* handle BSY=0, DRQ=0 as error */
947 if (likely(status & (ATA_ERR | ATA_DF)))
948 /* device stops HSM for abort/error */
949 qc->err_mask |= AC_ERR_DEV;
950 else {
951 /* HSM violation. Let EH handle this */
952 ata_ehi_push_desc(ehi,
953 "ST_FIRST: !(DRQ|ERR|DF)");
954 qc->err_mask |= AC_ERR_HSM;
955 }
956
957 ap->hsm_task_state = HSM_ST_ERR;
958 goto fsm_start;
959 }
960
961 /* Device should not ask for data transfer (DRQ=1)
962 * when it finds something wrong.
963 * We ignore DRQ here and stop the HSM by
964 * changing hsm_task_state to HSM_ST_ERR and
965 * let the EH abort the command or reset the device.
966 */
967 if (unlikely(status & (ATA_ERR | ATA_DF))) {
968 /* Some ATAPI tape drives forget to clear the ERR bit
969 * when doing the next command (mostly request sense).
970 * We ignore ERR here to workaround and proceed sending
971 * the CDB.
972 */
973 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
974 ata_ehi_push_desc(ehi, "ST_FIRST: "
975 "DRQ=1 with device error, "
976 "dev_stat 0x%X", status);
977 qc->err_mask |= AC_ERR_HSM;
978 ap->hsm_task_state = HSM_ST_ERR;
979 goto fsm_start;
980 }
981 }
982
983 if (qc->tf.protocol == ATA_PROT_PIO) {
984 /* PIO data out protocol.
985 * send first data block.
986 */
987
988 /* ata_pio_sectors() might change the state
989 * to HSM_ST_LAST. so, the state is changed here
990 * before ata_pio_sectors().
991 */
992 ap->hsm_task_state = HSM_ST;
993 ata_pio_sectors(qc);
994 } else
995 /* send CDB */
996 atapi_send_cdb(ap, qc);
997
998 /* if polling, ata_sff_pio_task() handles the rest.
999 * otherwise, interrupt handler takes over from here.
1000 */
1001 break;
1002
1003 case HSM_ST:
1004 /* complete command or read/write the data register */
1005 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1006 /* ATAPI PIO protocol */
1007 if ((status & ATA_DRQ) == 0) {
1008 /* No more data to transfer or device error.
1009 * Device error will be tagged in HSM_ST_LAST.
1010 */
1011 ap->hsm_task_state = HSM_ST_LAST;
1012 goto fsm_start;
1013 }
1014
1015 /* Device should not ask for data transfer (DRQ=1)
1016 * when it finds something wrong.
1017 * We ignore DRQ here and stop the HSM by
1018 * changing hsm_task_state to HSM_ST_ERR and
1019 * let the EH abort the command or reset the device.
1020 */
1021 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1022 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1023 "DRQ=1 with device error, "
1024 "dev_stat 0x%X", status);
1025 qc->err_mask |= AC_ERR_HSM;
1026 ap->hsm_task_state = HSM_ST_ERR;
1027 goto fsm_start;
1028 }
1029
1030 atapi_pio_bytes(qc);
1031
1032 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1033 /* bad ireason reported by device */
1034 goto fsm_start;
1035
1036 } else {
1037 /* ATA PIO protocol */
1038 if (unlikely((status & ATA_DRQ) == 0)) {
1039 /* handle BSY=0, DRQ=0 as error */
1040 if (likely(status & (ATA_ERR | ATA_DF))) {
1041 /* device stops HSM for abort/error */
1042 qc->err_mask |= AC_ERR_DEV;
1043
1044 /* If diagnostic failed and this is
1045 * IDENTIFY, it's likely a phantom
1046 * device. Mark hint.
1047 */
1048 if (qc->dev->horkage &
1049 ATA_HORKAGE_DIAGNOSTIC)
1050 qc->err_mask |=
1051 AC_ERR_NODEV_HINT;
1052 } else {
1053 /* HSM violation. Let EH handle this.
1054 * Phantom devices also trigger this
1055 * condition. Mark hint.
1056 */
1057 ata_ehi_push_desc(ehi, "ST-ATA: "
1058 "DRQ=0 without device error, "
1059 "dev_stat 0x%X", status);
1060 qc->err_mask |= AC_ERR_HSM |
1061 AC_ERR_NODEV_HINT;
1062 }
1063
1064 ap->hsm_task_state = HSM_ST_ERR;
1065 goto fsm_start;
1066 }
1067
1068 /* For PIO reads, some devices may ask for
1069 * data transfer (DRQ=1) alone with ERR=1.
1070 * We respect DRQ here and transfer one
1071 * block of junk data before changing the
1072 * hsm_task_state to HSM_ST_ERR.
1073 *
1074 * For PIO writes, ERR=1 DRQ=1 doesn't make
1075 * sense since the data block has been
1076 * transferred to the device.
1077 */
1078 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1079 /* data might be corrputed */
1080 qc->err_mask |= AC_ERR_DEV;
1081
1082 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1083 ata_pio_sectors(qc);
1084 status = ata_wait_idle(ap);
1085 }
1086
1087 if (status & (ATA_BUSY | ATA_DRQ)) {
1088 ata_ehi_push_desc(ehi, "ST-ATA: "
1089 "BUSY|DRQ persists on ERR|DF, "
1090 "dev_stat 0x%X", status);
1091 qc->err_mask |= AC_ERR_HSM;
1092 }
1093
1094 /* There are oddball controllers with
1095 * status register stuck at 0x7f and
1096 * lbal/m/h at zero which makes it
1097 * pass all other presence detection
1098 * mechanisms we have. Set NODEV_HINT
1099 * for it. Kernel bz#7241.
1100 */
1101 if (status == 0x7f)
1102 qc->err_mask |= AC_ERR_NODEV_HINT;
1103
1104 /* ata_pio_sectors() might change the
1105 * state to HSM_ST_LAST. so, the state
1106 * is changed after ata_pio_sectors().
1107 */
1108 ap->hsm_task_state = HSM_ST_ERR;
1109 goto fsm_start;
1110 }
1111
1112 ata_pio_sectors(qc);
1113
1114 if (ap->hsm_task_state == HSM_ST_LAST &&
1115 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1116 /* all data read */
1117 status = ata_wait_idle(ap);
1118 goto fsm_start;
1119 }
1120 }
1121
1122 poll_next = 1;
1123 break;
1124
1125 case HSM_ST_LAST:
1126 if (unlikely(!ata_ok(status))) {
1127 qc->err_mask |= __ac_err_mask(status);
1128 ap->hsm_task_state = HSM_ST_ERR;
1129 goto fsm_start;
1130 }
1131
1132 /* no more data to transfer */
1133 trace_ata_sff_hsm_command_complete(qc, status);
1134
1135 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1136
1137 ap->hsm_task_state = HSM_ST_IDLE;
1138
1139 /* complete taskfile transaction */
1140 ata_hsm_qc_complete(qc, in_wq);
1141
1142 poll_next = 0;
1143 break;
1144
1145 case HSM_ST_ERR:
1146 ap->hsm_task_state = HSM_ST_IDLE;
1147
1148 /* complete taskfile transaction */
1149 ata_hsm_qc_complete(qc, in_wq);
1150
1151 poll_next = 0;
1152 break;
1153 default:
1154 poll_next = 0;
1155 WARN(true, "ata%d: SFF host state machine in invalid state %d",
1156 ap->print_id, ap->hsm_task_state);
1157 }
1158
1159 return poll_next;
1160}
1161EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1162
1163void ata_sff_queue_work(struct work_struct *work)
1164{
1165 queue_work(ata_sff_wq, work);
1166}
1167EXPORT_SYMBOL_GPL(ata_sff_queue_work);
1168
1169void ata_sff_queue_delayed_work(struct delayed_work *dwork, unsigned long delay)
1170{
1171 queue_delayed_work(ata_sff_wq, dwork, delay);
1172}
1173EXPORT_SYMBOL_GPL(ata_sff_queue_delayed_work);
1174
1175void ata_sff_queue_pio_task(struct ata_link *link, unsigned long delay)
1176{
1177 struct ata_port *ap = link->ap;
1178
1179 WARN_ON((ap->sff_pio_task_link != NULL) &&
1180 (ap->sff_pio_task_link != link));
1181 ap->sff_pio_task_link = link;
1182
1183 /* may fail if ata_sff_flush_pio_task() in progress */
1184 ata_sff_queue_delayed_work(&ap->sff_pio_task, msecs_to_jiffies(delay));
1185}
1186EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task);
1187
1188void ata_sff_flush_pio_task(struct ata_port *ap)
1189{
1190 trace_ata_sff_flush_pio_task(ap);
1191
1192 cancel_delayed_work_sync(&ap->sff_pio_task);
1193
1194 /*
1195 * We wanna reset the HSM state to IDLE. If we do so without
1196 * grabbing the port lock, critical sections protected by it which
1197 * expect the HSM state to stay stable may get surprised. For
1198 * example, we may set IDLE in between the time
1199 * __ata_sff_port_intr() checks for HSM_ST_IDLE and before it calls
1200 * ata_sff_hsm_move() causing ata_sff_hsm_move() to BUG().
1201 */
1202 spin_lock_irq(ap->lock);
1203 ap->hsm_task_state = HSM_ST_IDLE;
1204 spin_unlock_irq(ap->lock);
1205
1206 ap->sff_pio_task_link = NULL;
1207}
1208
1209static void ata_sff_pio_task(struct work_struct *work)
1210{
1211 struct ata_port *ap =
1212 container_of(work, struct ata_port, sff_pio_task.work);
1213 struct ata_link *link = ap->sff_pio_task_link;
1214 struct ata_queued_cmd *qc;
1215 u8 status;
1216 int poll_next;
1217
1218 spin_lock_irq(ap->lock);
1219
1220 BUG_ON(ap->sff_pio_task_link == NULL);
1221 /* qc can be NULL if timeout occurred */
1222 qc = ata_qc_from_tag(ap, link->active_tag);
1223 if (!qc) {
1224 ap->sff_pio_task_link = NULL;
1225 goto out_unlock;
1226 }
1227
1228fsm_start:
1229 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1230
1231 /*
1232 * This is purely heuristic. This is a fast path.
1233 * Sometimes when we enter, BSY will be cleared in
1234 * a chk-status or two. If not, the drive is probably seeking
1235 * or something. Snooze for a couple msecs, then
1236 * chk-status again. If still busy, queue delayed work.
1237 */
1238 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1239 if (status & ATA_BUSY) {
1240 spin_unlock_irq(ap->lock);
1241 ata_msleep(ap, 2);
1242 spin_lock_irq(ap->lock);
1243
1244 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1245 if (status & ATA_BUSY) {
1246 ata_sff_queue_pio_task(link, ATA_SHORT_PAUSE);
1247 goto out_unlock;
1248 }
1249 }
1250
1251 /*
1252 * hsm_move() may trigger another command to be processed.
1253 * clean the link beforehand.
1254 */
1255 ap->sff_pio_task_link = NULL;
1256 /* move the HSM */
1257 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1258
1259 /* another command or interrupt handler
1260 * may be running at this point.
1261 */
1262 if (poll_next)
1263 goto fsm_start;
1264out_unlock:
1265 spin_unlock_irq(ap->lock);
1266}
1267
1268/**
1269 * ata_sff_qc_issue - issue taskfile to a SFF controller
1270 * @qc: command to issue to device
1271 *
1272 * This function issues a PIO or NODATA command to a SFF
1273 * controller.
1274 *
1275 * LOCKING:
1276 * spin_lock_irqsave(host lock)
1277 *
1278 * RETURNS:
1279 * Zero on success, AC_ERR_* mask on failure
1280 */
1281unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1282{
1283 struct ata_port *ap = qc->ap;
1284 struct ata_link *link = qc->dev->link;
1285
1286 /* Use polling pio if the LLD doesn't handle
1287 * interrupt driven pio and atapi CDB interrupt.
1288 */
1289 if (ap->flags & ATA_FLAG_PIO_POLLING)
1290 qc->tf.flags |= ATA_TFLAG_POLLING;
1291
1292 /* select the device */
1293 ata_dev_select(ap, qc->dev->devno, 1, 0);
1294
1295 /* start the command */
1296 switch (qc->tf.protocol) {
1297 case ATA_PROT_NODATA:
1298 if (qc->tf.flags & ATA_TFLAG_POLLING)
1299 ata_qc_set_polling(qc);
1300
1301 ata_tf_to_host(ap, &qc->tf, qc->tag);
1302 ap->hsm_task_state = HSM_ST_LAST;
1303
1304 if (qc->tf.flags & ATA_TFLAG_POLLING)
1305 ata_sff_queue_pio_task(link, 0);
1306
1307 break;
1308
1309 case ATA_PROT_PIO:
1310 if (qc->tf.flags & ATA_TFLAG_POLLING)
1311 ata_qc_set_polling(qc);
1312
1313 ata_tf_to_host(ap, &qc->tf, qc->tag);
1314
1315 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1316 /* PIO data out protocol */
1317 ap->hsm_task_state = HSM_ST_FIRST;
1318 ata_sff_queue_pio_task(link, 0);
1319
1320 /* always send first data block using the
1321 * ata_sff_pio_task() codepath.
1322 */
1323 } else {
1324 /* PIO data in protocol */
1325 ap->hsm_task_state = HSM_ST;
1326
1327 if (qc->tf.flags & ATA_TFLAG_POLLING)
1328 ata_sff_queue_pio_task(link, 0);
1329
1330 /* if polling, ata_sff_pio_task() handles the
1331 * rest. otherwise, interrupt handler takes
1332 * over from here.
1333 */
1334 }
1335
1336 break;
1337
1338 case ATAPI_PROT_PIO:
1339 case ATAPI_PROT_NODATA:
1340 if (qc->tf.flags & ATA_TFLAG_POLLING)
1341 ata_qc_set_polling(qc);
1342
1343 ata_tf_to_host(ap, &qc->tf, qc->tag);
1344
1345 ap->hsm_task_state = HSM_ST_FIRST;
1346
1347 /* send cdb by polling if no cdb interrupt */
1348 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1349 (qc->tf.flags & ATA_TFLAG_POLLING))
1350 ata_sff_queue_pio_task(link, 0);
1351 break;
1352
1353 default:
1354 return AC_ERR_SYSTEM;
1355 }
1356
1357 return 0;
1358}
1359EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1360
1361/**
1362 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1363 * @qc: qc to fill result TF for
1364 *
1365 * @qc is finished and result TF needs to be filled. Fill it
1366 * using ->sff_tf_read.
1367 *
1368 * LOCKING:
1369 * spin_lock_irqsave(host lock)
1370 */
1371void ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1372{
1373 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1374}
1375EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1376
1377static unsigned int ata_sff_idle_irq(struct ata_port *ap)
1378{
1379 ap->stats.idle_irq++;
1380
1381#ifdef ATA_IRQ_TRAP
1382 if ((ap->stats.idle_irq % 1000) == 0) {
1383 ap->ops->sff_check_status(ap);
1384 if (ap->ops->sff_irq_clear)
1385 ap->ops->sff_irq_clear(ap);
1386 ata_port_warn(ap, "irq trap\n");
1387 return 1;
1388 }
1389#endif
1390 return 0; /* irq not handled */
1391}
1392
1393static unsigned int __ata_sff_port_intr(struct ata_port *ap,
1394 struct ata_queued_cmd *qc,
1395 bool hsmv_on_idle)
1396{
1397 u8 status;
1398
1399 trace_ata_sff_port_intr(qc, hsmv_on_idle);
1400
1401 /* Check whether we are expecting interrupt in this state */
1402 switch (ap->hsm_task_state) {
1403 case HSM_ST_FIRST:
1404 /* Some pre-ATAPI-4 devices assert INTRQ
1405 * at this state when ready to receive CDB.
1406 */
1407
1408 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1409 * The flag was turned on only for atapi devices. No
1410 * need to check ata_is_atapi(qc->tf.protocol) again.
1411 */
1412 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1413 return ata_sff_idle_irq(ap);
1414 break;
1415 case HSM_ST_IDLE:
1416 return ata_sff_idle_irq(ap);
1417 default:
1418 break;
1419 }
1420
1421 /* check main status, clearing INTRQ if needed */
1422 status = ata_sff_irq_status(ap);
1423 if (status & ATA_BUSY) {
1424 if (hsmv_on_idle) {
1425 /* BMDMA engine is already stopped, we're screwed */
1426 qc->err_mask |= AC_ERR_HSM;
1427 ap->hsm_task_state = HSM_ST_ERR;
1428 } else
1429 return ata_sff_idle_irq(ap);
1430 }
1431
1432 /* clear irq events */
1433 if (ap->ops->sff_irq_clear)
1434 ap->ops->sff_irq_clear(ap);
1435
1436 ata_sff_hsm_move(ap, qc, status, 0);
1437
1438 return 1; /* irq handled */
1439}
1440
1441/**
1442 * ata_sff_port_intr - Handle SFF port interrupt
1443 * @ap: Port on which interrupt arrived (possibly...)
1444 * @qc: Taskfile currently active in engine
1445 *
1446 * Handle port interrupt for given queued command.
1447 *
1448 * LOCKING:
1449 * spin_lock_irqsave(host lock)
1450 *
1451 * RETURNS:
1452 * One if interrupt was handled, zero if not (shared irq).
1453 */
1454unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
1455{
1456 return __ata_sff_port_intr(ap, qc, false);
1457}
1458EXPORT_SYMBOL_GPL(ata_sff_port_intr);
1459
1460static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance,
1461 unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *))
1462{
1463 struct ata_host *host = dev_instance;
1464 bool retried = false;
1465 unsigned int i;
1466 unsigned int handled, idle, polling;
1467 unsigned long flags;
1468
1469 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1470 spin_lock_irqsave(&host->lock, flags);
1471
1472retry:
1473 handled = idle = polling = 0;
1474 for (i = 0; i < host->n_ports; i++) {
1475 struct ata_port *ap = host->ports[i];
1476 struct ata_queued_cmd *qc;
1477
1478 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1479 if (qc) {
1480 if (!(qc->tf.flags & ATA_TFLAG_POLLING))
1481 handled |= port_intr(ap, qc);
1482 else
1483 polling |= 1 << i;
1484 } else
1485 idle |= 1 << i;
1486 }
1487
1488 /*
1489 * If no port was expecting IRQ but the controller is actually
1490 * asserting IRQ line, nobody cared will ensue. Check IRQ
1491 * pending status if available and clear spurious IRQ.
1492 */
1493 if (!handled && !retried) {
1494 bool retry = false;
1495
1496 for (i = 0; i < host->n_ports; i++) {
1497 struct ata_port *ap = host->ports[i];
1498
1499 if (polling & (1 << i))
1500 continue;
1501
1502 if (!ap->ops->sff_irq_check ||
1503 !ap->ops->sff_irq_check(ap))
1504 continue;
1505
1506 if (idle & (1 << i)) {
1507 ap->ops->sff_check_status(ap);
1508 if (ap->ops->sff_irq_clear)
1509 ap->ops->sff_irq_clear(ap);
1510 } else {
1511 /* clear INTRQ and check if BUSY cleared */
1512 if (!(ap->ops->sff_check_status(ap) & ATA_BUSY))
1513 retry |= true;
1514 /*
1515 * With command in flight, we can't do
1516 * sff_irq_clear() w/o racing with completion.
1517 */
1518 }
1519 }
1520
1521 if (retry) {
1522 retried = true;
1523 goto retry;
1524 }
1525 }
1526
1527 spin_unlock_irqrestore(&host->lock, flags);
1528
1529 return IRQ_RETVAL(handled);
1530}
1531
1532/**
1533 * ata_sff_interrupt - Default SFF ATA host interrupt handler
1534 * @irq: irq line (unused)
1535 * @dev_instance: pointer to our ata_host information structure
1536 *
1537 * Default interrupt handler for PCI IDE devices. Calls
1538 * ata_sff_port_intr() for each port that is not disabled.
1539 *
1540 * LOCKING:
1541 * Obtains host lock during operation.
1542 *
1543 * RETURNS:
1544 * IRQ_NONE or IRQ_HANDLED.
1545 */
1546irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1547{
1548 return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr);
1549}
1550EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1551
1552/**
1553 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1554 * @ap: port that appears to have timed out
1555 *
1556 * Called from the libata error handlers when the core code suspects
1557 * an interrupt has been lost. If it has complete anything we can and
1558 * then return. Interface must support altstatus for this faster
1559 * recovery to occur.
1560 *
1561 * Locking:
1562 * Caller holds host lock
1563 */
1564
1565void ata_sff_lost_interrupt(struct ata_port *ap)
1566{
1567 u8 status = 0;
1568 struct ata_queued_cmd *qc;
1569
1570 /* Only one outstanding command per SFF channel */
1571 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1572 /* We cannot lose an interrupt on a non-existent or polled command */
1573 if (!qc || qc->tf.flags & ATA_TFLAG_POLLING)
1574 return;
1575 /* See if the controller thinks it is still busy - if so the command
1576 isn't a lost IRQ but is still in progress */
1577 if (WARN_ON_ONCE(!ata_sff_altstatus(ap, &status)))
1578 return;
1579 if (status & ATA_BUSY)
1580 return;
1581
1582 /* There was a command running, we are no longer busy and we have
1583 no interrupt. */
1584 ata_port_warn(ap, "lost interrupt (Status 0x%x)\n", status);
1585 /* Run the host interrupt logic as if the interrupt had not been
1586 lost */
1587 ata_sff_port_intr(ap, qc);
1588}
1589EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1590
1591/**
1592 * ata_sff_freeze - Freeze SFF controller port
1593 * @ap: port to freeze
1594 *
1595 * Freeze SFF controller port.
1596 *
1597 * LOCKING:
1598 * Inherited from caller.
1599 */
1600void ata_sff_freeze(struct ata_port *ap)
1601{
1602 ap->ctl |= ATA_NIEN;
1603 ap->last_ctl = ap->ctl;
1604
1605 ata_sff_set_devctl(ap, ap->ctl);
1606
1607 /* Under certain circumstances, some controllers raise IRQ on
1608 * ATA_NIEN manipulation. Also, many controllers fail to mask
1609 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1610 */
1611 ap->ops->sff_check_status(ap);
1612
1613 if (ap->ops->sff_irq_clear)
1614 ap->ops->sff_irq_clear(ap);
1615}
1616EXPORT_SYMBOL_GPL(ata_sff_freeze);
1617
1618/**
1619 * ata_sff_thaw - Thaw SFF controller port
1620 * @ap: port to thaw
1621 *
1622 * Thaw SFF controller port.
1623 *
1624 * LOCKING:
1625 * Inherited from caller.
1626 */
1627void ata_sff_thaw(struct ata_port *ap)
1628{
1629 /* clear & re-enable interrupts */
1630 ap->ops->sff_check_status(ap);
1631 if (ap->ops->sff_irq_clear)
1632 ap->ops->sff_irq_clear(ap);
1633 ata_sff_irq_on(ap);
1634}
1635EXPORT_SYMBOL_GPL(ata_sff_thaw);
1636
1637/**
1638 * ata_sff_prereset - prepare SFF link for reset
1639 * @link: SFF link to be reset
1640 * @deadline: deadline jiffies for the operation
1641 *
1642 * SFF link @link is about to be reset. Initialize it. It first
1643 * calls ata_std_prereset() and wait for !BSY if the port is
1644 * being softreset.
1645 *
1646 * LOCKING:
1647 * Kernel thread context (may sleep)
1648 *
1649 * RETURNS:
1650 * Always 0.
1651 */
1652int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1653{
1654 struct ata_eh_context *ehc = &link->eh_context;
1655 int rc;
1656
1657 /* The standard prereset is best-effort and always returns 0 */
1658 ata_std_prereset(link, deadline);
1659
1660 /* if we're about to do hardreset, nothing more to do */
1661 if (ehc->i.action & ATA_EH_HARDRESET)
1662 return 0;
1663
1664 /* wait for !BSY if we don't know that no device is attached */
1665 if (!ata_link_offline(link)) {
1666 rc = ata_sff_wait_ready(link, deadline);
1667 if (rc && rc != -ENODEV) {
1668 ata_link_warn(link,
1669 "device not ready (errno=%d), forcing hardreset\n",
1670 rc);
1671 ehc->i.action |= ATA_EH_HARDRESET;
1672 }
1673 }
1674
1675 return 0;
1676}
1677EXPORT_SYMBOL_GPL(ata_sff_prereset);
1678
1679/**
1680 * ata_devchk - PATA device presence detection
1681 * @ap: ATA channel to examine
1682 * @device: Device to examine (starting at zero)
1683 *
1684 * This technique was originally described in
1685 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1686 * later found its way into the ATA/ATAPI spec.
1687 *
1688 * Write a pattern to the ATA shadow registers,
1689 * and if a device is present, it will respond by
1690 * correctly storing and echoing back the
1691 * ATA shadow register contents.
1692 *
1693 * RETURN:
1694 * true if device is present, false if not.
1695 *
1696 * LOCKING:
1697 * caller.
1698 */
1699static bool ata_devchk(struct ata_port *ap, unsigned int device)
1700{
1701 struct ata_ioports *ioaddr = &ap->ioaddr;
1702 u8 nsect, lbal;
1703
1704 ap->ops->sff_dev_select(ap, device);
1705
1706 iowrite8(0x55, ioaddr->nsect_addr);
1707 iowrite8(0xaa, ioaddr->lbal_addr);
1708
1709 iowrite8(0xaa, ioaddr->nsect_addr);
1710 iowrite8(0x55, ioaddr->lbal_addr);
1711
1712 iowrite8(0x55, ioaddr->nsect_addr);
1713 iowrite8(0xaa, ioaddr->lbal_addr);
1714
1715 nsect = ioread8(ioaddr->nsect_addr);
1716 lbal = ioread8(ioaddr->lbal_addr);
1717
1718 if ((nsect == 0x55) && (lbal == 0xaa))
1719 return true; /* we found a device */
1720
1721 return false; /* nothing found */
1722}
1723
1724/**
1725 * ata_sff_dev_classify - Parse returned ATA device signature
1726 * @dev: ATA device to classify (starting at zero)
1727 * @present: device seems present
1728 * @r_err: Value of error register on completion
1729 *
1730 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1731 * an ATA/ATAPI-defined set of values is placed in the ATA
1732 * shadow registers, indicating the results of device detection
1733 * and diagnostics.
1734 *
1735 * Select the ATA device, and read the values from the ATA shadow
1736 * registers. Then parse according to the Error register value,
1737 * and the spec-defined values examined by ata_dev_classify().
1738 *
1739 * LOCKING:
1740 * caller.
1741 *
1742 * RETURNS:
1743 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1744 */
1745unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1746 u8 *r_err)
1747{
1748 struct ata_port *ap = dev->link->ap;
1749 struct ata_taskfile tf;
1750 unsigned int class;
1751 u8 err;
1752
1753 ap->ops->sff_dev_select(ap, dev->devno);
1754
1755 memset(&tf, 0, sizeof(tf));
1756
1757 ap->ops->sff_tf_read(ap, &tf);
1758 err = tf.error;
1759 if (r_err)
1760 *r_err = err;
1761
1762 /* see if device passed diags: continue and warn later */
1763 if (err == 0)
1764 /* diagnostic fail : do nothing _YET_ */
1765 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
1766 else if (err == 1)
1767 /* do nothing */ ;
1768 else if ((dev->devno == 0) && (err == 0x81))
1769 /* do nothing */ ;
1770 else
1771 return ATA_DEV_NONE;
1772
1773 /* determine if device is ATA or ATAPI */
1774 class = ata_port_classify(ap, &tf);
1775 switch (class) {
1776 case ATA_DEV_UNKNOWN:
1777 /*
1778 * If the device failed diagnostic, it's likely to
1779 * have reported incorrect device signature too.
1780 * Assume ATA device if the device seems present but
1781 * device signature is invalid with diagnostic
1782 * failure.
1783 */
1784 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
1785 class = ATA_DEV_ATA;
1786 else
1787 class = ATA_DEV_NONE;
1788 break;
1789 case ATA_DEV_ATA:
1790 if (ap->ops->sff_check_status(ap) == 0)
1791 class = ATA_DEV_NONE;
1792 break;
1793 }
1794 return class;
1795}
1796EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
1797
1798/**
1799 * ata_sff_wait_after_reset - wait for devices to become ready after reset
1800 * @link: SFF link which is just reset
1801 * @devmask: mask of present devices
1802 * @deadline: deadline jiffies for the operation
1803 *
1804 * Wait devices attached to SFF @link to become ready after
1805 * reset. It contains preceding 150ms wait to avoid accessing TF
1806 * status register too early.
1807 *
1808 * LOCKING:
1809 * Kernel thread context (may sleep).
1810 *
1811 * RETURNS:
1812 * 0 on success, -ENODEV if some or all of devices in @devmask
1813 * don't seem to exist. -errno on other errors.
1814 */
1815int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
1816 unsigned long deadline)
1817{
1818 struct ata_port *ap = link->ap;
1819 struct ata_ioports *ioaddr = &ap->ioaddr;
1820 unsigned int dev0 = devmask & (1 << 0);
1821 unsigned int dev1 = devmask & (1 << 1);
1822 int rc, ret = 0;
1823
1824 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
1825
1826 /* always check readiness of the master device */
1827 rc = ata_sff_wait_ready(link, deadline);
1828 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
1829 * and TF status is 0xff, bail out on it too.
1830 */
1831 if (rc)
1832 return rc;
1833
1834 /* if device 1 was found in ata_devchk, wait for register
1835 * access briefly, then wait for BSY to clear.
1836 */
1837 if (dev1) {
1838 int i;
1839
1840 ap->ops->sff_dev_select(ap, 1);
1841
1842 /* Wait for register access. Some ATAPI devices fail
1843 * to set nsect/lbal after reset, so don't waste too
1844 * much time on it. We're gonna wait for !BSY anyway.
1845 */
1846 for (i = 0; i < 2; i++) {
1847 u8 nsect, lbal;
1848
1849 nsect = ioread8(ioaddr->nsect_addr);
1850 lbal = ioread8(ioaddr->lbal_addr);
1851 if ((nsect == 1) && (lbal == 1))
1852 break;
1853 ata_msleep(ap, 50); /* give drive a breather */
1854 }
1855
1856 rc = ata_sff_wait_ready(link, deadline);
1857 if (rc) {
1858 if (rc != -ENODEV)
1859 return rc;
1860 ret = rc;
1861 }
1862 }
1863
1864 /* is all this really necessary? */
1865 ap->ops->sff_dev_select(ap, 0);
1866 if (dev1)
1867 ap->ops->sff_dev_select(ap, 1);
1868 if (dev0)
1869 ap->ops->sff_dev_select(ap, 0);
1870
1871 return ret;
1872}
1873EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
1874
1875static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
1876 unsigned long deadline)
1877{
1878 struct ata_ioports *ioaddr = &ap->ioaddr;
1879
1880 if (ap->ioaddr.ctl_addr) {
1881 /* software reset. causes dev0 to be selected */
1882 iowrite8(ap->ctl, ioaddr->ctl_addr);
1883 udelay(20); /* FIXME: flush */
1884 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1885 udelay(20); /* FIXME: flush */
1886 iowrite8(ap->ctl, ioaddr->ctl_addr);
1887 ap->last_ctl = ap->ctl;
1888 }
1889
1890 /* wait the port to become ready */
1891 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
1892}
1893
1894/**
1895 * ata_sff_softreset - reset host port via ATA SRST
1896 * @link: ATA link to reset
1897 * @classes: resulting classes of attached devices
1898 * @deadline: deadline jiffies for the operation
1899 *
1900 * Reset host port using ATA SRST.
1901 *
1902 * LOCKING:
1903 * Kernel thread context (may sleep)
1904 *
1905 * RETURNS:
1906 * 0 on success, -errno otherwise.
1907 */
1908int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
1909 unsigned long deadline)
1910{
1911 struct ata_port *ap = link->ap;
1912 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
1913 unsigned int devmask = 0;
1914 int rc;
1915 u8 err;
1916
1917 /* determine if device 0/1 are present */
1918 if (ata_devchk(ap, 0))
1919 devmask |= (1 << 0);
1920 if (slave_possible && ata_devchk(ap, 1))
1921 devmask |= (1 << 1);
1922
1923 /* select device 0 again */
1924 ap->ops->sff_dev_select(ap, 0);
1925
1926 /* issue bus reset */
1927 rc = ata_bus_softreset(ap, devmask, deadline);
1928 /* if link is occupied, -ENODEV too is an error */
1929 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1930 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
1931 return rc;
1932 }
1933
1934 /* determine by signature whether we have ATA or ATAPI devices */
1935 classes[0] = ata_sff_dev_classify(&link->device[0],
1936 devmask & (1 << 0), &err);
1937 if (slave_possible && err != 0x81)
1938 classes[1] = ata_sff_dev_classify(&link->device[1],
1939 devmask & (1 << 1), &err);
1940
1941 return 0;
1942}
1943EXPORT_SYMBOL_GPL(ata_sff_softreset);
1944
1945/**
1946 * sata_sff_hardreset - reset host port via SATA phy reset
1947 * @link: link to reset
1948 * @class: resulting class of attached device
1949 * @deadline: deadline jiffies for the operation
1950 *
1951 * SATA phy-reset host port using DET bits of SControl register,
1952 * wait for !BSY and classify the attached device.
1953 *
1954 * LOCKING:
1955 * Kernel thread context (may sleep)
1956 *
1957 * RETURNS:
1958 * 0 on success, -errno otherwise.
1959 */
1960int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
1961 unsigned long deadline)
1962{
1963 struct ata_eh_context *ehc = &link->eh_context;
1964 const unsigned int *timing = sata_ehc_deb_timing(ehc);
1965 bool online;
1966 int rc;
1967
1968 rc = sata_link_hardreset(link, timing, deadline, &online,
1969 ata_sff_check_ready);
1970 if (online)
1971 *class = ata_sff_dev_classify(link->device, 1, NULL);
1972
1973 return rc;
1974}
1975EXPORT_SYMBOL_GPL(sata_sff_hardreset);
1976
1977/**
1978 * ata_sff_postreset - SFF postreset callback
1979 * @link: the target SFF ata_link
1980 * @classes: classes of attached devices
1981 *
1982 * This function is invoked after a successful reset. It first
1983 * calls ata_std_postreset() and performs SFF specific postreset
1984 * processing.
1985 *
1986 * LOCKING:
1987 * Kernel thread context (may sleep)
1988 */
1989void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
1990{
1991 struct ata_port *ap = link->ap;
1992
1993 ata_std_postreset(link, classes);
1994
1995 /* is double-select really necessary? */
1996 if (classes[0] != ATA_DEV_NONE)
1997 ap->ops->sff_dev_select(ap, 1);
1998 if (classes[1] != ATA_DEV_NONE)
1999 ap->ops->sff_dev_select(ap, 0);
2000
2001 /* bail out if no device is present */
2002 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE)
2003 return;
2004
2005 /* set up device control */
2006 if (ata_sff_set_devctl(ap, ap->ctl))
2007 ap->last_ctl = ap->ctl;
2008}
2009EXPORT_SYMBOL_GPL(ata_sff_postreset);
2010
2011/**
2012 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2013 * @qc: command
2014 *
2015 * Drain the FIFO and device of any stuck data following a command
2016 * failing to complete. In some cases this is necessary before a
2017 * reset will recover the device.
2018 *
2019 */
2020
2021void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2022{
2023 int count;
2024 struct ata_port *ap;
2025
2026 /* We only need to flush incoming data when a command was running */
2027 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2028 return;
2029
2030 ap = qc->ap;
2031 /* Drain up to 64K of data before we give up this recovery method */
2032 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2033 && count < 65536; count += 2)
2034 ioread16(ap->ioaddr.data_addr);
2035
2036 if (count)
2037 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
2038
2039}
2040EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2041
2042/**
2043 * ata_sff_error_handler - Stock error handler for SFF controller
2044 * @ap: port to handle error for
2045 *
2046 * Stock error handler for SFF controller. It can handle both
2047 * PATA and SATA controllers. Many controllers should be able to
2048 * use this EH as-is or with some added handling before and
2049 * after.
2050 *
2051 * LOCKING:
2052 * Kernel thread context (may sleep)
2053 */
2054void ata_sff_error_handler(struct ata_port *ap)
2055{
2056 ata_reset_fn_t softreset = ap->ops->softreset;
2057 ata_reset_fn_t hardreset = ap->ops->hardreset;
2058 struct ata_queued_cmd *qc;
2059 unsigned long flags;
2060
2061 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2062 if (qc && !(qc->flags & ATA_QCFLAG_EH))
2063 qc = NULL;
2064
2065 spin_lock_irqsave(ap->lock, flags);
2066
2067 /*
2068 * We *MUST* do FIFO draining before we issue a reset as
2069 * several devices helpfully clear their internal state and
2070 * will lock solid if we touch the data port post reset. Pass
2071 * qc in case anyone wants to do different PIO/DMA recovery or
2072 * has per command fixups
2073 */
2074 if (ap->ops->sff_drain_fifo)
2075 ap->ops->sff_drain_fifo(qc);
2076
2077 spin_unlock_irqrestore(ap->lock, flags);
2078
2079 /* ignore built-in hardresets if SCR access is not available */
2080 if ((hardreset == sata_std_hardreset ||
2081 hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link))
2082 hardreset = NULL;
2083
2084 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2085 ap->ops->postreset);
2086}
2087EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2088
2089/**
2090 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2091 * @ioaddr: IO address structure to be initialized
2092 *
2093 * Utility function which initializes data_addr, error_addr,
2094 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2095 * device_addr, status_addr, and command_addr to standard offsets
2096 * relative to cmd_addr.
2097 *
2098 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2099 */
2100void ata_sff_std_ports(struct ata_ioports *ioaddr)
2101{
2102 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2103 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2104 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2105 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2106 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2107 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2108 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2109 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2110 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2111 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2112}
2113EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2114
2115#ifdef CONFIG_PCI
2116
2117static bool ata_resources_present(struct pci_dev *pdev, int port)
2118{
2119 int i;
2120
2121 /* Check the PCI resources for this channel are enabled */
2122 port *= 2;
2123 for (i = 0; i < 2; i++) {
2124 if (pci_resource_start(pdev, port + i) == 0 ||
2125 pci_resource_len(pdev, port + i) == 0)
2126 return false;
2127 }
2128 return true;
2129}
2130
2131/**
2132 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2133 * @host: target ATA host
2134 *
2135 * Acquire native PCI ATA resources for @host and initialize the
2136 * first two ports of @host accordingly. Ports marked dummy are
2137 * skipped and allocation failure makes the port dummy.
2138 *
2139 * Note that native PCI resources are valid even for legacy hosts
2140 * as we fix up pdev resources array early in boot, so this
2141 * function can be used for both native and legacy SFF hosts.
2142 *
2143 * LOCKING:
2144 * Inherited from calling layer (may sleep).
2145 *
2146 * RETURNS:
2147 * 0 if at least one port is initialized, -ENODEV if no port is
2148 * available.
2149 */
2150int ata_pci_sff_init_host(struct ata_host *host)
2151{
2152 struct device *gdev = host->dev;
2153 struct pci_dev *pdev = to_pci_dev(gdev);
2154 unsigned int mask = 0;
2155 int i, rc;
2156
2157 /* request, iomap BARs and init port addresses accordingly */
2158 for (i = 0; i < 2; i++) {
2159 struct ata_port *ap = host->ports[i];
2160 int base = i * 2;
2161 void __iomem * const *iomap;
2162
2163 if (ata_port_is_dummy(ap))
2164 continue;
2165
2166 /* Discard disabled ports. Some controllers show
2167 * their unused channels this way. Disabled ports are
2168 * made dummy.
2169 */
2170 if (!ata_resources_present(pdev, i)) {
2171 ap->ops = &ata_dummy_port_ops;
2172 continue;
2173 }
2174
2175 rc = pcim_iomap_regions(pdev, 0x3 << base,
2176 dev_driver_string(gdev));
2177 if (rc) {
2178 dev_warn(gdev,
2179 "failed to request/iomap BARs for port %d (errno=%d)\n",
2180 i, rc);
2181 if (rc == -EBUSY)
2182 pcim_pin_device(pdev);
2183 ap->ops = &ata_dummy_port_ops;
2184 continue;
2185 }
2186 host->iomap = iomap = pcim_iomap_table(pdev);
2187
2188 ap->ioaddr.cmd_addr = iomap[base];
2189 ap->ioaddr.altstatus_addr =
2190 ap->ioaddr.ctl_addr = (void __iomem *)
2191 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2192 ata_sff_std_ports(&ap->ioaddr);
2193
2194 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2195 (unsigned long long)pci_resource_start(pdev, base),
2196 (unsigned long long)pci_resource_start(pdev, base + 1));
2197
2198 mask |= 1 << i;
2199 }
2200
2201 if (!mask) {
2202 dev_err(gdev, "no available native port\n");
2203 return -ENODEV;
2204 }
2205
2206 return 0;
2207}
2208EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2209
2210/**
2211 * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host
2212 * @pdev: target PCI device
2213 * @ppi: array of port_info, must be enough for two ports
2214 * @r_host: out argument for the initialized ATA host
2215 *
2216 * Helper to allocate PIO-only SFF ATA host for @pdev, acquire
2217 * all PCI resources and initialize it accordingly in one go.
2218 *
2219 * LOCKING:
2220 * Inherited from calling layer (may sleep).
2221 *
2222 * RETURNS:
2223 * 0 on success, -errno otherwise.
2224 */
2225int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2226 const struct ata_port_info * const *ppi,
2227 struct ata_host **r_host)
2228{
2229 struct ata_host *host;
2230 int rc;
2231
2232 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2233 return -ENOMEM;
2234
2235 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2236 if (!host) {
2237 dev_err(&pdev->dev, "failed to allocate ATA host\n");
2238 rc = -ENOMEM;
2239 goto err_out;
2240 }
2241
2242 rc = ata_pci_sff_init_host(host);
2243 if (rc)
2244 goto err_out;
2245
2246 devres_remove_group(&pdev->dev, NULL);
2247 *r_host = host;
2248 return 0;
2249
2250err_out:
2251 devres_release_group(&pdev->dev, NULL);
2252 return rc;
2253}
2254EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2255
2256/**
2257 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2258 * @host: target SFF ATA host
2259 * @irq_handler: irq_handler used when requesting IRQ(s)
2260 * @sht: scsi_host_template to use when registering the host
2261 *
2262 * This is the counterpart of ata_host_activate() for SFF ATA
2263 * hosts. This separate helper is necessary because SFF hosts
2264 * use two separate interrupts in legacy mode.
2265 *
2266 * LOCKING:
2267 * Inherited from calling layer (may sleep).
2268 *
2269 * RETURNS:
2270 * 0 on success, -errno otherwise.
2271 */
2272int ata_pci_sff_activate_host(struct ata_host *host,
2273 irq_handler_t irq_handler,
2274 const struct scsi_host_template *sht)
2275{
2276 struct device *dev = host->dev;
2277 struct pci_dev *pdev = to_pci_dev(dev);
2278 const char *drv_name = dev_driver_string(host->dev);
2279 int legacy_mode = 0, rc;
2280
2281 rc = ata_host_start(host);
2282 if (rc)
2283 return rc;
2284
2285 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2286 u8 tmp8, mask = 0;
2287
2288 /*
2289 * ATA spec says we should use legacy mode when one
2290 * port is in legacy mode, but disabled ports on some
2291 * PCI hosts appear as fixed legacy ports, e.g SB600/700
2292 * on which the secondary port is not wired, so
2293 * ignore ports that are marked as 'dummy' during
2294 * this check
2295 */
2296 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2297 if (!ata_port_is_dummy(host->ports[0]))
2298 mask |= (1 << 0);
2299 if (!ata_port_is_dummy(host->ports[1]))
2300 mask |= (1 << 2);
2301 if ((tmp8 & mask) != mask)
2302 legacy_mode = 1;
2303 }
2304
2305 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2306 return -ENOMEM;
2307
2308 if (!legacy_mode && pdev->irq) {
2309 int i;
2310
2311 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2312 IRQF_SHARED, drv_name, host);
2313 if (rc)
2314 goto out;
2315
2316 for (i = 0; i < 2; i++) {
2317 if (ata_port_is_dummy(host->ports[i]))
2318 continue;
2319 ata_port_desc_misc(host->ports[i], pdev->irq);
2320 }
2321 } else if (legacy_mode) {
2322 if (!ata_port_is_dummy(host->ports[0])) {
2323 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2324 irq_handler, IRQF_SHARED,
2325 drv_name, host);
2326 if (rc)
2327 goto out;
2328
2329 ata_port_desc_misc(host->ports[0],
2330 ATA_PRIMARY_IRQ(pdev));
2331 }
2332
2333 if (!ata_port_is_dummy(host->ports[1])) {
2334 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2335 irq_handler, IRQF_SHARED,
2336 drv_name, host);
2337 if (rc)
2338 goto out;
2339
2340 ata_port_desc_misc(host->ports[1],
2341 ATA_SECONDARY_IRQ(pdev));
2342 }
2343 }
2344
2345 rc = ata_host_register(host, sht);
2346out:
2347 if (rc == 0)
2348 devres_remove_group(dev, NULL);
2349 else
2350 devres_release_group(dev, NULL);
2351
2352 return rc;
2353}
2354EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
2355
2356static const struct ata_port_info *ata_sff_find_valid_pi(
2357 const struct ata_port_info * const *ppi)
2358{
2359 int i;
2360
2361 /* look up the first valid port_info */
2362 for (i = 0; i < 2 && ppi[i]; i++)
2363 if (ppi[i]->port_ops != &ata_dummy_port_ops)
2364 return ppi[i];
2365
2366 return NULL;
2367}
2368
2369static int ata_pci_init_one(struct pci_dev *pdev,
2370 const struct ata_port_info * const *ppi,
2371 const struct scsi_host_template *sht, void *host_priv,
2372 int hflags, bool bmdma)
2373{
2374 struct device *dev = &pdev->dev;
2375 const struct ata_port_info *pi;
2376 struct ata_host *host = NULL;
2377 int rc;
2378
2379 pi = ata_sff_find_valid_pi(ppi);
2380 if (!pi) {
2381 dev_err(&pdev->dev, "no valid port_info specified\n");
2382 return -EINVAL;
2383 }
2384
2385 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2386 return -ENOMEM;
2387
2388 rc = pcim_enable_device(pdev);
2389 if (rc)
2390 goto out;
2391
2392#ifdef CONFIG_ATA_BMDMA
2393 if (bmdma)
2394 /* prepare and activate BMDMA host */
2395 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
2396 else
2397#endif
2398 /* prepare and activate SFF host */
2399 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
2400 if (rc)
2401 goto out;
2402 host->private_data = host_priv;
2403 host->flags |= hflags;
2404
2405#ifdef CONFIG_ATA_BMDMA
2406 if (bmdma) {
2407 pci_set_master(pdev);
2408 rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
2409 } else
2410#endif
2411 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
2412out:
2413 if (rc == 0)
2414 devres_remove_group(&pdev->dev, NULL);
2415 else
2416 devres_release_group(&pdev->dev, NULL);
2417
2418 return rc;
2419}
2420
2421/**
2422 * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller
2423 * @pdev: Controller to be initialized
2424 * @ppi: array of port_info, must be enough for two ports
2425 * @sht: scsi_host_template to use when registering the host
2426 * @host_priv: host private_data
2427 * @hflag: host flags
2428 *
2429 * This is a helper function which can be called from a driver's
2430 * xxx_init_one() probe function if the hardware uses traditional
2431 * IDE taskfile registers and is PIO only.
2432 *
2433 * ASSUMPTION:
2434 * Nobody makes a single channel controller that appears solely as
2435 * the secondary legacy port on PCI.
2436 *
2437 * LOCKING:
2438 * Inherited from PCI layer (may sleep).
2439 *
2440 * RETURNS:
2441 * Zero on success, negative on errno-based value on error.
2442 */
2443int ata_pci_sff_init_one(struct pci_dev *pdev,
2444 const struct ata_port_info * const *ppi,
2445 const struct scsi_host_template *sht, void *host_priv, int hflag)
2446{
2447 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflag, 0);
2448}
2449EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
2450
2451#endif /* CONFIG_PCI */
2452
2453/*
2454 * BMDMA support
2455 */
2456
2457#ifdef CONFIG_ATA_BMDMA
2458
2459const struct ata_port_operations ata_bmdma_port_ops = {
2460 .inherits = &ata_sff_port_ops,
2461
2462 .error_handler = ata_bmdma_error_handler,
2463 .post_internal_cmd = ata_bmdma_post_internal_cmd,
2464
2465 .qc_prep = ata_bmdma_qc_prep,
2466 .qc_issue = ata_bmdma_qc_issue,
2467
2468 .sff_irq_clear = ata_bmdma_irq_clear,
2469 .bmdma_setup = ata_bmdma_setup,
2470 .bmdma_start = ata_bmdma_start,
2471 .bmdma_stop = ata_bmdma_stop,
2472 .bmdma_status = ata_bmdma_status,
2473
2474 .port_start = ata_bmdma_port_start,
2475};
2476EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
2477
2478const struct ata_port_operations ata_bmdma32_port_ops = {
2479 .inherits = &ata_bmdma_port_ops,
2480
2481 .sff_data_xfer = ata_sff_data_xfer32,
2482 .port_start = ata_bmdma_port_start32,
2483};
2484EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
2485
2486/**
2487 * ata_bmdma_fill_sg - Fill PCI IDE PRD table
2488 * @qc: Metadata associated with taskfile to be transferred
2489 *
2490 * Fill PCI IDE PRD (scatter-gather) table with segments
2491 * associated with the current disk command.
2492 *
2493 * LOCKING:
2494 * spin_lock_irqsave(host lock)
2495 *
2496 */
2497static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc)
2498{
2499 struct ata_port *ap = qc->ap;
2500 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2501 struct scatterlist *sg;
2502 unsigned int si, pi;
2503
2504 pi = 0;
2505 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2506 u32 addr, offset;
2507 u32 sg_len, len;
2508
2509 /* determine if physical DMA addr spans 64K boundary.
2510 * Note h/w doesn't support 64-bit, so we unconditionally
2511 * truncate dma_addr_t to u32.
2512 */
2513 addr = (u32) sg_dma_address(sg);
2514 sg_len = sg_dma_len(sg);
2515
2516 while (sg_len) {
2517 offset = addr & 0xffff;
2518 len = sg_len;
2519 if ((offset + sg_len) > 0x10000)
2520 len = 0x10000 - offset;
2521
2522 prd[pi].addr = cpu_to_le32(addr);
2523 prd[pi].flags_len = cpu_to_le32(len & 0xffff);
2524
2525 pi++;
2526 sg_len -= len;
2527 addr += len;
2528 }
2529 }
2530
2531 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2532}
2533
2534/**
2535 * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table
2536 * @qc: Metadata associated with taskfile to be transferred
2537 *
2538 * Fill PCI IDE PRD (scatter-gather) table with segments
2539 * associated with the current disk command. Perform the fill
2540 * so that we avoid writing any length 64K records for
2541 * controllers that don't follow the spec.
2542 *
2543 * LOCKING:
2544 * spin_lock_irqsave(host lock)
2545 *
2546 */
2547static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc)
2548{
2549 struct ata_port *ap = qc->ap;
2550 struct ata_bmdma_prd *prd = ap->bmdma_prd;
2551 struct scatterlist *sg;
2552 unsigned int si, pi;
2553
2554 pi = 0;
2555 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2556 u32 addr, offset;
2557 u32 sg_len, len, blen;
2558
2559 /* determine if physical DMA addr spans 64K boundary.
2560 * Note h/w doesn't support 64-bit, so we unconditionally
2561 * truncate dma_addr_t to u32.
2562 */
2563 addr = (u32) sg_dma_address(sg);
2564 sg_len = sg_dma_len(sg);
2565
2566 while (sg_len) {
2567 offset = addr & 0xffff;
2568 len = sg_len;
2569 if ((offset + sg_len) > 0x10000)
2570 len = 0x10000 - offset;
2571
2572 blen = len & 0xffff;
2573 prd[pi].addr = cpu_to_le32(addr);
2574 if (blen == 0) {
2575 /* Some PATA chipsets like the CS5530 can't
2576 cope with 0x0000 meaning 64K as the spec
2577 says */
2578 prd[pi].flags_len = cpu_to_le32(0x8000);
2579 blen = 0x8000;
2580 prd[++pi].addr = cpu_to_le32(addr + 0x8000);
2581 }
2582 prd[pi].flags_len = cpu_to_le32(blen);
2583
2584 pi++;
2585 sg_len -= len;
2586 addr += len;
2587 }
2588 }
2589
2590 prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2591}
2592
2593/**
2594 * ata_bmdma_qc_prep - Prepare taskfile for submission
2595 * @qc: Metadata associated with taskfile to be prepared
2596 *
2597 * Prepare ATA taskfile for submission.
2598 *
2599 * LOCKING:
2600 * spin_lock_irqsave(host lock)
2601 */
2602enum ata_completion_errors ata_bmdma_qc_prep(struct ata_queued_cmd *qc)
2603{
2604 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2605 return AC_ERR_OK;
2606
2607 ata_bmdma_fill_sg(qc);
2608
2609 return AC_ERR_OK;
2610}
2611EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep);
2612
2613/**
2614 * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission
2615 * @qc: Metadata associated with taskfile to be prepared
2616 *
2617 * Prepare ATA taskfile for submission.
2618 *
2619 * LOCKING:
2620 * spin_lock_irqsave(host lock)
2621 */
2622enum ata_completion_errors ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc)
2623{
2624 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2625 return AC_ERR_OK;
2626
2627 ata_bmdma_fill_sg_dumb(qc);
2628
2629 return AC_ERR_OK;
2630}
2631EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep);
2632
2633/**
2634 * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller
2635 * @qc: command to issue to device
2636 *
2637 * This function issues a PIO, NODATA or DMA command to a
2638 * SFF/BMDMA controller. PIO and NODATA are handled by
2639 * ata_sff_qc_issue().
2640 *
2641 * LOCKING:
2642 * spin_lock_irqsave(host lock)
2643 *
2644 * RETURNS:
2645 * Zero on success, AC_ERR_* mask on failure
2646 */
2647unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc)
2648{
2649 struct ata_port *ap = qc->ap;
2650 struct ata_link *link = qc->dev->link;
2651
2652 /* defer PIO handling to sff_qc_issue */
2653 if (!ata_is_dma(qc->tf.protocol))
2654 return ata_sff_qc_issue(qc);
2655
2656 /* select the device */
2657 ata_dev_select(ap, qc->dev->devno, 1, 0);
2658
2659 /* start the command */
2660 switch (qc->tf.protocol) {
2661 case ATA_PROT_DMA:
2662 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2663
2664 trace_ata_tf_load(ap, &qc->tf);
2665 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2666 trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
2667 ap->ops->bmdma_setup(qc); /* set up bmdma */
2668 trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
2669 ap->ops->bmdma_start(qc); /* initiate bmdma */
2670 ap->hsm_task_state = HSM_ST_LAST;
2671 break;
2672
2673 case ATAPI_PROT_DMA:
2674 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
2675
2676 trace_ata_tf_load(ap, &qc->tf);
2677 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2678 trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
2679 ap->ops->bmdma_setup(qc); /* set up bmdma */
2680 ap->hsm_task_state = HSM_ST_FIRST;
2681
2682 /* send cdb by polling if no cdb interrupt */
2683 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
2684 ata_sff_queue_pio_task(link, 0);
2685 break;
2686
2687 default:
2688 WARN_ON(1);
2689 return AC_ERR_SYSTEM;
2690 }
2691
2692 return 0;
2693}
2694EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue);
2695
2696/**
2697 * ata_bmdma_port_intr - Handle BMDMA port interrupt
2698 * @ap: Port on which interrupt arrived (possibly...)
2699 * @qc: Taskfile currently active in engine
2700 *
2701 * Handle port interrupt for given queued command.
2702 *
2703 * LOCKING:
2704 * spin_lock_irqsave(host lock)
2705 *
2706 * RETURNS:
2707 * One if interrupt was handled, zero if not (shared irq).
2708 */
2709unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
2710{
2711 struct ata_eh_info *ehi = &ap->link.eh_info;
2712 u8 host_stat = 0;
2713 bool bmdma_stopped = false;
2714 unsigned int handled;
2715
2716 if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) {
2717 /* check status of DMA engine */
2718 host_stat = ap->ops->bmdma_status(ap);
2719 trace_ata_bmdma_status(ap, host_stat);
2720
2721 /* if it's not our irq... */
2722 if (!(host_stat & ATA_DMA_INTR))
2723 return ata_sff_idle_irq(ap);
2724
2725 /* before we do anything else, clear DMA-Start bit */
2726 trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2727 ap->ops->bmdma_stop(qc);
2728 bmdma_stopped = true;
2729
2730 if (unlikely(host_stat & ATA_DMA_ERR)) {
2731 /* error when transferring data to/from memory */
2732 qc->err_mask |= AC_ERR_HOST_BUS;
2733 ap->hsm_task_state = HSM_ST_ERR;
2734 }
2735 }
2736
2737 handled = __ata_sff_port_intr(ap, qc, bmdma_stopped);
2738
2739 if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol))
2740 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
2741
2742 return handled;
2743}
2744EXPORT_SYMBOL_GPL(ata_bmdma_port_intr);
2745
2746/**
2747 * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler
2748 * @irq: irq line (unused)
2749 * @dev_instance: pointer to our ata_host information structure
2750 *
2751 * Default interrupt handler for PCI IDE devices. Calls
2752 * ata_bmdma_port_intr() for each port that is not disabled.
2753 *
2754 * LOCKING:
2755 * Obtains host lock during operation.
2756 *
2757 * RETURNS:
2758 * IRQ_NONE or IRQ_HANDLED.
2759 */
2760irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance)
2761{
2762 return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr);
2763}
2764EXPORT_SYMBOL_GPL(ata_bmdma_interrupt);
2765
2766/**
2767 * ata_bmdma_error_handler - Stock error handler for BMDMA controller
2768 * @ap: port to handle error for
2769 *
2770 * Stock error handler for BMDMA controller. It can handle both
2771 * PATA and SATA controllers. Most BMDMA controllers should be
2772 * able to use this EH as-is or with some added handling before
2773 * and after.
2774 *
2775 * LOCKING:
2776 * Kernel thread context (may sleep)
2777 */
2778void ata_bmdma_error_handler(struct ata_port *ap)
2779{
2780 struct ata_queued_cmd *qc;
2781 unsigned long flags;
2782 bool thaw = false;
2783
2784 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2785 if (qc && !(qc->flags & ATA_QCFLAG_EH))
2786 qc = NULL;
2787
2788 /* reset PIO HSM and stop DMA engine */
2789 spin_lock_irqsave(ap->lock, flags);
2790
2791 if (qc && ata_is_dma(qc->tf.protocol)) {
2792 u8 host_stat;
2793
2794 host_stat = ap->ops->bmdma_status(ap);
2795 trace_ata_bmdma_status(ap, host_stat);
2796
2797 /* BMDMA controllers indicate host bus error by
2798 * setting DMA_ERR bit and timing out. As it wasn't
2799 * really a timeout event, adjust error mask and
2800 * cancel frozen state.
2801 */
2802 if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) {
2803 qc->err_mask = AC_ERR_HOST_BUS;
2804 thaw = true;
2805 }
2806
2807 trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2808 ap->ops->bmdma_stop(qc);
2809
2810 /* if we're gonna thaw, make sure IRQ is clear */
2811 if (thaw) {
2812 ap->ops->sff_check_status(ap);
2813 if (ap->ops->sff_irq_clear)
2814 ap->ops->sff_irq_clear(ap);
2815 }
2816 }
2817
2818 spin_unlock_irqrestore(ap->lock, flags);
2819
2820 if (thaw)
2821 ata_eh_thaw_port(ap);
2822
2823 ata_sff_error_handler(ap);
2824}
2825EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
2826
2827/**
2828 * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA
2829 * @qc: internal command to clean up
2830 *
2831 * LOCKING:
2832 * Kernel thread context (may sleep)
2833 */
2834void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc)
2835{
2836 struct ata_port *ap = qc->ap;
2837 unsigned long flags;
2838
2839 if (ata_is_dma(qc->tf.protocol)) {
2840 spin_lock_irqsave(ap->lock, flags);
2841 trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
2842 ap->ops->bmdma_stop(qc);
2843 spin_unlock_irqrestore(ap->lock, flags);
2844 }
2845}
2846EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
2847
2848/**
2849 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
2850 * @ap: Port associated with this ATA transaction.
2851 *
2852 * Clear interrupt and error flags in DMA status register.
2853 *
2854 * May be used as the irq_clear() entry in ata_port_operations.
2855 *
2856 * LOCKING:
2857 * spin_lock_irqsave(host lock)
2858 */
2859void ata_bmdma_irq_clear(struct ata_port *ap)
2860{
2861 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2862
2863 if (!mmio)
2864 return;
2865
2866 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
2867}
2868EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
2869
2870/**
2871 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2872 * @qc: Info associated with this ATA transaction.
2873 *
2874 * LOCKING:
2875 * spin_lock_irqsave(host lock)
2876 */
2877void ata_bmdma_setup(struct ata_queued_cmd *qc)
2878{
2879 struct ata_port *ap = qc->ap;
2880 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2881 u8 dmactl;
2882
2883 /* load PRD table addr. */
2884 mb(); /* make sure PRD table writes are visible to controller */
2885 iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2886
2887 /* specify data direction, triple-check start bit is clear */
2888 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2889 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2890 if (!rw)
2891 dmactl |= ATA_DMA_WR;
2892 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2893
2894 /* issue r/w command */
2895 ap->ops->sff_exec_command(ap, &qc->tf);
2896}
2897EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2898
2899/**
2900 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2901 * @qc: Info associated with this ATA transaction.
2902 *
2903 * LOCKING:
2904 * spin_lock_irqsave(host lock)
2905 */
2906void ata_bmdma_start(struct ata_queued_cmd *qc)
2907{
2908 struct ata_port *ap = qc->ap;
2909 u8 dmactl;
2910
2911 /* start host DMA transaction */
2912 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2913 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2914
2915 /* Strictly, one may wish to issue an ioread8() here, to
2916 * flush the mmio write. However, control also passes
2917 * to the hardware at this point, and it will interrupt
2918 * us when we are to resume control. So, in effect,
2919 * we don't care when the mmio write flushes.
2920 * Further, a read of the DMA status register _immediately_
2921 * following the write may not be what certain flaky hardware
2922 * is expected, so I think it is best to not add a readb()
2923 * without first all the MMIO ATA cards/mobos.
2924 * Or maybe I'm just being paranoid.
2925 *
2926 * FIXME: The posting of this write means I/O starts are
2927 * unnecessarily delayed for MMIO
2928 */
2929}
2930EXPORT_SYMBOL_GPL(ata_bmdma_start);
2931
2932/**
2933 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2934 * @qc: Command we are ending DMA for
2935 *
2936 * Clears the ATA_DMA_START flag in the dma control register
2937 *
2938 * May be used as the bmdma_stop() entry in ata_port_operations.
2939 *
2940 * LOCKING:
2941 * spin_lock_irqsave(host lock)
2942 */
2943void ata_bmdma_stop(struct ata_queued_cmd *qc)
2944{
2945 struct ata_port *ap = qc->ap;
2946 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2947
2948 /* clear start/stop bit */
2949 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2950 mmio + ATA_DMA_CMD);
2951
2952 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2953 ata_sff_dma_pause(ap);
2954}
2955EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2956
2957/**
2958 * ata_bmdma_status - Read PCI IDE BMDMA status
2959 * @ap: Port associated with this ATA transaction.
2960 *
2961 * Read and return BMDMA status register.
2962 *
2963 * May be used as the bmdma_status() entry in ata_port_operations.
2964 *
2965 * LOCKING:
2966 * spin_lock_irqsave(host lock)
2967 */
2968u8 ata_bmdma_status(struct ata_port *ap)
2969{
2970 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2971}
2972EXPORT_SYMBOL_GPL(ata_bmdma_status);
2973
2974
2975/**
2976 * ata_bmdma_port_start - Set port up for bmdma.
2977 * @ap: Port to initialize
2978 *
2979 * Called just after data structures for each port are
2980 * initialized. Allocates space for PRD table.
2981 *
2982 * May be used as the port_start() entry in ata_port_operations.
2983 *
2984 * LOCKING:
2985 * Inherited from caller.
2986 */
2987int ata_bmdma_port_start(struct ata_port *ap)
2988{
2989 if (ap->mwdma_mask || ap->udma_mask) {
2990 ap->bmdma_prd =
2991 dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ,
2992 &ap->bmdma_prd_dma, GFP_KERNEL);
2993 if (!ap->bmdma_prd)
2994 return -ENOMEM;
2995 }
2996
2997 return 0;
2998}
2999EXPORT_SYMBOL_GPL(ata_bmdma_port_start);
3000
3001/**
3002 * ata_bmdma_port_start32 - Set port up for dma.
3003 * @ap: Port to initialize
3004 *
3005 * Called just after data structures for each port are
3006 * initialized. Enables 32bit PIO and allocates space for PRD
3007 * table.
3008 *
3009 * May be used as the port_start() entry in ata_port_operations for
3010 * devices that are capable of 32bit PIO.
3011 *
3012 * LOCKING:
3013 * Inherited from caller.
3014 */
3015int ata_bmdma_port_start32(struct ata_port *ap)
3016{
3017 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
3018 return ata_bmdma_port_start(ap);
3019}
3020EXPORT_SYMBOL_GPL(ata_bmdma_port_start32);
3021
3022#ifdef CONFIG_PCI
3023
3024/**
3025 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
3026 * @pdev: PCI device
3027 *
3028 * Some PCI ATA devices report simplex mode but in fact can be told to
3029 * enter non simplex mode. This implements the necessary logic to
3030 * perform the task on such devices. Calling it on other devices will
3031 * have -undefined- behaviour.
3032 */
3033int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
3034{
3035 unsigned long bmdma = pci_resource_start(pdev, 4);
3036 u8 simplex;
3037
3038 if (bmdma == 0)
3039 return -ENOENT;
3040
3041 simplex = inb(bmdma + 0x02);
3042 outb(simplex & 0x60, bmdma + 0x02);
3043 simplex = inb(bmdma + 0x02);
3044 if (simplex & 0x80)
3045 return -EOPNOTSUPP;
3046 return 0;
3047}
3048EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
3049
3050static void ata_bmdma_nodma(struct ata_host *host, const char *reason)
3051{
3052 int i;
3053
3054 dev_err(host->dev, "BMDMA: %s, falling back to PIO\n", reason);
3055
3056 for (i = 0; i < 2; i++) {
3057 host->ports[i]->mwdma_mask = 0;
3058 host->ports[i]->udma_mask = 0;
3059 }
3060}
3061
3062/**
3063 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
3064 * @host: target ATA host
3065 *
3066 * Acquire PCI BMDMA resources and initialize @host accordingly.
3067 *
3068 * LOCKING:
3069 * Inherited from calling layer (may sleep).
3070 */
3071void ata_pci_bmdma_init(struct ata_host *host)
3072{
3073 struct device *gdev = host->dev;
3074 struct pci_dev *pdev = to_pci_dev(gdev);
3075 int i, rc;
3076
3077 /* No BAR4 allocation: No DMA */
3078 if (pci_resource_start(pdev, 4) == 0) {
3079 ata_bmdma_nodma(host, "BAR4 is zero");
3080 return;
3081 }
3082
3083 /*
3084 * Some controllers require BMDMA region to be initialized
3085 * even if DMA is not in use to clear IRQ status via
3086 * ->sff_irq_clear method. Try to initialize bmdma_addr
3087 * regardless of dma masks.
3088 */
3089 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
3090 if (rc)
3091 ata_bmdma_nodma(host, "failed to set dma mask");
3092
3093 /* request and iomap DMA region */
3094 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
3095 if (rc) {
3096 ata_bmdma_nodma(host, "failed to request/iomap BAR4");
3097 return;
3098 }
3099 host->iomap = pcim_iomap_table(pdev);
3100
3101 for (i = 0; i < 2; i++) {
3102 struct ata_port *ap = host->ports[i];
3103 void __iomem *bmdma = host->iomap[4] + 8 * i;
3104
3105 if (ata_port_is_dummy(ap))
3106 continue;
3107
3108 ap->ioaddr.bmdma_addr = bmdma;
3109 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
3110 (ioread8(bmdma + 2) & 0x80))
3111 host->flags |= ATA_HOST_SIMPLEX;
3112
3113 ata_port_desc(ap, "bmdma 0x%llx",
3114 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
3115 }
3116}
3117EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
3118
3119/**
3120 * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host
3121 * @pdev: target PCI device
3122 * @ppi: array of port_info, must be enough for two ports
3123 * @r_host: out argument for the initialized ATA host
3124 *
3125 * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI
3126 * resources and initialize it accordingly in one go.
3127 *
3128 * LOCKING:
3129 * Inherited from calling layer (may sleep).
3130 *
3131 * RETURNS:
3132 * 0 on success, -errno otherwise.
3133 */
3134int ata_pci_bmdma_prepare_host(struct pci_dev *pdev,
3135 const struct ata_port_info * const * ppi,
3136 struct ata_host **r_host)
3137{
3138 int rc;
3139
3140 rc = ata_pci_sff_prepare_host(pdev, ppi, r_host);
3141 if (rc)
3142 return rc;
3143
3144 ata_pci_bmdma_init(*r_host);
3145 return 0;
3146}
3147EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host);
3148
3149/**
3150 * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller
3151 * @pdev: Controller to be initialized
3152 * @ppi: array of port_info, must be enough for two ports
3153 * @sht: scsi_host_template to use when registering the host
3154 * @host_priv: host private_data
3155 * @hflags: host flags
3156 *
3157 * This function is similar to ata_pci_sff_init_one() but also
3158 * takes care of BMDMA initialization.
3159 *
3160 * LOCKING:
3161 * Inherited from PCI layer (may sleep).
3162 *
3163 * RETURNS:
3164 * Zero on success, negative on errno-based value on error.
3165 */
3166int ata_pci_bmdma_init_one(struct pci_dev *pdev,
3167 const struct ata_port_info * const * ppi,
3168 const struct scsi_host_template *sht, void *host_priv,
3169 int hflags)
3170{
3171 return ata_pci_init_one(pdev, ppi, sht, host_priv, hflags, 1);
3172}
3173EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one);
3174
3175#endif /* CONFIG_PCI */
3176#endif /* CONFIG_ATA_BMDMA */
3177
3178/**
3179 * ata_sff_port_init - Initialize SFF/BMDMA ATA port
3180 * @ap: Port to initialize
3181 *
3182 * Called on port allocation to initialize SFF/BMDMA specific
3183 * fields.
3184 *
3185 * LOCKING:
3186 * None.
3187 */
3188void ata_sff_port_init(struct ata_port *ap)
3189{
3190 INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task);
3191 ap->ctl = ATA_DEVCTL_OBS;
3192 ap->last_ctl = 0xFF;
3193}
3194
3195int __init ata_sff_init(void)
3196{
3197 ata_sff_wq = alloc_workqueue("ata_sff", WQ_MEM_RECLAIM, WQ_MAX_ACTIVE);
3198 if (!ata_sff_wq)
3199 return -ENOMEM;
3200
3201 return 0;
3202}
3203
3204void ata_sff_exit(void)
3205{
3206 destroy_workqueue(ata_sff_wq);
3207}