Loading...
1/*
2 * Copyright (c) 2007 Ben Dooks
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 *
7 * PWM driver for Samsung SoCs
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/export.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/pwm.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/time.h>
27
28/* For struct samsung_timer_variant and samsung_pwm_lock. */
29#include <clocksource/samsung_pwm.h>
30
31#define REG_TCFG0 0x00
32#define REG_TCFG1 0x04
33#define REG_TCON 0x08
34
35#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
36#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
37
38#define TCFG0_PRESCALER_MASK 0xff
39#define TCFG0_PRESCALER1_SHIFT 8
40
41#define TCFG1_MUX_MASK 0xf
42#define TCFG1_SHIFT(chan) (4 * (chan))
43
44/*
45 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
46 * bits (one channel) after channel 0, so channels have different numbering
47 * when accessing TCON register. See to_tcon_channel() function.
48 *
49 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
50 * in its set of bits is 2 as opposed to 3 for other channels.
51 */
52#define TCON_START(chan) BIT(4 * (chan) + 0)
53#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
54#define TCON_INVERT(chan) BIT(4 * (chan) + 2)
55#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
56#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
57#define TCON_AUTORELOAD(chan) \
58 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
59
60/**
61 * struct samsung_pwm_channel - private data of PWM channel
62 * @period_ns: current period in nanoseconds programmed to the hardware
63 * @duty_ns: current duty time in nanoseconds programmed to the hardware
64 * @tin_ns: time of one timer tick in nanoseconds with current timer rate
65 */
66struct samsung_pwm_channel {
67 u32 period_ns;
68 u32 duty_ns;
69 u32 tin_ns;
70};
71
72/**
73 * struct samsung_pwm_chip - private data of PWM chip
74 * @chip: generic PWM chip
75 * @variant: local copy of hardware variant data
76 * @inverter_mask: inverter status for all channels - one bit per channel
77 * @base: base address of mapped PWM registers
78 * @base_clk: base clock used to drive the timers
79 * @tclk0: external clock 0 (can be ERR_PTR if not present)
80 * @tclk1: external clock 1 (can be ERR_PTR if not present)
81 */
82struct samsung_pwm_chip {
83 struct pwm_chip chip;
84 struct samsung_pwm_variant variant;
85 u8 inverter_mask;
86
87 void __iomem *base;
88 struct clk *base_clk;
89 struct clk *tclk0;
90 struct clk *tclk1;
91};
92
93#ifndef CONFIG_CLKSRC_SAMSUNG_PWM
94/*
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
96 * and some registers need access synchronization. If both drivers are
97 * compiled in, the spinlock is defined in the clocksource driver,
98 * otherwise following definition is used.
99 *
100 * Currently we do not need any more complex synchronization method
101 * because all the supported SoCs contain only one instance of the PWM
102 * IP. Should this change, both drivers will need to be modified to
103 * properly synchronize accesses to particular instances.
104 */
105static DEFINE_SPINLOCK(samsung_pwm_lock);
106#endif
107
108static inline
109struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
110{
111 return container_of(chip, struct samsung_pwm_chip, chip);
112}
113
114static inline unsigned int to_tcon_channel(unsigned int channel)
115{
116 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
117 return (channel == 0) ? 0 : (channel + 1);
118}
119
120static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
121 unsigned int channel, u8 divisor)
122{
123 u8 shift = TCFG1_SHIFT(channel);
124 unsigned long flags;
125 u32 reg;
126 u8 bits;
127
128 bits = (fls(divisor) - 1) - pwm->variant.div_base;
129
130 spin_lock_irqsave(&samsung_pwm_lock, flags);
131
132 reg = readl(pwm->base + REG_TCFG1);
133 reg &= ~(TCFG1_MUX_MASK << shift);
134 reg |= bits << shift;
135 writel(reg, pwm->base + REG_TCFG1);
136
137 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
138}
139
140static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
141{
142 struct samsung_pwm_variant *variant = &chip->variant;
143 u32 reg;
144
145 reg = readl(chip->base + REG_TCFG1);
146 reg >>= TCFG1_SHIFT(chan);
147 reg &= TCFG1_MUX_MASK;
148
149 return (BIT(reg) & variant->tclk_mask) == 0;
150}
151
152static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
153 unsigned int chan)
154{
155 unsigned long rate;
156 u32 reg;
157
158 rate = clk_get_rate(chip->base_clk);
159
160 reg = readl(chip->base + REG_TCFG0);
161 if (chan >= 2)
162 reg >>= TCFG0_PRESCALER1_SHIFT;
163 reg &= TCFG0_PRESCALER_MASK;
164
165 return rate / (reg + 1);
166}
167
168static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
169 unsigned int chan, unsigned long freq)
170{
171 struct samsung_pwm_variant *variant = &chip->variant;
172 unsigned long rate;
173 struct clk *clk;
174 u8 div;
175
176 if (!pwm_samsung_is_tdiv(chip, chan)) {
177 clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
178 if (!IS_ERR(clk)) {
179 rate = clk_get_rate(clk);
180 if (rate)
181 return rate;
182 }
183
184 dev_warn(chip->chip.dev,
185 "tclk of PWM %d is inoperational, using tdiv\n", chan);
186 }
187
188 rate = pwm_samsung_get_tin_rate(chip, chan);
189 dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
190
191 /*
192 * Compare minimum PWM frequency that can be achieved with possible
193 * divider settings and choose the lowest divisor that can generate
194 * frequencies lower than requested.
195 */
196 for (div = variant->div_base; div < 4; ++div)
197 if ((rate >> (variant->bits + div)) < freq)
198 break;
199
200 pwm_samsung_set_divisor(chip, chan, BIT(div));
201
202 return rate >> div;
203}
204
205static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
206{
207 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
208 struct samsung_pwm_channel *our_chan;
209
210 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
211 dev_warn(chip->dev,
212 "tried to request PWM channel %d without output\n",
213 pwm->hwpwm);
214 return -EINVAL;
215 }
216
217 our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
218 if (!our_chan)
219 return -ENOMEM;
220
221 pwm_set_chip_data(pwm, our_chan);
222
223 return 0;
224}
225
226static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
227{
228 devm_kfree(chip->dev, pwm_get_chip_data(pwm));
229 pwm_set_chip_data(pwm, NULL);
230}
231
232static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
233{
234 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
235 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
236 unsigned long flags;
237 u32 tcon;
238
239 spin_lock_irqsave(&samsung_pwm_lock, flags);
240
241 tcon = readl(our_chip->base + REG_TCON);
242
243 tcon &= ~TCON_START(tcon_chan);
244 tcon |= TCON_MANUALUPDATE(tcon_chan);
245 writel(tcon, our_chip->base + REG_TCON);
246
247 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
248 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
249 writel(tcon, our_chip->base + REG_TCON);
250
251 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
252
253 return 0;
254}
255
256static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
257{
258 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
259 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
260 unsigned long flags;
261 u32 tcon;
262
263 spin_lock_irqsave(&samsung_pwm_lock, flags);
264
265 tcon = readl(our_chip->base + REG_TCON);
266 tcon &= ~TCON_AUTORELOAD(tcon_chan);
267 writel(tcon, our_chip->base + REG_TCON);
268
269 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
270}
271
272static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
273 struct pwm_device *pwm)
274{
275 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
276 u32 tcon;
277 unsigned long flags;
278
279 spin_lock_irqsave(&samsung_pwm_lock, flags);
280
281 tcon = readl(chip->base + REG_TCON);
282 tcon |= TCON_MANUALUPDATE(tcon_chan);
283 writel(tcon, chip->base + REG_TCON);
284
285 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
286 writel(tcon, chip->base + REG_TCON);
287
288 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
289}
290
291static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
292 int duty_ns, int period_ns)
293{
294 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
295 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
296 u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
297
298 /*
299 * We currently avoid using 64bit arithmetic by using the
300 * fact that anything faster than 1Hz is easily representable
301 * by 32bits.
302 */
303 if (period_ns > NSEC_PER_SEC)
304 return -ERANGE;
305
306 if (period_ns == chan->period_ns && duty_ns == chan->duty_ns)
307 return 0;
308
309 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
310 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
311
312 /* We need tick count for calculation, not last tick. */
313 ++tcnt;
314
315 /* Check to see if we are changing the clock rate of the PWM. */
316 if (chan->period_ns != period_ns) {
317 unsigned long tin_rate;
318 u32 period;
319
320 period = NSEC_PER_SEC / period_ns;
321
322 dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
323 duty_ns, period_ns, period);
324
325 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
326
327 dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
328
329 tin_ns = NSEC_PER_SEC / tin_rate;
330 tcnt = period_ns / tin_ns;
331 }
332
333 /* Period is too short. */
334 if (tcnt <= 1)
335 return -ERANGE;
336
337 /* Note that counters count down. */
338 tcmp = duty_ns / tin_ns;
339
340 /* 0% duty is not available */
341 if (!tcmp)
342 ++tcmp;
343
344 tcmp = tcnt - tcmp;
345
346 /* Decrement to get tick numbers, instead of tick counts. */
347 --tcnt;
348 /* -1UL will give 100% duty. */
349 --tcmp;
350
351 dev_dbg(our_chip->chip.dev,
352 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
353
354 /* Update PWM registers. */
355 writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
356 writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
357
358 /*
359 * In case the PWM is currently at 100% duty cycle, force a manual
360 * update to prevent the signal staying high if the PWM is disabled
361 * shortly afer this update (before it autoreloaded the new values).
362 */
363 if (oldtcmp == (u32) -1) {
364 dev_dbg(our_chip->chip.dev, "Forcing manual update");
365 pwm_samsung_manual_update(our_chip, pwm);
366 }
367
368 chan->period_ns = period_ns;
369 chan->tin_ns = tin_ns;
370 chan->duty_ns = duty_ns;
371
372 return 0;
373}
374
375static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip,
376 unsigned int channel, bool invert)
377{
378 unsigned int tcon_chan = to_tcon_channel(channel);
379 unsigned long flags;
380 u32 tcon;
381
382 spin_lock_irqsave(&samsung_pwm_lock, flags);
383
384 tcon = readl(chip->base + REG_TCON);
385
386 if (invert) {
387 chip->inverter_mask |= BIT(channel);
388 tcon |= TCON_INVERT(tcon_chan);
389 } else {
390 chip->inverter_mask &= ~BIT(channel);
391 tcon &= ~TCON_INVERT(tcon_chan);
392 }
393
394 writel(tcon, chip->base + REG_TCON);
395
396 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
397}
398
399static int pwm_samsung_set_polarity(struct pwm_chip *chip,
400 struct pwm_device *pwm,
401 enum pwm_polarity polarity)
402{
403 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
404 bool invert = (polarity == PWM_POLARITY_NORMAL);
405
406 /* Inverted means normal in the hardware. */
407 pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
408
409 return 0;
410}
411
412static const struct pwm_ops pwm_samsung_ops = {
413 .request = pwm_samsung_request,
414 .free = pwm_samsung_free,
415 .enable = pwm_samsung_enable,
416 .disable = pwm_samsung_disable,
417 .config = pwm_samsung_config,
418 .set_polarity = pwm_samsung_set_polarity,
419 .owner = THIS_MODULE,
420};
421
422#ifdef CONFIG_OF
423static const struct samsung_pwm_variant s3c24xx_variant = {
424 .bits = 16,
425 .div_base = 1,
426 .has_tint_cstat = false,
427 .tclk_mask = BIT(4),
428};
429
430static const struct samsung_pwm_variant s3c64xx_variant = {
431 .bits = 32,
432 .div_base = 0,
433 .has_tint_cstat = true,
434 .tclk_mask = BIT(7) | BIT(6) | BIT(5),
435};
436
437static const struct samsung_pwm_variant s5p64x0_variant = {
438 .bits = 32,
439 .div_base = 0,
440 .has_tint_cstat = true,
441 .tclk_mask = 0,
442};
443
444static const struct samsung_pwm_variant s5pc100_variant = {
445 .bits = 32,
446 .div_base = 0,
447 .has_tint_cstat = true,
448 .tclk_mask = BIT(5),
449};
450
451static const struct of_device_id samsung_pwm_matches[] = {
452 { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
453 { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
454 { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
455 { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
456 { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
457 {},
458};
459MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
460
461static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
462{
463 struct device_node *np = chip->chip.dev->of_node;
464 const struct of_device_id *match;
465 struct property *prop;
466 const __be32 *cur;
467 u32 val;
468
469 match = of_match_node(samsung_pwm_matches, np);
470 if (!match)
471 return -ENODEV;
472
473 memcpy(&chip->variant, match->data, sizeof(chip->variant));
474
475 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
476 if (val >= SAMSUNG_PWM_NUM) {
477 dev_err(chip->chip.dev,
478 "%s: invalid channel index in samsung,pwm-outputs property\n",
479 __func__);
480 continue;
481 }
482 chip->variant.output_mask |= BIT(val);
483 }
484
485 return 0;
486}
487#else
488static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
489{
490 return -ENODEV;
491}
492#endif
493
494static int pwm_samsung_probe(struct platform_device *pdev)
495{
496 struct device *dev = &pdev->dev;
497 struct samsung_pwm_chip *chip;
498 struct resource *res;
499 unsigned int chan;
500 int ret;
501
502 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
503 if (chip == NULL)
504 return -ENOMEM;
505
506 chip->chip.dev = &pdev->dev;
507 chip->chip.ops = &pwm_samsung_ops;
508 chip->chip.base = -1;
509 chip->chip.npwm = SAMSUNG_PWM_NUM;
510 chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
511
512 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
513 ret = pwm_samsung_parse_dt(chip);
514 if (ret)
515 return ret;
516
517 chip->chip.of_xlate = of_pwm_xlate_with_flags;
518 chip->chip.of_pwm_n_cells = 3;
519 } else {
520 if (!pdev->dev.platform_data) {
521 dev_err(&pdev->dev, "no platform data specified\n");
522 return -EINVAL;
523 }
524
525 memcpy(&chip->variant, pdev->dev.platform_data,
526 sizeof(chip->variant));
527 }
528
529 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
530 chip->base = devm_ioremap_resource(&pdev->dev, res);
531 if (IS_ERR(chip->base))
532 return PTR_ERR(chip->base);
533
534 chip->base_clk = devm_clk_get(&pdev->dev, "timers");
535 if (IS_ERR(chip->base_clk)) {
536 dev_err(dev, "failed to get timer base clk\n");
537 return PTR_ERR(chip->base_clk);
538 }
539
540 ret = clk_prepare_enable(chip->base_clk);
541 if (ret < 0) {
542 dev_err(dev, "failed to enable base clock\n");
543 return ret;
544 }
545
546 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
547 if (chip->variant.output_mask & BIT(chan))
548 pwm_samsung_set_invert(chip, chan, true);
549
550 /* Following clocks are optional. */
551 chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
552 chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
553
554 platform_set_drvdata(pdev, chip);
555
556 ret = pwmchip_add(&chip->chip);
557 if (ret < 0) {
558 dev_err(dev, "failed to register PWM chip\n");
559 clk_disable_unprepare(chip->base_clk);
560 return ret;
561 }
562
563 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
564 clk_get_rate(chip->base_clk),
565 !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0,
566 !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0);
567
568 return 0;
569}
570
571static int pwm_samsung_remove(struct platform_device *pdev)
572{
573 struct samsung_pwm_chip *chip = platform_get_drvdata(pdev);
574 int ret;
575
576 ret = pwmchip_remove(&chip->chip);
577 if (ret < 0)
578 return ret;
579
580 clk_disable_unprepare(chip->base_clk);
581
582 return 0;
583}
584
585#ifdef CONFIG_PM_SLEEP
586static int pwm_samsung_suspend(struct device *dev)
587{
588 struct samsung_pwm_chip *chip = dev_get_drvdata(dev);
589 unsigned int i;
590
591 /*
592 * No one preserves these values during suspend so reset them.
593 * Otherwise driver leaves PWM unconfigured if same values are
594 * passed to pwm_config() next time.
595 */
596 for (i = 0; i < SAMSUNG_PWM_NUM; ++i) {
597 struct pwm_device *pwm = &chip->chip.pwms[i];
598 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
599
600 if (!chan)
601 continue;
602
603 chan->period_ns = 0;
604 chan->duty_ns = 0;
605 }
606
607 return 0;
608}
609
610static int pwm_samsung_resume(struct device *dev)
611{
612 struct samsung_pwm_chip *chip = dev_get_drvdata(dev);
613 unsigned int chan;
614
615 /*
616 * Inverter setting must be preserved across suspend/resume
617 * as nobody really seems to configure it more than once.
618 */
619 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) {
620 if (chip->variant.output_mask & BIT(chan))
621 pwm_samsung_set_invert(chip, chan,
622 chip->inverter_mask & BIT(chan));
623 }
624
625 return 0;
626}
627#endif
628
629static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, pwm_samsung_suspend,
630 pwm_samsung_resume);
631
632static struct platform_driver pwm_samsung_driver = {
633 .driver = {
634 .name = "samsung-pwm",
635 .pm = &pwm_samsung_pm_ops,
636 .of_match_table = of_match_ptr(samsung_pwm_matches),
637 },
638 .probe = pwm_samsung_probe,
639 .remove = pwm_samsung_remove,
640};
641module_platform_driver(pwm_samsung_driver);
642
643MODULE_LICENSE("GPL");
644MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
645MODULE_ALIAS("platform:samsung-pwm");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2007 Ben Dooks
4 * Copyright (c) 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
6 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
7 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
8 *
9 * PWM driver for Samsung SoCs
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/export.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/time.h>
25
26/* For struct samsung_timer_variant and samsung_pwm_lock. */
27#include <clocksource/samsung_pwm.h>
28
29#define REG_TCFG0 0x00
30#define REG_TCFG1 0x04
31#define REG_TCON 0x08
32
33#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
34#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
35
36#define TCFG0_PRESCALER_MASK 0xff
37#define TCFG0_PRESCALER1_SHIFT 8
38
39#define TCFG1_MUX_MASK 0xf
40#define TCFG1_SHIFT(chan) (4 * (chan))
41
42/*
43 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
44 * bits (one channel) after channel 0, so channels have different numbering
45 * when accessing TCON register. See to_tcon_channel() function.
46 *
47 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
48 * in its set of bits is 2 as opposed to 3 for other channels.
49 */
50#define TCON_START(chan) BIT(4 * (chan) + 0)
51#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
52#define TCON_INVERT(chan) BIT(4 * (chan) + 2)
53#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
54#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
55#define TCON_AUTORELOAD(chan) \
56 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
57
58/**
59 * struct samsung_pwm_channel - private data of PWM channel
60 * @period_ns: current period in nanoseconds programmed to the hardware
61 * @duty_ns: current duty time in nanoseconds programmed to the hardware
62 * @tin_ns: time of one timer tick in nanoseconds with current timer rate
63 */
64struct samsung_pwm_channel {
65 u32 period_ns;
66 u32 duty_ns;
67 u32 tin_ns;
68};
69
70/**
71 * struct samsung_pwm_chip - private data of PWM chip
72 * @chip: generic PWM chip
73 * @variant: local copy of hardware variant data
74 * @inverter_mask: inverter status for all channels - one bit per channel
75 * @disabled_mask: disabled status for all channels - one bit per channel
76 * @base: base address of mapped PWM registers
77 * @base_clk: base clock used to drive the timers
78 * @tclk0: external clock 0 (can be ERR_PTR if not present)
79 * @tclk1: external clock 1 (can be ERR_PTR if not present)
80 * @channel: per channel driver data
81 */
82struct samsung_pwm_chip {
83 struct pwm_chip chip;
84 struct samsung_pwm_variant variant;
85 u8 inverter_mask;
86 u8 disabled_mask;
87
88 void __iomem *base;
89 struct clk *base_clk;
90 struct clk *tclk0;
91 struct clk *tclk1;
92 struct samsung_pwm_channel channel[SAMSUNG_PWM_NUM];
93};
94
95#ifndef CONFIG_CLKSRC_SAMSUNG_PWM
96/*
97 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
98 * and some registers need access synchronization. If both drivers are
99 * compiled in, the spinlock is defined in the clocksource driver,
100 * otherwise following definition is used.
101 *
102 * Currently we do not need any more complex synchronization method
103 * because all the supported SoCs contain only one instance of the PWM
104 * IP. Should this change, both drivers will need to be modified to
105 * properly synchronize accesses to particular instances.
106 */
107static DEFINE_SPINLOCK(samsung_pwm_lock);
108#endif
109
110static inline
111struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
112{
113 return container_of(chip, struct samsung_pwm_chip, chip);
114}
115
116static inline unsigned int to_tcon_channel(unsigned int channel)
117{
118 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
119 return (channel == 0) ? 0 : (channel + 1);
120}
121
122static void __pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,
123 struct pwm_device *pwm)
124{
125 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
126 u32 tcon;
127
128 tcon = readl(our_chip->base + REG_TCON);
129 tcon |= TCON_MANUALUPDATE(tcon_chan);
130 writel(tcon, our_chip->base + REG_TCON);
131
132 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
133 writel(tcon, our_chip->base + REG_TCON);
134}
135
136static void pwm_samsung_set_divisor(struct samsung_pwm_chip *our_chip,
137 unsigned int channel, u8 divisor)
138{
139 u8 shift = TCFG1_SHIFT(channel);
140 unsigned long flags;
141 u32 reg;
142 u8 bits;
143
144 bits = (fls(divisor) - 1) - our_chip->variant.div_base;
145
146 spin_lock_irqsave(&samsung_pwm_lock, flags);
147
148 reg = readl(our_chip->base + REG_TCFG1);
149 reg &= ~(TCFG1_MUX_MASK << shift);
150 reg |= bits << shift;
151 writel(reg, our_chip->base + REG_TCFG1);
152
153 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
154}
155
156static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *our_chip, unsigned int chan)
157{
158 struct samsung_pwm_variant *variant = &our_chip->variant;
159 u32 reg;
160
161 reg = readl(our_chip->base + REG_TCFG1);
162 reg >>= TCFG1_SHIFT(chan);
163 reg &= TCFG1_MUX_MASK;
164
165 return (BIT(reg) & variant->tclk_mask) == 0;
166}
167
168static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *our_chip,
169 unsigned int chan)
170{
171 unsigned long rate;
172 u32 reg;
173
174 rate = clk_get_rate(our_chip->base_clk);
175
176 reg = readl(our_chip->base + REG_TCFG0);
177 if (chan >= 2)
178 reg >>= TCFG0_PRESCALER1_SHIFT;
179 reg &= TCFG0_PRESCALER_MASK;
180
181 return rate / (reg + 1);
182}
183
184static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *our_chip,
185 unsigned int chan, unsigned long freq)
186{
187 struct samsung_pwm_variant *variant = &our_chip->variant;
188 unsigned long rate;
189 struct clk *clk;
190 u8 div;
191
192 if (!pwm_samsung_is_tdiv(our_chip, chan)) {
193 clk = (chan < 2) ? our_chip->tclk0 : our_chip->tclk1;
194 if (!IS_ERR(clk)) {
195 rate = clk_get_rate(clk);
196 if (rate)
197 return rate;
198 }
199
200 dev_warn(our_chip->chip.dev,
201 "tclk of PWM %d is inoperational, using tdiv\n", chan);
202 }
203
204 rate = pwm_samsung_get_tin_rate(our_chip, chan);
205 dev_dbg(our_chip->chip.dev, "tin parent at %lu\n", rate);
206
207 /*
208 * Compare minimum PWM frequency that can be achieved with possible
209 * divider settings and choose the lowest divisor that can generate
210 * frequencies lower than requested.
211 */
212 if (variant->bits < 32) {
213 /* Only for s3c24xx */
214 for (div = variant->div_base; div < 4; ++div)
215 if ((rate >> (variant->bits + div)) < freq)
216 break;
217 } else {
218 /*
219 * Other variants have enough counter bits to generate any
220 * requested rate, so no need to check higher divisors.
221 */
222 div = variant->div_base;
223 }
224
225 pwm_samsung_set_divisor(our_chip, chan, BIT(div));
226
227 return rate >> div;
228}
229
230static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
231{
232 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
233
234 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
235 dev_warn(chip->dev,
236 "tried to request PWM channel %d without output\n",
237 pwm->hwpwm);
238 return -EINVAL;
239 }
240
241 memset(&our_chip->channel[pwm->hwpwm], 0, sizeof(our_chip->channel[pwm->hwpwm]));
242
243 return 0;
244}
245
246static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
247{
248 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
249 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
250 unsigned long flags;
251 u32 tcon;
252
253 spin_lock_irqsave(&samsung_pwm_lock, flags);
254
255 tcon = readl(our_chip->base + REG_TCON);
256
257 tcon &= ~TCON_START(tcon_chan);
258 tcon |= TCON_MANUALUPDATE(tcon_chan);
259 writel(tcon, our_chip->base + REG_TCON);
260
261 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
262 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
263 writel(tcon, our_chip->base + REG_TCON);
264
265 our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
266
267 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
268
269 return 0;
270}
271
272static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
273{
274 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
275 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
276 unsigned long flags;
277 u32 tcon;
278
279 spin_lock_irqsave(&samsung_pwm_lock, flags);
280
281 tcon = readl(our_chip->base + REG_TCON);
282 tcon &= ~TCON_AUTORELOAD(tcon_chan);
283 writel(tcon, our_chip->base + REG_TCON);
284
285 /*
286 * In case the PWM is at 100% duty cycle, force a manual
287 * update to prevent the signal from staying high.
288 */
289 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U)
290 __pwm_samsung_manual_update(our_chip, pwm);
291
292 our_chip->disabled_mask |= BIT(pwm->hwpwm);
293
294 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
295}
296
297static void pwm_samsung_manual_update(struct samsung_pwm_chip *our_chip,
298 struct pwm_device *pwm)
299{
300 unsigned long flags;
301
302 spin_lock_irqsave(&samsung_pwm_lock, flags);
303
304 __pwm_samsung_manual_update(our_chip, pwm);
305
306 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
307}
308
309static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
310 int duty_ns, int period_ns, bool force_period)
311{
312 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
313 struct samsung_pwm_channel *chan = &our_chip->channel[pwm->hwpwm];
314 u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
315
316 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
317 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
318
319 /* We need tick count for calculation, not last tick. */
320 ++tcnt;
321
322 /* Check to see if we are changing the clock rate of the PWM. */
323 if (chan->period_ns != period_ns || force_period) {
324 unsigned long tin_rate;
325 u32 period;
326
327 period = NSEC_PER_SEC / period_ns;
328
329 dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
330 duty_ns, period_ns, period);
331
332 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
333
334 dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
335
336 tin_ns = NSEC_PER_SEC / tin_rate;
337 tcnt = period_ns / tin_ns;
338 }
339
340 /* Period is too short. */
341 if (tcnt <= 1)
342 return -ERANGE;
343
344 /* Note that counters count down. */
345 tcmp = duty_ns / tin_ns;
346
347 /* 0% duty is not available */
348 if (!tcmp)
349 ++tcmp;
350
351 tcmp = tcnt - tcmp;
352
353 /* Decrement to get tick numbers, instead of tick counts. */
354 --tcnt;
355 /* -1UL will give 100% duty. */
356 --tcmp;
357
358 dev_dbg(our_chip->chip.dev,
359 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
360
361 /* Update PWM registers. */
362 writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
363 writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
364
365 /*
366 * In case the PWM is currently at 100% duty cycle, force a manual
367 * update to prevent the signal staying high if the PWM is disabled
368 * shortly afer this update (before it autoreloaded the new values).
369 */
370 if (oldtcmp == (u32) -1) {
371 dev_dbg(our_chip->chip.dev, "Forcing manual update");
372 pwm_samsung_manual_update(our_chip, pwm);
373 }
374
375 chan->period_ns = period_ns;
376 chan->tin_ns = tin_ns;
377 chan->duty_ns = duty_ns;
378
379 return 0;
380}
381
382static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
383 int duty_ns, int period_ns)
384{
385 return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false);
386}
387
388static void pwm_samsung_set_invert(struct samsung_pwm_chip *our_chip,
389 unsigned int channel, bool invert)
390{
391 unsigned int tcon_chan = to_tcon_channel(channel);
392 unsigned long flags;
393 u32 tcon;
394
395 spin_lock_irqsave(&samsung_pwm_lock, flags);
396
397 tcon = readl(our_chip->base + REG_TCON);
398
399 if (invert) {
400 our_chip->inverter_mask |= BIT(channel);
401 tcon |= TCON_INVERT(tcon_chan);
402 } else {
403 our_chip->inverter_mask &= ~BIT(channel);
404 tcon &= ~TCON_INVERT(tcon_chan);
405 }
406
407 writel(tcon, our_chip->base + REG_TCON);
408
409 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
410}
411
412static int pwm_samsung_set_polarity(struct pwm_chip *chip,
413 struct pwm_device *pwm,
414 enum pwm_polarity polarity)
415{
416 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
417 bool invert = (polarity == PWM_POLARITY_NORMAL);
418
419 /* Inverted means normal in the hardware. */
420 pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
421
422 return 0;
423}
424
425static int pwm_samsung_apply(struct pwm_chip *chip, struct pwm_device *pwm,
426 const struct pwm_state *state)
427{
428 int err, enabled = pwm->state.enabled;
429
430 if (state->polarity != pwm->state.polarity) {
431 if (enabled) {
432 pwm_samsung_disable(chip, pwm);
433 enabled = false;
434 }
435
436 err = pwm_samsung_set_polarity(chip, pwm, state->polarity);
437 if (err)
438 return err;
439 }
440
441 if (!state->enabled) {
442 if (enabled)
443 pwm_samsung_disable(chip, pwm);
444
445 return 0;
446 }
447
448 /*
449 * We currently avoid using 64bit arithmetic by using the
450 * fact that anything faster than 1Hz is easily representable
451 * by 32bits.
452 */
453 if (state->period > NSEC_PER_SEC)
454 return -ERANGE;
455
456 err = pwm_samsung_config(chip, pwm, state->duty_cycle, state->period);
457 if (err)
458 return err;
459
460 if (!pwm->state.enabled)
461 err = pwm_samsung_enable(chip, pwm);
462
463 return err;
464}
465
466static const struct pwm_ops pwm_samsung_ops = {
467 .request = pwm_samsung_request,
468 .apply = pwm_samsung_apply,
469};
470
471#ifdef CONFIG_OF
472static const struct samsung_pwm_variant s3c24xx_variant = {
473 .bits = 16,
474 .div_base = 1,
475 .has_tint_cstat = false,
476 .tclk_mask = BIT(4),
477};
478
479static const struct samsung_pwm_variant s3c64xx_variant = {
480 .bits = 32,
481 .div_base = 0,
482 .has_tint_cstat = true,
483 .tclk_mask = BIT(7) | BIT(6) | BIT(5),
484};
485
486static const struct samsung_pwm_variant s5p64x0_variant = {
487 .bits = 32,
488 .div_base = 0,
489 .has_tint_cstat = true,
490 .tclk_mask = 0,
491};
492
493static const struct samsung_pwm_variant s5pc100_variant = {
494 .bits = 32,
495 .div_base = 0,
496 .has_tint_cstat = true,
497 .tclk_mask = BIT(5),
498};
499
500static const struct of_device_id samsung_pwm_matches[] = {
501 { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
502 { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
503 { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
504 { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
505 { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
506 {},
507};
508MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
509
510static int pwm_samsung_parse_dt(struct samsung_pwm_chip *our_chip)
511{
512 struct device_node *np = our_chip->chip.dev->of_node;
513 const struct of_device_id *match;
514 struct property *prop;
515 const __be32 *cur;
516 u32 val;
517
518 match = of_match_node(samsung_pwm_matches, np);
519 if (!match)
520 return -ENODEV;
521
522 memcpy(&our_chip->variant, match->data, sizeof(our_chip->variant));
523
524 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
525 if (val >= SAMSUNG_PWM_NUM) {
526 dev_err(our_chip->chip.dev,
527 "%s: invalid channel index in samsung,pwm-outputs property\n",
528 __func__);
529 continue;
530 }
531 our_chip->variant.output_mask |= BIT(val);
532 }
533
534 return 0;
535}
536#else
537static int pwm_samsung_parse_dt(struct samsung_pwm_chip *our_chip)
538{
539 return -ENODEV;
540}
541#endif
542
543static int pwm_samsung_probe(struct platform_device *pdev)
544{
545 struct device *dev = &pdev->dev;
546 struct samsung_pwm_chip *our_chip;
547 unsigned int chan;
548 int ret;
549
550 our_chip = devm_kzalloc(&pdev->dev, sizeof(*our_chip), GFP_KERNEL);
551 if (our_chip == NULL)
552 return -ENOMEM;
553
554 our_chip->chip.dev = &pdev->dev;
555 our_chip->chip.ops = &pwm_samsung_ops;
556 our_chip->chip.npwm = SAMSUNG_PWM_NUM;
557 our_chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
558
559 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
560 ret = pwm_samsung_parse_dt(our_chip);
561 if (ret)
562 return ret;
563 } else {
564 if (!pdev->dev.platform_data) {
565 dev_err(&pdev->dev, "no platform data specified\n");
566 return -EINVAL;
567 }
568
569 memcpy(&our_chip->variant, pdev->dev.platform_data,
570 sizeof(our_chip->variant));
571 }
572
573 our_chip->base = devm_platform_ioremap_resource(pdev, 0);
574 if (IS_ERR(our_chip->base))
575 return PTR_ERR(our_chip->base);
576
577 our_chip->base_clk = devm_clk_get(&pdev->dev, "timers");
578 if (IS_ERR(our_chip->base_clk)) {
579 dev_err(dev, "failed to get timer base clk\n");
580 return PTR_ERR(our_chip->base_clk);
581 }
582
583 ret = clk_prepare_enable(our_chip->base_clk);
584 if (ret < 0) {
585 dev_err(dev, "failed to enable base clock\n");
586 return ret;
587 }
588
589 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
590 if (our_chip->variant.output_mask & BIT(chan))
591 pwm_samsung_set_invert(our_chip, chan, true);
592
593 /* Following clocks are optional. */
594 our_chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
595 our_chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
596
597 platform_set_drvdata(pdev, our_chip);
598
599 ret = pwmchip_add(&our_chip->chip);
600 if (ret < 0) {
601 dev_err(dev, "failed to register PWM chip\n");
602 clk_disable_unprepare(our_chip->base_clk);
603 return ret;
604 }
605
606 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
607 clk_get_rate(our_chip->base_clk),
608 !IS_ERR(our_chip->tclk0) ? clk_get_rate(our_chip->tclk0) : 0,
609 !IS_ERR(our_chip->tclk1) ? clk_get_rate(our_chip->tclk1) : 0);
610
611 return 0;
612}
613
614static void pwm_samsung_remove(struct platform_device *pdev)
615{
616 struct samsung_pwm_chip *our_chip = platform_get_drvdata(pdev);
617
618 pwmchip_remove(&our_chip->chip);
619
620 clk_disable_unprepare(our_chip->base_clk);
621}
622
623static int pwm_samsung_resume(struct device *dev)
624{
625 struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev);
626 struct pwm_chip *chip = &our_chip->chip;
627 unsigned int i;
628
629 for (i = 0; i < SAMSUNG_PWM_NUM; i++) {
630 struct pwm_device *pwm = &chip->pwms[i];
631 struct samsung_pwm_channel *chan = &our_chip->channel[i];
632
633 if (!test_bit(PWMF_REQUESTED, &pwm->flags))
634 continue;
635
636 if (our_chip->variant.output_mask & BIT(i))
637 pwm_samsung_set_invert(our_chip, i,
638 our_chip->inverter_mask & BIT(i));
639
640 if (chan->period_ns) {
641 __pwm_samsung_config(chip, pwm, chan->duty_ns,
642 chan->period_ns, true);
643 /* needed to make PWM disable work on Odroid-XU3 */
644 pwm_samsung_manual_update(our_chip, pwm);
645 }
646
647 if (our_chip->disabled_mask & BIT(i))
648 pwm_samsung_disable(chip, pwm);
649 else
650 pwm_samsung_enable(chip, pwm);
651 }
652
653 return 0;
654}
655
656static DEFINE_SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume);
657
658static struct platform_driver pwm_samsung_driver = {
659 .driver = {
660 .name = "samsung-pwm",
661 .pm = pm_ptr(&pwm_samsung_pm_ops),
662 .of_match_table = of_match_ptr(samsung_pwm_matches),
663 },
664 .probe = pwm_samsung_probe,
665 .remove_new = pwm_samsung_remove,
666};
667module_platform_driver(pwm_samsung_driver);
668
669MODULE_LICENSE("GPL");
670MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
671MODULE_ALIAS("platform:samsung-pwm");