Loading...
1/*
2 * Copyright (c) 2007 Ben Dooks
3 * Copyright (c) 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
6 *
7 * PWM driver for Samsung SoCs
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/export.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/pwm.h>
24#include <linux/slab.h>
25#include <linux/spinlock.h>
26#include <linux/time.h>
27
28/* For struct samsung_timer_variant and samsung_pwm_lock. */
29#include <clocksource/samsung_pwm.h>
30
31#define REG_TCFG0 0x00
32#define REG_TCFG1 0x04
33#define REG_TCON 0x08
34
35#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
36#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
37
38#define TCFG0_PRESCALER_MASK 0xff
39#define TCFG0_PRESCALER1_SHIFT 8
40
41#define TCFG1_MUX_MASK 0xf
42#define TCFG1_SHIFT(chan) (4 * (chan))
43
44/*
45 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
46 * bits (one channel) after channel 0, so channels have different numbering
47 * when accessing TCON register. See to_tcon_channel() function.
48 *
49 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
50 * in its set of bits is 2 as opposed to 3 for other channels.
51 */
52#define TCON_START(chan) BIT(4 * (chan) + 0)
53#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
54#define TCON_INVERT(chan) BIT(4 * (chan) + 2)
55#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
56#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
57#define TCON_AUTORELOAD(chan) \
58 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
59
60/**
61 * struct samsung_pwm_channel - private data of PWM channel
62 * @period_ns: current period in nanoseconds programmed to the hardware
63 * @duty_ns: current duty time in nanoseconds programmed to the hardware
64 * @tin_ns: time of one timer tick in nanoseconds with current timer rate
65 */
66struct samsung_pwm_channel {
67 u32 period_ns;
68 u32 duty_ns;
69 u32 tin_ns;
70};
71
72/**
73 * struct samsung_pwm_chip - private data of PWM chip
74 * @chip: generic PWM chip
75 * @variant: local copy of hardware variant data
76 * @inverter_mask: inverter status for all channels - one bit per channel
77 * @base: base address of mapped PWM registers
78 * @base_clk: base clock used to drive the timers
79 * @tclk0: external clock 0 (can be ERR_PTR if not present)
80 * @tclk1: external clock 1 (can be ERR_PTR if not present)
81 */
82struct samsung_pwm_chip {
83 struct pwm_chip chip;
84 struct samsung_pwm_variant variant;
85 u8 inverter_mask;
86
87 void __iomem *base;
88 struct clk *base_clk;
89 struct clk *tclk0;
90 struct clk *tclk1;
91};
92
93#ifndef CONFIG_CLKSRC_SAMSUNG_PWM
94/*
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
96 * and some registers need access synchronization. If both drivers are
97 * compiled in, the spinlock is defined in the clocksource driver,
98 * otherwise following definition is used.
99 *
100 * Currently we do not need any more complex synchronization method
101 * because all the supported SoCs contain only one instance of the PWM
102 * IP. Should this change, both drivers will need to be modified to
103 * properly synchronize accesses to particular instances.
104 */
105static DEFINE_SPINLOCK(samsung_pwm_lock);
106#endif
107
108static inline
109struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
110{
111 return container_of(chip, struct samsung_pwm_chip, chip);
112}
113
114static inline unsigned int to_tcon_channel(unsigned int channel)
115{
116 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
117 return (channel == 0) ? 0 : (channel + 1);
118}
119
120static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
121 unsigned int channel, u8 divisor)
122{
123 u8 shift = TCFG1_SHIFT(channel);
124 unsigned long flags;
125 u32 reg;
126 u8 bits;
127
128 bits = (fls(divisor) - 1) - pwm->variant.div_base;
129
130 spin_lock_irqsave(&samsung_pwm_lock, flags);
131
132 reg = readl(pwm->base + REG_TCFG1);
133 reg &= ~(TCFG1_MUX_MASK << shift);
134 reg |= bits << shift;
135 writel(reg, pwm->base + REG_TCFG1);
136
137 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
138}
139
140static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
141{
142 struct samsung_pwm_variant *variant = &chip->variant;
143 u32 reg;
144
145 reg = readl(chip->base + REG_TCFG1);
146 reg >>= TCFG1_SHIFT(chan);
147 reg &= TCFG1_MUX_MASK;
148
149 return (BIT(reg) & variant->tclk_mask) == 0;
150}
151
152static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
153 unsigned int chan)
154{
155 unsigned long rate;
156 u32 reg;
157
158 rate = clk_get_rate(chip->base_clk);
159
160 reg = readl(chip->base + REG_TCFG0);
161 if (chan >= 2)
162 reg >>= TCFG0_PRESCALER1_SHIFT;
163 reg &= TCFG0_PRESCALER_MASK;
164
165 return rate / (reg + 1);
166}
167
168static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
169 unsigned int chan, unsigned long freq)
170{
171 struct samsung_pwm_variant *variant = &chip->variant;
172 unsigned long rate;
173 struct clk *clk;
174 u8 div;
175
176 if (!pwm_samsung_is_tdiv(chip, chan)) {
177 clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
178 if (!IS_ERR(clk)) {
179 rate = clk_get_rate(clk);
180 if (rate)
181 return rate;
182 }
183
184 dev_warn(chip->chip.dev,
185 "tclk of PWM %d is inoperational, using tdiv\n", chan);
186 }
187
188 rate = pwm_samsung_get_tin_rate(chip, chan);
189 dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
190
191 /*
192 * Compare minimum PWM frequency that can be achieved with possible
193 * divider settings and choose the lowest divisor that can generate
194 * frequencies lower than requested.
195 */
196 for (div = variant->div_base; div < 4; ++div)
197 if ((rate >> (variant->bits + div)) < freq)
198 break;
199
200 pwm_samsung_set_divisor(chip, chan, BIT(div));
201
202 return rate >> div;
203}
204
205static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
206{
207 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
208 struct samsung_pwm_channel *our_chan;
209
210 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
211 dev_warn(chip->dev,
212 "tried to request PWM channel %d without output\n",
213 pwm->hwpwm);
214 return -EINVAL;
215 }
216
217 our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
218 if (!our_chan)
219 return -ENOMEM;
220
221 pwm_set_chip_data(pwm, our_chan);
222
223 return 0;
224}
225
226static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
227{
228 devm_kfree(chip->dev, pwm_get_chip_data(pwm));
229 pwm_set_chip_data(pwm, NULL);
230}
231
232static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
233{
234 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
235 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
236 unsigned long flags;
237 u32 tcon;
238
239 spin_lock_irqsave(&samsung_pwm_lock, flags);
240
241 tcon = readl(our_chip->base + REG_TCON);
242
243 tcon &= ~TCON_START(tcon_chan);
244 tcon |= TCON_MANUALUPDATE(tcon_chan);
245 writel(tcon, our_chip->base + REG_TCON);
246
247 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
248 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
249 writel(tcon, our_chip->base + REG_TCON);
250
251 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
252
253 return 0;
254}
255
256static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
257{
258 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
259 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
260 unsigned long flags;
261 u32 tcon;
262
263 spin_lock_irqsave(&samsung_pwm_lock, flags);
264
265 tcon = readl(our_chip->base + REG_TCON);
266 tcon &= ~TCON_AUTORELOAD(tcon_chan);
267 writel(tcon, our_chip->base + REG_TCON);
268
269 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
270}
271
272static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
273 struct pwm_device *pwm)
274{
275 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
276 u32 tcon;
277 unsigned long flags;
278
279 spin_lock_irqsave(&samsung_pwm_lock, flags);
280
281 tcon = readl(chip->base + REG_TCON);
282 tcon |= TCON_MANUALUPDATE(tcon_chan);
283 writel(tcon, chip->base + REG_TCON);
284
285 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
286 writel(tcon, chip->base + REG_TCON);
287
288 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
289}
290
291static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
292 int duty_ns, int period_ns)
293{
294 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
295 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
296 u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
297
298 /*
299 * We currently avoid using 64bit arithmetic by using the
300 * fact that anything faster than 1Hz is easily representable
301 * by 32bits.
302 */
303 if (period_ns > NSEC_PER_SEC)
304 return -ERANGE;
305
306 if (period_ns == chan->period_ns && duty_ns == chan->duty_ns)
307 return 0;
308
309 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
310 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
311
312 /* We need tick count for calculation, not last tick. */
313 ++tcnt;
314
315 /* Check to see if we are changing the clock rate of the PWM. */
316 if (chan->period_ns != period_ns) {
317 unsigned long tin_rate;
318 u32 period;
319
320 period = NSEC_PER_SEC / period_ns;
321
322 dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
323 duty_ns, period_ns, period);
324
325 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
326
327 dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
328
329 tin_ns = NSEC_PER_SEC / tin_rate;
330 tcnt = period_ns / tin_ns;
331 }
332
333 /* Period is too short. */
334 if (tcnt <= 1)
335 return -ERANGE;
336
337 /* Note that counters count down. */
338 tcmp = duty_ns / tin_ns;
339
340 /* 0% duty is not available */
341 if (!tcmp)
342 ++tcmp;
343
344 tcmp = tcnt - tcmp;
345
346 /* Decrement to get tick numbers, instead of tick counts. */
347 --tcnt;
348 /* -1UL will give 100% duty. */
349 --tcmp;
350
351 dev_dbg(our_chip->chip.dev,
352 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
353
354 /* Update PWM registers. */
355 writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
356 writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
357
358 /*
359 * In case the PWM is currently at 100% duty cycle, force a manual
360 * update to prevent the signal staying high if the PWM is disabled
361 * shortly afer this update (before it autoreloaded the new values).
362 */
363 if (oldtcmp == (u32) -1) {
364 dev_dbg(our_chip->chip.dev, "Forcing manual update");
365 pwm_samsung_manual_update(our_chip, pwm);
366 }
367
368 chan->period_ns = period_ns;
369 chan->tin_ns = tin_ns;
370 chan->duty_ns = duty_ns;
371
372 return 0;
373}
374
375static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip,
376 unsigned int channel, bool invert)
377{
378 unsigned int tcon_chan = to_tcon_channel(channel);
379 unsigned long flags;
380 u32 tcon;
381
382 spin_lock_irqsave(&samsung_pwm_lock, flags);
383
384 tcon = readl(chip->base + REG_TCON);
385
386 if (invert) {
387 chip->inverter_mask |= BIT(channel);
388 tcon |= TCON_INVERT(tcon_chan);
389 } else {
390 chip->inverter_mask &= ~BIT(channel);
391 tcon &= ~TCON_INVERT(tcon_chan);
392 }
393
394 writel(tcon, chip->base + REG_TCON);
395
396 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
397}
398
399static int pwm_samsung_set_polarity(struct pwm_chip *chip,
400 struct pwm_device *pwm,
401 enum pwm_polarity polarity)
402{
403 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
404 bool invert = (polarity == PWM_POLARITY_NORMAL);
405
406 /* Inverted means normal in the hardware. */
407 pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
408
409 return 0;
410}
411
412static const struct pwm_ops pwm_samsung_ops = {
413 .request = pwm_samsung_request,
414 .free = pwm_samsung_free,
415 .enable = pwm_samsung_enable,
416 .disable = pwm_samsung_disable,
417 .config = pwm_samsung_config,
418 .set_polarity = pwm_samsung_set_polarity,
419 .owner = THIS_MODULE,
420};
421
422#ifdef CONFIG_OF
423static const struct samsung_pwm_variant s3c24xx_variant = {
424 .bits = 16,
425 .div_base = 1,
426 .has_tint_cstat = false,
427 .tclk_mask = BIT(4),
428};
429
430static const struct samsung_pwm_variant s3c64xx_variant = {
431 .bits = 32,
432 .div_base = 0,
433 .has_tint_cstat = true,
434 .tclk_mask = BIT(7) | BIT(6) | BIT(5),
435};
436
437static const struct samsung_pwm_variant s5p64x0_variant = {
438 .bits = 32,
439 .div_base = 0,
440 .has_tint_cstat = true,
441 .tclk_mask = 0,
442};
443
444static const struct samsung_pwm_variant s5pc100_variant = {
445 .bits = 32,
446 .div_base = 0,
447 .has_tint_cstat = true,
448 .tclk_mask = BIT(5),
449};
450
451static const struct of_device_id samsung_pwm_matches[] = {
452 { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
453 { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
454 { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
455 { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
456 { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
457 {},
458};
459MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
460
461static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
462{
463 struct device_node *np = chip->chip.dev->of_node;
464 const struct of_device_id *match;
465 struct property *prop;
466 const __be32 *cur;
467 u32 val;
468
469 match = of_match_node(samsung_pwm_matches, np);
470 if (!match)
471 return -ENODEV;
472
473 memcpy(&chip->variant, match->data, sizeof(chip->variant));
474
475 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
476 if (val >= SAMSUNG_PWM_NUM) {
477 dev_err(chip->chip.dev,
478 "%s: invalid channel index in samsung,pwm-outputs property\n",
479 __func__);
480 continue;
481 }
482 chip->variant.output_mask |= BIT(val);
483 }
484
485 return 0;
486}
487#else
488static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
489{
490 return -ENODEV;
491}
492#endif
493
494static int pwm_samsung_probe(struct platform_device *pdev)
495{
496 struct device *dev = &pdev->dev;
497 struct samsung_pwm_chip *chip;
498 struct resource *res;
499 unsigned int chan;
500 int ret;
501
502 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
503 if (chip == NULL)
504 return -ENOMEM;
505
506 chip->chip.dev = &pdev->dev;
507 chip->chip.ops = &pwm_samsung_ops;
508 chip->chip.base = -1;
509 chip->chip.npwm = SAMSUNG_PWM_NUM;
510 chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
511
512 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
513 ret = pwm_samsung_parse_dt(chip);
514 if (ret)
515 return ret;
516
517 chip->chip.of_xlate = of_pwm_xlate_with_flags;
518 chip->chip.of_pwm_n_cells = 3;
519 } else {
520 if (!pdev->dev.platform_data) {
521 dev_err(&pdev->dev, "no platform data specified\n");
522 return -EINVAL;
523 }
524
525 memcpy(&chip->variant, pdev->dev.platform_data,
526 sizeof(chip->variant));
527 }
528
529 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
530 chip->base = devm_ioremap_resource(&pdev->dev, res);
531 if (IS_ERR(chip->base))
532 return PTR_ERR(chip->base);
533
534 chip->base_clk = devm_clk_get(&pdev->dev, "timers");
535 if (IS_ERR(chip->base_clk)) {
536 dev_err(dev, "failed to get timer base clk\n");
537 return PTR_ERR(chip->base_clk);
538 }
539
540 ret = clk_prepare_enable(chip->base_clk);
541 if (ret < 0) {
542 dev_err(dev, "failed to enable base clock\n");
543 return ret;
544 }
545
546 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
547 if (chip->variant.output_mask & BIT(chan))
548 pwm_samsung_set_invert(chip, chan, true);
549
550 /* Following clocks are optional. */
551 chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
552 chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
553
554 platform_set_drvdata(pdev, chip);
555
556 ret = pwmchip_add(&chip->chip);
557 if (ret < 0) {
558 dev_err(dev, "failed to register PWM chip\n");
559 clk_disable_unprepare(chip->base_clk);
560 return ret;
561 }
562
563 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
564 clk_get_rate(chip->base_clk),
565 !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0,
566 !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0);
567
568 return 0;
569}
570
571static int pwm_samsung_remove(struct platform_device *pdev)
572{
573 struct samsung_pwm_chip *chip = platform_get_drvdata(pdev);
574 int ret;
575
576 ret = pwmchip_remove(&chip->chip);
577 if (ret < 0)
578 return ret;
579
580 clk_disable_unprepare(chip->base_clk);
581
582 return 0;
583}
584
585#ifdef CONFIG_PM_SLEEP
586static int pwm_samsung_suspend(struct device *dev)
587{
588 struct samsung_pwm_chip *chip = dev_get_drvdata(dev);
589 unsigned int i;
590
591 /*
592 * No one preserves these values during suspend so reset them.
593 * Otherwise driver leaves PWM unconfigured if same values are
594 * passed to pwm_config() next time.
595 */
596 for (i = 0; i < SAMSUNG_PWM_NUM; ++i) {
597 struct pwm_device *pwm = &chip->chip.pwms[i];
598 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
599
600 if (!chan)
601 continue;
602
603 chan->period_ns = 0;
604 chan->duty_ns = 0;
605 }
606
607 return 0;
608}
609
610static int pwm_samsung_resume(struct device *dev)
611{
612 struct samsung_pwm_chip *chip = dev_get_drvdata(dev);
613 unsigned int chan;
614
615 /*
616 * Inverter setting must be preserved across suspend/resume
617 * as nobody really seems to configure it more than once.
618 */
619 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) {
620 if (chip->variant.output_mask & BIT(chan))
621 pwm_samsung_set_invert(chip, chan,
622 chip->inverter_mask & BIT(chan));
623 }
624
625 return 0;
626}
627#endif
628
629static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, pwm_samsung_suspend,
630 pwm_samsung_resume);
631
632static struct platform_driver pwm_samsung_driver = {
633 .driver = {
634 .name = "samsung-pwm",
635 .pm = &pwm_samsung_pm_ops,
636 .of_match_table = of_match_ptr(samsung_pwm_matches),
637 },
638 .probe = pwm_samsung_probe,
639 .remove = pwm_samsung_remove,
640};
641module_platform_driver(pwm_samsung_driver);
642
643MODULE_LICENSE("GPL");
644MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
645MODULE_ALIAS("platform:samsung-pwm");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2007 Ben Dooks
4 * Copyright (c) 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
6 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
7 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
8 *
9 * PWM driver for Samsung SoCs
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/export.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24#include <linux/time.h>
25
26/* For struct samsung_timer_variant and samsung_pwm_lock. */
27#include <clocksource/samsung_pwm.h>
28
29#define REG_TCFG0 0x00
30#define REG_TCFG1 0x04
31#define REG_TCON 0x08
32
33#define REG_TCNTB(chan) (0x0c + ((chan) * 0xc))
34#define REG_TCMPB(chan) (0x10 + ((chan) * 0xc))
35
36#define TCFG0_PRESCALER_MASK 0xff
37#define TCFG0_PRESCALER1_SHIFT 8
38
39#define TCFG1_MUX_MASK 0xf
40#define TCFG1_SHIFT(chan) (4 * (chan))
41
42/*
43 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
44 * bits (one channel) after channel 0, so channels have different numbering
45 * when accessing TCON register. See to_tcon_channel() function.
46 *
47 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
48 * in its set of bits is 2 as opposed to 3 for other channels.
49 */
50#define TCON_START(chan) BIT(4 * (chan) + 0)
51#define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1)
52#define TCON_INVERT(chan) BIT(4 * (chan) + 2)
53#define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3)
54#define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2)
55#define TCON_AUTORELOAD(chan) \
56 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
57
58/**
59 * struct samsung_pwm_channel - private data of PWM channel
60 * @period_ns: current period in nanoseconds programmed to the hardware
61 * @duty_ns: current duty time in nanoseconds programmed to the hardware
62 * @tin_ns: time of one timer tick in nanoseconds with current timer rate
63 */
64struct samsung_pwm_channel {
65 u32 period_ns;
66 u32 duty_ns;
67 u32 tin_ns;
68};
69
70/**
71 * struct samsung_pwm_chip - private data of PWM chip
72 * @chip: generic PWM chip
73 * @variant: local copy of hardware variant data
74 * @inverter_mask: inverter status for all channels - one bit per channel
75 * @disabled_mask: disabled status for all channels - one bit per channel
76 * @base: base address of mapped PWM registers
77 * @base_clk: base clock used to drive the timers
78 * @tclk0: external clock 0 (can be ERR_PTR if not present)
79 * @tclk1: external clock 1 (can be ERR_PTR if not present)
80 */
81struct samsung_pwm_chip {
82 struct pwm_chip chip;
83 struct samsung_pwm_variant variant;
84 u8 inverter_mask;
85 u8 disabled_mask;
86
87 void __iomem *base;
88 struct clk *base_clk;
89 struct clk *tclk0;
90 struct clk *tclk1;
91};
92
93#ifndef CONFIG_CLKSRC_SAMSUNG_PWM
94/*
95 * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers
96 * and some registers need access synchronization. If both drivers are
97 * compiled in, the spinlock is defined in the clocksource driver,
98 * otherwise following definition is used.
99 *
100 * Currently we do not need any more complex synchronization method
101 * because all the supported SoCs contain only one instance of the PWM
102 * IP. Should this change, both drivers will need to be modified to
103 * properly synchronize accesses to particular instances.
104 */
105static DEFINE_SPINLOCK(samsung_pwm_lock);
106#endif
107
108static inline
109struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip)
110{
111 return container_of(chip, struct samsung_pwm_chip, chip);
112}
113
114static inline unsigned int to_tcon_channel(unsigned int channel)
115{
116 /* TCON register has a gap of 4 bits (1 channel) after channel 0 */
117 return (channel == 0) ? 0 : (channel + 1);
118}
119
120static void __pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
121 struct pwm_device *pwm)
122{
123 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
124 u32 tcon;
125
126 tcon = readl(chip->base + REG_TCON);
127 tcon |= TCON_MANUALUPDATE(tcon_chan);
128 writel(tcon, chip->base + REG_TCON);
129
130 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
131 writel(tcon, chip->base + REG_TCON);
132}
133
134static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm,
135 unsigned int channel, u8 divisor)
136{
137 u8 shift = TCFG1_SHIFT(channel);
138 unsigned long flags;
139 u32 reg;
140 u8 bits;
141
142 bits = (fls(divisor) - 1) - pwm->variant.div_base;
143
144 spin_lock_irqsave(&samsung_pwm_lock, flags);
145
146 reg = readl(pwm->base + REG_TCFG1);
147 reg &= ~(TCFG1_MUX_MASK << shift);
148 reg |= bits << shift;
149 writel(reg, pwm->base + REG_TCFG1);
150
151 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
152}
153
154static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan)
155{
156 struct samsung_pwm_variant *variant = &chip->variant;
157 u32 reg;
158
159 reg = readl(chip->base + REG_TCFG1);
160 reg >>= TCFG1_SHIFT(chan);
161 reg &= TCFG1_MUX_MASK;
162
163 return (BIT(reg) & variant->tclk_mask) == 0;
164}
165
166static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip,
167 unsigned int chan)
168{
169 unsigned long rate;
170 u32 reg;
171
172 rate = clk_get_rate(chip->base_clk);
173
174 reg = readl(chip->base + REG_TCFG0);
175 if (chan >= 2)
176 reg >>= TCFG0_PRESCALER1_SHIFT;
177 reg &= TCFG0_PRESCALER_MASK;
178
179 return rate / (reg + 1);
180}
181
182static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip,
183 unsigned int chan, unsigned long freq)
184{
185 struct samsung_pwm_variant *variant = &chip->variant;
186 unsigned long rate;
187 struct clk *clk;
188 u8 div;
189
190 if (!pwm_samsung_is_tdiv(chip, chan)) {
191 clk = (chan < 2) ? chip->tclk0 : chip->tclk1;
192 if (!IS_ERR(clk)) {
193 rate = clk_get_rate(clk);
194 if (rate)
195 return rate;
196 }
197
198 dev_warn(chip->chip.dev,
199 "tclk of PWM %d is inoperational, using tdiv\n", chan);
200 }
201
202 rate = pwm_samsung_get_tin_rate(chip, chan);
203 dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate);
204
205 /*
206 * Compare minimum PWM frequency that can be achieved with possible
207 * divider settings and choose the lowest divisor that can generate
208 * frequencies lower than requested.
209 */
210 if (variant->bits < 32) {
211 /* Only for s3c24xx */
212 for (div = variant->div_base; div < 4; ++div)
213 if ((rate >> (variant->bits + div)) < freq)
214 break;
215 } else {
216 /*
217 * Other variants have enough counter bits to generate any
218 * requested rate, so no need to check higher divisors.
219 */
220 div = variant->div_base;
221 }
222
223 pwm_samsung_set_divisor(chip, chan, BIT(div));
224
225 return rate >> div;
226}
227
228static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm)
229{
230 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
231 struct samsung_pwm_channel *our_chan;
232
233 if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) {
234 dev_warn(chip->dev,
235 "tried to request PWM channel %d without output\n",
236 pwm->hwpwm);
237 return -EINVAL;
238 }
239
240 our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL);
241 if (!our_chan)
242 return -ENOMEM;
243
244 pwm_set_chip_data(pwm, our_chan);
245
246 return 0;
247}
248
249static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm)
250{
251 kfree(pwm_get_chip_data(pwm));
252}
253
254static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm)
255{
256 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
257 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
258 unsigned long flags;
259 u32 tcon;
260
261 spin_lock_irqsave(&samsung_pwm_lock, flags);
262
263 tcon = readl(our_chip->base + REG_TCON);
264
265 tcon &= ~TCON_START(tcon_chan);
266 tcon |= TCON_MANUALUPDATE(tcon_chan);
267 writel(tcon, our_chip->base + REG_TCON);
268
269 tcon &= ~TCON_MANUALUPDATE(tcon_chan);
270 tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan);
271 writel(tcon, our_chip->base + REG_TCON);
272
273 our_chip->disabled_mask &= ~BIT(pwm->hwpwm);
274
275 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
276
277 return 0;
278}
279
280static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm)
281{
282 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
283 unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm);
284 unsigned long flags;
285 u32 tcon;
286
287 spin_lock_irqsave(&samsung_pwm_lock, flags);
288
289 tcon = readl(our_chip->base + REG_TCON);
290 tcon &= ~TCON_AUTORELOAD(tcon_chan);
291 writel(tcon, our_chip->base + REG_TCON);
292
293 /*
294 * In case the PWM is at 100% duty cycle, force a manual
295 * update to prevent the signal from staying high.
296 */
297 if (readl(our_chip->base + REG_TCMPB(pwm->hwpwm)) == (u32)-1U)
298 __pwm_samsung_manual_update(our_chip, pwm);
299
300 our_chip->disabled_mask |= BIT(pwm->hwpwm);
301
302 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
303}
304
305static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip,
306 struct pwm_device *pwm)
307{
308 unsigned long flags;
309
310 spin_lock_irqsave(&samsung_pwm_lock, flags);
311
312 __pwm_samsung_manual_update(chip, pwm);
313
314 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
315}
316
317static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
318 int duty_ns, int period_ns, bool force_period)
319{
320 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
321 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
322 u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp;
323
324 tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm));
325 oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm));
326
327 /* We need tick count for calculation, not last tick. */
328 ++tcnt;
329
330 /* Check to see if we are changing the clock rate of the PWM. */
331 if (chan->period_ns != period_ns || force_period) {
332 unsigned long tin_rate;
333 u32 period;
334
335 period = NSEC_PER_SEC / period_ns;
336
337 dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n",
338 duty_ns, period_ns, period);
339
340 tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period);
341
342 dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate);
343
344 tin_ns = NSEC_PER_SEC / tin_rate;
345 tcnt = period_ns / tin_ns;
346 }
347
348 /* Period is too short. */
349 if (tcnt <= 1)
350 return -ERANGE;
351
352 /* Note that counters count down. */
353 tcmp = duty_ns / tin_ns;
354
355 /* 0% duty is not available */
356 if (!tcmp)
357 ++tcmp;
358
359 tcmp = tcnt - tcmp;
360
361 /* Decrement to get tick numbers, instead of tick counts. */
362 --tcnt;
363 /* -1UL will give 100% duty. */
364 --tcmp;
365
366 dev_dbg(our_chip->chip.dev,
367 "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
368
369 /* Update PWM registers. */
370 writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm));
371 writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm));
372
373 /*
374 * In case the PWM is currently at 100% duty cycle, force a manual
375 * update to prevent the signal staying high if the PWM is disabled
376 * shortly afer this update (before it autoreloaded the new values).
377 */
378 if (oldtcmp == (u32) -1) {
379 dev_dbg(our_chip->chip.dev, "Forcing manual update");
380 pwm_samsung_manual_update(our_chip, pwm);
381 }
382
383 chan->period_ns = period_ns;
384 chan->tin_ns = tin_ns;
385 chan->duty_ns = duty_ns;
386
387 return 0;
388}
389
390static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm,
391 int duty_ns, int period_ns)
392{
393 return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false);
394}
395
396static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip,
397 unsigned int channel, bool invert)
398{
399 unsigned int tcon_chan = to_tcon_channel(channel);
400 unsigned long flags;
401 u32 tcon;
402
403 spin_lock_irqsave(&samsung_pwm_lock, flags);
404
405 tcon = readl(chip->base + REG_TCON);
406
407 if (invert) {
408 chip->inverter_mask |= BIT(channel);
409 tcon |= TCON_INVERT(tcon_chan);
410 } else {
411 chip->inverter_mask &= ~BIT(channel);
412 tcon &= ~TCON_INVERT(tcon_chan);
413 }
414
415 writel(tcon, chip->base + REG_TCON);
416
417 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
418}
419
420static int pwm_samsung_set_polarity(struct pwm_chip *chip,
421 struct pwm_device *pwm,
422 enum pwm_polarity polarity)
423{
424 struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip);
425 bool invert = (polarity == PWM_POLARITY_NORMAL);
426
427 /* Inverted means normal in the hardware. */
428 pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert);
429
430 return 0;
431}
432
433static int pwm_samsung_apply(struct pwm_chip *chip, struct pwm_device *pwm,
434 const struct pwm_state *state)
435{
436 int err, enabled = pwm->state.enabled;
437
438 if (state->polarity != pwm->state.polarity) {
439 if (enabled) {
440 pwm_samsung_disable(chip, pwm);
441 enabled = false;
442 }
443
444 err = pwm_samsung_set_polarity(chip, pwm, state->polarity);
445 if (err)
446 return err;
447 }
448
449 if (!state->enabled) {
450 if (enabled)
451 pwm_samsung_disable(chip, pwm);
452
453 return 0;
454 }
455
456 /*
457 * We currently avoid using 64bit arithmetic by using the
458 * fact that anything faster than 1Hz is easily representable
459 * by 32bits.
460 */
461 if (state->period > NSEC_PER_SEC)
462 return -ERANGE;
463
464 err = pwm_samsung_config(chip, pwm, state->duty_cycle, state->period);
465 if (err)
466 return err;
467
468 if (!pwm->state.enabled)
469 err = pwm_samsung_enable(chip, pwm);
470
471 return err;
472}
473
474static const struct pwm_ops pwm_samsung_ops = {
475 .request = pwm_samsung_request,
476 .free = pwm_samsung_free,
477 .apply = pwm_samsung_apply,
478 .owner = THIS_MODULE,
479};
480
481#ifdef CONFIG_OF
482static const struct samsung_pwm_variant s3c24xx_variant = {
483 .bits = 16,
484 .div_base = 1,
485 .has_tint_cstat = false,
486 .tclk_mask = BIT(4),
487};
488
489static const struct samsung_pwm_variant s3c64xx_variant = {
490 .bits = 32,
491 .div_base = 0,
492 .has_tint_cstat = true,
493 .tclk_mask = BIT(7) | BIT(6) | BIT(5),
494};
495
496static const struct samsung_pwm_variant s5p64x0_variant = {
497 .bits = 32,
498 .div_base = 0,
499 .has_tint_cstat = true,
500 .tclk_mask = 0,
501};
502
503static const struct samsung_pwm_variant s5pc100_variant = {
504 .bits = 32,
505 .div_base = 0,
506 .has_tint_cstat = true,
507 .tclk_mask = BIT(5),
508};
509
510static const struct of_device_id samsung_pwm_matches[] = {
511 { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant },
512 { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant },
513 { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant },
514 { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant },
515 { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant },
516 {},
517};
518MODULE_DEVICE_TABLE(of, samsung_pwm_matches);
519
520static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
521{
522 struct device_node *np = chip->chip.dev->of_node;
523 const struct of_device_id *match;
524 struct property *prop;
525 const __be32 *cur;
526 u32 val;
527
528 match = of_match_node(samsung_pwm_matches, np);
529 if (!match)
530 return -ENODEV;
531
532 memcpy(&chip->variant, match->data, sizeof(chip->variant));
533
534 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
535 if (val >= SAMSUNG_PWM_NUM) {
536 dev_err(chip->chip.dev,
537 "%s: invalid channel index in samsung,pwm-outputs property\n",
538 __func__);
539 continue;
540 }
541 chip->variant.output_mask |= BIT(val);
542 }
543
544 return 0;
545}
546#else
547static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip)
548{
549 return -ENODEV;
550}
551#endif
552
553static int pwm_samsung_probe(struct platform_device *pdev)
554{
555 struct device *dev = &pdev->dev;
556 struct samsung_pwm_chip *chip;
557 unsigned int chan;
558 int ret;
559
560 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
561 if (chip == NULL)
562 return -ENOMEM;
563
564 chip->chip.dev = &pdev->dev;
565 chip->chip.ops = &pwm_samsung_ops;
566 chip->chip.npwm = SAMSUNG_PWM_NUM;
567 chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1;
568
569 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
570 ret = pwm_samsung_parse_dt(chip);
571 if (ret)
572 return ret;
573 } else {
574 if (!pdev->dev.platform_data) {
575 dev_err(&pdev->dev, "no platform data specified\n");
576 return -EINVAL;
577 }
578
579 memcpy(&chip->variant, pdev->dev.platform_data,
580 sizeof(chip->variant));
581 }
582
583 chip->base = devm_platform_ioremap_resource(pdev, 0);
584 if (IS_ERR(chip->base))
585 return PTR_ERR(chip->base);
586
587 chip->base_clk = devm_clk_get(&pdev->dev, "timers");
588 if (IS_ERR(chip->base_clk)) {
589 dev_err(dev, "failed to get timer base clk\n");
590 return PTR_ERR(chip->base_clk);
591 }
592
593 ret = clk_prepare_enable(chip->base_clk);
594 if (ret < 0) {
595 dev_err(dev, "failed to enable base clock\n");
596 return ret;
597 }
598
599 for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan)
600 if (chip->variant.output_mask & BIT(chan))
601 pwm_samsung_set_invert(chip, chan, true);
602
603 /* Following clocks are optional. */
604 chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0");
605 chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1");
606
607 platform_set_drvdata(pdev, chip);
608
609 ret = pwmchip_add(&chip->chip);
610 if (ret < 0) {
611 dev_err(dev, "failed to register PWM chip\n");
612 clk_disable_unprepare(chip->base_clk);
613 return ret;
614 }
615
616 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n",
617 clk_get_rate(chip->base_clk),
618 !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0,
619 !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0);
620
621 return 0;
622}
623
624static int pwm_samsung_remove(struct platform_device *pdev)
625{
626 struct samsung_pwm_chip *chip = platform_get_drvdata(pdev);
627
628 pwmchip_remove(&chip->chip);
629
630 clk_disable_unprepare(chip->base_clk);
631
632 return 0;
633}
634
635#ifdef CONFIG_PM_SLEEP
636static int pwm_samsung_resume(struct device *dev)
637{
638 struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev);
639 struct pwm_chip *chip = &our_chip->chip;
640 unsigned int i;
641
642 for (i = 0; i < SAMSUNG_PWM_NUM; i++) {
643 struct pwm_device *pwm = &chip->pwms[i];
644 struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm);
645
646 if (!chan)
647 continue;
648
649 if (our_chip->variant.output_mask & BIT(i))
650 pwm_samsung_set_invert(our_chip, i,
651 our_chip->inverter_mask & BIT(i));
652
653 if (chan->period_ns) {
654 __pwm_samsung_config(chip, pwm, chan->duty_ns,
655 chan->period_ns, true);
656 /* needed to make PWM disable work on Odroid-XU3 */
657 pwm_samsung_manual_update(our_chip, pwm);
658 }
659
660 if (our_chip->disabled_mask & BIT(i))
661 pwm_samsung_disable(chip, pwm);
662 else
663 pwm_samsung_enable(chip, pwm);
664 }
665
666 return 0;
667}
668#endif
669
670static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume);
671
672static struct platform_driver pwm_samsung_driver = {
673 .driver = {
674 .name = "samsung-pwm",
675 .pm = &pwm_samsung_pm_ops,
676 .of_match_table = of_match_ptr(samsung_pwm_matches),
677 },
678 .probe = pwm_samsung_probe,
679 .remove = pwm_samsung_remove,
680};
681module_platform_driver(pwm_samsung_driver);
682
683MODULE_LICENSE("GPL");
684MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
685MODULE_ALIAS("platform:samsung-pwm");