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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_H_
28#define _I40E_H_
29
30#include <net/tcp.h>
31#include <net/udp.h>
32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/aer.h>
37#include <linux/netdevice.h>
38#include <linux/ioport.h>
39#include <linux/iommu.h>
40#include <linux/slab.h>
41#include <linux/list.h>
42#include <linux/string.h>
43#include <linux/in.h>
44#include <linux/ip.h>
45#include <linux/sctp.h>
46#include <linux/pkt_sched.h>
47#include <linux/ipv6.h>
48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
51#include <linux/if_vlan.h>
52#include <linux/if_bridge.h>
53#include <linux/clocksource.h>
54#include <linux/net_tstamp.h>
55#include <linux/ptp_clock_kernel.h>
56#include "i40e_type.h"
57#include "i40e_prototype.h"
58#ifdef I40E_FCOE
59#include "i40e_fcoe.h"
60#endif
61#include "i40e_client.h"
62#include "i40e_virtchnl.h"
63#include "i40e_virtchnl_pf.h"
64#include "i40e_txrx.h"
65#include "i40e_dcb.h"
66
67/* Useful i40e defaults */
68#define I40E_MAX_VEB 16
69
70#define I40E_MAX_NUM_DESCRIPTORS 4096
71#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
72#define I40E_DEFAULT_NUM_DESCRIPTORS 512
73#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
74#define I40E_MIN_NUM_DESCRIPTORS 64
75#define I40E_MIN_MSIX 2
76#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
77#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
78/* max 16 qps */
79#define i40e_default_queues_per_vmdq(pf) \
80 (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
81#define I40E_DEFAULT_QUEUES_PER_VF 4
82#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
83#define i40e_pf_get_max_q_per_tc(pf) \
84 (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
85#define I40E_FDIR_RING 0
86#define I40E_FDIR_RING_COUNT 32
87#ifdef I40E_FCOE
88#define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */
89#define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */
90#endif /* I40E_FCOE */
91#define I40E_MAX_AQ_BUF_SIZE 4096
92#define I40E_AQ_LEN 256
93#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
94#define I40E_MAX_USER_PRIORITY 8
95#define I40E_DEFAULT_MSG_ENABLE 4
96#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
97#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
98
99/* Ethtool Private Flags */
100#define I40E_PRIV_FLAGS_NPAR_FLAG BIT(0)
101#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
102#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
103#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
104#define I40E_PRIV_FLAGS_PS BIT(4)
105#define I40E_PRIV_FLAGS_HW_ATR_EVICT BIT(5)
106
107#define I40E_NVM_VERSION_LO_SHIFT 0
108#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
109#define I40E_NVM_VERSION_HI_SHIFT 12
110#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
111#define I40E_OEM_VER_BUILD_MASK 0xffff
112#define I40E_OEM_VER_PATCH_MASK 0xff
113#define I40E_OEM_VER_BUILD_SHIFT 8
114#define I40E_OEM_VER_SHIFT 24
115#define I40E_PHY_DEBUG_PORT BIT(4)
116
117/* The values in here are decimal coded as hex as is the case in the NVM map*/
118#define I40E_CURRENT_NVM_VERSION_HI 0x2
119#define I40E_CURRENT_NVM_VERSION_LO 0x40
120
121/* magic for getting defines into strings */
122#define STRINGIFY(foo) #foo
123#define XSTRINGIFY(bar) STRINGIFY(bar)
124
125#define I40E_RX_DESC(R, i) \
126 ((ring_is_16byte_desc_enabled(R)) \
127 ? (union i40e_32byte_rx_desc *) \
128 (&(((union i40e_16byte_rx_desc *)((R)->desc))[i])) \
129 : (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])))
130#define I40E_TX_DESC(R, i) \
131 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
132#define I40E_TX_CTXTDESC(R, i) \
133 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
134#define I40E_TX_FDIRDESC(R, i) \
135 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
136
137/* default to trying for four seconds */
138#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
139
140/**
141 * i40e_is_mac_710 - Return true if MAC is X710/XL710
142 * @hw: ptr to the hardware info
143 **/
144static inline bool i40e_is_mac_710(struct i40e_hw *hw)
145{
146 if ((hw->mac.type == I40E_MAC_X710) ||
147 (hw->mac.type == I40E_MAC_XL710))
148 return true;
149
150 return false;
151}
152
153/* driver state flags */
154enum i40e_state_t {
155 __I40E_TESTING,
156 __I40E_CONFIG_BUSY,
157 __I40E_CONFIG_DONE,
158 __I40E_DOWN,
159 __I40E_NEEDS_RESTART,
160 __I40E_SERVICE_SCHED,
161 __I40E_ADMINQ_EVENT_PENDING,
162 __I40E_MDD_EVENT_PENDING,
163 __I40E_VFLR_EVENT_PENDING,
164 __I40E_RESET_RECOVERY_PENDING,
165 __I40E_RESET_INTR_RECEIVED,
166 __I40E_REINIT_REQUESTED,
167 __I40E_PF_RESET_REQUESTED,
168 __I40E_CORE_RESET_REQUESTED,
169 __I40E_GLOBAL_RESET_REQUESTED,
170 __I40E_EMP_RESET_REQUESTED,
171 __I40E_EMP_RESET_INTR_RECEIVED,
172 __I40E_FILTER_OVERFLOW_PROMISC,
173 __I40E_SUSPENDED,
174 __I40E_PTP_TX_IN_PROGRESS,
175 __I40E_BAD_EEPROM,
176 __I40E_DOWN_REQUESTED,
177 __I40E_FD_FLUSH_REQUESTED,
178 __I40E_RESET_FAILED,
179 __I40E_PORT_TX_SUSPENDED,
180 __I40E_VF_DISABLE,
181};
182
183enum i40e_interrupt_policy {
184 I40E_INTERRUPT_BEST_CASE,
185 I40E_INTERRUPT_MEDIUM,
186 I40E_INTERRUPT_LOWEST
187};
188
189struct i40e_lump_tracking {
190 u16 num_entries;
191 u16 search_hint;
192 u16 list[0];
193#define I40E_PILE_VALID_BIT 0x8000
194#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
195};
196
197#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
198#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
199#define I40E_FDIR_BUFFER_FULL_MARGIN 10
200#define I40E_FDIR_BUFFER_HEAD_ROOM 32
201#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
202
203#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
204#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
205
206enum i40e_fd_stat_idx {
207 I40E_FD_STAT_ATR,
208 I40E_FD_STAT_SB,
209 I40E_FD_STAT_ATR_TUNNEL,
210 I40E_FD_STAT_PF_COUNT
211};
212#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
213#define I40E_FD_ATR_STAT_IDX(pf_id) \
214 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
215#define I40E_FD_SB_STAT_IDX(pf_id) \
216 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
217#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
218 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
219
220struct i40e_fdir_filter {
221 struct hlist_node fdir_node;
222 /* filter ipnut set */
223 u8 flow_type;
224 u8 ip4_proto;
225 /* TX packet view of src and dst */
226 __be32 dst_ip[4];
227 __be32 src_ip[4];
228 __be16 src_port;
229 __be16 dst_port;
230 __be32 sctp_v_tag;
231 /* filter control */
232 u16 q_index;
233 u8 flex_off;
234 u8 pctype;
235 u16 dest_vsi;
236 u8 dest_ctl;
237 u8 fd_status;
238 u16 cnt_index;
239 u32 fd_id;
240};
241
242#define I40E_ETH_P_LLDP 0x88cc
243
244#define I40E_DCB_PRIO_TYPE_STRICT 0
245#define I40E_DCB_PRIO_TYPE_ETS 1
246#define I40E_DCB_STRICT_PRIO_CREDITS 127
247#define I40E_MAX_USER_PRIORITY 8
248/* DCB per TC information data structure */
249struct i40e_tc_info {
250 u16 qoffset; /* Queue offset from base queue */
251 u16 qcount; /* Total Queues */
252 u8 netdev_tc; /* Netdev TC index if netdev associated */
253};
254
255/* TC configuration data structure */
256struct i40e_tc_configuration {
257 u8 numtc; /* Total number of enabled TCs */
258 u8 enabled_tc; /* TC map */
259 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
260};
261
262struct i40e_udp_port_config {
263 __be16 index;
264 u8 type;
265};
266
267/* struct that defines the Ethernet device */
268struct i40e_pf {
269 struct pci_dev *pdev;
270 struct i40e_hw hw;
271 unsigned long state;
272 struct msix_entry *msix_entries;
273 bool fc_autoneg_status;
274
275 u16 eeprom_version;
276 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
277 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
278 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
279 u16 num_req_vfs; /* num VFs requested for this VF */
280 u16 num_vf_qps; /* num queue pairs per VF */
281#ifdef I40E_FCOE
282 u16 num_fcoe_qps; /* num fcoe queues this PF has set up */
283 u16 num_fcoe_msix; /* num queue vectors per fcoe pool */
284#endif /* I40E_FCOE */
285 u16 num_lan_qps; /* num lan queues this PF has set up */
286 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
287 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
288 int iwarp_base_vector;
289 int queues_left; /* queues left unclaimed */
290 u16 alloc_rss_size; /* allocated RSS queues */
291 u16 rss_size_max; /* HW defined max RSS queues */
292 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
293 u16 num_alloc_vsi; /* num VSIs this driver supports */
294 u8 atr_sample_rate;
295 bool wol_en;
296
297 struct hlist_head fdir_filter_list;
298 u16 fdir_pf_active_filters;
299 unsigned long fd_flush_timestamp;
300 u32 fd_flush_cnt;
301 u32 fd_add_err;
302 u32 fd_atr_cnt;
303 u32 fd_tcp_rule;
304
305 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
306 u16 pending_udp_bitmap;
307
308 enum i40e_interrupt_policy int_policy;
309 u16 rx_itr_default;
310 u16 tx_itr_default;
311 u32 msg_enable;
312 char int_name[I40E_INT_NAME_STR_LEN];
313 u16 adminq_work_limit; /* num of admin receive queue desc to process */
314 unsigned long service_timer_period;
315 unsigned long service_timer_previous;
316 struct timer_list service_timer;
317 struct work_struct service_task;
318
319 u64 flags;
320#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
321#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
322#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
323#define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4)
324#define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5)
325#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
326#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
327#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
328#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
329#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
330#ifdef I40E_FCOE
331#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
332#endif /* I40E_FCOE */
333#define I40E_FLAG_16BYTE_RX_DESC_ENABLED BIT_ULL(13)
334#define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14)
335#define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
336#define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT_ULL(16)
337#define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17)
338#define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18)
339#define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
340#define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
341#define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
342#define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
343#define I40E_FLAG_PTP BIT_ULL(25)
344#define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
345#define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27)
346#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
347#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
348#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
349#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
350#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
351#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
352#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
353#define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
354#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
355#define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
356#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
357#define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE BIT_ULL(41)
358#define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42)
359#define I40E_FLAG_100M_SGMII_CAPABLE BIT_ULL(43)
360#define I40E_FLAG_RESTART_AUTONEG BIT_ULL(44)
361#define I40E_FLAG_NO_DCB_SUPPORT BIT_ULL(45)
362#define I40E_FLAG_USE_SET_LLDP_MIB BIT_ULL(46)
363#define I40E_FLAG_STOP_FW_LLDP BIT_ULL(47)
364#define I40E_FLAG_HAVE_10GBASET_PHY BIT_ULL(48)
365#define I40E_FLAG_PF_MAC BIT_ULL(50)
366
367 /* tracks features that get auto disabled by errors */
368 u64 auto_disable_flags;
369
370#ifdef I40E_FCOE
371 struct i40e_fcoe fcoe;
372
373#endif /* I40E_FCOE */
374 bool stat_offsets_loaded;
375 struct i40e_hw_port_stats stats;
376 struct i40e_hw_port_stats stats_offsets;
377 u32 tx_timeout_count;
378 u32 tx_timeout_recovery_level;
379 unsigned long tx_timeout_last_recovery;
380 u32 tx_sluggish_count;
381 u32 hw_csum_rx_error;
382 u32 led_status;
383 u16 corer_count; /* Core reset count */
384 u16 globr_count; /* Global reset count */
385 u16 empr_count; /* EMP reset count */
386 u16 pfr_count; /* PF reset count */
387 u16 sw_int_count; /* SW interrupt count */
388
389 struct mutex switch_mutex;
390 u16 lan_vsi; /* our default LAN VSI */
391 u16 lan_veb; /* initial relay, if exists */
392#define I40E_NO_VEB 0xffff
393#define I40E_NO_VSI 0xffff
394 u16 next_vsi; /* Next unallocated VSI - 0-based! */
395 struct i40e_vsi **vsi;
396 struct i40e_veb *veb[I40E_MAX_VEB];
397
398 struct i40e_lump_tracking *qp_pile;
399 struct i40e_lump_tracking *irq_pile;
400
401 /* switch config info */
402 u16 pf_seid;
403 u16 main_vsi_seid;
404 u16 mac_seid;
405 struct kobject *switch_kobj;
406#ifdef CONFIG_DEBUG_FS
407 struct dentry *i40e_dbg_pf;
408#endif /* CONFIG_DEBUG_FS */
409 bool cur_promisc;
410
411 u16 instance; /* A unique number per i40e_pf instance in the system */
412
413 /* sr-iov config info */
414 struct i40e_vf *vf;
415 int num_alloc_vfs; /* actual number of VFs allocated */
416 u32 vf_aq_requests;
417 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
418
419 /* DCBx/DCBNL capability for PF that indicates
420 * whether DCBx is managed by firmware or host
421 * based agent (LLDPAD). Also, indicates what
422 * flavor of DCBx protocol (IEEE/CEE) is supported
423 * by the device. For now we're supporting IEEE
424 * mode only.
425 */
426 u16 dcbx_cap;
427
428 u32 fcoe_hmc_filt_num;
429 u32 fcoe_hmc_cntx_num;
430 struct i40e_filter_control_settings filter_settings;
431
432 struct ptp_clock *ptp_clock;
433 struct ptp_clock_info ptp_caps;
434 struct sk_buff *ptp_tx_skb;
435 struct hwtstamp_config tstamp_config;
436 unsigned long last_rx_ptp_check;
437 spinlock_t tmreg_lock; /* Used to protect the device time registers. */
438 u64 ptp_base_adj;
439 u32 tx_hwtstamp_timeouts;
440 u32 rx_hwtstamp_cleared;
441 bool ptp_tx;
442 bool ptp_rx;
443 u16 rss_table_size; /* HW RSS table size */
444 /* These are only valid in NPAR modes */
445 u32 npar_max_bw;
446 u32 npar_min_bw;
447
448 u32 ioremap_len;
449 u32 fd_inv;
450 u16 phy_led_val;
451};
452
453struct i40e_mac_filter {
454 struct list_head list;
455 u8 macaddr[ETH_ALEN];
456#define I40E_VLAN_ANY -1
457 s16 vlan;
458 u8 counter; /* number of instances of this filter */
459 bool is_vf; /* filter belongs to a VF */
460 bool is_netdev; /* filter belongs to a netdev */
461 bool changed; /* filter needs to be sync'd to the HW */
462 bool is_laa; /* filter is a Locally Administered Address */
463};
464
465struct i40e_veb {
466 struct i40e_pf *pf;
467 u16 idx;
468 u16 veb_idx; /* index of VEB parent */
469 u16 seid;
470 u16 uplink_seid;
471 u16 stats_idx; /* index of VEB parent */
472 u8 enabled_tc;
473 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
474 u16 flags;
475 u16 bw_limit;
476 u8 bw_max_quanta;
477 bool is_abs_credits;
478 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
479 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
480 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
481 struct kobject *kobj;
482 bool stat_offsets_loaded;
483 struct i40e_eth_stats stats;
484 struct i40e_eth_stats stats_offsets;
485 struct i40e_veb_tc_stats tc_stats;
486 struct i40e_veb_tc_stats tc_stats_offsets;
487};
488
489/* struct that defines a VSI, associated with a dev */
490struct i40e_vsi {
491 struct net_device *netdev;
492 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
493 bool netdev_registered;
494 bool stat_offsets_loaded;
495
496 u32 current_netdev_flags;
497 unsigned long state;
498#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
499#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
500 unsigned long flags;
501
502 /* Per VSI lock to protect elements/list (MAC filter) */
503 spinlock_t mac_filter_list_lock;
504 struct list_head mac_filter_list;
505
506 /* VSI stats */
507 struct rtnl_link_stats64 net_stats;
508 struct rtnl_link_stats64 net_stats_offsets;
509 struct i40e_eth_stats eth_stats;
510 struct i40e_eth_stats eth_stats_offsets;
511#ifdef I40E_FCOE
512 struct i40e_fcoe_stats fcoe_stats;
513 struct i40e_fcoe_stats fcoe_stats_offsets;
514 bool fcoe_stat_offsets_loaded;
515#endif
516 u32 tx_restart;
517 u32 tx_busy;
518 u64 tx_linearize;
519 u64 tx_force_wb;
520 u64 tx_lost_interrupt;
521 u32 rx_buf_failed;
522 u32 rx_page_failed;
523
524 /* These are containers of ring pointers, allocated at run-time */
525 struct i40e_ring **rx_rings;
526 struct i40e_ring **tx_rings;
527
528 u16 work_limit;
529 u16 int_rate_limit; /* value in usecs */
530
531 u16 rss_table_size; /* HW RSS table size */
532 u16 rss_size; /* Allocated RSS queues */
533 u8 *rss_hkey_user; /* User configured hash keys */
534 u8 *rss_lut_user; /* User configured lookup table entries */
535
536 u16 max_frame;
537 u16 rx_hdr_len;
538 u16 rx_buf_len;
539 u8 dtype;
540
541 /* List of q_vectors allocated to this VSI */
542 struct i40e_q_vector **q_vectors;
543 int num_q_vectors;
544 int base_vector;
545 bool irqs_ready;
546
547 u16 seid; /* HW index of this VSI (absolute index) */
548 u16 id; /* VSI number */
549 u16 uplink_seid;
550
551 u16 base_queue; /* vsi's first queue in hw array */
552 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
553 u16 req_queue_pairs; /* User requested queue pairs */
554 u16 num_queue_pairs; /* Used tx and rx pairs */
555 u16 num_desc;
556 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
557 u16 vf_id; /* Virtual function ID for SRIOV VSIs */
558
559 struct i40e_tc_configuration tc_config;
560 struct i40e_aqc_vsi_properties_data info;
561
562 /* VSI BW limit (absolute across all TCs) */
563 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
564 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
565
566 /* Relative TC credits across VSIs */
567 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
568 /* TC BW limit credits within VSI */
569 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
570 /* TC BW limit max quanta within VSI */
571 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
572
573 struct i40e_pf *back; /* Backreference to associated PF */
574 u16 idx; /* index in pf->vsi[] */
575 u16 veb_idx; /* index of VEB parent */
576 struct kobject *kobj; /* sysfs object */
577 bool current_isup; /* Sync 'link up' logging */
578
579 void *priv; /* client driver data reference. */
580
581 /* VSI specific handlers */
582 irqreturn_t (*irq_handler)(int irq, void *data);
583
584 /* current rxnfc data */
585 struct ethtool_rxnfc rxnfc; /* current rss hash opts */
586} ____cacheline_internodealigned_in_smp;
587
588struct i40e_netdev_priv {
589 struct i40e_vsi *vsi;
590};
591
592/* struct that defines an interrupt vector */
593struct i40e_q_vector {
594 struct i40e_vsi *vsi;
595
596 u16 v_idx; /* index in the vsi->q_vector array. */
597 u16 reg_idx; /* register index of the interrupt */
598
599 struct napi_struct napi;
600
601 struct i40e_ring_container rx;
602 struct i40e_ring_container tx;
603
604 u8 num_ringpairs; /* total number of ring pairs in vector */
605
606#define I40E_Q_VECTOR_HUNG_DETECT 0 /* Bit Index for hung detection logic */
607 unsigned long hung_detected; /* Set/Reset for hung_detection logic */
608
609 cpumask_t affinity_mask;
610 struct rcu_head rcu; /* to avoid race with update stats on free */
611 char name[I40E_INT_NAME_STR_LEN];
612 bool arm_wb_state;
613#define ITR_COUNTDOWN_START 100
614 u8 itr_countdown; /* when 0 should adjust ITR */
615} ____cacheline_internodealigned_in_smp;
616
617/* lan device */
618struct i40e_device {
619 struct list_head list;
620 struct i40e_pf *pf;
621};
622
623/**
624 * i40e_nvm_version_str - format the NVM version strings
625 * @hw: ptr to the hardware info
626 **/
627static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
628{
629 static char buf[32];
630 u32 full_ver;
631 u8 ver, patch;
632 u16 build;
633
634 full_ver = hw->nvm.oem_ver;
635 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
636 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
637 I40E_OEM_VER_BUILD_MASK);
638 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
639
640 snprintf(buf, sizeof(buf),
641 "%x.%02x 0x%x %d.%d.%d",
642 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
643 I40E_NVM_VERSION_HI_SHIFT,
644 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
645 I40E_NVM_VERSION_LO_SHIFT,
646 hw->nvm.eetrack, ver, build, patch);
647
648 return buf;
649}
650
651/**
652 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
653 * @netdev: the corresponding netdev
654 *
655 * Return the PF struct for the given netdev
656 **/
657static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
658{
659 struct i40e_netdev_priv *np = netdev_priv(netdev);
660 struct i40e_vsi *vsi = np->vsi;
661
662 return vsi->back;
663}
664
665static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
666 irqreturn_t (*irq_handler)(int, void *))
667{
668 vsi->irq_handler = irq_handler;
669}
670
671/**
672 * i40e_rx_is_programming_status - check for programming status descriptor
673 * @qw: the first quad word of the program status descriptor
674 *
675 * The value of in the descriptor length field indicate if this
676 * is a programming status descriptor for flow director or FCoE
677 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
678 * it is a packet descriptor.
679 **/
680static inline bool i40e_rx_is_programming_status(u64 qw)
681{
682 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
683 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
684}
685
686/**
687 * i40e_get_fd_cnt_all - get the total FD filter space available
688 * @pf: pointer to the PF struct
689 **/
690static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
691{
692 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
693}
694
695/* needed by i40e_ethtool.c */
696int i40e_up(struct i40e_vsi *vsi);
697void i40e_down(struct i40e_vsi *vsi);
698extern const char i40e_driver_name[];
699extern const char i40e_driver_version_str[];
700void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
701void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
702int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
703int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
704struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
705void i40e_update_stats(struct i40e_vsi *vsi);
706void i40e_update_eth_stats(struct i40e_vsi *vsi);
707struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
708int i40e_fetch_switch_configuration(struct i40e_pf *pf,
709 bool printconfig);
710
711int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
712 struct i40e_pf *pf, bool add);
713int i40e_add_del_fdir(struct i40e_vsi *vsi,
714 struct i40e_fdir_filter *input, bool add);
715void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
716u32 i40e_get_current_fd_count(struct i40e_pf *pf);
717u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
718u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
719u32 i40e_get_global_fd_count(struct i40e_pf *pf);
720bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
721void i40e_set_ethtool_ops(struct net_device *netdev);
722struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
723 u8 *macaddr, s16 vlan,
724 bool is_vf, bool is_netdev);
725void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan,
726 bool is_vf, bool is_netdev);
727int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
728struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
729 u16 uplink, u32 param1);
730int i40e_vsi_release(struct i40e_vsi *vsi);
731struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type,
732 struct i40e_vsi *start_vsi);
733#ifdef I40E_FCOE
734void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
735 struct i40e_vsi_context *ctxt,
736 u8 enabled_tc, bool is_add);
737#endif
738void i40e_service_event_schedule(struct i40e_pf *pf);
739void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
740 u8 *msg, u16 len);
741
742int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable);
743int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
744struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
745 u16 downlink_seid, u8 enabled_tc);
746void i40e_veb_release(struct i40e_veb *veb);
747
748int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
749int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
750void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
751void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
752void i40e_pf_reset_stats(struct i40e_pf *pf);
753#ifdef CONFIG_DEBUG_FS
754void i40e_dbg_pf_init(struct i40e_pf *pf);
755void i40e_dbg_pf_exit(struct i40e_pf *pf);
756void i40e_dbg_init(void);
757void i40e_dbg_exit(void);
758#else
759static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
760static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
761static inline void i40e_dbg_init(void) {}
762static inline void i40e_dbg_exit(void) {}
763#endif /* CONFIG_DEBUG_FS*/
764/* needed by client drivers */
765int i40e_lan_add_device(struct i40e_pf *pf);
766int i40e_lan_del_device(struct i40e_pf *pf);
767void i40e_client_subtask(struct i40e_pf *pf);
768void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
769void i40e_notify_client_of_netdev_open(struct i40e_vsi *vsi);
770void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
771void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
772void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
773int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id,
774 enum i40e_client_type type);
775/**
776 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
777 * @vsi: pointer to a vsi
778 * @vector: enable a particular Hw Interrupt vector, without base_vector
779 **/
780static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
781{
782 struct i40e_pf *pf = vsi->back;
783 struct i40e_hw *hw = &pf->hw;
784 u32 val;
785
786 /* definitely clear the PBA here, as this function is meant to
787 * clean out all previous interrupts AND enable the interrupt
788 */
789 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
790 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
791 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
792 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
793 /* skip the flush */
794}
795
796void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
797void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba);
798#ifdef I40E_FCOE
799struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
800 struct net_device *netdev,
801 struct rtnl_link_stats64 *storage);
802int i40e_set_mac(struct net_device *netdev, void *p);
803void i40e_set_rx_mode(struct net_device *netdev);
804#endif
805int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
806#ifdef I40E_FCOE
807void i40e_tx_timeout(struct net_device *netdev);
808int i40e_vlan_rx_add_vid(struct net_device *netdev,
809 __always_unused __be16 proto, u16 vid);
810int i40e_vlan_rx_kill_vid(struct net_device *netdev,
811 __always_unused __be16 proto, u16 vid);
812#endif
813int i40e_open(struct net_device *netdev);
814int i40e_vsi_open(struct i40e_vsi *vsi);
815void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
816int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);
817int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid);
818struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
819 bool is_vf, bool is_netdev);
820int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
821 bool is_vf, bool is_netdev);
822bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
823struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
824 bool is_vf, bool is_netdev);
825#ifdef I40E_FCOE
826int i40e_close(struct net_device *netdev);
827int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
828 struct tc_to_netdev *tc);
829void i40e_netpoll(struct net_device *netdev);
830int i40e_fcoe_enable(struct net_device *netdev);
831int i40e_fcoe_disable(struct net_device *netdev);
832int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt);
833u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf);
834void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi);
835void i40e_fcoe_vsi_setup(struct i40e_pf *pf);
836void i40e_init_pf_fcoe(struct i40e_pf *pf);
837int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi);
838void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi);
839int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring,
840 union i40e_rx_desc *rx_desc,
841 struct sk_buff *skb);
842void i40e_fcoe_handle_status(struct i40e_ring *rx_ring,
843 union i40e_rx_desc *rx_desc, u8 prog_id);
844#endif /* I40E_FCOE */
845void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
846#ifdef CONFIG_I40E_DCB
847void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
848 struct i40e_dcbx_config *old_cfg,
849 struct i40e_dcbx_config *new_cfg);
850void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
851void i40e_dcbnl_setup(struct i40e_vsi *vsi);
852bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
853 struct i40e_dcbx_config *old_cfg,
854 struct i40e_dcbx_config *new_cfg);
855#endif /* CONFIG_I40E_DCB */
856void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
857void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
858void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
859void i40e_ptp_set_increment(struct i40e_pf *pf);
860int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
861int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
862void i40e_ptp_init(struct i40e_pf *pf);
863void i40e_ptp_stop(struct i40e_pf *pf);
864int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
865i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
866i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
867i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
868void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
869#endif /* _I40E_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4#ifndef _I40E_H_
5#define _I40E_H_
6
7#include <linux/pci.h>
8#include <linux/ptp_clock_kernel.h>
9#include <linux/types.h>
10#include <linux/avf/virtchnl.h>
11#include <linux/net/intel/i40e_client.h>
12#include <net/devlink.h>
13#include <net/pkt_cls.h>
14#include <net/udp_tunnel.h>
15#include "i40e_dcb.h"
16#include "i40e_debug.h"
17#include "i40e_devlink.h"
18#include "i40e_io.h"
19#include "i40e_prototype.h"
20#include "i40e_register.h"
21#include "i40e_txrx.h"
22
23/* Useful i40e defaults */
24#define I40E_MAX_VEB 16
25
26#define I40E_MAX_NUM_DESCRIPTORS 4096
27#define I40E_MAX_NUM_DESCRIPTORS_XL710 8160
28#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
29#define I40E_DEFAULT_NUM_DESCRIPTORS 512
30#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
31#define I40E_MIN_NUM_DESCRIPTORS 64
32#define I40E_MIN_MSIX 2
33#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
34#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
35/* max 16 qps */
36#define i40e_default_queues_per_vmdq(pf) \
37 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
38#define I40E_DEFAULT_QUEUES_PER_VF 4
39#define I40E_MAX_VF_QUEUES 16
40#define i40e_pf_get_max_q_per_tc(pf) \
41 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
42#define I40E_FDIR_RING_COUNT 32
43#define I40E_MAX_AQ_BUF_SIZE 4096
44#define I40E_AQ_LEN 256
45#define I40E_MIN_ARQ_LEN 1
46#define I40E_MIN_ASQ_LEN 2
47#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
48#define I40E_MAX_USER_PRIORITY 8
49#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
50#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
51#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
52
53#define I40E_PHY_DEBUG_ALL \
54 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
55 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
56
57#define I40E_OEM_EETRACK_ID 0xffffffff
58#define I40E_NVM_VERSION_LO_MASK GENMASK(7, 0)
59#define I40E_NVM_VERSION_HI_MASK GENMASK(15, 12)
60#define I40E_OEM_VER_BUILD_MASK GENMASK(23, 8)
61#define I40E_OEM_VER_PATCH_MASK GENMASK(7, 0)
62#define I40E_OEM_VER_MASK GENMASK(31, 24)
63#define I40E_OEM_GEN_MASK GENMASK(31, 24)
64#define I40E_OEM_SNAP_MASK GENMASK(23, 16)
65#define I40E_OEM_RELEASE_MASK GENMASK(15, 0)
66
67#define I40E_RX_DESC(R, i) \
68 (&(((union i40e_rx_desc *)((R)->desc))[i]))
69#define I40E_TX_DESC(R, i) \
70 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
71#define I40E_TX_CTXTDESC(R, i) \
72 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
73#define I40E_TX_FDIRDESC(R, i) \
74 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
75
76/* BW rate limiting */
77#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
78#define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
79#define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
80
81/* driver state flags */
82enum i40e_state {
83 __I40E_TESTING,
84 __I40E_CONFIG_BUSY,
85 __I40E_CONFIG_DONE,
86 __I40E_DOWN,
87 __I40E_SERVICE_SCHED,
88 __I40E_ADMINQ_EVENT_PENDING,
89 __I40E_MDD_EVENT_PENDING,
90 __I40E_VFLR_EVENT_PENDING,
91 __I40E_RESET_RECOVERY_PENDING,
92 __I40E_TIMEOUT_RECOVERY_PENDING,
93 __I40E_MISC_IRQ_REQUESTED,
94 __I40E_RESET_INTR_RECEIVED,
95 __I40E_REINIT_REQUESTED,
96 __I40E_PF_RESET_REQUESTED,
97 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
98 __I40E_CORE_RESET_REQUESTED,
99 __I40E_GLOBAL_RESET_REQUESTED,
100 __I40E_EMP_RESET_INTR_RECEIVED,
101 __I40E_SUSPENDED,
102 __I40E_PTP_TX_IN_PROGRESS,
103 __I40E_BAD_EEPROM,
104 __I40E_DOWN_REQUESTED,
105 __I40E_FD_FLUSH_REQUESTED,
106 __I40E_FD_ATR_AUTO_DISABLED,
107 __I40E_FD_SB_AUTO_DISABLED,
108 __I40E_RESET_FAILED,
109 __I40E_PORT_SUSPENDED,
110 __I40E_VF_DISABLE,
111 __I40E_MACVLAN_SYNC_PENDING,
112 __I40E_TEMP_LINK_POLLING,
113 __I40E_CLIENT_SERVICE_REQUESTED,
114 __I40E_CLIENT_L2_CHANGE,
115 __I40E_CLIENT_RESET,
116 __I40E_VIRTCHNL_OP_PENDING,
117 __I40E_RECOVERY_MODE,
118 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */
119 __I40E_IN_REMOVE,
120 __I40E_VFS_RELEASING,
121 /* This must be last as it determines the size of the BITMAP */
122 __I40E_STATE_SIZE__,
123};
124
125#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
126#define I40E_PF_RESET_AND_REBUILD_FLAG \
127 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
128
129/* VSI state flags */
130enum i40e_vsi_state {
131 __I40E_VSI_DOWN,
132 __I40E_VSI_NEEDS_RESTART,
133 __I40E_VSI_SYNCING_FILTERS,
134 __I40E_VSI_OVERFLOW_PROMISC,
135 __I40E_VSI_REINIT_REQUESTED,
136 __I40E_VSI_DOWN_REQUESTED,
137 __I40E_VSI_RELEASING,
138 /* This must be last as it determines the size of the BITMAP */
139 __I40E_VSI_STATE_SIZE__,
140};
141
142enum i40e_pf_flags {
143 I40E_FLAG_MSI_ENA,
144 I40E_FLAG_MSIX_ENA,
145 I40E_FLAG_RSS_ENA,
146 I40E_FLAG_VMDQ_ENA,
147 I40E_FLAG_SRIOV_ENA,
148 I40E_FLAG_DCB_CAPABLE,
149 I40E_FLAG_DCB_ENA,
150 I40E_FLAG_FD_SB_ENA,
151 I40E_FLAG_FD_ATR_ENA,
152 I40E_FLAG_MFP_ENA,
153 I40E_FLAG_HW_ATR_EVICT_ENA,
154 I40E_FLAG_VEB_MODE_ENA,
155 I40E_FLAG_VEB_STATS_ENA,
156 I40E_FLAG_LINK_POLLING_ENA,
157 I40E_FLAG_TRUE_PROMISC_ENA,
158 I40E_FLAG_LEGACY_RX_ENA,
159 I40E_FLAG_PTP_ENA,
160 I40E_FLAG_IWARP_ENA,
161 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA,
162 I40E_FLAG_SOURCE_PRUNING_DIS,
163 I40E_FLAG_TC_MQPRIO_ENA,
164 I40E_FLAG_FD_SB_INACTIVE,
165 I40E_FLAG_FD_SB_TO_CLOUD_FILTER,
166 I40E_FLAG_FW_LLDP_DIS,
167 I40E_FLAG_RS_FEC,
168 I40E_FLAG_BASE_R_FEC,
169 /* TOTAL_PORT_SHUTDOWN_ENA
170 * Allows to physically disable the link on the NIC's port.
171 * If enabled, (after link down request from the OS)
172 * no link, traffic or led activity is possible on that port.
173 *
174 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA is set, the
175 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA must be explicitly forced
176 * to true and cannot be disabled by system admin at that time.
177 * The functionalities are exclusive in terms of configuration, but
178 * they also have similar behavior (allowing to disable physical
179 * link of the port), with following differences:
180 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and
181 * is supported by whole family of 7xx Intel Ethernet Controllers
182 * - TOTAL_PORT_SHUTDOWN_ENA may be enabled only before OS loads
183 * (in BIOS) only if motherboard's BIOS and NIC's FW has support of it
184 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought
185 * down by sending phy_type=0 to NIC's FW
186 * - when TOTAL_PORT_SHUTDOWN_ENA is used, phy_type is not altered,
187 * instead the link is being brought down by clearing
188 * bit (I40E_AQ_PHY_ENABLE_LINK) in abilities field of
189 * i40e_aq_set_phy_config structure
190 */
191 I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA,
192 I40E_FLAG_VF_VLAN_PRUNING_ENA,
193 I40E_PF_FLAGS_NBITS, /* must be last */
194};
195
196enum i40e_interrupt_policy {
197 I40E_INTERRUPT_BEST_CASE,
198 I40E_INTERRUPT_MEDIUM,
199 I40E_INTERRUPT_LOWEST
200};
201
202struct i40e_lump_tracking {
203 u16 num_entries;
204 u16 list[];
205#define I40E_PILE_VALID_BIT 0x8000
206#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
207};
208
209#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
210#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
211#define I40E_FDIR_BUFFER_FULL_MARGIN 10
212#define I40E_FDIR_BUFFER_HEAD_ROOM 32
213#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
214
215#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
216#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
217#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
218
219enum i40e_fd_stat_idx {
220 I40E_FD_STAT_ATR,
221 I40E_FD_STAT_SB,
222 I40E_FD_STAT_ATR_TUNNEL,
223 I40E_FD_STAT_PF_COUNT
224};
225#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
226#define I40E_FD_ATR_STAT_IDX(pf_id) \
227 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
228#define I40E_FD_SB_STAT_IDX(pf_id) \
229 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
230#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
231 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
232
233/* The following structure contains the data parsed from the user-defined
234 * field of the ethtool_rx_flow_spec structure.
235 */
236struct i40e_rx_flow_userdef {
237 bool flex_filter;
238 u16 flex_word;
239 u16 flex_offset;
240};
241
242struct i40e_fdir_filter {
243 struct hlist_node fdir_node;
244 /* filter ipnut set */
245 u8 flow_type;
246 u8 ipl4_proto;
247 /* TX packet view of src and dst */
248 __be32 dst_ip;
249 __be32 src_ip;
250 __be32 dst_ip6[4];
251 __be32 src_ip6[4];
252 __be16 src_port;
253 __be16 dst_port;
254 __be32 sctp_v_tag;
255
256 __be16 vlan_etype;
257 __be16 vlan_tag;
258 /* Flexible data to match within the packet payload */
259 __be16 flex_word;
260 u16 flex_offset;
261 bool flex_filter;
262
263 /* filter control */
264 u16 q_index;
265 u8 flex_off;
266 u8 pctype;
267 u16 dest_vsi;
268 u8 dest_ctl;
269 u8 fd_status;
270 u16 cnt_index;
271 u32 fd_id;
272};
273
274#define I40E_CLOUD_FIELD_OMAC BIT(0)
275#define I40E_CLOUD_FIELD_IMAC BIT(1)
276#define I40E_CLOUD_FIELD_IVLAN BIT(2)
277#define I40E_CLOUD_FIELD_TEN_ID BIT(3)
278#define I40E_CLOUD_FIELD_IIP BIT(4)
279
280#define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
281#define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
282#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
283 I40E_CLOUD_FIELD_IVLAN)
284#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
285 I40E_CLOUD_FIELD_TEN_ID)
286#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
287 I40E_CLOUD_FIELD_IMAC | \
288 I40E_CLOUD_FIELD_TEN_ID)
289#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
290 I40E_CLOUD_FIELD_IVLAN | \
291 I40E_CLOUD_FIELD_TEN_ID)
292#define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
293
294struct i40e_cloud_filter {
295 struct hlist_node cloud_node;
296 unsigned long cookie;
297 /* cloud filter input set follows */
298 u8 dst_mac[ETH_ALEN];
299 u8 src_mac[ETH_ALEN];
300 __be16 vlan_id;
301 u16 seid; /* filter control */
302 __be16 dst_port;
303 __be16 src_port;
304 u32 tenant_id;
305 union {
306 struct {
307 struct in_addr dst_ip;
308 struct in_addr src_ip;
309 } v4;
310 struct {
311 struct in6_addr dst_ip6;
312 struct in6_addr src_ip6;
313 } v6;
314 } ip;
315#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
316#define src_ipv6 ip.v6.src_ip6.s6_addr32
317#define dst_ipv4 ip.v4.dst_ip.s_addr
318#define src_ipv4 ip.v4.src_ip.s_addr
319 u16 n_proto; /* Ethernet Protocol */
320 u8 ip_proto; /* IPPROTO value */
321 u8 flags;
322#define I40E_CLOUD_TNL_TYPE_NONE 0xff
323 u8 tunnel_type;
324};
325
326#define I40E_DCB_PRIO_TYPE_STRICT 0
327#define I40E_DCB_PRIO_TYPE_ETS 1
328#define I40E_DCB_STRICT_PRIO_CREDITS 127
329/* DCB per TC information data structure */
330struct i40e_tc_info {
331 u16 qoffset; /* Queue offset from base queue */
332 u16 qcount; /* Total Queues */
333 u8 netdev_tc; /* Netdev TC index if netdev associated */
334};
335
336/* TC configuration data structure */
337struct i40e_tc_configuration {
338 u8 numtc; /* Total number of enabled TCs */
339 u8 enabled_tc; /* TC map */
340 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
341};
342
343#define I40E_UDP_PORT_INDEX_UNUSED 255
344struct i40e_udp_port_config {
345 /* AdminQ command interface expects port number in Host byte order */
346 u16 port;
347 u8 type;
348 u8 filter_index;
349};
350
351/* macros related to FLX_PIT */
352#define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
353 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
354 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
355#define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
356 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
357 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
358#define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
359 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
360 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
361#define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
362 I40E_FLEX_SET_FSIZE(fsize) | \
363 I40E_FLEX_SET_SRC_WORD(src))
364
365
366#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
367
368/* macros related to GLQF_ORT */
369#define I40E_ORT_SET_IDX(idx) (((idx) << \
370 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
371 I40E_GLQF_ORT_PIT_INDX_MASK)
372
373#define I40E_ORT_SET_COUNT(count) (((count) << \
374 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
375 I40E_GLQF_ORT_FIELD_CNT_MASK)
376
377#define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
378 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
379 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
380
381#define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
382 I40E_ORT_SET_COUNT(count) | \
383 I40E_ORT_SET_PAYLOAD(payload))
384
385#define I40E_L3_GLQF_ORT_IDX 34
386#define I40E_L4_GLQF_ORT_IDX 35
387
388/* Flex PIT register index */
389#define I40E_FLEX_PIT_IDX_START_L3 3
390#define I40E_FLEX_PIT_IDX_START_L4 6
391
392#define I40E_FLEX_PIT_TABLE_SIZE 3
393
394#define I40E_FLEX_DEST_UNUSED 63
395
396#define I40E_FLEX_INDEX_ENTRIES 8
397
398/* Flex MASK to disable all flexible entries */
399#define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
400 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
401 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
402 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
403
404#define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
405 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
406 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
407 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
408 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
409 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
410
411#define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
412 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
413 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
414 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
415 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
416 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
417
418struct i40e_flex_pit {
419 struct list_head list;
420 u16 src_offset;
421 u8 pit_index;
422};
423
424struct i40e_fwd_adapter {
425 struct net_device *netdev;
426 int bit_no;
427};
428
429struct i40e_channel {
430 struct list_head list;
431 bool initialized;
432 u8 type;
433 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
434 u16 stat_counter_idx;
435 u16 base_queue;
436 u16 num_queue_pairs; /* Requested by user */
437 u16 seid;
438
439 u8 enabled_tc;
440 struct i40e_aqc_vsi_properties_data info;
441
442 u64 max_tx_rate;
443 struct i40e_fwd_adapter *fwd;
444
445 /* track this channel belongs to which VSI */
446 struct i40e_vsi *parent_vsi;
447};
448
449struct i40e_ptp_pins_settings;
450
451static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
452{
453 return !!ch->fwd;
454}
455
456static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
457{
458 if (i40e_is_channel_macvlan(ch))
459 return ch->fwd->netdev->dev_addr;
460 else
461 return NULL;
462}
463
464/* struct that defines the Ethernet device */
465struct i40e_pf {
466 struct pci_dev *pdev;
467 struct devlink_port devlink_port;
468 struct i40e_hw hw;
469 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
470 struct msix_entry *msix_entries;
471
472 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
473 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
474 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
475 u16 num_req_vfs; /* num VFs requested for this PF */
476 u16 num_vf_qps; /* num queue pairs per VF */
477 u16 num_lan_qps; /* num lan queues this PF has set up */
478 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
479 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
480 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
481 int iwarp_base_vector;
482 int queues_left; /* queues left unclaimed */
483 u16 alloc_rss_size; /* allocated RSS queues */
484 u16 rss_size_max; /* HW defined max RSS queues */
485 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
486 u16 num_alloc_vsi; /* num VSIs this driver supports */
487 bool wol_en;
488
489 struct hlist_head fdir_filter_list;
490 u16 fdir_pf_active_filters;
491 unsigned long fd_flush_timestamp;
492 u32 fd_flush_cnt;
493 u32 fd_add_err;
494 u32 fd_atr_cnt;
495
496 /* Book-keeping of side-band filter count per flow-type.
497 * This is used to detect and handle input set changes for
498 * respective flow-type.
499 */
500 u16 fd_tcp4_filter_cnt;
501 u16 fd_udp4_filter_cnt;
502 u16 fd_sctp4_filter_cnt;
503 u16 fd_ip4_filter_cnt;
504
505 u16 fd_tcp6_filter_cnt;
506 u16 fd_udp6_filter_cnt;
507 u16 fd_sctp6_filter_cnt;
508 u16 fd_ip6_filter_cnt;
509
510 /* Flexible filter table values that need to be programmed into
511 * hardware, which expects L3 and L4 to be programmed separately. We
512 * need to ensure that the values are in ascended order and don't have
513 * duplicates, so we track each L3 and L4 values in separate lists.
514 */
515 struct list_head l3_flex_pit_list;
516 struct list_head l4_flex_pit_list;
517
518 struct udp_tunnel_nic_shared udp_tunnel_shared;
519 struct udp_tunnel_nic_info udp_tunnel_nic;
520
521 struct hlist_head cloud_filter_list;
522 u16 num_cloud_filters;
523
524 u16 rx_itr_default;
525 u16 tx_itr_default;
526 u32 msg_enable;
527 char int_name[I40E_INT_NAME_STR_LEN];
528 unsigned long service_timer_period;
529 unsigned long service_timer_previous;
530 struct timer_list service_timer;
531 struct work_struct service_task;
532
533 DECLARE_BITMAP(flags, I40E_PF_FLAGS_NBITS);
534 struct i40e_client_instance *cinst;
535 bool stat_offsets_loaded;
536 struct i40e_hw_port_stats stats;
537 struct i40e_hw_port_stats stats_offsets;
538 u32 tx_timeout_count;
539 u32 tx_timeout_recovery_level;
540 unsigned long tx_timeout_last_recovery;
541 u32 hw_csum_rx_error;
542 u32 led_status;
543 u16 corer_count; /* Core reset count */
544 u16 globr_count; /* Global reset count */
545 u16 empr_count; /* EMP reset count */
546 u16 pfr_count; /* PF reset count */
547 u16 sw_int_count; /* SW interrupt count */
548
549 struct mutex switch_mutex;
550 u16 lan_vsi; /* our default LAN VSI */
551 u16 lan_veb; /* initial relay, if exists */
552#define I40E_NO_VEB 0xffff
553#define I40E_NO_VSI 0xffff
554 u16 next_vsi; /* Next unallocated VSI - 0-based! */
555 struct i40e_vsi **vsi;
556 struct i40e_veb *veb[I40E_MAX_VEB];
557
558 struct i40e_lump_tracking *qp_pile;
559 struct i40e_lump_tracking *irq_pile;
560
561 /* switch config info */
562 u16 main_vsi_seid;
563 u16 mac_seid;
564#ifdef CONFIG_DEBUG_FS
565 struct dentry *i40e_dbg_pf;
566#endif /* CONFIG_DEBUG_FS */
567 bool cur_promisc;
568
569 /* sr-iov config info */
570 struct i40e_vf *vf;
571 int num_alloc_vfs; /* actual number of VFs allocated */
572 u32 vf_aq_requests;
573 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
574
575 /* DCBx/DCBNL capability for PF that indicates
576 * whether DCBx is managed by firmware or host
577 * based agent (LLDPAD). Also, indicates what
578 * flavor of DCBx protocol (IEEE/CEE) is supported
579 * by the device. For now we're supporting IEEE
580 * mode only.
581 */
582 u16 dcbx_cap;
583
584 struct i40e_filter_control_settings filter_settings;
585 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
586 struct i40e_dcbx_config tmp_cfg;
587
588/* GPIO defines used by PTP */
589#define I40E_SDP3_2 18
590#define I40E_SDP3_3 19
591#define I40E_GPIO_4 20
592#define I40E_LED2_0 26
593#define I40E_LED2_1 27
594#define I40E_LED3_0 28
595#define I40E_LED3_1 29
596#define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
597 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
598#define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
599 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
600#define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
601 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
602#define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
603 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
604#define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2)
605#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
606 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
607#define I40E_GLGEN_GPIO_CTL_DIR_OUT \
608 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
609#define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
610 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
611#define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
612 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
613#define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
614 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
615#define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
616 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
617#define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
618 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
619#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
620 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
621#define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
622 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
623 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
624 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
625#define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
626 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
627 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
628 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
629#define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
630 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
631 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
632 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
633 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
634#define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
635 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
636 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
637 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
638 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
639#define I40E_GLGEN_GPIO_CTL_LED_INIT \
640 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
641 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
642 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
643 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
644 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
645 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
646#define I40E_PRTTSYN_AUX_1_INSTNT \
647 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
648#define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
649 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
650#define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
651#define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
652 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
653#define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */
654#define I40E_PTP_2_SEC_DELAY 2
655
656 struct ptp_clock *ptp_clock;
657 struct ptp_clock_info ptp_caps;
658 struct sk_buff *ptp_tx_skb;
659 unsigned long ptp_tx_start;
660 struct hwtstamp_config tstamp_config;
661 struct timespec64 ptp_prev_hw_time;
662 struct work_struct ptp_extts0_work;
663 ktime_t ptp_reset_start;
664 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
665 u32 ptp_adj_mult;
666 u32 tx_hwtstamp_timeouts;
667 u32 tx_hwtstamp_skipped;
668 u32 rx_hwtstamp_cleared;
669 u32 latch_event_flags;
670 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
671 unsigned long latch_events[4];
672 bool ptp_tx;
673 bool ptp_rx;
674 struct i40e_ptp_pins_settings *ptp_pins;
675 u16 rss_table_size; /* HW RSS table size */
676 u32 max_bw;
677 u32 min_bw;
678
679 u32 ioremap_len;
680 u32 fd_inv;
681 u16 phy_led_val;
682
683 u16 last_sw_conf_flags;
684 u16 last_sw_conf_valid_flags;
685 /* List to keep previous DDP profiles to be rolled back in the future */
686 struct list_head ddp_old_prof;
687};
688
689/**
690 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
691 * @macaddr: the MAC Address as the base key
692 *
693 * Simply copies the address and returns it as a u64 for hashing
694 **/
695static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
696{
697 u64 key = 0;
698
699 ether_addr_copy((u8 *)&key, macaddr);
700 return key;
701}
702
703enum i40e_filter_state {
704 I40E_FILTER_INVALID = 0, /* Invalid state */
705 I40E_FILTER_NEW, /* New, not sent to FW yet */
706 I40E_FILTER_ACTIVE, /* Added to switch by FW */
707 I40E_FILTER_FAILED, /* Rejected by FW */
708 I40E_FILTER_REMOVE, /* To be removed */
709/* There is no 'removed' state; the filter struct is freed */
710};
711struct i40e_mac_filter {
712 struct hlist_node hlist;
713 u8 macaddr[ETH_ALEN];
714#define I40E_VLAN_ANY -1
715 s16 vlan;
716 enum i40e_filter_state state;
717};
718
719/* Wrapper structure to keep track of filters while we are preparing to send
720 * firmware commands. We cannot send firmware commands while holding a
721 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
722 * a separate structure, which will track the state change and update the real
723 * filter while under lock. We can't simply hold the filters in a separate
724 * list, as this opens a window for a race condition when adding new MAC
725 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
726 */
727struct i40e_new_mac_filter {
728 struct hlist_node hlist;
729 struct i40e_mac_filter *f;
730
731 /* Track future changes to state separately */
732 enum i40e_filter_state state;
733};
734
735struct i40e_veb {
736 struct i40e_pf *pf;
737 u16 idx;
738 u16 veb_idx; /* index of VEB parent */
739 u16 seid;
740 u16 uplink_seid;
741 u16 stats_idx; /* index of VEB parent */
742 u8 enabled_tc;
743 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
744 u16 flags;
745 u16 bw_limit;
746 u8 bw_max_quanta;
747 bool is_abs_credits;
748 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
749 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
750 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
751 struct kobject *kobj;
752 bool stat_offsets_loaded;
753 struct i40e_eth_stats stats;
754 struct i40e_eth_stats stats_offsets;
755 struct i40e_veb_tc_stats tc_stats;
756 struct i40e_veb_tc_stats tc_stats_offsets;
757};
758
759/* struct that defines a VSI, associated with a dev */
760struct i40e_vsi {
761 struct net_device *netdev;
762 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
763 bool netdev_registered;
764 bool stat_offsets_loaded;
765
766 u32 current_netdev_flags;
767 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
768#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
769#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
770 unsigned long flags;
771
772 /* Per VSI lock to protect elements/hash (MAC filter) */
773 spinlock_t mac_filter_hash_lock;
774 /* Fixed size hash table with 2^8 buckets for MAC filters */
775 DECLARE_HASHTABLE(mac_filter_hash, 8);
776 bool has_vlan_filter;
777
778 /* VSI stats */
779 struct rtnl_link_stats64 net_stats;
780 struct rtnl_link_stats64 net_stats_offsets;
781 struct i40e_eth_stats eth_stats;
782 struct i40e_eth_stats eth_stats_offsets;
783 u64 tx_restart;
784 u64 tx_busy;
785 u64 tx_linearize;
786 u64 tx_force_wb;
787 u64 tx_stopped;
788 u64 rx_buf_failed;
789 u64 rx_page_failed;
790 u64 rx_page_reuse;
791 u64 rx_page_alloc;
792 u64 rx_page_waive;
793 u64 rx_page_busy;
794
795 /* These are containers of ring pointers, allocated at run-time */
796 struct i40e_ring **rx_rings;
797 struct i40e_ring **tx_rings;
798 struct i40e_ring **xdp_rings; /* XDP Tx rings */
799
800 u32 active_filters;
801 u32 promisc_threshold;
802
803 u16 work_limit;
804 u16 int_rate_limit; /* value in usecs */
805
806 u16 rss_table_size; /* HW RSS table size */
807 u16 rss_size; /* Allocated RSS queues */
808 u8 *rss_hkey_user; /* User configured hash keys */
809 u8 *rss_lut_user; /* User configured lookup table entries */
810
811
812 u16 max_frame;
813 u16 rx_buf_len;
814
815 struct bpf_prog *xdp_prog;
816
817 /* List of q_vectors allocated to this VSI */
818 struct i40e_q_vector **q_vectors;
819 int num_q_vectors;
820 int base_vector;
821 bool irqs_ready;
822
823 u16 seid; /* HW index of this VSI (absolute index) */
824 u16 id; /* VSI number */
825 u16 uplink_seid;
826
827 u16 base_queue; /* vsi's first queue in hw array */
828 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
829 u16 req_queue_pairs; /* User requested queue pairs */
830 u16 num_queue_pairs; /* Used tx and rx pairs */
831 u16 num_tx_desc;
832 u16 num_rx_desc;
833 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
834 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
835
836 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
837 struct i40e_tc_configuration tc_config;
838 struct i40e_aqc_vsi_properties_data info;
839
840 /* VSI BW limit (absolute across all TCs) */
841 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
842 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
843
844 /* Relative TC credits across VSIs */
845 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
846 /* TC BW limit credits within VSI */
847 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
848 /* TC BW limit max quanta within VSI */
849 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
850
851 struct i40e_pf *back; /* Backreference to associated PF */
852 u16 idx; /* index in pf->vsi[] */
853 u16 veb_idx; /* index of VEB parent */
854 struct kobject *kobj; /* sysfs object */
855 bool current_isup; /* Sync 'link up' logging */
856 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
857
858 /* channel specific fields */
859 u16 cnt_q_avail; /* num of queues available for channel usage */
860 u16 orig_rss_size;
861 u16 current_rss_size;
862 bool reconfig_rss;
863
864 u16 next_base_queue; /* next queue to be used for channel setup */
865
866 struct list_head ch_list;
867 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
868
869 /* macvlan fields */
870#define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
871#define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
872 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
873 struct list_head macvlan_list;
874 int macvlan_cnt;
875
876 void *priv; /* client driver data reference. */
877
878 /* VSI specific handlers */
879 irqreturn_t (*irq_handler)(int irq, void *data);
880
881 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
882} ____cacheline_internodealigned_in_smp;
883
884struct i40e_netdev_priv {
885 struct i40e_vsi *vsi;
886};
887
888extern struct ida i40e_client_ida;
889
890/* struct that defines an interrupt vector */
891struct i40e_q_vector {
892 struct i40e_vsi *vsi;
893
894 u16 v_idx; /* index in the vsi->q_vector array. */
895 u16 reg_idx; /* register index of the interrupt */
896
897 struct napi_struct napi;
898
899 struct i40e_ring_container rx;
900 struct i40e_ring_container tx;
901
902 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
903 u8 num_ringpairs; /* total number of ring pairs in vector */
904
905 cpumask_t affinity_mask;
906 struct irq_affinity_notify affinity_notify;
907
908 struct rcu_head rcu; /* to avoid race with update stats on free */
909 char name[I40E_INT_NAME_STR_LEN];
910 bool arm_wb_state;
911 int irq_num; /* IRQ assigned to this q_vector */
912} ____cacheline_internodealigned_in_smp;
913
914/* lan device */
915struct i40e_device {
916 struct list_head list;
917 struct i40e_pf *pf;
918};
919
920/**
921 * i40e_info_nvm_ver - format the NVM version string
922 * @hw: ptr to the hardware info
923 * @buf: string buffer to store
924 * @len: buffer size
925 *
926 * Formats NVM version string as:
927 * <gen>.<snap>.<release> when eetrackid == I40E_OEM_EETRACK_ID
928 * <nvm_major>.<nvm_minor> otherwise
929 **/
930static inline void i40e_info_nvm_ver(struct i40e_hw *hw, char *buf, size_t len)
931{
932 struct i40e_nvm_info *nvm = &hw->nvm;
933
934 if (nvm->eetrack == I40E_OEM_EETRACK_ID) {
935 u32 full_ver = nvm->oem_ver;
936 u8 gen, snap;
937 u16 release;
938
939 gen = FIELD_GET(I40E_OEM_GEN_MASK, full_ver);
940 snap = FIELD_GET(I40E_OEM_SNAP_MASK, full_ver);
941 release = FIELD_GET(I40E_OEM_RELEASE_MASK, full_ver);
942 snprintf(buf, len, "%x.%x.%x", gen, snap, release);
943 } else {
944 u8 major, minor;
945
946 major = FIELD_GET(I40E_NVM_VERSION_HI_MASK, nvm->version);
947 minor = FIELD_GET(I40E_NVM_VERSION_LO_MASK, nvm->version);
948 snprintf(buf, len, "%x.%02x", major, minor);
949 }
950}
951
952/**
953 * i40e_info_eetrack - format the EETrackID string
954 * @hw: ptr to the hardware info
955 * @buf: string buffer to store
956 * @len: buffer size
957 *
958 * Returns hexadecimally formated EETrackID if it is
959 * different from I40E_OEM_EETRACK_ID or empty string.
960 **/
961static inline void i40e_info_eetrack(struct i40e_hw *hw, char *buf, size_t len)
962{
963 struct i40e_nvm_info *nvm = &hw->nvm;
964
965 buf[0] = '\0';
966 if (nvm->eetrack != I40E_OEM_EETRACK_ID)
967 snprintf(buf, len, "0x%08x", nvm->eetrack);
968}
969
970/**
971 * i40e_info_civd_ver - format the NVM version strings
972 * @hw: ptr to the hardware info
973 * @buf: string buffer to store
974 * @len: buffer size
975 *
976 * Returns formated combo image version if adapter's EETrackID is
977 * different from I40E_OEM_EETRACK_ID or empty string.
978 **/
979static inline void i40e_info_civd_ver(struct i40e_hw *hw, char *buf, size_t len)
980{
981 struct i40e_nvm_info *nvm = &hw->nvm;
982
983 buf[0] = '\0';
984 if (nvm->eetrack != I40E_OEM_EETRACK_ID) {
985 u32 full_ver = nvm->oem_ver;
986 u8 major, minor;
987 u16 build;
988
989 major = FIELD_GET(I40E_OEM_VER_MASK, full_ver);
990 build = FIELD_GET(I40E_OEM_VER_BUILD_MASK, full_ver);
991 minor = FIELD_GET(I40E_OEM_VER_PATCH_MASK, full_ver);
992 snprintf(buf, len, "%d.%d.%d", major, build, minor);
993 }
994}
995
996/**
997 * i40e_nvm_version_str - format the NVM version strings
998 * @hw: ptr to the hardware info
999 * @buf: string buffer to store
1000 * @len: buffer size
1001 **/
1002static inline char *i40e_nvm_version_str(struct i40e_hw *hw, char *buf,
1003 size_t len)
1004{
1005 char ver[16] = " ";
1006
1007 /* Get NVM version */
1008 i40e_info_nvm_ver(hw, buf, len);
1009
1010 /* Append EETrackID if provided */
1011 i40e_info_eetrack(hw, &ver[1], sizeof(ver) - 1);
1012 if (strlen(ver) > 1)
1013 strlcat(buf, ver, len);
1014
1015 /* Append combo image version if provided */
1016 i40e_info_civd_ver(hw, &ver[1], sizeof(ver) - 1);
1017 if (strlen(ver) > 1)
1018 strlcat(buf, ver, len);
1019
1020 return buf;
1021}
1022
1023/**
1024 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1025 * @netdev: the corresponding netdev
1026 *
1027 * Return the PF struct for the given netdev
1028 **/
1029static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1030{
1031 struct i40e_netdev_priv *np = netdev_priv(netdev);
1032 struct i40e_vsi *vsi = np->vsi;
1033
1034 return vsi->back;
1035}
1036
1037static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1038 irqreturn_t (*irq_handler)(int, void *))
1039{
1040 vsi->irq_handler = irq_handler;
1041}
1042
1043/**
1044 * i40e_get_fd_cnt_all - get the total FD filter space available
1045 * @pf: pointer to the PF struct
1046 **/
1047static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1048{
1049 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1050}
1051
1052/**
1053 * i40e_read_fd_input_set - reads value of flow director input set register
1054 * @pf: pointer to the PF struct
1055 * @addr: register addr
1056 *
1057 * This function reads value of flow director input set register
1058 * specified by 'addr' (which is specific to flow-type)
1059 **/
1060static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1061{
1062 u64 val;
1063
1064 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1065 val <<= 32;
1066 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1067
1068 return val;
1069}
1070
1071/**
1072 * i40e_write_fd_input_set - writes value into flow director input set register
1073 * @pf: pointer to the PF struct
1074 * @addr: register addr
1075 * @val: value to be written
1076 *
1077 * This function writes specified value to the register specified by 'addr'.
1078 * This register is input set register based on flow-type.
1079 **/
1080static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1081 u16 addr, u64 val)
1082{
1083 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1084 (u32)(val >> 32));
1085 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1086 (u32)(val & 0xFFFFFFFFULL));
1087}
1088
1089/**
1090 * i40e_get_pf_count - get PCI PF count.
1091 * @hw: pointer to a hw.
1092 *
1093 * Reports the function number of the highest PCI physical
1094 * function plus 1 as it is loaded from the NVM.
1095 *
1096 * Return: PCI PF count.
1097 **/
1098static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1099{
1100 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1101 rd32(hw, I40E_GLGEN_PCIFCNCNT));
1102}
1103
1104/* needed by i40e_ethtool.c */
1105int i40e_up(struct i40e_vsi *vsi);
1106void i40e_down(struct i40e_vsi *vsi);
1107extern const char i40e_driver_name[];
1108void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1109void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1110int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1111int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1112void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1113 u16 rss_table_size, u16 rss_size);
1114struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1115/**
1116 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1117 * @pf: PF to search for VSI
1118 * @type: Value indicating type of VSI we are looking for
1119 **/
1120static inline struct i40e_vsi *
1121i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1122{
1123 int i;
1124
1125 for (i = 0; i < pf->num_alloc_vsi; i++) {
1126 struct i40e_vsi *vsi = pf->vsi[i];
1127
1128 if (vsi && vsi->type == type)
1129 return vsi;
1130 }
1131
1132 return NULL;
1133}
1134void i40e_update_stats(struct i40e_vsi *vsi);
1135void i40e_update_veb_stats(struct i40e_veb *veb);
1136void i40e_update_eth_stats(struct i40e_vsi *vsi);
1137struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1138int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1139 bool printconfig);
1140
1141int i40e_add_del_fdir(struct i40e_vsi *vsi,
1142 struct i40e_fdir_filter *input, bool add);
1143void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1144u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1145u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1146u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1147u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1148bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1149void i40e_set_ethtool_ops(struct net_device *netdev);
1150struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1151 const u8 *macaddr, s16 vlan);
1152void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1153void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1154int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1155struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1156 u16 uplink, u32 param1);
1157int i40e_vsi_release(struct i40e_vsi *vsi);
1158void i40e_service_event_schedule(struct i40e_pf *pf);
1159void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1160 u8 *msg, u16 len);
1161
1162int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1163 bool enable);
1164int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1165int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1166void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1167void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1168int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1169int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1170struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1171 u16 downlink_seid, u8 enabled_tc);
1172void i40e_veb_release(struct i40e_veb *veb);
1173
1174int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1175int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1176void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1177void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1178void i40e_pf_reset_stats(struct i40e_pf *pf);
1179#ifdef CONFIG_DEBUG_FS
1180void i40e_dbg_pf_init(struct i40e_pf *pf);
1181void i40e_dbg_pf_exit(struct i40e_pf *pf);
1182void i40e_dbg_init(void);
1183void i40e_dbg_exit(void);
1184#else
1185static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1186static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1187static inline void i40e_dbg_init(void) {}
1188static inline void i40e_dbg_exit(void) {}
1189#endif /* CONFIG_DEBUG_FS*/
1190/* needed by client drivers */
1191int i40e_lan_add_device(struct i40e_pf *pf);
1192int i40e_lan_del_device(struct i40e_pf *pf);
1193void i40e_client_subtask(struct i40e_pf *pf);
1194void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1195void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1196void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1197void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1198void i40e_client_update_msix_info(struct i40e_pf *pf);
1199int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1200/**
1201 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1202 * @vsi: pointer to a vsi
1203 * @vector: enable a particular Hw Interrupt vector, without base_vector
1204 **/
1205static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1206{
1207 struct i40e_pf *pf = vsi->back;
1208 struct i40e_hw *hw = &pf->hw;
1209 u32 val;
1210
1211 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1212 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1213 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1214 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1215 /* skip the flush */
1216}
1217
1218void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1219void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1220int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1221int i40e_open(struct net_device *netdev);
1222int i40e_close(struct net_device *netdev);
1223int i40e_vsi_open(struct i40e_vsi *vsi);
1224void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1225int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1226int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1227void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1228void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1229struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1230 const u8 *macaddr);
1231int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1232bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1233int i40e_count_filters(struct i40e_vsi *vsi);
1234struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1235void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1236static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1237{
1238 return test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags);
1239}
1240
1241#ifdef CONFIG_I40E_DCB
1242void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1243 struct i40e_dcbx_config *old_cfg,
1244 struct i40e_dcbx_config *new_cfg);
1245void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1246void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1247bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1248 struct i40e_dcbx_config *old_cfg,
1249 struct i40e_dcbx_config *new_cfg);
1250int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1251int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1252#endif /* CONFIG_I40E_DCB */
1253void i40e_ptp_rx_hang(struct i40e_pf *pf);
1254void i40e_ptp_tx_hang(struct i40e_pf *pf);
1255void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1256void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1257void i40e_ptp_set_increment(struct i40e_pf *pf);
1258int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1259int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1260void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1261void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1262void i40e_ptp_init(struct i40e_pf *pf);
1263void i40e_ptp_stop(struct i40e_pf *pf);
1264int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1265int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1266int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1267int i40e_get_partition_bw_setting(struct i40e_pf *pf);
1268int i40e_set_partition_bw_setting(struct i40e_pf *pf);
1269int i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1270void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1271
1272void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags);
1273
1274static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1275{
1276 return !!READ_ONCE(vsi->xdp_prog);
1277}
1278
1279int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1280int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1281int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1282 struct i40e_cloud_filter *filter,
1283 bool add);
1284int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1285 struct i40e_cloud_filter *filter,
1286 bool add);
1287
1288/**
1289 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1290 * @pf: pointer to a pf.
1291 *
1292 * Check and return state of flag I40E_FLAG_TC_MQPRIO.
1293 *
1294 * Return: true/false if I40E_FLAG_TC_MQPRIO is set or not
1295 **/
1296static inline bool i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)
1297{
1298 return test_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags);
1299}
1300
1301/**
1302 * i40e_hw_to_pf - get pf pointer from the hardware structure
1303 * @hw: pointer to the device HW structure
1304 **/
1305static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw)
1306{
1307 return container_of(hw, struct i40e_pf, hw);
1308}
1309
1310struct device *i40e_hw_to_dev(struct i40e_hw *hw);
1311
1312#endif /* _I40E_H_ */