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1/*
2 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
3 *
4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29#include <linux/module.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/usb/usb_phy_generic.h>
36
37#include <mach/da8xx.h>
38#include <linux/platform_data/usb-davinci.h>
39
40#include "musb_core.h"
41
42/*
43 * DA8XX specific definitions
44 */
45
46/* USB 2.0 OTG module registers */
47#define DA8XX_USB_REVISION_REG 0x00
48#define DA8XX_USB_CTRL_REG 0x04
49#define DA8XX_USB_STAT_REG 0x08
50#define DA8XX_USB_EMULATION_REG 0x0c
51#define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
52#define DA8XX_USB_AUTOREQ_REG 0x14
53#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
54#define DA8XX_USB_TEARDOWN_REG 0x1c
55#define DA8XX_USB_INTR_SRC_REG 0x20
56#define DA8XX_USB_INTR_SRC_SET_REG 0x24
57#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
58#define DA8XX_USB_INTR_MASK_REG 0x2c
59#define DA8XX_USB_INTR_MASK_SET_REG 0x30
60#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
61#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
62#define DA8XX_USB_END_OF_INTR_REG 0x3c
63#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
64
65/* Control register bits */
66#define DA8XX_SOFT_RESET_MASK 1
67
68#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
69#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
70
71/* USB interrupt register bits */
72#define DA8XX_INTR_USB_SHIFT 16
73#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
74 /* interrupts and DRVVBUS interrupt */
75#define DA8XX_INTR_DRVVBUS 0x100
76#define DA8XX_INTR_RX_SHIFT 8
77#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
78#define DA8XX_INTR_TX_SHIFT 0
79#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
80
81#define DA8XX_MENTOR_CORE_OFFSET 0x400
82
83#define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
84
85struct da8xx_glue {
86 struct device *dev;
87 struct platform_device *musb;
88 struct platform_device *phy;
89 struct clk *clk;
90};
91
92/*
93 * REVISIT (PM): we should be able to keep the PHY in low power mode most
94 * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
95 * and, when in host mode, autosuspending idle root ports... PHY_PLLON
96 * (overriding SUSPENDM?) then likely needs to stay off.
97 */
98
99static inline void phy_on(void)
100{
101 u32 cfgchip2 = __raw_readl(CFGCHIP2);
102
103 /*
104 * Start the on-chip PHY and its PLL.
105 */
106 cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
107 cfgchip2 |= CFGCHIP2_PHY_PLLON;
108 __raw_writel(cfgchip2, CFGCHIP2);
109
110 pr_info("Waiting for USB PHY clock good...\n");
111 while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
112 cpu_relax();
113}
114
115static inline void phy_off(void)
116{
117 u32 cfgchip2 = __raw_readl(CFGCHIP2);
118
119 /*
120 * Ensure that USB 1.1 reference clock is not being sourced from
121 * USB 2.0 PHY. Otherwise do not power down the PHY.
122 */
123 if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
124 (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
125 pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
126 "can't power it down\n");
127 return;
128 }
129
130 /*
131 * Power down the on-chip PHY.
132 */
133 cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
134 __raw_writel(cfgchip2, CFGCHIP2);
135}
136
137/*
138 * Because we don't set CTRL.UINT, it's "important" to:
139 * - not read/write INTRUSB/INTRUSBE (except during
140 * initial setup, as a workaround);
141 * - use INTSET/INTCLR instead.
142 */
143
144/**
145 * da8xx_musb_enable - enable interrupts
146 */
147static void da8xx_musb_enable(struct musb *musb)
148{
149 void __iomem *reg_base = musb->ctrl_base;
150 u32 mask;
151
152 /* Workaround: setup IRQs through both register sets. */
153 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
154 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
155 DA8XX_INTR_USB_MASK;
156 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
157
158 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
159 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
160 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
161}
162
163/**
164 * da8xx_musb_disable - disable HDRC and flush interrupts
165 */
166static void da8xx_musb_disable(struct musb *musb)
167{
168 void __iomem *reg_base = musb->ctrl_base;
169
170 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
171 DA8XX_INTR_USB_MASK |
172 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
173 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
174 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
175}
176
177#define portstate(stmt) stmt
178
179static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
180{
181 WARN_ON(is_on && is_peripheral_active(musb));
182}
183
184#define POLL_SECONDS 2
185
186static struct timer_list otg_workaround;
187
188static void otg_timer(unsigned long _musb)
189{
190 struct musb *musb = (void *)_musb;
191 void __iomem *mregs = musb->mregs;
192 u8 devctl;
193 unsigned long flags;
194
195 /*
196 * We poll because DaVinci's won't expose several OTG-critical
197 * status change events (from the transceiver) otherwise.
198 */
199 devctl = musb_readb(mregs, MUSB_DEVCTL);
200 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
201 usb_otg_state_string(musb->xceiv->otg->state));
202
203 spin_lock_irqsave(&musb->lock, flags);
204 switch (musb->xceiv->otg->state) {
205 case OTG_STATE_A_WAIT_BCON:
206 devctl &= ~MUSB_DEVCTL_SESSION;
207 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
208
209 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
210 if (devctl & MUSB_DEVCTL_BDEVICE) {
211 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
212 MUSB_DEV_MODE(musb);
213 } else {
214 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
215 MUSB_HST_MODE(musb);
216 }
217 break;
218 case OTG_STATE_A_WAIT_VFALL:
219 /*
220 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
221 * RTL seems to mis-handle session "start" otherwise (or in
222 * our case "recover"), in routine "VBUS was valid by the time
223 * VBUSERR got reported during enumeration" cases.
224 */
225 if (devctl & MUSB_DEVCTL_VBUS) {
226 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
227 break;
228 }
229 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
230 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
231 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
232 break;
233 case OTG_STATE_B_IDLE:
234 /*
235 * There's no ID-changed IRQ, so we have no good way to tell
236 * when to switch to the A-Default state machine (by setting
237 * the DEVCTL.Session bit).
238 *
239 * Workaround: whenever we're in B_IDLE, try setting the
240 * session flag every few seconds. If it works, ID was
241 * grounded and we're now in the A-Default state machine.
242 *
243 * NOTE: setting the session flag is _supposed_ to trigger
244 * SRP but clearly it doesn't.
245 */
246 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
247 devctl = musb_readb(mregs, MUSB_DEVCTL);
248 if (devctl & MUSB_DEVCTL_BDEVICE)
249 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
250 else
251 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
252 break;
253 default:
254 break;
255 }
256 spin_unlock_irqrestore(&musb->lock, flags);
257}
258
259static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
260{
261 static unsigned long last_timer;
262
263 if (timeout == 0)
264 timeout = jiffies + msecs_to_jiffies(3);
265
266 /* Never idle if active, or when VBUS timeout is not set as host */
267 if (musb->is_active || (musb->a_wait_bcon == 0 &&
268 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
269 dev_dbg(musb->controller, "%s active, deleting timer\n",
270 usb_otg_state_string(musb->xceiv->otg->state));
271 del_timer(&otg_workaround);
272 last_timer = jiffies;
273 return;
274 }
275
276 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
277 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
278 return;
279 }
280 last_timer = timeout;
281
282 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
283 usb_otg_state_string(musb->xceiv->otg->state),
284 jiffies_to_msecs(timeout - jiffies));
285 mod_timer(&otg_workaround, timeout);
286}
287
288static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
289{
290 struct musb *musb = hci;
291 void __iomem *reg_base = musb->ctrl_base;
292 struct usb_otg *otg = musb->xceiv->otg;
293 unsigned long flags;
294 irqreturn_t ret = IRQ_NONE;
295 u32 status;
296
297 spin_lock_irqsave(&musb->lock, flags);
298
299 /*
300 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
301 * the Mentor registers (except for setup), use the TI ones and EOI.
302 */
303
304 /* Acknowledge and handle non-CPPI interrupts */
305 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
306 if (!status)
307 goto eoi;
308
309 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
310 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
311
312 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
313 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
314 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
315
316 /*
317 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
318 * DA8xx's missing ID change IRQ. We need an ID change IRQ to
319 * switch appropriately between halves of the OTG state machine.
320 * Managing DEVCTL.Session per Mentor docs requires that we know its
321 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
322 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
323 */
324 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
325 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
326 void __iomem *mregs = musb->mregs;
327 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
328 int err;
329
330 err = musb->int_usb & MUSB_INTR_VBUSERROR;
331 if (err) {
332 /*
333 * The Mentor core doesn't debounce VBUS as needed
334 * to cope with device connect current spikes. This
335 * means it's not uncommon for bus-powered devices
336 * to get VBUS errors during enumeration.
337 *
338 * This is a workaround, but newer RTL from Mentor
339 * seems to allow a better one: "re"-starting sessions
340 * without waiting for VBUS to stop registering in
341 * devctl.
342 */
343 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
344 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
345 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
346 WARNING("VBUS error workaround (delay coming)\n");
347 } else if (drvvbus) {
348 MUSB_HST_MODE(musb);
349 otg->default_a = 1;
350 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
351 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
352 del_timer(&otg_workaround);
353 } else {
354 musb->is_active = 0;
355 MUSB_DEV_MODE(musb);
356 otg->default_a = 0;
357 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
358 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
359 }
360
361 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
362 drvvbus ? "on" : "off",
363 usb_otg_state_string(musb->xceiv->otg->state),
364 err ? " ERROR" : "",
365 devctl);
366 ret = IRQ_HANDLED;
367 }
368
369 if (musb->int_tx || musb->int_rx || musb->int_usb)
370 ret |= musb_interrupt(musb);
371
372 eoi:
373 /* EOI needs to be written for the IRQ to be re-asserted. */
374 if (ret == IRQ_HANDLED || status)
375 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
376
377 /* Poll for ID change */
378 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
379 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
380
381 spin_unlock_irqrestore(&musb->lock, flags);
382
383 return ret;
384}
385
386static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
387{
388 u32 cfgchip2 = __raw_readl(CFGCHIP2);
389
390 cfgchip2 &= ~CFGCHIP2_OTGMODE;
391 switch (musb_mode) {
392 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
393 cfgchip2 |= CFGCHIP2_FORCE_HOST;
394 break;
395 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
396 cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
397 break;
398 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
399 cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
400 break;
401 default:
402 dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
403 }
404
405 __raw_writel(cfgchip2, CFGCHIP2);
406 return 0;
407}
408
409static int da8xx_musb_init(struct musb *musb)
410{
411 void __iomem *reg_base = musb->ctrl_base;
412 u32 rev;
413 int ret = -ENODEV;
414
415 musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
416
417 /* Returns zero if e.g. not clocked */
418 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
419 if (!rev)
420 goto fail;
421
422 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
423 if (IS_ERR_OR_NULL(musb->xceiv)) {
424 ret = -EPROBE_DEFER;
425 goto fail;
426 }
427
428 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
429
430 /* Reset the controller */
431 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
432
433 /* Start the on-chip PHY and its PLL. */
434 phy_on();
435
436 msleep(5);
437
438 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
439 pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
440 rev, __raw_readl(CFGCHIP2),
441 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
442
443 musb->isr = da8xx_musb_interrupt;
444 return 0;
445fail:
446 return ret;
447}
448
449static int da8xx_musb_exit(struct musb *musb)
450{
451 del_timer_sync(&otg_workaround);
452
453 phy_off();
454
455 usb_put_phy(musb->xceiv);
456
457 return 0;
458}
459
460static const struct musb_platform_ops da8xx_ops = {
461 .quirks = MUSB_DMA_CPPI | MUSB_INDEXED_EP,
462 .init = da8xx_musb_init,
463 .exit = da8xx_musb_exit,
464
465 .fifo_mode = 2,
466#ifdef CONFIG_USB_TI_CPPI_DMA
467 .dma_init = cppi_dma_controller_create,
468 .dma_exit = cppi_dma_controller_destroy,
469#endif
470 .enable = da8xx_musb_enable,
471 .disable = da8xx_musb_disable,
472
473 .set_mode = da8xx_musb_set_mode,
474 .try_idle = da8xx_musb_try_idle,
475
476 .set_vbus = da8xx_musb_set_vbus,
477};
478
479static const struct platform_device_info da8xx_dev_info = {
480 .name = "musb-hdrc",
481 .id = PLATFORM_DEVID_AUTO,
482 .dma_mask = DMA_BIT_MASK(32),
483};
484
485static int da8xx_probe(struct platform_device *pdev)
486{
487 struct resource musb_resources[2];
488 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
489 struct platform_device *musb;
490 struct da8xx_glue *glue;
491 struct platform_device_info pinfo;
492 struct clk *clk;
493
494 int ret = -ENOMEM;
495
496 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
497 if (!glue) {
498 dev_err(&pdev->dev, "failed to allocate glue context\n");
499 goto err0;
500 }
501
502 clk = clk_get(&pdev->dev, "usb20");
503 if (IS_ERR(clk)) {
504 dev_err(&pdev->dev, "failed to get clock\n");
505 ret = PTR_ERR(clk);
506 goto err3;
507 }
508
509 ret = clk_enable(clk);
510 if (ret) {
511 dev_err(&pdev->dev, "failed to enable clock\n");
512 goto err4;
513 }
514
515 glue->dev = &pdev->dev;
516 glue->clk = clk;
517
518 pdata->platform_ops = &da8xx_ops;
519
520 glue->phy = usb_phy_generic_register();
521 if (IS_ERR(glue->phy)) {
522 ret = PTR_ERR(glue->phy);
523 goto err5;
524 }
525 platform_set_drvdata(pdev, glue);
526
527 memset(musb_resources, 0x00, sizeof(*musb_resources) *
528 ARRAY_SIZE(musb_resources));
529
530 musb_resources[0].name = pdev->resource[0].name;
531 musb_resources[0].start = pdev->resource[0].start;
532 musb_resources[0].end = pdev->resource[0].end;
533 musb_resources[0].flags = pdev->resource[0].flags;
534
535 musb_resources[1].name = pdev->resource[1].name;
536 musb_resources[1].start = pdev->resource[1].start;
537 musb_resources[1].end = pdev->resource[1].end;
538 musb_resources[1].flags = pdev->resource[1].flags;
539
540 pinfo = da8xx_dev_info;
541 pinfo.parent = &pdev->dev;
542 pinfo.res = musb_resources;
543 pinfo.num_res = ARRAY_SIZE(musb_resources);
544 pinfo.data = pdata;
545 pinfo.size_data = sizeof(*pdata);
546
547 glue->musb = musb = platform_device_register_full(&pinfo);
548 if (IS_ERR(musb)) {
549 ret = PTR_ERR(musb);
550 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
551 goto err6;
552 }
553
554 return 0;
555
556err6:
557 usb_phy_generic_unregister(glue->phy);
558
559err5:
560 clk_disable(clk);
561
562err4:
563 clk_put(clk);
564
565err3:
566 kfree(glue);
567
568err0:
569 return ret;
570}
571
572static int da8xx_remove(struct platform_device *pdev)
573{
574 struct da8xx_glue *glue = platform_get_drvdata(pdev);
575
576 platform_device_unregister(glue->musb);
577 usb_phy_generic_unregister(glue->phy);
578 clk_disable(glue->clk);
579 clk_put(glue->clk);
580 kfree(glue);
581
582 return 0;
583}
584
585static struct platform_driver da8xx_driver = {
586 .probe = da8xx_probe,
587 .remove = da8xx_remove,
588 .driver = {
589 .name = "musb-da8xx",
590 },
591};
592
593MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
594MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
595MODULE_LICENSE("GPL v2");
596module_platform_driver(da8xx_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
4 *
5 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
6 *
7 * Based on the DaVinci "glue layer" code.
8 * Copyright (C) 2005-2006 by Texas Instruments
9 *
10 * DT support
11 * Copyright (c) 2016 Petr Kulhavy <petr@barix.com>
12 *
13 * This file is part of the Inventra Controller Driver for Linux.
14 */
15
16#include <linux/module.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/of_platform.h>
21#include <linux/phy/phy.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/usb/usb_phy_generic.h>
25
26#include "musb_core.h"
27
28/*
29 * DA8XX specific definitions
30 */
31
32/* USB 2.0 OTG module registers */
33#define DA8XX_USB_REVISION_REG 0x00
34#define DA8XX_USB_CTRL_REG 0x04
35#define DA8XX_USB_STAT_REG 0x08
36#define DA8XX_USB_EMULATION_REG 0x0c
37#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
38#define DA8XX_USB_INTR_SRC_REG 0x20
39#define DA8XX_USB_INTR_SRC_SET_REG 0x24
40#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
41#define DA8XX_USB_INTR_MASK_REG 0x2c
42#define DA8XX_USB_INTR_MASK_SET_REG 0x30
43#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
44#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
45#define DA8XX_USB_END_OF_INTR_REG 0x3c
46#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
47
48/* Control register bits */
49#define DA8XX_SOFT_RESET_MASK 1
50
51#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
52#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
53
54/* USB interrupt register bits */
55#define DA8XX_INTR_USB_SHIFT 16
56#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
57 /* interrupts and DRVVBUS interrupt */
58#define DA8XX_INTR_DRVVBUS 0x100
59#define DA8XX_INTR_RX_SHIFT 8
60#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
61#define DA8XX_INTR_TX_SHIFT 0
62#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
63
64#define DA8XX_MENTOR_CORE_OFFSET 0x400
65
66struct da8xx_glue {
67 struct device *dev;
68 struct platform_device *musb;
69 struct platform_device *usb_phy;
70 struct clk *clk;
71 struct phy *phy;
72};
73
74/*
75 * Because we don't set CTRL.UINT, it's "important" to:
76 * - not read/write INTRUSB/INTRUSBE (except during
77 * initial setup, as a workaround);
78 * - use INTSET/INTCLR instead.
79 */
80
81/**
82 * da8xx_musb_enable - enable interrupts
83 */
84static void da8xx_musb_enable(struct musb *musb)
85{
86 void __iomem *reg_base = musb->ctrl_base;
87 u32 mask;
88
89 /* Workaround: setup IRQs through both register sets. */
90 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
91 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
92 DA8XX_INTR_USB_MASK;
93 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
94
95 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
96 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
97 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
98}
99
100/**
101 * da8xx_musb_disable - disable HDRC and flush interrupts
102 */
103static void da8xx_musb_disable(struct musb *musb)
104{
105 void __iomem *reg_base = musb->ctrl_base;
106
107 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
108 DA8XX_INTR_USB_MASK |
109 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
110 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
111}
112
113#define portstate(stmt) stmt
114
115static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
116{
117 WARN_ON(is_on && is_peripheral_active(musb));
118}
119
120#define POLL_SECONDS 2
121
122static void otg_timer(struct timer_list *t)
123{
124 struct musb *musb = from_timer(musb, t, dev_timer);
125 void __iomem *mregs = musb->mregs;
126 u8 devctl;
127 unsigned long flags;
128
129 /*
130 * We poll because DaVinci's won't expose several OTG-critical
131 * status change events (from the transceiver) otherwise.
132 */
133 devctl = musb_readb(mregs, MUSB_DEVCTL);
134 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
135 usb_otg_state_string(musb->xceiv->otg->state));
136
137 spin_lock_irqsave(&musb->lock, flags);
138 switch (musb->xceiv->otg->state) {
139 case OTG_STATE_A_WAIT_BCON:
140 devctl &= ~MUSB_DEVCTL_SESSION;
141 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
142
143 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
144 if (devctl & MUSB_DEVCTL_BDEVICE) {
145 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
146 MUSB_DEV_MODE(musb);
147 } else {
148 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
149 MUSB_HST_MODE(musb);
150 }
151 break;
152 case OTG_STATE_A_WAIT_VFALL:
153 /*
154 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
155 * RTL seems to mis-handle session "start" otherwise (or in
156 * our case "recover"), in routine "VBUS was valid by the time
157 * VBUSERR got reported during enumeration" cases.
158 */
159 if (devctl & MUSB_DEVCTL_VBUS) {
160 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
161 break;
162 }
163 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
164 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
165 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
166 break;
167 case OTG_STATE_B_IDLE:
168 /*
169 * There's no ID-changed IRQ, so we have no good way to tell
170 * when to switch to the A-Default state machine (by setting
171 * the DEVCTL.Session bit).
172 *
173 * Workaround: whenever we're in B_IDLE, try setting the
174 * session flag every few seconds. If it works, ID was
175 * grounded and we're now in the A-Default state machine.
176 *
177 * NOTE: setting the session flag is _supposed_ to trigger
178 * SRP but clearly it doesn't.
179 */
180 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
181 devctl = musb_readb(mregs, MUSB_DEVCTL);
182 if (devctl & MUSB_DEVCTL_BDEVICE)
183 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
184 else
185 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
186 break;
187 default:
188 break;
189 }
190 spin_unlock_irqrestore(&musb->lock, flags);
191}
192
193static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
194{
195 static unsigned long last_timer;
196
197 if (timeout == 0)
198 timeout = jiffies + msecs_to_jiffies(3);
199
200 /* Never idle if active, or when VBUS timeout is not set as host */
201 if (musb->is_active || (musb->a_wait_bcon == 0 &&
202 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
203 dev_dbg(musb->controller, "%s active, deleting timer\n",
204 usb_otg_state_string(musb->xceiv->otg->state));
205 del_timer(&musb->dev_timer);
206 last_timer = jiffies;
207 return;
208 }
209
210 if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) {
211 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
212 return;
213 }
214 last_timer = timeout;
215
216 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
217 usb_otg_state_string(musb->xceiv->otg->state),
218 jiffies_to_msecs(timeout - jiffies));
219 mod_timer(&musb->dev_timer, timeout);
220}
221
222static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
223{
224 struct musb *musb = hci;
225 void __iomem *reg_base = musb->ctrl_base;
226 unsigned long flags;
227 irqreturn_t ret = IRQ_NONE;
228 u32 status;
229
230 spin_lock_irqsave(&musb->lock, flags);
231
232 /*
233 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
234 * the Mentor registers (except for setup), use the TI ones and EOI.
235 */
236
237 /* Acknowledge and handle non-CPPI interrupts */
238 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
239 if (!status)
240 goto eoi;
241
242 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
243 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
244
245 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
246 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
247 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
248
249 /*
250 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
251 * DA8xx's missing ID change IRQ. We need an ID change IRQ to
252 * switch appropriately between halves of the OTG state machine.
253 * Managing DEVCTL.Session per Mentor docs requires that we know its
254 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
255 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
256 */
257 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
258 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
259 void __iomem *mregs = musb->mregs;
260 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
261 int err;
262
263 err = musb->int_usb & MUSB_INTR_VBUSERROR;
264 if (err) {
265 /*
266 * The Mentor core doesn't debounce VBUS as needed
267 * to cope with device connect current spikes. This
268 * means it's not uncommon for bus-powered devices
269 * to get VBUS errors during enumeration.
270 *
271 * This is a workaround, but newer RTL from Mentor
272 * seems to allow a better one: "re"-starting sessions
273 * without waiting for VBUS to stop registering in
274 * devctl.
275 */
276 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
277 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
278 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
279 WARNING("VBUS error workaround (delay coming)\n");
280 } else if (drvvbus) {
281 MUSB_HST_MODE(musb);
282 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
283 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
284 del_timer(&musb->dev_timer);
285 } else if (!(musb->int_usb & MUSB_INTR_BABBLE)) {
286 /*
287 * When babble condition happens, drvvbus interrupt
288 * is also generated. Ignore this drvvbus interrupt
289 * and let babble interrupt handler recovers the
290 * controller; otherwise, the host-mode flag is lost
291 * due to the MUSB_DEV_MODE() call below and babble
292 * recovery logic will not be called.
293 */
294 musb->is_active = 0;
295 MUSB_DEV_MODE(musb);
296 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
297 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
298 }
299
300 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
301 drvvbus ? "on" : "off",
302 usb_otg_state_string(musb->xceiv->otg->state),
303 err ? " ERROR" : "",
304 devctl);
305 ret = IRQ_HANDLED;
306 }
307
308 if (musb->int_tx || musb->int_rx || musb->int_usb)
309 ret |= musb_interrupt(musb);
310
311 eoi:
312 /* EOI needs to be written for the IRQ to be re-asserted. */
313 if (ret == IRQ_HANDLED || status)
314 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
315
316 /* Poll for ID change */
317 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
318 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
319
320 spin_unlock_irqrestore(&musb->lock, flags);
321
322 return ret;
323}
324
325static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
326{
327 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
328 enum phy_mode phy_mode;
329
330 /*
331 * The PHY has some issues when it is forced in device or host mode.
332 * Unless the user request another mode, configure the PHY in OTG mode.
333 */
334 if (!musb->is_initialized)
335 return phy_set_mode(glue->phy, PHY_MODE_USB_OTG);
336
337 switch (musb_mode) {
338 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
339 phy_mode = PHY_MODE_USB_HOST;
340 break;
341 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
342 phy_mode = PHY_MODE_USB_DEVICE;
343 break;
344 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
345 phy_mode = PHY_MODE_USB_OTG;
346 break;
347 default:
348 return -EINVAL;
349 }
350
351 return phy_set_mode(glue->phy, phy_mode);
352}
353
354static int da8xx_musb_init(struct musb *musb)
355{
356 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
357 void __iomem *reg_base = musb->ctrl_base;
358 u32 rev;
359 int ret = -ENODEV;
360
361 musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
362
363 ret = clk_prepare_enable(glue->clk);
364 if (ret) {
365 dev_err(glue->dev, "failed to enable clock\n");
366 return ret;
367 }
368
369 /* Returns zero if e.g. not clocked */
370 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
371 if (!rev)
372 goto fail;
373
374 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
375 if (IS_ERR_OR_NULL(musb->xceiv)) {
376 ret = -EPROBE_DEFER;
377 goto fail;
378 }
379
380 timer_setup(&musb->dev_timer, otg_timer, 0);
381
382 /* Reset the controller */
383 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
384
385 /* Start the on-chip PHY and its PLL. */
386 ret = phy_init(glue->phy);
387 if (ret) {
388 dev_err(glue->dev, "Failed to init phy.\n");
389 goto fail;
390 }
391
392 ret = phy_power_on(glue->phy);
393 if (ret) {
394 dev_err(glue->dev, "Failed to power on phy.\n");
395 goto err_phy_power_on;
396 }
397
398 msleep(5);
399
400 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
401 pr_debug("DA8xx OTG revision %08x, control %02x\n", rev,
402 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
403
404 musb->isr = da8xx_musb_interrupt;
405 return 0;
406
407err_phy_power_on:
408 phy_exit(glue->phy);
409fail:
410 clk_disable_unprepare(glue->clk);
411 return ret;
412}
413
414static int da8xx_musb_exit(struct musb *musb)
415{
416 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
417
418 del_timer_sync(&musb->dev_timer);
419
420 phy_power_off(glue->phy);
421 phy_exit(glue->phy);
422 clk_disable_unprepare(glue->clk);
423
424 usb_put_phy(musb->xceiv);
425
426 return 0;
427}
428
429static inline u8 get_vbus_power(struct device *dev)
430{
431 struct regulator *vbus_supply;
432 int current_uA;
433
434 vbus_supply = regulator_get_optional(dev, "vbus");
435 if (IS_ERR(vbus_supply))
436 return 255;
437 current_uA = regulator_get_current_limit(vbus_supply);
438 regulator_put(vbus_supply);
439 if (current_uA <= 0 || current_uA > 510000)
440 return 255;
441 return current_uA / 1000 / 2;
442}
443
444#ifdef CONFIG_USB_TI_CPPI41_DMA
445static void da8xx_dma_controller_callback(struct dma_controller *c)
446{
447 struct musb *musb = c->musb;
448 void __iomem *reg_base = musb->ctrl_base;
449
450 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
451}
452
453static struct dma_controller *
454da8xx_dma_controller_create(struct musb *musb, void __iomem *base)
455{
456 struct dma_controller *controller;
457
458 controller = cppi41_dma_controller_create(musb, base);
459 if (IS_ERR_OR_NULL(controller))
460 return controller;
461
462 controller->dma_callback = da8xx_dma_controller_callback;
463
464 return controller;
465}
466#endif
467
468static const struct musb_platform_ops da8xx_ops = {
469 .quirks = MUSB_INDEXED_EP | MUSB_PRESERVE_SESSION |
470 MUSB_DMA_CPPI41 | MUSB_DA8XX,
471 .init = da8xx_musb_init,
472 .exit = da8xx_musb_exit,
473
474 .fifo_mode = 2,
475#ifdef CONFIG_USB_TI_CPPI41_DMA
476 .dma_init = da8xx_dma_controller_create,
477 .dma_exit = cppi41_dma_controller_destroy,
478#endif
479 .enable = da8xx_musb_enable,
480 .disable = da8xx_musb_disable,
481
482 .set_mode = da8xx_musb_set_mode,
483 .try_idle = da8xx_musb_try_idle,
484
485 .set_vbus = da8xx_musb_set_vbus,
486};
487
488static const struct platform_device_info da8xx_dev_info = {
489 .name = "musb-hdrc",
490 .id = PLATFORM_DEVID_AUTO,
491 .dma_mask = DMA_BIT_MASK(32),
492};
493
494static const struct musb_hdrc_config da8xx_config = {
495 .ram_bits = 10,
496 .num_eps = 5,
497 .multipoint = 1,
498};
499
500static struct of_dev_auxdata da8xx_auxdata_lookup[] = {
501 OF_DEV_AUXDATA("ti,da830-cppi41", 0x01e01000, "cppi41-dmaengine",
502 NULL),
503 {}
504};
505
506static int da8xx_probe(struct platform_device *pdev)
507{
508 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
509 struct da8xx_glue *glue;
510 struct platform_device_info pinfo;
511 struct clk *clk;
512 struct device_node *np = pdev->dev.of_node;
513 int ret;
514
515 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
516 if (!glue)
517 return -ENOMEM;
518
519 clk = devm_clk_get(&pdev->dev, NULL);
520 if (IS_ERR(clk)) {
521 dev_err(&pdev->dev, "failed to get clock\n");
522 return PTR_ERR(clk);
523 }
524
525 glue->phy = devm_phy_get(&pdev->dev, "usb-phy");
526 if (IS_ERR(glue->phy))
527 return dev_err_probe(&pdev->dev, PTR_ERR(glue->phy),
528 "failed to get phy\n");
529
530 glue->dev = &pdev->dev;
531 glue->clk = clk;
532
533 if (IS_ENABLED(CONFIG_OF) && np) {
534 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
535 if (!pdata)
536 return -ENOMEM;
537
538 pdata->config = &da8xx_config;
539 pdata->mode = musb_get_mode(&pdev->dev);
540 pdata->power = get_vbus_power(&pdev->dev);
541 }
542
543 pdata->platform_ops = &da8xx_ops;
544
545 glue->usb_phy = usb_phy_generic_register();
546 ret = PTR_ERR_OR_ZERO(glue->usb_phy);
547 if (ret) {
548 dev_err(&pdev->dev, "failed to register usb_phy\n");
549 return ret;
550 }
551 platform_set_drvdata(pdev, glue);
552
553 ret = of_platform_populate(pdev->dev.of_node, NULL,
554 da8xx_auxdata_lookup, &pdev->dev);
555 if (ret)
556 return ret;
557
558 pinfo = da8xx_dev_info;
559 pinfo.parent = &pdev->dev;
560 pinfo.res = pdev->resource;
561 pinfo.num_res = pdev->num_resources;
562 pinfo.data = pdata;
563 pinfo.size_data = sizeof(*pdata);
564 pinfo.fwnode = of_fwnode_handle(np);
565 pinfo.of_node_reused = true;
566
567 glue->musb = platform_device_register_full(&pinfo);
568 ret = PTR_ERR_OR_ZERO(glue->musb);
569 if (ret) {
570 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
571 usb_phy_generic_unregister(glue->usb_phy);
572 }
573
574 return ret;
575}
576
577static int da8xx_remove(struct platform_device *pdev)
578{
579 struct da8xx_glue *glue = platform_get_drvdata(pdev);
580
581 platform_device_unregister(glue->musb);
582 usb_phy_generic_unregister(glue->usb_phy);
583
584 return 0;
585}
586
587#ifdef CONFIG_PM_SLEEP
588static int da8xx_suspend(struct device *dev)
589{
590 int ret;
591 struct da8xx_glue *glue = dev_get_drvdata(dev);
592
593 ret = phy_power_off(glue->phy);
594 if (ret)
595 return ret;
596 clk_disable_unprepare(glue->clk);
597
598 return 0;
599}
600
601static int da8xx_resume(struct device *dev)
602{
603 int ret;
604 struct da8xx_glue *glue = dev_get_drvdata(dev);
605
606 ret = clk_prepare_enable(glue->clk);
607 if (ret)
608 return ret;
609 return phy_power_on(glue->phy);
610}
611#endif
612
613static SIMPLE_DEV_PM_OPS(da8xx_pm_ops, da8xx_suspend, da8xx_resume);
614
615#ifdef CONFIG_OF
616static const struct of_device_id da8xx_id_table[] = {
617 {
618 .compatible = "ti,da830-musb",
619 },
620 {},
621};
622MODULE_DEVICE_TABLE(of, da8xx_id_table);
623#endif
624
625static struct platform_driver da8xx_driver = {
626 .probe = da8xx_probe,
627 .remove = da8xx_remove,
628 .driver = {
629 .name = "musb-da8xx",
630 .pm = &da8xx_pm_ops,
631 .of_match_table = of_match_ptr(da8xx_id_table),
632 },
633};
634
635MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
636MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
637MODULE_LICENSE("GPL v2");
638module_platform_driver(da8xx_driver);