Loading...
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/iommu.h>
13#include <linux/reset.h>
14
15#include <soc/tegra/pmc.h>
16
17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
20
21#include <drm/drm_atomic.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_plane_helper.h>
24
25struct tegra_dc_soc_info {
26 bool supports_border_color;
27 bool supports_interlacing;
28 bool supports_cursor;
29 bool supports_block_linear;
30 unsigned int pitch_align;
31 bool has_powergate;
32};
33
34struct tegra_plane {
35 struct drm_plane base;
36 unsigned int index;
37};
38
39static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
40{
41 return container_of(plane, struct tegra_plane, base);
42}
43
44struct tegra_dc_state {
45 struct drm_crtc_state base;
46
47 struct clk *clk;
48 unsigned long pclk;
49 unsigned int div;
50
51 u32 planes;
52};
53
54static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
55{
56 if (state)
57 return container_of(state, struct tegra_dc_state, base);
58
59 return NULL;
60}
61
62struct tegra_plane_state {
63 struct drm_plane_state base;
64
65 struct tegra_bo_tiling tiling;
66 u32 format;
67 u32 swap;
68};
69
70static inline struct tegra_plane_state *
71to_tegra_plane_state(struct drm_plane_state *state)
72{
73 if (state)
74 return container_of(state, struct tegra_plane_state, base);
75
76 return NULL;
77}
78
79static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
80{
81 stats->frames = 0;
82 stats->vblank = 0;
83 stats->underflow = 0;
84 stats->overflow = 0;
85}
86
87/*
88 * Reads the active copy of a register. This takes the dc->lock spinlock to
89 * prevent races with the VBLANK processing which also needs access to the
90 * active copy of some registers.
91 */
92static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
93{
94 unsigned long flags;
95 u32 value;
96
97 spin_lock_irqsave(&dc->lock, flags);
98
99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
100 value = tegra_dc_readl(dc, offset);
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
102
103 spin_unlock_irqrestore(&dc->lock, flags);
104 return value;
105}
106
107/*
108 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
109 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
110 * Latching happens mmediately if the display controller is in STOP mode or
111 * on the next frame boundary otherwise.
112 *
113 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
114 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
115 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
116 * into the ACTIVE copy, either immediately if the display controller is in
117 * STOP mode, or at the next frame boundary otherwise.
118 */
119void tegra_dc_commit(struct tegra_dc *dc)
120{
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
123}
124
125static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
126{
127 /* assume no swapping of fetched data */
128 if (swap)
129 *swap = BYTE_SWAP_NOSWAP;
130
131 switch (fourcc) {
132 case DRM_FORMAT_XBGR8888:
133 *format = WIN_COLOR_DEPTH_R8G8B8A8;
134 break;
135
136 case DRM_FORMAT_XRGB8888:
137 *format = WIN_COLOR_DEPTH_B8G8R8A8;
138 break;
139
140 case DRM_FORMAT_RGB565:
141 *format = WIN_COLOR_DEPTH_B5G6R5;
142 break;
143
144 case DRM_FORMAT_UYVY:
145 *format = WIN_COLOR_DEPTH_YCbCr422;
146 break;
147
148 case DRM_FORMAT_YUYV:
149 if (swap)
150 *swap = BYTE_SWAP_SWAP2;
151
152 *format = WIN_COLOR_DEPTH_YCbCr422;
153 break;
154
155 case DRM_FORMAT_YUV420:
156 *format = WIN_COLOR_DEPTH_YCbCr420P;
157 break;
158
159 case DRM_FORMAT_YUV422:
160 *format = WIN_COLOR_DEPTH_YCbCr422P;
161 break;
162
163 default:
164 return -EINVAL;
165 }
166
167 return 0;
168}
169
170static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
171{
172 switch (format) {
173 case WIN_COLOR_DEPTH_YCbCr422:
174 case WIN_COLOR_DEPTH_YUV422:
175 if (planar)
176 *planar = false;
177
178 return true;
179
180 case WIN_COLOR_DEPTH_YCbCr420P:
181 case WIN_COLOR_DEPTH_YUV420P:
182 case WIN_COLOR_DEPTH_YCbCr422P:
183 case WIN_COLOR_DEPTH_YUV422P:
184 case WIN_COLOR_DEPTH_YCbCr422R:
185 case WIN_COLOR_DEPTH_YUV422R:
186 case WIN_COLOR_DEPTH_YCbCr422RA:
187 case WIN_COLOR_DEPTH_YUV422RA:
188 if (planar)
189 *planar = true;
190
191 return true;
192 }
193
194 if (planar)
195 *planar = false;
196
197 return false;
198}
199
200static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
201 unsigned int bpp)
202{
203 fixed20_12 outf = dfixed_init(out);
204 fixed20_12 inf = dfixed_init(in);
205 u32 dda_inc;
206 int max;
207
208 if (v)
209 max = 15;
210 else {
211 switch (bpp) {
212 case 2:
213 max = 8;
214 break;
215
216 default:
217 WARN_ON_ONCE(1);
218 /* fallthrough */
219 case 4:
220 max = 4;
221 break;
222 }
223 }
224
225 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
226 inf.full -= dfixed_const(1);
227
228 dda_inc = dfixed_div(inf, outf);
229 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
230
231 return dda_inc;
232}
233
234static inline u32 compute_initial_dda(unsigned int in)
235{
236 fixed20_12 inf = dfixed_init(in);
237 return dfixed_frac(inf);
238}
239
240static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
241 const struct tegra_dc_window *window)
242{
243 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
244 unsigned long value, flags;
245 bool yuv, planar;
246
247 /*
248 * For YUV planar modes, the number of bytes per pixel takes into
249 * account only the luma component and therefore is 1.
250 */
251 yuv = tegra_dc_format_is_yuv(window->format, &planar);
252 if (!yuv)
253 bpp = window->bits_per_pixel / 8;
254 else
255 bpp = planar ? 1 : 2;
256
257 spin_lock_irqsave(&dc->lock, flags);
258
259 value = WINDOW_A_SELECT << index;
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
261
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
264
265 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
266 tegra_dc_writel(dc, value, DC_WIN_POSITION);
267
268 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
269 tegra_dc_writel(dc, value, DC_WIN_SIZE);
270
271 h_offset = window->src.x * bpp;
272 v_offset = window->src.y;
273 h_size = window->src.w * bpp;
274 v_size = window->src.h;
275
276 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
278
279 /*
280 * For DDA computations the number of bytes per pixel for YUV planar
281 * modes needs to take into account all Y, U and V components.
282 */
283 if (yuv && planar)
284 bpp = 2;
285
286 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
287 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
288
289 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
290 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
291
292 h_dda = compute_initial_dda(window->src.x);
293 v_dda = compute_initial_dda(window->src.y);
294
295 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
296 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
297
298 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
299 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
300
301 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
302
303 if (yuv && planar) {
304 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
305 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
306 value = window->stride[1] << 16 | window->stride[0];
307 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
308 } else {
309 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
310 }
311
312 if (window->bottom_up)
313 v_offset += window->src.h - 1;
314
315 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
316 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
317
318 if (dc->soc->supports_block_linear) {
319 unsigned long height = window->tiling.value;
320
321 switch (window->tiling.mode) {
322 case TEGRA_BO_TILING_MODE_PITCH:
323 value = DC_WINBUF_SURFACE_KIND_PITCH;
324 break;
325
326 case TEGRA_BO_TILING_MODE_TILED:
327 value = DC_WINBUF_SURFACE_KIND_TILED;
328 break;
329
330 case TEGRA_BO_TILING_MODE_BLOCK:
331 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
332 DC_WINBUF_SURFACE_KIND_BLOCK;
333 break;
334 }
335
336 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
337 } else {
338 switch (window->tiling.mode) {
339 case TEGRA_BO_TILING_MODE_PITCH:
340 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
341 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
342 break;
343
344 case TEGRA_BO_TILING_MODE_TILED:
345 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
346 DC_WIN_BUFFER_ADDR_MODE_TILE;
347 break;
348
349 case TEGRA_BO_TILING_MODE_BLOCK:
350 /*
351 * No need to handle this here because ->atomic_check
352 * will already have filtered it out.
353 */
354 break;
355 }
356
357 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
358 }
359
360 value = WIN_ENABLE;
361
362 if (yuv) {
363 /* setup default colorspace conversion coefficients */
364 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
365 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
366 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
367 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
368 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
369 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
370 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
371 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
372
373 value |= CSC_ENABLE;
374 } else if (window->bits_per_pixel < 24) {
375 value |= COLOR_EXPAND;
376 }
377
378 if (window->bottom_up)
379 value |= V_DIRECTION;
380
381 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
382
383 /*
384 * Disable blending and assume Window A is the bottom-most window,
385 * Window C is the top-most window and Window B is in the middle.
386 */
387 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
389
390 switch (index) {
391 case 0:
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
395 break;
396
397 case 1:
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
399 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
401 break;
402
403 case 2:
404 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
407 break;
408 }
409
410 spin_unlock_irqrestore(&dc->lock, flags);
411}
412
413static void tegra_plane_destroy(struct drm_plane *plane)
414{
415 struct tegra_plane *p = to_tegra_plane(plane);
416
417 drm_plane_cleanup(plane);
418 kfree(p);
419}
420
421static const u32 tegra_primary_plane_formats[] = {
422 DRM_FORMAT_XBGR8888,
423 DRM_FORMAT_XRGB8888,
424 DRM_FORMAT_RGB565,
425};
426
427static void tegra_primary_plane_destroy(struct drm_plane *plane)
428{
429 tegra_plane_destroy(plane);
430}
431
432static void tegra_plane_reset(struct drm_plane *plane)
433{
434 struct tegra_plane_state *state;
435
436 if (plane->state)
437 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
438
439 kfree(plane->state);
440 plane->state = NULL;
441
442 state = kzalloc(sizeof(*state), GFP_KERNEL);
443 if (state) {
444 plane->state = &state->base;
445 plane->state->plane = plane;
446 }
447}
448
449static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
450{
451 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
452 struct tegra_plane_state *copy;
453
454 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
455 if (!copy)
456 return NULL;
457
458 __drm_atomic_helper_plane_duplicate_state(plane, ©->base);
459 copy->tiling = state->tiling;
460 copy->format = state->format;
461 copy->swap = state->swap;
462
463 return ©->base;
464}
465
466static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
467 struct drm_plane_state *state)
468{
469 __drm_atomic_helper_plane_destroy_state(plane, state);
470 kfree(state);
471}
472
473static const struct drm_plane_funcs tegra_primary_plane_funcs = {
474 .update_plane = drm_atomic_helper_update_plane,
475 .disable_plane = drm_atomic_helper_disable_plane,
476 .destroy = tegra_primary_plane_destroy,
477 .reset = tegra_plane_reset,
478 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
479 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
480};
481
482static int tegra_plane_prepare_fb(struct drm_plane *plane,
483 const struct drm_plane_state *new_state)
484{
485 return 0;
486}
487
488static void tegra_plane_cleanup_fb(struct drm_plane *plane,
489 const struct drm_plane_state *old_fb)
490{
491}
492
493static int tegra_plane_state_add(struct tegra_plane *plane,
494 struct drm_plane_state *state)
495{
496 struct drm_crtc_state *crtc_state;
497 struct tegra_dc_state *tegra;
498
499 /* Propagate errors from allocation or locking failures. */
500 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
501 if (IS_ERR(crtc_state))
502 return PTR_ERR(crtc_state);
503
504 tegra = to_dc_state(crtc_state);
505
506 tegra->planes |= WIN_A_ACT_REQ << plane->index;
507
508 return 0;
509}
510
511static int tegra_plane_atomic_check(struct drm_plane *plane,
512 struct drm_plane_state *state)
513{
514 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
515 struct tegra_bo_tiling *tiling = &plane_state->tiling;
516 struct tegra_plane *tegra = to_tegra_plane(plane);
517 struct tegra_dc *dc = to_tegra_dc(state->crtc);
518 int err;
519
520 /* no need for further checks if the plane is being disabled */
521 if (!state->crtc)
522 return 0;
523
524 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
525 &plane_state->swap);
526 if (err < 0)
527 return err;
528
529 err = tegra_fb_get_tiling(state->fb, tiling);
530 if (err < 0)
531 return err;
532
533 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
534 !dc->soc->supports_block_linear) {
535 DRM_ERROR("hardware doesn't support block linear mode\n");
536 return -EINVAL;
537 }
538
539 /*
540 * Tegra doesn't support different strides for U and V planes so we
541 * error out if the user tries to display a framebuffer with such a
542 * configuration.
543 */
544 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
545 if (state->fb->pitches[2] != state->fb->pitches[1]) {
546 DRM_ERROR("unsupported UV-plane configuration\n");
547 return -EINVAL;
548 }
549 }
550
551 err = tegra_plane_state_add(tegra, state);
552 if (err < 0)
553 return err;
554
555 return 0;
556}
557
558static void tegra_plane_atomic_update(struct drm_plane *plane,
559 struct drm_plane_state *old_state)
560{
561 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
562 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
563 struct drm_framebuffer *fb = plane->state->fb;
564 struct tegra_plane *p = to_tegra_plane(plane);
565 struct tegra_dc_window window;
566 unsigned int i;
567
568 /* rien ne va plus */
569 if (!plane->state->crtc || !plane->state->fb)
570 return;
571
572 memset(&window, 0, sizeof(window));
573 window.src.x = plane->state->src_x >> 16;
574 window.src.y = plane->state->src_y >> 16;
575 window.src.w = plane->state->src_w >> 16;
576 window.src.h = plane->state->src_h >> 16;
577 window.dst.x = plane->state->crtc_x;
578 window.dst.y = plane->state->crtc_y;
579 window.dst.w = plane->state->crtc_w;
580 window.dst.h = plane->state->crtc_h;
581 window.bits_per_pixel = fb->bits_per_pixel;
582 window.bottom_up = tegra_fb_is_bottom_up(fb);
583
584 /* copy from state */
585 window.tiling = state->tiling;
586 window.format = state->format;
587 window.swap = state->swap;
588
589 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
590 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
591
592 window.base[i] = bo->paddr + fb->offsets[i];
593 window.stride[i] = fb->pitches[i];
594 }
595
596 tegra_dc_setup_window(dc, p->index, &window);
597}
598
599static void tegra_plane_atomic_disable(struct drm_plane *plane,
600 struct drm_plane_state *old_state)
601{
602 struct tegra_plane *p = to_tegra_plane(plane);
603 struct tegra_dc *dc;
604 unsigned long flags;
605 u32 value;
606
607 /* rien ne va plus */
608 if (!old_state || !old_state->crtc)
609 return;
610
611 dc = to_tegra_dc(old_state->crtc);
612
613 spin_lock_irqsave(&dc->lock, flags);
614
615 value = WINDOW_A_SELECT << p->index;
616 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
617
618 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
619 value &= ~WIN_ENABLE;
620 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
621
622 spin_unlock_irqrestore(&dc->lock, flags);
623}
624
625static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
626 .prepare_fb = tegra_plane_prepare_fb,
627 .cleanup_fb = tegra_plane_cleanup_fb,
628 .atomic_check = tegra_plane_atomic_check,
629 .atomic_update = tegra_plane_atomic_update,
630 .atomic_disable = tegra_plane_atomic_disable,
631};
632
633static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
634 struct tegra_dc *dc)
635{
636 /*
637 * Ideally this would use drm_crtc_mask(), but that would require the
638 * CRTC to already be in the mode_config's list of CRTCs. However, it
639 * will only be added to that list in the drm_crtc_init_with_planes()
640 * (in tegra_dc_init()), which in turn requires registration of these
641 * planes. So we have ourselves a nice little chicken and egg problem
642 * here.
643 *
644 * We work around this by manually creating the mask from the number
645 * of CRTCs that have been registered, and should therefore always be
646 * the same as drm_crtc_index() after registration.
647 */
648 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
649 struct tegra_plane *plane;
650 unsigned int num_formats;
651 const u32 *formats;
652 int err;
653
654 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
655 if (!plane)
656 return ERR_PTR(-ENOMEM);
657
658 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
659 formats = tegra_primary_plane_formats;
660
661 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
662 &tegra_primary_plane_funcs, formats,
663 num_formats, DRM_PLANE_TYPE_PRIMARY,
664 NULL);
665 if (err < 0) {
666 kfree(plane);
667 return ERR_PTR(err);
668 }
669
670 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
671
672 return &plane->base;
673}
674
675static const u32 tegra_cursor_plane_formats[] = {
676 DRM_FORMAT_RGBA8888,
677};
678
679static int tegra_cursor_atomic_check(struct drm_plane *plane,
680 struct drm_plane_state *state)
681{
682 struct tegra_plane *tegra = to_tegra_plane(plane);
683 int err;
684
685 /* no need for further checks if the plane is being disabled */
686 if (!state->crtc)
687 return 0;
688
689 /* scaling not supported for cursor */
690 if ((state->src_w >> 16 != state->crtc_w) ||
691 (state->src_h >> 16 != state->crtc_h))
692 return -EINVAL;
693
694 /* only square cursors supported */
695 if (state->src_w != state->src_h)
696 return -EINVAL;
697
698 if (state->crtc_w != 32 && state->crtc_w != 64 &&
699 state->crtc_w != 128 && state->crtc_w != 256)
700 return -EINVAL;
701
702 err = tegra_plane_state_add(tegra, state);
703 if (err < 0)
704 return err;
705
706 return 0;
707}
708
709static void tegra_cursor_atomic_update(struct drm_plane *plane,
710 struct drm_plane_state *old_state)
711{
712 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
713 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
714 struct drm_plane_state *state = plane->state;
715 u32 value = CURSOR_CLIP_DISPLAY;
716
717 /* rien ne va plus */
718 if (!plane->state->crtc || !plane->state->fb)
719 return;
720
721 switch (state->crtc_w) {
722 case 32:
723 value |= CURSOR_SIZE_32x32;
724 break;
725
726 case 64:
727 value |= CURSOR_SIZE_64x64;
728 break;
729
730 case 128:
731 value |= CURSOR_SIZE_128x128;
732 break;
733
734 case 256:
735 value |= CURSOR_SIZE_256x256;
736 break;
737
738 default:
739 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
740 state->crtc_h);
741 return;
742 }
743
744 value |= (bo->paddr >> 10) & 0x3fffff;
745 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
746
747#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
748 value = (bo->paddr >> 32) & 0x3;
749 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
750#endif
751
752 /* enable cursor and set blend mode */
753 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
754 value |= CURSOR_ENABLE;
755 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
756
757 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
758 value &= ~CURSOR_DST_BLEND_MASK;
759 value &= ~CURSOR_SRC_BLEND_MASK;
760 value |= CURSOR_MODE_NORMAL;
761 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
762 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
763 value |= CURSOR_ALPHA;
764 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
765
766 /* position the cursor */
767 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
768 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
769}
770
771static void tegra_cursor_atomic_disable(struct drm_plane *plane,
772 struct drm_plane_state *old_state)
773{
774 struct tegra_dc *dc;
775 u32 value;
776
777 /* rien ne va plus */
778 if (!old_state || !old_state->crtc)
779 return;
780
781 dc = to_tegra_dc(old_state->crtc);
782
783 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
784 value &= ~CURSOR_ENABLE;
785 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
786}
787
788static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
789 .update_plane = drm_atomic_helper_update_plane,
790 .disable_plane = drm_atomic_helper_disable_plane,
791 .destroy = tegra_plane_destroy,
792 .reset = tegra_plane_reset,
793 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
794 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
795};
796
797static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
798 .prepare_fb = tegra_plane_prepare_fb,
799 .cleanup_fb = tegra_plane_cleanup_fb,
800 .atomic_check = tegra_cursor_atomic_check,
801 .atomic_update = tegra_cursor_atomic_update,
802 .atomic_disable = tegra_cursor_atomic_disable,
803};
804
805static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
806 struct tegra_dc *dc)
807{
808 struct tegra_plane *plane;
809 unsigned int num_formats;
810 const u32 *formats;
811 int err;
812
813 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
814 if (!plane)
815 return ERR_PTR(-ENOMEM);
816
817 /*
818 * This index is kind of fake. The cursor isn't a regular plane, but
819 * its update and activation request bits in DC_CMD_STATE_CONTROL do
820 * use the same programming. Setting this fake index here allows the
821 * code in tegra_add_plane_state() to do the right thing without the
822 * need to special-casing the cursor plane.
823 */
824 plane->index = 6;
825
826 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
827 formats = tegra_cursor_plane_formats;
828
829 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
830 &tegra_cursor_plane_funcs, formats,
831 num_formats, DRM_PLANE_TYPE_CURSOR,
832 NULL);
833 if (err < 0) {
834 kfree(plane);
835 return ERR_PTR(err);
836 }
837
838 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
839
840 return &plane->base;
841}
842
843static void tegra_overlay_plane_destroy(struct drm_plane *plane)
844{
845 tegra_plane_destroy(plane);
846}
847
848static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
849 .update_plane = drm_atomic_helper_update_plane,
850 .disable_plane = drm_atomic_helper_disable_plane,
851 .destroy = tegra_overlay_plane_destroy,
852 .reset = tegra_plane_reset,
853 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
854 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
855};
856
857static const uint32_t tegra_overlay_plane_formats[] = {
858 DRM_FORMAT_XBGR8888,
859 DRM_FORMAT_XRGB8888,
860 DRM_FORMAT_RGB565,
861 DRM_FORMAT_UYVY,
862 DRM_FORMAT_YUYV,
863 DRM_FORMAT_YUV420,
864 DRM_FORMAT_YUV422,
865};
866
867static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
868 .prepare_fb = tegra_plane_prepare_fb,
869 .cleanup_fb = tegra_plane_cleanup_fb,
870 .atomic_check = tegra_plane_atomic_check,
871 .atomic_update = tegra_plane_atomic_update,
872 .atomic_disable = tegra_plane_atomic_disable,
873};
874
875static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
876 struct tegra_dc *dc,
877 unsigned int index)
878{
879 struct tegra_plane *plane;
880 unsigned int num_formats;
881 const u32 *formats;
882 int err;
883
884 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
885 if (!plane)
886 return ERR_PTR(-ENOMEM);
887
888 plane->index = index;
889
890 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
891 formats = tegra_overlay_plane_formats;
892
893 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
894 &tegra_overlay_plane_funcs, formats,
895 num_formats, DRM_PLANE_TYPE_OVERLAY,
896 NULL);
897 if (err < 0) {
898 kfree(plane);
899 return ERR_PTR(err);
900 }
901
902 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
903
904 return &plane->base;
905}
906
907static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
908{
909 struct drm_plane *plane;
910 unsigned int i;
911
912 for (i = 0; i < 2; i++) {
913 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
914 if (IS_ERR(plane))
915 return PTR_ERR(plane);
916 }
917
918 return 0;
919}
920
921u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
922{
923 if (dc->syncpt)
924 return host1x_syncpt_read(dc->syncpt);
925
926 /* fallback to software emulated VBLANK counter */
927 return drm_crtc_vblank_count(&dc->base);
928}
929
930void tegra_dc_enable_vblank(struct tegra_dc *dc)
931{
932 unsigned long value, flags;
933
934 spin_lock_irqsave(&dc->lock, flags);
935
936 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
937 value |= VBLANK_INT;
938 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
939
940 spin_unlock_irqrestore(&dc->lock, flags);
941}
942
943void tegra_dc_disable_vblank(struct tegra_dc *dc)
944{
945 unsigned long value, flags;
946
947 spin_lock_irqsave(&dc->lock, flags);
948
949 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
950 value &= ~VBLANK_INT;
951 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
952
953 spin_unlock_irqrestore(&dc->lock, flags);
954}
955
956static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
957{
958 struct drm_device *drm = dc->base.dev;
959 struct drm_crtc *crtc = &dc->base;
960 unsigned long flags, base;
961 struct tegra_bo *bo;
962
963 spin_lock_irqsave(&drm->event_lock, flags);
964
965 if (!dc->event) {
966 spin_unlock_irqrestore(&drm->event_lock, flags);
967 return;
968 }
969
970 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
971
972 spin_lock(&dc->lock);
973
974 /* check if new start address has been latched */
975 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
976 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
977 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
978 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
979
980 spin_unlock(&dc->lock);
981
982 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
983 drm_crtc_send_vblank_event(crtc, dc->event);
984 drm_crtc_vblank_put(crtc);
985 dc->event = NULL;
986 }
987
988 spin_unlock_irqrestore(&drm->event_lock, flags);
989}
990
991static void tegra_dc_destroy(struct drm_crtc *crtc)
992{
993 drm_crtc_cleanup(crtc);
994}
995
996static void tegra_crtc_reset(struct drm_crtc *crtc)
997{
998 struct tegra_dc_state *state;
999
1000 if (crtc->state)
1001 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1002
1003 kfree(crtc->state);
1004 crtc->state = NULL;
1005
1006 state = kzalloc(sizeof(*state), GFP_KERNEL);
1007 if (state) {
1008 crtc->state = &state->base;
1009 crtc->state->crtc = crtc;
1010 }
1011
1012 drm_crtc_vblank_reset(crtc);
1013}
1014
1015static struct drm_crtc_state *
1016tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1017{
1018 struct tegra_dc_state *state = to_dc_state(crtc->state);
1019 struct tegra_dc_state *copy;
1020
1021 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1022 if (!copy)
1023 return NULL;
1024
1025 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1026 copy->clk = state->clk;
1027 copy->pclk = state->pclk;
1028 copy->div = state->div;
1029 copy->planes = state->planes;
1030
1031 return ©->base;
1032}
1033
1034static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1035 struct drm_crtc_state *state)
1036{
1037 __drm_atomic_helper_crtc_destroy_state(crtc, state);
1038 kfree(state);
1039}
1040
1041static const struct drm_crtc_funcs tegra_crtc_funcs = {
1042 .page_flip = drm_atomic_helper_page_flip,
1043 .set_config = drm_atomic_helper_set_config,
1044 .destroy = tegra_dc_destroy,
1045 .reset = tegra_crtc_reset,
1046 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1047 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1048};
1049
1050static int tegra_dc_set_timings(struct tegra_dc *dc,
1051 struct drm_display_mode *mode)
1052{
1053 unsigned int h_ref_to_sync = 1;
1054 unsigned int v_ref_to_sync = 1;
1055 unsigned long value;
1056
1057 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058
1059 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1061
1062 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063 ((mode->hsync_end - mode->hsync_start) << 0);
1064 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1065
1066 value = ((mode->vtotal - mode->vsync_end) << 16) |
1067 ((mode->htotal - mode->hsync_end) << 0);
1068 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1069
1070 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071 ((mode->hsync_start - mode->hdisplay) << 0);
1072 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1073
1074 value = (mode->vdisplay << 16) | mode->hdisplay;
1075 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1076
1077 return 0;
1078}
1079
1080/**
1081 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1082 * state
1083 * @dc: display controller
1084 * @crtc_state: CRTC atomic state
1085 * @clk: parent clock for display controller
1086 * @pclk: pixel clock
1087 * @div: shift clock divider
1088 *
1089 * Returns:
1090 * 0 on success or a negative error-code on failure.
1091 */
1092int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093 struct drm_crtc_state *crtc_state,
1094 struct clk *clk, unsigned long pclk,
1095 unsigned int div)
1096{
1097 struct tegra_dc_state *state = to_dc_state(crtc_state);
1098
1099 if (!clk_has_parent(dc->clk, clk))
1100 return -EINVAL;
1101
1102 state->clk = clk;
1103 state->pclk = pclk;
1104 state->div = div;
1105
1106 return 0;
1107}
1108
1109static void tegra_dc_commit_state(struct tegra_dc *dc,
1110 struct tegra_dc_state *state)
1111{
1112 u32 value;
1113 int err;
1114
1115 err = clk_set_parent(dc->clk, state->clk);
1116 if (err < 0)
1117 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1118
1119 /*
1120 * Outputs may not want to change the parent clock rate. This is only
1121 * relevant to Tegra20 where only a single display PLL is available.
1122 * Since that PLL would typically be used for HDMI, an internal LVDS
1123 * panel would need to be driven by some other clock such as PLL_P
1124 * which is shared with other peripherals. Changing the clock rate
1125 * should therefore be avoided.
1126 */
1127 if (state->pclk > 0) {
1128 err = clk_set_rate(state->clk, state->pclk);
1129 if (err < 0)
1130 dev_err(dc->dev,
1131 "failed to set clock rate to %lu Hz\n",
1132 state->pclk);
1133 }
1134
1135 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1136 state->div);
1137 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138
1139 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1141}
1142
1143static void tegra_dc_stop(struct tegra_dc *dc)
1144{
1145 u32 value;
1146
1147 /* stop the display controller */
1148 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1149 value &= ~DISP_CTRL_MODE_MASK;
1150 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1151
1152 tegra_dc_commit(dc);
1153}
1154
1155static bool tegra_dc_idle(struct tegra_dc *dc)
1156{
1157 u32 value;
1158
1159 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1160
1161 return (value & DISP_CTRL_MODE_MASK) == 0;
1162}
1163
1164static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1165{
1166 timeout = jiffies + msecs_to_jiffies(timeout);
1167
1168 while (time_before(jiffies, timeout)) {
1169 if (tegra_dc_idle(dc))
1170 return 0;
1171
1172 usleep_range(1000, 2000);
1173 }
1174
1175 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1176 return -ETIMEDOUT;
1177}
1178
1179static void tegra_crtc_disable(struct drm_crtc *crtc)
1180{
1181 struct tegra_dc *dc = to_tegra_dc(crtc);
1182 u32 value;
1183
1184 if (!tegra_dc_idle(dc)) {
1185 tegra_dc_stop(dc);
1186
1187 /*
1188 * Ignore the return value, there isn't anything useful to do
1189 * in case this fails.
1190 */
1191 tegra_dc_wait_idle(dc, 100);
1192 }
1193
1194 /*
1195 * This should really be part of the RGB encoder driver, but clearing
1196 * these bits has the side-effect of stopping the display controller.
1197 * When that happens no VBLANK interrupts will be raised. At the same
1198 * time the encoder is disabled before the display controller, so the
1199 * above code is always going to timeout waiting for the controller
1200 * to go idle.
1201 *
1202 * Given the close coupling between the RGB encoder and the display
1203 * controller doing it here is still kind of okay. None of the other
1204 * encoder drivers require these bits to be cleared.
1205 *
1206 * XXX: Perhaps given that the display controller is switched off at
1207 * this point anyway maybe clearing these bits isn't even useful for
1208 * the RGB encoder?
1209 */
1210 if (dc->rgb) {
1211 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1212 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1213 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1214 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1215 }
1216
1217 tegra_dc_stats_reset(&dc->stats);
1218 drm_crtc_vblank_off(crtc);
1219}
1220
1221static void tegra_crtc_enable(struct drm_crtc *crtc)
1222{
1223 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1224 struct tegra_dc_state *state = to_dc_state(crtc->state);
1225 struct tegra_dc *dc = to_tegra_dc(crtc);
1226 u32 value;
1227
1228 tegra_dc_commit_state(dc, state);
1229
1230 /* program display mode */
1231 tegra_dc_set_timings(dc, mode);
1232
1233 /* interlacing isn't supported yet, so disable it */
1234 if (dc->soc->supports_interlacing) {
1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1236 value &= ~INTERLACE_ENABLE;
1237 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1238 }
1239
1240 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1241 value &= ~DISP_CTRL_MODE_MASK;
1242 value |= DISP_CTRL_MODE_C_DISPLAY;
1243 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1244
1245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1246 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1247 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1249
1250 tegra_dc_commit(dc);
1251
1252 drm_crtc_vblank_on(crtc);
1253}
1254
1255static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1256 struct drm_crtc_state *state)
1257{
1258 return 0;
1259}
1260
1261static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1262 struct drm_crtc_state *old_crtc_state)
1263{
1264 struct tegra_dc *dc = to_tegra_dc(crtc);
1265
1266 if (crtc->state->event) {
1267 crtc->state->event->pipe = drm_crtc_index(crtc);
1268
1269 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1270
1271 dc->event = crtc->state->event;
1272 crtc->state->event = NULL;
1273 }
1274}
1275
1276static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1277 struct drm_crtc_state *old_crtc_state)
1278{
1279 struct tegra_dc_state *state = to_dc_state(crtc->state);
1280 struct tegra_dc *dc = to_tegra_dc(crtc);
1281
1282 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1283 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1284}
1285
1286static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1287 .disable = tegra_crtc_disable,
1288 .enable = tegra_crtc_enable,
1289 .atomic_check = tegra_crtc_atomic_check,
1290 .atomic_begin = tegra_crtc_atomic_begin,
1291 .atomic_flush = tegra_crtc_atomic_flush,
1292};
1293
1294static irqreturn_t tegra_dc_irq(int irq, void *data)
1295{
1296 struct tegra_dc *dc = data;
1297 unsigned long status;
1298
1299 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1300 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1301
1302 if (status & FRAME_END_INT) {
1303 /*
1304 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1305 */
1306 dc->stats.frames++;
1307 }
1308
1309 if (status & VBLANK_INT) {
1310 /*
1311 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1312 */
1313 drm_crtc_handle_vblank(&dc->base);
1314 tegra_dc_finish_page_flip(dc);
1315 dc->stats.vblank++;
1316 }
1317
1318 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1319 /*
1320 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1321 */
1322 dc->stats.underflow++;
1323 }
1324
1325 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1326 /*
1327 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1328 */
1329 dc->stats.overflow++;
1330 }
1331
1332 return IRQ_HANDLED;
1333}
1334
1335static int tegra_dc_show_regs(struct seq_file *s, void *data)
1336{
1337 struct drm_info_node *node = s->private;
1338 struct tegra_dc *dc = node->info_ent->data;
1339 int err = 0;
1340
1341 drm_modeset_lock_crtc(&dc->base, NULL);
1342
1343 if (!dc->base.state->active) {
1344 err = -EBUSY;
1345 goto unlock;
1346 }
1347
1348#define DUMP_REG(name) \
1349 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1350 tegra_dc_readl(dc, name))
1351
1352 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1353 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1354 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1355 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1356 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1357 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1358 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1359 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1360 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1361 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1362 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1363 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1364 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1365 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1366 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1367 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1368 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1369 DUMP_REG(DC_CMD_INT_STATUS);
1370 DUMP_REG(DC_CMD_INT_MASK);
1371 DUMP_REG(DC_CMD_INT_ENABLE);
1372 DUMP_REG(DC_CMD_INT_TYPE);
1373 DUMP_REG(DC_CMD_INT_POLARITY);
1374 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1375 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1376 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1377 DUMP_REG(DC_CMD_STATE_ACCESS);
1378 DUMP_REG(DC_CMD_STATE_CONTROL);
1379 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1380 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1381 DUMP_REG(DC_COM_CRC_CONTROL);
1382 DUMP_REG(DC_COM_CRC_CHECKSUM);
1383 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1384 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1385 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1386 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1387 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1388 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1389 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1390 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1391 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1392 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1393 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1394 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1395 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1396 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1397 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1398 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1399 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1400 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1401 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1402 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1403 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1404 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1405 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1406 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1407 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1408 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1409 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1410 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1411 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1412 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1413 DUMP_REG(DC_COM_SPI_CONTROL);
1414 DUMP_REG(DC_COM_SPI_START_BYTE);
1415 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1416 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1417 DUMP_REG(DC_COM_HSPI_CS_DC);
1418 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1419 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1420 DUMP_REG(DC_COM_GPIO_CTRL);
1421 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1422 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1423 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1424 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1425 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1426 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1427 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1428 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1429 DUMP_REG(DC_DISP_REF_TO_SYNC);
1430 DUMP_REG(DC_DISP_SYNC_WIDTH);
1431 DUMP_REG(DC_DISP_BACK_PORCH);
1432 DUMP_REG(DC_DISP_ACTIVE);
1433 DUMP_REG(DC_DISP_FRONT_PORCH);
1434 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1435 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1436 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1437 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1438 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1439 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1440 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1441 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1442 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1443 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1444 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1445 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1446 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1447 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1448 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1449 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1450 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1451 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1452 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1453 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1454 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1455 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1456 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1457 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1458 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1459 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1460 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1461 DUMP_REG(DC_DISP_M0_CONTROL);
1462 DUMP_REG(DC_DISP_M1_CONTROL);
1463 DUMP_REG(DC_DISP_DI_CONTROL);
1464 DUMP_REG(DC_DISP_PP_CONTROL);
1465 DUMP_REG(DC_DISP_PP_SELECT_A);
1466 DUMP_REG(DC_DISP_PP_SELECT_B);
1467 DUMP_REG(DC_DISP_PP_SELECT_C);
1468 DUMP_REG(DC_DISP_PP_SELECT_D);
1469 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1470 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1471 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1472 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1473 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1474 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1475 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1476 DUMP_REG(DC_DISP_BORDER_COLOR);
1477 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1478 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1479 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1480 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1481 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1482 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1483 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1484 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1485 DUMP_REG(DC_DISP_CURSOR_POSITION);
1486 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1487 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1488 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1489 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1490 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1491 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1492 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1493 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1494 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1495 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1496 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1497 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1498 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1499 DUMP_REG(DC_DISP_SD_CONTROL);
1500 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1501 DUMP_REG(DC_DISP_SD_LUT(0));
1502 DUMP_REG(DC_DISP_SD_LUT(1));
1503 DUMP_REG(DC_DISP_SD_LUT(2));
1504 DUMP_REG(DC_DISP_SD_LUT(3));
1505 DUMP_REG(DC_DISP_SD_LUT(4));
1506 DUMP_REG(DC_DISP_SD_LUT(5));
1507 DUMP_REG(DC_DISP_SD_LUT(6));
1508 DUMP_REG(DC_DISP_SD_LUT(7));
1509 DUMP_REG(DC_DISP_SD_LUT(8));
1510 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1511 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1512 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1513 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1514 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1515 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1516 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1517 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1518 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1519 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1520 DUMP_REG(DC_DISP_SD_BL_TF(0));
1521 DUMP_REG(DC_DISP_SD_BL_TF(1));
1522 DUMP_REG(DC_DISP_SD_BL_TF(2));
1523 DUMP_REG(DC_DISP_SD_BL_TF(3));
1524 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1525 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1526 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1527 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1528 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1529 DUMP_REG(DC_WIN_WIN_OPTIONS);
1530 DUMP_REG(DC_WIN_BYTE_SWAP);
1531 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1532 DUMP_REG(DC_WIN_COLOR_DEPTH);
1533 DUMP_REG(DC_WIN_POSITION);
1534 DUMP_REG(DC_WIN_SIZE);
1535 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1536 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1537 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1538 DUMP_REG(DC_WIN_DDA_INC);
1539 DUMP_REG(DC_WIN_LINE_STRIDE);
1540 DUMP_REG(DC_WIN_BUF_STRIDE);
1541 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1542 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1543 DUMP_REG(DC_WIN_DV_CONTROL);
1544 DUMP_REG(DC_WIN_BLEND_NOKEY);
1545 DUMP_REG(DC_WIN_BLEND_1WIN);
1546 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1547 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1548 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1549 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1550 DUMP_REG(DC_WINBUF_START_ADDR);
1551 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1552 DUMP_REG(DC_WINBUF_START_ADDR_U);
1553 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1554 DUMP_REG(DC_WINBUF_START_ADDR_V);
1555 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1556 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1557 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1558 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1559 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1560 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1561 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1562 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1563 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1564
1565#undef DUMP_REG
1566
1567unlock:
1568 drm_modeset_unlock_crtc(&dc->base);
1569 return err;
1570}
1571
1572static int tegra_dc_show_crc(struct seq_file *s, void *data)
1573{
1574 struct drm_info_node *node = s->private;
1575 struct tegra_dc *dc = node->info_ent->data;
1576 int err = 0;
1577 u32 value;
1578
1579 drm_modeset_lock_crtc(&dc->base, NULL);
1580
1581 if (!dc->base.state->active) {
1582 err = -EBUSY;
1583 goto unlock;
1584 }
1585
1586 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1587 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1588 tegra_dc_commit(dc);
1589
1590 drm_crtc_wait_one_vblank(&dc->base);
1591 drm_crtc_wait_one_vblank(&dc->base);
1592
1593 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1594 seq_printf(s, "%08x\n", value);
1595
1596 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1597
1598unlock:
1599 drm_modeset_unlock_crtc(&dc->base);
1600 return err;
1601}
1602
1603static int tegra_dc_show_stats(struct seq_file *s, void *data)
1604{
1605 struct drm_info_node *node = s->private;
1606 struct tegra_dc *dc = node->info_ent->data;
1607
1608 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1609 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1610 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1611 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1612
1613 return 0;
1614}
1615
1616static struct drm_info_list debugfs_files[] = {
1617 { "regs", tegra_dc_show_regs, 0, NULL },
1618 { "crc", tegra_dc_show_crc, 0, NULL },
1619 { "stats", tegra_dc_show_stats, 0, NULL },
1620};
1621
1622static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1623{
1624 unsigned int i;
1625 char *name;
1626 int err;
1627
1628 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1629 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1630 kfree(name);
1631
1632 if (!dc->debugfs)
1633 return -ENOMEM;
1634
1635 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1636 GFP_KERNEL);
1637 if (!dc->debugfs_files) {
1638 err = -ENOMEM;
1639 goto remove;
1640 }
1641
1642 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1643 dc->debugfs_files[i].data = dc;
1644
1645 err = drm_debugfs_create_files(dc->debugfs_files,
1646 ARRAY_SIZE(debugfs_files),
1647 dc->debugfs, minor);
1648 if (err < 0)
1649 goto free;
1650
1651 dc->minor = minor;
1652
1653 return 0;
1654
1655free:
1656 kfree(dc->debugfs_files);
1657 dc->debugfs_files = NULL;
1658remove:
1659 debugfs_remove(dc->debugfs);
1660 dc->debugfs = NULL;
1661
1662 return err;
1663}
1664
1665static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1666{
1667 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1668 dc->minor);
1669 dc->minor = NULL;
1670
1671 kfree(dc->debugfs_files);
1672 dc->debugfs_files = NULL;
1673
1674 debugfs_remove(dc->debugfs);
1675 dc->debugfs = NULL;
1676
1677 return 0;
1678}
1679
1680static int tegra_dc_init(struct host1x_client *client)
1681{
1682 struct drm_device *drm = dev_get_drvdata(client->parent);
1683 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1684 struct tegra_dc *dc = host1x_client_to_dc(client);
1685 struct tegra_drm *tegra = drm->dev_private;
1686 struct drm_plane *primary = NULL;
1687 struct drm_plane *cursor = NULL;
1688 u32 value;
1689 int err;
1690
1691 dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1692 if (!dc->syncpt)
1693 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1694
1695 if (tegra->domain) {
1696 err = iommu_attach_device(tegra->domain, dc->dev);
1697 if (err < 0) {
1698 dev_err(dc->dev, "failed to attach to domain: %d\n",
1699 err);
1700 return err;
1701 }
1702
1703 dc->domain = tegra->domain;
1704 }
1705
1706 primary = tegra_dc_primary_plane_create(drm, dc);
1707 if (IS_ERR(primary)) {
1708 err = PTR_ERR(primary);
1709 goto cleanup;
1710 }
1711
1712 if (dc->soc->supports_cursor) {
1713 cursor = tegra_dc_cursor_plane_create(drm, dc);
1714 if (IS_ERR(cursor)) {
1715 err = PTR_ERR(cursor);
1716 goto cleanup;
1717 }
1718 }
1719
1720 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1721 &tegra_crtc_funcs, NULL);
1722 if (err < 0)
1723 goto cleanup;
1724
1725 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1726 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1727
1728 /*
1729 * Keep track of the minimum pitch alignment across all display
1730 * controllers.
1731 */
1732 if (dc->soc->pitch_align > tegra->pitch_align)
1733 tegra->pitch_align = dc->soc->pitch_align;
1734
1735 err = tegra_dc_rgb_init(drm, dc);
1736 if (err < 0 && err != -ENODEV) {
1737 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1738 goto cleanup;
1739 }
1740
1741 err = tegra_dc_add_planes(drm, dc);
1742 if (err < 0)
1743 goto cleanup;
1744
1745 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1746 err = tegra_dc_debugfs_init(dc, drm->primary);
1747 if (err < 0)
1748 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1749 }
1750
1751 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1752 dev_name(dc->dev), dc);
1753 if (err < 0) {
1754 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1755 err);
1756 goto cleanup;
1757 }
1758
1759 /* initialize display controller */
1760 if (dc->syncpt) {
1761 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1762
1763 value = SYNCPT_CNTRL_NO_STALL;
1764 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1765
1766 value = SYNCPT_VSYNC_ENABLE | syncpt;
1767 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1768 }
1769
1770 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1771 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1772 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1773
1774 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1775 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1776 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1777
1778 /* initialize timer */
1779 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1780 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1781 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1782
1783 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1784 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1785 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1786
1787 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1788 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1789 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1790
1791 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1792 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1793 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1794
1795 if (dc->soc->supports_border_color)
1796 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1797
1798 tegra_dc_stats_reset(&dc->stats);
1799
1800 return 0;
1801
1802cleanup:
1803 if (cursor)
1804 drm_plane_cleanup(cursor);
1805
1806 if (primary)
1807 drm_plane_cleanup(primary);
1808
1809 if (tegra->domain) {
1810 iommu_detach_device(tegra->domain, dc->dev);
1811 dc->domain = NULL;
1812 }
1813
1814 return err;
1815}
1816
1817static int tegra_dc_exit(struct host1x_client *client)
1818{
1819 struct tegra_dc *dc = host1x_client_to_dc(client);
1820 int err;
1821
1822 devm_free_irq(dc->dev, dc->irq, dc);
1823
1824 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1825 err = tegra_dc_debugfs_exit(dc);
1826 if (err < 0)
1827 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1828 }
1829
1830 err = tegra_dc_rgb_exit(dc);
1831 if (err) {
1832 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1833 return err;
1834 }
1835
1836 if (dc->domain) {
1837 iommu_detach_device(dc->domain, dc->dev);
1838 dc->domain = NULL;
1839 }
1840
1841 host1x_syncpt_free(dc->syncpt);
1842
1843 return 0;
1844}
1845
1846static const struct host1x_client_ops dc_client_ops = {
1847 .init = tegra_dc_init,
1848 .exit = tegra_dc_exit,
1849};
1850
1851static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1852 .supports_border_color = true,
1853 .supports_interlacing = false,
1854 .supports_cursor = false,
1855 .supports_block_linear = false,
1856 .pitch_align = 8,
1857 .has_powergate = false,
1858};
1859
1860static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1861 .supports_border_color = true,
1862 .supports_interlacing = false,
1863 .supports_cursor = false,
1864 .supports_block_linear = false,
1865 .pitch_align = 8,
1866 .has_powergate = false,
1867};
1868
1869static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1870 .supports_border_color = true,
1871 .supports_interlacing = false,
1872 .supports_cursor = false,
1873 .supports_block_linear = false,
1874 .pitch_align = 64,
1875 .has_powergate = true,
1876};
1877
1878static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1879 .supports_border_color = false,
1880 .supports_interlacing = true,
1881 .supports_cursor = true,
1882 .supports_block_linear = true,
1883 .pitch_align = 64,
1884 .has_powergate = true,
1885};
1886
1887static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1888 .supports_border_color = false,
1889 .supports_interlacing = true,
1890 .supports_cursor = true,
1891 .supports_block_linear = true,
1892 .pitch_align = 64,
1893 .has_powergate = true,
1894};
1895
1896static const struct of_device_id tegra_dc_of_match[] = {
1897 {
1898 .compatible = "nvidia,tegra210-dc",
1899 .data = &tegra210_dc_soc_info,
1900 }, {
1901 .compatible = "nvidia,tegra124-dc",
1902 .data = &tegra124_dc_soc_info,
1903 }, {
1904 .compatible = "nvidia,tegra114-dc",
1905 .data = &tegra114_dc_soc_info,
1906 }, {
1907 .compatible = "nvidia,tegra30-dc",
1908 .data = &tegra30_dc_soc_info,
1909 }, {
1910 .compatible = "nvidia,tegra20-dc",
1911 .data = &tegra20_dc_soc_info,
1912 }, {
1913 /* sentinel */
1914 }
1915};
1916MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1917
1918static int tegra_dc_parse_dt(struct tegra_dc *dc)
1919{
1920 struct device_node *np;
1921 u32 value = 0;
1922 int err;
1923
1924 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1925 if (err < 0) {
1926 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1927
1928 /*
1929 * If the nvidia,head property isn't present, try to find the
1930 * correct head number by looking up the position of this
1931 * display controller's node within the device tree. Assuming
1932 * that the nodes are ordered properly in the DTS file and
1933 * that the translation into a flattened device tree blob
1934 * preserves that ordering this will actually yield the right
1935 * head number.
1936 *
1937 * If those assumptions don't hold, this will still work for
1938 * cases where only a single display controller is used.
1939 */
1940 for_each_matching_node(np, tegra_dc_of_match) {
1941 if (np == dc->dev->of_node) {
1942 of_node_put(np);
1943 break;
1944 }
1945
1946 value++;
1947 }
1948 }
1949
1950 dc->pipe = value;
1951
1952 return 0;
1953}
1954
1955static int tegra_dc_probe(struct platform_device *pdev)
1956{
1957 const struct of_device_id *id;
1958 struct resource *regs;
1959 struct tegra_dc *dc;
1960 int err;
1961
1962 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1963 if (!dc)
1964 return -ENOMEM;
1965
1966 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1967 if (!id)
1968 return -ENODEV;
1969
1970 spin_lock_init(&dc->lock);
1971 INIT_LIST_HEAD(&dc->list);
1972 dc->dev = &pdev->dev;
1973 dc->soc = id->data;
1974
1975 err = tegra_dc_parse_dt(dc);
1976 if (err < 0)
1977 return err;
1978
1979 dc->clk = devm_clk_get(&pdev->dev, NULL);
1980 if (IS_ERR(dc->clk)) {
1981 dev_err(&pdev->dev, "failed to get clock\n");
1982 return PTR_ERR(dc->clk);
1983 }
1984
1985 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1986 if (IS_ERR(dc->rst)) {
1987 dev_err(&pdev->dev, "failed to get reset\n");
1988 return PTR_ERR(dc->rst);
1989 }
1990
1991 if (dc->soc->has_powergate) {
1992 if (dc->pipe == 0)
1993 dc->powergate = TEGRA_POWERGATE_DIS;
1994 else
1995 dc->powergate = TEGRA_POWERGATE_DISB;
1996
1997 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1998 dc->rst);
1999 if (err < 0) {
2000 dev_err(&pdev->dev, "failed to power partition: %d\n",
2001 err);
2002 return err;
2003 }
2004 } else {
2005 err = clk_prepare_enable(dc->clk);
2006 if (err < 0) {
2007 dev_err(&pdev->dev, "failed to enable clock: %d\n",
2008 err);
2009 return err;
2010 }
2011
2012 err = reset_control_deassert(dc->rst);
2013 if (err < 0) {
2014 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2015 err);
2016 return err;
2017 }
2018 }
2019
2020 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2022 if (IS_ERR(dc->regs))
2023 return PTR_ERR(dc->regs);
2024
2025 dc->irq = platform_get_irq(pdev, 0);
2026 if (dc->irq < 0) {
2027 dev_err(&pdev->dev, "failed to get IRQ\n");
2028 return -ENXIO;
2029 }
2030
2031 INIT_LIST_HEAD(&dc->client.list);
2032 dc->client.ops = &dc_client_ops;
2033 dc->client.dev = &pdev->dev;
2034
2035 err = tegra_dc_rgb_probe(dc);
2036 if (err < 0 && err != -ENODEV) {
2037 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2038 return err;
2039 }
2040
2041 err = host1x_client_register(&dc->client);
2042 if (err < 0) {
2043 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2044 err);
2045 return err;
2046 }
2047
2048 platform_set_drvdata(pdev, dc);
2049
2050 return 0;
2051}
2052
2053static int tegra_dc_remove(struct platform_device *pdev)
2054{
2055 struct tegra_dc *dc = platform_get_drvdata(pdev);
2056 int err;
2057
2058 err = host1x_client_unregister(&dc->client);
2059 if (err < 0) {
2060 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2061 err);
2062 return err;
2063 }
2064
2065 err = tegra_dc_rgb_remove(dc);
2066 if (err < 0) {
2067 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2068 return err;
2069 }
2070
2071 reset_control_assert(dc->rst);
2072
2073 if (dc->soc->has_powergate)
2074 tegra_powergate_power_off(dc->powergate);
2075
2076 clk_disable_unprepare(dc->clk);
2077
2078 return 0;
2079}
2080
2081struct platform_driver tegra_dc_driver = {
2082 .driver = {
2083 .name = "tegra-dc",
2084 .of_match_table = tegra_dc_of_match,
2085 },
2086 .probe = tegra_dc_probe,
2087 .remove = tegra_dc_remove,
2088};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/dma-mapping.h>
11#include <linux/iommu.h>
12#include <linux/interconnect.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pm_domain.h>
16#include <linux/pm_opp.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19
20#include <soc/tegra/common.h>
21#include <soc/tegra/pmc.h>
22
23#include <drm/drm_atomic.h>
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_blend.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_fourcc.h>
28#include <drm/drm_framebuffer.h>
29#include <drm/drm_vblank.h>
30
31#include "dc.h"
32#include "drm.h"
33#include "gem.h"
34#include "hub.h"
35#include "plane.h"
36
37static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
38 struct drm_crtc_state *state);
39
40static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
41{
42 stats->frames = 0;
43 stats->vblank = 0;
44 stats->underflow = 0;
45 stats->overflow = 0;
46}
47
48/* Reads the active copy of a register. */
49static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
50{
51 u32 value;
52
53 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
54 value = tegra_dc_readl(dc, offset);
55 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
56
57 return value;
58}
59
60static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
61 unsigned int offset)
62{
63 if (offset >= 0x500 && offset <= 0x638) {
64 offset = 0x000 + (offset - 0x500);
65 return plane->offset + offset;
66 }
67
68 if (offset >= 0x700 && offset <= 0x719) {
69 offset = 0x180 + (offset - 0x700);
70 return plane->offset + offset;
71 }
72
73 if (offset >= 0x800 && offset <= 0x839) {
74 offset = 0x1c0 + (offset - 0x800);
75 return plane->offset + offset;
76 }
77
78 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
79
80 return plane->offset + offset;
81}
82
83static inline u32 tegra_plane_readl(struct tegra_plane *plane,
84 unsigned int offset)
85{
86 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
87}
88
89static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
90 unsigned int offset)
91{
92 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
93}
94
95bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
96{
97 struct device_node *np = dc->dev->of_node;
98 struct of_phandle_iterator it;
99 int err;
100
101 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
102 if (it.node == dev->of_node)
103 return true;
104
105 return false;
106}
107
108/*
109 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
110 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
111 * Latching happens mmediately if the display controller is in STOP mode or
112 * on the next frame boundary otherwise.
113 *
114 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
115 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
116 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
117 * into the ACTIVE copy, either immediately if the display controller is in
118 * STOP mode, or at the next frame boundary otherwise.
119 */
120void tegra_dc_commit(struct tegra_dc *dc)
121{
122 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
123 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
124}
125
126static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
127 unsigned int bpp)
128{
129 fixed20_12 outf = dfixed_init(out);
130 fixed20_12 inf = dfixed_init(in);
131 u32 dda_inc;
132 int max;
133
134 if (v)
135 max = 15;
136 else {
137 switch (bpp) {
138 case 2:
139 max = 8;
140 break;
141
142 default:
143 WARN_ON_ONCE(1);
144 fallthrough;
145 case 4:
146 max = 4;
147 break;
148 }
149 }
150
151 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
152 inf.full -= dfixed_const(1);
153
154 dda_inc = dfixed_div(inf, outf);
155 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
156
157 return dda_inc;
158}
159
160static inline u32 compute_initial_dda(unsigned int in)
161{
162 fixed20_12 inf = dfixed_init(in);
163 return dfixed_frac(inf);
164}
165
166static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
167{
168 u32 background[3] = {
169 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
170 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
171 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
172 };
173 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
174 BLEND_COLOR_KEY_NONE;
175 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
176 struct tegra_plane_state *state;
177 u32 blending[2];
178 unsigned int i;
179
180 /* disable blending for non-overlapping case */
181 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
182 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
183
184 state = to_tegra_plane_state(plane->base.state);
185
186 if (state->opaque) {
187 /*
188 * Since custom fix-weight blending isn't utilized and weight
189 * of top window is set to max, we can enforce dependent
190 * blending which in this case results in transparent bottom
191 * window if top window is opaque and if top window enables
192 * alpha blending, then bottom window is getting alpha value
193 * of 1 minus the sum of alpha components of the overlapping
194 * plane.
195 */
196 background[0] |= BLEND_CONTROL_DEPENDENT;
197 background[1] |= BLEND_CONTROL_DEPENDENT;
198
199 /*
200 * The region where three windows overlap is the intersection
201 * of the two regions where two windows overlap. It contributes
202 * to the area if all of the windows on top of it have an alpha
203 * component.
204 */
205 switch (state->base.normalized_zpos) {
206 case 0:
207 if (state->blending[0].alpha &&
208 state->blending[1].alpha)
209 background[2] |= BLEND_CONTROL_DEPENDENT;
210 break;
211
212 case 1:
213 background[2] |= BLEND_CONTROL_DEPENDENT;
214 break;
215 }
216 } else {
217 /*
218 * Enable alpha blending if pixel format has an alpha
219 * component.
220 */
221 foreground |= BLEND_CONTROL_ALPHA;
222
223 /*
224 * If any of the windows on top of this window is opaque, it
225 * will completely conceal this window within that area. If
226 * top window has an alpha component, it is blended over the
227 * bottom window.
228 */
229 for (i = 0; i < 2; i++) {
230 if (state->blending[i].alpha &&
231 state->blending[i].top)
232 background[i] |= BLEND_CONTROL_DEPENDENT;
233 }
234
235 switch (state->base.normalized_zpos) {
236 case 0:
237 if (state->blending[0].alpha &&
238 state->blending[1].alpha)
239 background[2] |= BLEND_CONTROL_DEPENDENT;
240 break;
241
242 case 1:
243 /*
244 * When both middle and topmost windows have an alpha,
245 * these windows a mixed together and then the result
246 * is blended over the bottom window.
247 */
248 if (state->blending[0].alpha &&
249 state->blending[0].top)
250 background[2] |= BLEND_CONTROL_ALPHA;
251
252 if (state->blending[1].alpha &&
253 state->blending[1].top)
254 background[2] |= BLEND_CONTROL_ALPHA;
255 break;
256 }
257 }
258
259 switch (state->base.normalized_zpos) {
260 case 0:
261 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
262 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
263 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
264 break;
265
266 case 1:
267 /*
268 * If window B / C is topmost, then X / Y registers are
269 * matching the order of blending[...] state indices,
270 * otherwise a swap is required.
271 */
272 if (!state->blending[0].top && state->blending[1].top) {
273 blending[0] = foreground;
274 blending[1] = background[1];
275 } else {
276 blending[0] = background[0];
277 blending[1] = foreground;
278 }
279
280 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
283 break;
284
285 case 2:
286 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
287 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
288 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
289 break;
290 }
291}
292
293static void tegra_plane_setup_blending(struct tegra_plane *plane,
294 const struct tegra_dc_window *window)
295{
296 u32 value;
297
298 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
299 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
300 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
301 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
302
303 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
304 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
305 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
306 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
307
308 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
309 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
310}
311
312static bool
313tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
314 const struct tegra_dc_window *window)
315{
316 struct tegra_dc *dc = plane->dc;
317
318 if (window->src.w == window->dst.w)
319 return false;
320
321 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
322 return false;
323
324 return true;
325}
326
327static bool
328tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
329 const struct tegra_dc_window *window)
330{
331 struct tegra_dc *dc = plane->dc;
332
333 if (window->src.h == window->dst.h)
334 return false;
335
336 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
337 return false;
338
339 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
340 return false;
341
342 return true;
343}
344
345static void tegra_dc_setup_window(struct tegra_plane *plane,
346 const struct tegra_dc_window *window)
347{
348 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
349 struct tegra_dc *dc = plane->dc;
350 unsigned int planes;
351 u32 value;
352 bool yuv;
353
354 /*
355 * For YUV planar modes, the number of bytes per pixel takes into
356 * account only the luma component and therefore is 1.
357 */
358 yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL);
359 if (!yuv)
360 bpp = window->bits_per_pixel / 8;
361 else
362 bpp = (planes > 1) ? 1 : 2;
363
364 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
365 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
366
367 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
368 tegra_plane_writel(plane, value, DC_WIN_POSITION);
369
370 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
371 tegra_plane_writel(plane, value, DC_WIN_SIZE);
372
373 h_offset = window->src.x * bpp;
374 v_offset = window->src.y;
375 h_size = window->src.w * bpp;
376 v_size = window->src.h;
377
378 if (window->reflect_x)
379 h_offset += (window->src.w - 1) * bpp;
380
381 if (window->reflect_y)
382 v_offset += window->src.h - 1;
383
384 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
385 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
386
387 /*
388 * For DDA computations the number of bytes per pixel for YUV planar
389 * modes needs to take into account all Y, U and V components.
390 */
391 if (yuv && planes > 1)
392 bpp = 2;
393
394 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
395 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
396
397 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
398 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
399
400 h_dda = compute_initial_dda(window->src.x);
401 v_dda = compute_initial_dda(window->src.y);
402
403 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
404 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
405
406 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
407 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
408
409 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
410
411 if (yuv && planes > 1) {
412 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
413
414 if (planes > 2)
415 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
416
417 value = window->stride[1] << 16 | window->stride[0];
418 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
419 } else {
420 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
421 }
422
423 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
424 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
425
426 if (dc->soc->supports_block_linear) {
427 unsigned long height = window->tiling.value;
428
429 switch (window->tiling.mode) {
430 case TEGRA_BO_TILING_MODE_PITCH:
431 value = DC_WINBUF_SURFACE_KIND_PITCH;
432 break;
433
434 case TEGRA_BO_TILING_MODE_TILED:
435 value = DC_WINBUF_SURFACE_KIND_TILED;
436 break;
437
438 case TEGRA_BO_TILING_MODE_BLOCK:
439 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
440 DC_WINBUF_SURFACE_KIND_BLOCK;
441 break;
442 }
443
444 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
445 } else {
446 switch (window->tiling.mode) {
447 case TEGRA_BO_TILING_MODE_PITCH:
448 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
449 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
450 break;
451
452 case TEGRA_BO_TILING_MODE_TILED:
453 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
454 DC_WIN_BUFFER_ADDR_MODE_TILE;
455 break;
456
457 case TEGRA_BO_TILING_MODE_BLOCK:
458 /*
459 * No need to handle this here because ->atomic_check
460 * will already have filtered it out.
461 */
462 break;
463 }
464
465 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
466 }
467
468 value = WIN_ENABLE;
469
470 if (yuv) {
471 /* setup default colorspace conversion coefficients */
472 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
473 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
474 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
475 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
476 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
477 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
478 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
479 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
480
481 value |= CSC_ENABLE;
482 } else if (window->bits_per_pixel < 24) {
483 value |= COLOR_EXPAND;
484 }
485
486 if (window->reflect_x)
487 value |= H_DIRECTION;
488
489 if (window->reflect_y)
490 value |= V_DIRECTION;
491
492 if (tegra_plane_use_horizontal_filtering(plane, window)) {
493 /*
494 * Enable horizontal 6-tap filter and set filtering
495 * coefficients to the default values defined in TRM.
496 */
497 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
498 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
499 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
500 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
501 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
502 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
503 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
504 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
505 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
506 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
507 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
508 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
509 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
510 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
511 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
512 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
513
514 value |= H_FILTER;
515 }
516
517 if (tegra_plane_use_vertical_filtering(plane, window)) {
518 unsigned int i, k;
519
520 /*
521 * Enable vertical 2-tap filter and set filtering
522 * coefficients to the default values defined in TRM.
523 */
524 for (i = 0, k = 128; i < 16; i++, k -= 8)
525 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
526
527 value |= V_FILTER;
528 }
529
530 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
531
532 if (dc->soc->has_legacy_blending)
533 tegra_plane_setup_blending_legacy(plane);
534 else
535 tegra_plane_setup_blending(plane, window);
536}
537
538static const u32 tegra20_primary_formats[] = {
539 DRM_FORMAT_ARGB4444,
540 DRM_FORMAT_ARGB1555,
541 DRM_FORMAT_RGB565,
542 DRM_FORMAT_RGBA5551,
543 DRM_FORMAT_ABGR8888,
544 DRM_FORMAT_ARGB8888,
545 /* non-native formats */
546 DRM_FORMAT_XRGB1555,
547 DRM_FORMAT_RGBX5551,
548 DRM_FORMAT_XBGR8888,
549 DRM_FORMAT_XRGB8888,
550};
551
552static const u64 tegra20_modifiers[] = {
553 DRM_FORMAT_MOD_LINEAR,
554 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
555 DRM_FORMAT_MOD_INVALID
556};
557
558static const u32 tegra114_primary_formats[] = {
559 DRM_FORMAT_ARGB4444,
560 DRM_FORMAT_ARGB1555,
561 DRM_FORMAT_RGB565,
562 DRM_FORMAT_RGBA5551,
563 DRM_FORMAT_ABGR8888,
564 DRM_FORMAT_ARGB8888,
565 /* new on Tegra114 */
566 DRM_FORMAT_ABGR4444,
567 DRM_FORMAT_ABGR1555,
568 DRM_FORMAT_BGRA5551,
569 DRM_FORMAT_XRGB1555,
570 DRM_FORMAT_RGBX5551,
571 DRM_FORMAT_XBGR1555,
572 DRM_FORMAT_BGRX5551,
573 DRM_FORMAT_BGR565,
574 DRM_FORMAT_BGRA8888,
575 DRM_FORMAT_RGBA8888,
576 DRM_FORMAT_XRGB8888,
577 DRM_FORMAT_XBGR8888,
578};
579
580static const u32 tegra124_primary_formats[] = {
581 DRM_FORMAT_ARGB4444,
582 DRM_FORMAT_ARGB1555,
583 DRM_FORMAT_RGB565,
584 DRM_FORMAT_RGBA5551,
585 DRM_FORMAT_ABGR8888,
586 DRM_FORMAT_ARGB8888,
587 /* new on Tegra114 */
588 DRM_FORMAT_ABGR4444,
589 DRM_FORMAT_ABGR1555,
590 DRM_FORMAT_BGRA5551,
591 DRM_FORMAT_XRGB1555,
592 DRM_FORMAT_RGBX5551,
593 DRM_FORMAT_XBGR1555,
594 DRM_FORMAT_BGRX5551,
595 DRM_FORMAT_BGR565,
596 DRM_FORMAT_BGRA8888,
597 DRM_FORMAT_RGBA8888,
598 DRM_FORMAT_XRGB8888,
599 DRM_FORMAT_XBGR8888,
600 /* new on Tegra124 */
601 DRM_FORMAT_RGBX8888,
602 DRM_FORMAT_BGRX8888,
603};
604
605static const u64 tegra124_modifiers[] = {
606 DRM_FORMAT_MOD_LINEAR,
607 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
608 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
609 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
610 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
611 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
612 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
613 DRM_FORMAT_MOD_INVALID
614};
615
616static int tegra_plane_atomic_check(struct drm_plane *plane,
617 struct drm_atomic_state *state)
618{
619 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
620 plane);
621 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
622 unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
623 DRM_MODE_REFLECT_X |
624 DRM_MODE_REFLECT_Y;
625 unsigned int rotation = new_plane_state->rotation;
626 struct tegra_bo_tiling *tiling = &plane_state->tiling;
627 struct tegra_plane *tegra = to_tegra_plane(plane);
628 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
629 int err;
630
631 plane_state->peak_memory_bandwidth = 0;
632 plane_state->avg_memory_bandwidth = 0;
633
634 /* no need for further checks if the plane is being disabled */
635 if (!new_plane_state->crtc) {
636 plane_state->total_peak_memory_bandwidth = 0;
637 return 0;
638 }
639
640 err = tegra_plane_format(new_plane_state->fb->format->format,
641 &plane_state->format,
642 &plane_state->swap);
643 if (err < 0)
644 return err;
645
646 /*
647 * Tegra20 and Tegra30 are special cases here because they support
648 * only variants of specific formats with an alpha component, but not
649 * the corresponding opaque formats. However, the opaque formats can
650 * be emulated by disabling alpha blending for the plane.
651 */
652 if (dc->soc->has_legacy_blending) {
653 err = tegra_plane_setup_legacy_state(tegra, plane_state);
654 if (err < 0)
655 return err;
656 }
657
658 err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
659 if (err < 0)
660 return err;
661
662 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
663 !dc->soc->supports_block_linear) {
664 DRM_ERROR("hardware doesn't support block linear mode\n");
665 return -EINVAL;
666 }
667
668 /*
669 * Older userspace used custom BO flag in order to specify the Y
670 * reflection, while modern userspace uses the generic DRM rotation
671 * property in order to achieve the same result. The legacy BO flag
672 * duplicates the DRM rotation property when both are set.
673 */
674 if (tegra_fb_is_bottom_up(new_plane_state->fb))
675 rotation |= DRM_MODE_REFLECT_Y;
676
677 rotation = drm_rotation_simplify(rotation, supported_rotation);
678
679 if (rotation & DRM_MODE_REFLECT_X)
680 plane_state->reflect_x = true;
681 else
682 plane_state->reflect_x = false;
683
684 if (rotation & DRM_MODE_REFLECT_Y)
685 plane_state->reflect_y = true;
686 else
687 plane_state->reflect_y = false;
688
689 /*
690 * Tegra doesn't support different strides for U and V planes so we
691 * error out if the user tries to display a framebuffer with such a
692 * configuration.
693 */
694 if (new_plane_state->fb->format->num_planes > 2) {
695 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
696 DRM_ERROR("unsupported UV-plane configuration\n");
697 return -EINVAL;
698 }
699 }
700
701 err = tegra_plane_state_add(tegra, new_plane_state);
702 if (err < 0)
703 return err;
704
705 return 0;
706}
707
708static void tegra_plane_atomic_disable(struct drm_plane *plane,
709 struct drm_atomic_state *state)
710{
711 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
712 plane);
713 struct tegra_plane *p = to_tegra_plane(plane);
714 u32 value;
715
716 /* rien ne va plus */
717 if (!old_state || !old_state->crtc)
718 return;
719
720 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
721 value &= ~WIN_ENABLE;
722 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
723}
724
725static void tegra_plane_atomic_update(struct drm_plane *plane,
726 struct drm_atomic_state *state)
727{
728 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
729 plane);
730 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
731 struct drm_framebuffer *fb = new_state->fb;
732 struct tegra_plane *p = to_tegra_plane(plane);
733 struct tegra_dc_window window;
734 unsigned int i;
735
736 /* rien ne va plus */
737 if (!new_state->crtc || !new_state->fb)
738 return;
739
740 if (!new_state->visible)
741 return tegra_plane_atomic_disable(plane, state);
742
743 memset(&window, 0, sizeof(window));
744 window.src.x = new_state->src.x1 >> 16;
745 window.src.y = new_state->src.y1 >> 16;
746 window.src.w = drm_rect_width(&new_state->src) >> 16;
747 window.src.h = drm_rect_height(&new_state->src) >> 16;
748 window.dst.x = new_state->dst.x1;
749 window.dst.y = new_state->dst.y1;
750 window.dst.w = drm_rect_width(&new_state->dst);
751 window.dst.h = drm_rect_height(&new_state->dst);
752 window.bits_per_pixel = fb->format->cpp[0] * 8;
753 window.reflect_x = tegra_plane_state->reflect_x;
754 window.reflect_y = tegra_plane_state->reflect_y;
755
756 /* copy from state */
757 window.zpos = new_state->normalized_zpos;
758 window.tiling = tegra_plane_state->tiling;
759 window.format = tegra_plane_state->format;
760 window.swap = tegra_plane_state->swap;
761
762 for (i = 0; i < fb->format->num_planes; i++) {
763 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
764
765 /*
766 * Tegra uses a shared stride for UV planes. Framebuffers are
767 * already checked for this in the tegra_plane_atomic_check()
768 * function, so it's safe to ignore the V-plane pitch here.
769 */
770 if (i < 2)
771 window.stride[i] = fb->pitches[i];
772 }
773
774 tegra_dc_setup_window(p, &window);
775}
776
777static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
778 .prepare_fb = tegra_plane_prepare_fb,
779 .cleanup_fb = tegra_plane_cleanup_fb,
780 .atomic_check = tegra_plane_atomic_check,
781 .atomic_disable = tegra_plane_atomic_disable,
782 .atomic_update = tegra_plane_atomic_update,
783};
784
785static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
786{
787 /*
788 * Ideally this would use drm_crtc_mask(), but that would require the
789 * CRTC to already be in the mode_config's list of CRTCs. However, it
790 * will only be added to that list in the drm_crtc_init_with_planes()
791 * (in tegra_dc_init()), which in turn requires registration of these
792 * planes. So we have ourselves a nice little chicken and egg problem
793 * here.
794 *
795 * We work around this by manually creating the mask from the number
796 * of CRTCs that have been registered, and should therefore always be
797 * the same as drm_crtc_index() after registration.
798 */
799 return 1 << drm->mode_config.num_crtc;
800}
801
802static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
803 struct tegra_dc *dc)
804{
805 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
806 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
807 struct tegra_plane *plane;
808 unsigned int num_formats;
809 const u64 *modifiers;
810 const u32 *formats;
811 int err;
812
813 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
814 if (!plane)
815 return ERR_PTR(-ENOMEM);
816
817 /* Always use window A as primary window */
818 plane->offset = 0xa00;
819 plane->index = 0;
820 plane->dc = dc;
821
822 num_formats = dc->soc->num_primary_formats;
823 formats = dc->soc->primary_formats;
824 modifiers = dc->soc->modifiers;
825
826 err = tegra_plane_interconnect_init(plane);
827 if (err) {
828 kfree(plane);
829 return ERR_PTR(err);
830 }
831
832 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
833 &tegra_plane_funcs, formats,
834 num_formats, modifiers, type, NULL);
835 if (err < 0) {
836 kfree(plane);
837 return ERR_PTR(err);
838 }
839
840 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
841 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
842
843 err = drm_plane_create_rotation_property(&plane->base,
844 DRM_MODE_ROTATE_0,
845 DRM_MODE_ROTATE_0 |
846 DRM_MODE_ROTATE_180 |
847 DRM_MODE_REFLECT_X |
848 DRM_MODE_REFLECT_Y);
849 if (err < 0)
850 dev_err(dc->dev, "failed to create rotation property: %d\n",
851 err);
852
853 return &plane->base;
854}
855
856static const u32 tegra_legacy_cursor_plane_formats[] = {
857 DRM_FORMAT_RGBA8888,
858};
859
860static const u32 tegra_cursor_plane_formats[] = {
861 DRM_FORMAT_ARGB8888,
862};
863
864static int tegra_cursor_atomic_check(struct drm_plane *plane,
865 struct drm_atomic_state *state)
866{
867 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
868 plane);
869 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
870 struct tegra_plane *tegra = to_tegra_plane(plane);
871 int err;
872
873 plane_state->peak_memory_bandwidth = 0;
874 plane_state->avg_memory_bandwidth = 0;
875
876 /* no need for further checks if the plane is being disabled */
877 if (!new_plane_state->crtc) {
878 plane_state->total_peak_memory_bandwidth = 0;
879 return 0;
880 }
881
882 /* scaling not supported for cursor */
883 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
884 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
885 return -EINVAL;
886
887 /* only square cursors supported */
888 if (new_plane_state->src_w != new_plane_state->src_h)
889 return -EINVAL;
890
891 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
892 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
893 return -EINVAL;
894
895 err = tegra_plane_state_add(tegra, new_plane_state);
896 if (err < 0)
897 return err;
898
899 return 0;
900}
901
902static void __tegra_cursor_atomic_update(struct drm_plane *plane,
903 struct drm_plane_state *new_state)
904{
905 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
906 struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
907 struct tegra_drm *tegra = plane->dev->dev_private;
908#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
909 u64 dma_mask = *dc->dev->dma_mask;
910#endif
911 unsigned int x, y;
912 u32 value = 0;
913
914 /* rien ne va plus */
915 if (!new_state->crtc || !new_state->fb)
916 return;
917
918 /*
919 * Legacy display supports hardware clipping of the cursor, but
920 * nvdisplay relies on software to clip the cursor to the screen.
921 */
922 if (!dc->soc->has_nvdisplay)
923 value |= CURSOR_CLIP_DISPLAY;
924
925 switch (new_state->crtc_w) {
926 case 32:
927 value |= CURSOR_SIZE_32x32;
928 break;
929
930 case 64:
931 value |= CURSOR_SIZE_64x64;
932 break;
933
934 case 128:
935 value |= CURSOR_SIZE_128x128;
936 break;
937
938 case 256:
939 value |= CURSOR_SIZE_256x256;
940 break;
941
942 default:
943 WARN(1, "cursor size %ux%u not supported\n",
944 new_state->crtc_w, new_state->crtc_h);
945 return;
946 }
947
948 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
949 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
950
951#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
952 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32);
953 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
954#endif
955
956 /* enable cursor and set blend mode */
957 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
958 value |= CURSOR_ENABLE;
959 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
960
961 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
962 value &= ~CURSOR_DST_BLEND_MASK;
963 value &= ~CURSOR_SRC_BLEND_MASK;
964
965 if (dc->soc->has_nvdisplay)
966 value &= ~CURSOR_COMPOSITION_MODE_XOR;
967 else
968 value |= CURSOR_MODE_NORMAL;
969
970 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
971 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
972 value |= CURSOR_ALPHA;
973 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
974
975 /* nvdisplay relies on software for clipping */
976 if (dc->soc->has_nvdisplay) {
977 struct drm_rect src;
978
979 x = new_state->dst.x1;
980 y = new_state->dst.y1;
981
982 drm_rect_fp_to_int(&src, &new_state->src);
983
984 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask);
985 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
986
987 value = (drm_rect_height(&src) & tegra->vmask) << 16 |
988 (drm_rect_width(&src) & tegra->hmask);
989 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
990 } else {
991 x = new_state->crtc_x;
992 y = new_state->crtc_y;
993 }
994
995 /* position the cursor */
996 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask);
997 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
998}
999
1000static void tegra_cursor_atomic_update(struct drm_plane *plane,
1001 struct drm_atomic_state *state)
1002{
1003 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1004
1005 __tegra_cursor_atomic_update(plane, new_state);
1006}
1007
1008static void tegra_cursor_atomic_disable(struct drm_plane *plane,
1009 struct drm_atomic_state *state)
1010{
1011 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
1012 plane);
1013 struct tegra_dc *dc;
1014 u32 value;
1015
1016 /* rien ne va plus */
1017 if (!old_state || !old_state->crtc)
1018 return;
1019
1020 dc = to_tegra_dc(old_state->crtc);
1021
1022 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1023 value &= ~CURSOR_ENABLE;
1024 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1025}
1026
1027static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state)
1028{
1029 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1030 struct drm_crtc_state *crtc_state;
1031 int min_scale, max_scale;
1032 int err;
1033
1034 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc);
1035 if (WARN_ON(!crtc_state))
1036 return -EINVAL;
1037
1038 if (!crtc_state->active)
1039 return -EINVAL;
1040
1041 if (plane->state->crtc != new_state->crtc ||
1042 plane->state->src_w != new_state->src_w ||
1043 plane->state->src_h != new_state->src_h ||
1044 plane->state->crtc_w != new_state->crtc_w ||
1045 plane->state->crtc_h != new_state->crtc_h ||
1046 plane->state->fb != new_state->fb ||
1047 plane->state->fb == NULL)
1048 return -EINVAL;
1049
1050 min_scale = (1 << 16) / 8;
1051 max_scale = (8 << 16) / 1;
1052
1053 err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale,
1054 true, true);
1055 if (err < 0)
1056 return err;
1057
1058 if (new_state->visible != plane->state->visible)
1059 return -EINVAL;
1060
1061 return 0;
1062}
1063
1064static void tegra_cursor_atomic_async_update(struct drm_plane *plane,
1065 struct drm_atomic_state *state)
1066{
1067 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1068 struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
1069
1070 plane->state->src_x = new_state->src_x;
1071 plane->state->src_y = new_state->src_y;
1072 plane->state->crtc_x = new_state->crtc_x;
1073 plane->state->crtc_y = new_state->crtc_y;
1074
1075 if (new_state->visible) {
1076 struct tegra_plane *p = to_tegra_plane(plane);
1077 u32 value;
1078
1079 __tegra_cursor_atomic_update(plane, new_state);
1080
1081 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE;
1082 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1083 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1084
1085 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ;
1086 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1087 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1088 }
1089}
1090
1091static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
1092 .prepare_fb = tegra_plane_prepare_fb,
1093 .cleanup_fb = tegra_plane_cleanup_fb,
1094 .atomic_check = tegra_cursor_atomic_check,
1095 .atomic_update = tegra_cursor_atomic_update,
1096 .atomic_disable = tegra_cursor_atomic_disable,
1097 .atomic_async_check = tegra_cursor_atomic_async_check,
1098 .atomic_async_update = tegra_cursor_atomic_async_update,
1099};
1100
1101static const uint64_t linear_modifiers[] = {
1102 DRM_FORMAT_MOD_LINEAR,
1103 DRM_FORMAT_MOD_INVALID
1104};
1105
1106static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
1107 struct tegra_dc *dc)
1108{
1109 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1110 struct tegra_plane *plane;
1111 unsigned int num_formats;
1112 const u32 *formats;
1113 int err;
1114
1115 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1116 if (!plane)
1117 return ERR_PTR(-ENOMEM);
1118
1119 /*
1120 * This index is kind of fake. The cursor isn't a regular plane, but
1121 * its update and activation request bits in DC_CMD_STATE_CONTROL do
1122 * use the same programming. Setting this fake index here allows the
1123 * code in tegra_add_plane_state() to do the right thing without the
1124 * need to special-casing the cursor plane.
1125 */
1126 plane->index = 6;
1127 plane->dc = dc;
1128
1129 if (!dc->soc->has_nvdisplay) {
1130 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats);
1131 formats = tegra_legacy_cursor_plane_formats;
1132
1133 err = tegra_plane_interconnect_init(plane);
1134 if (err) {
1135 kfree(plane);
1136 return ERR_PTR(err);
1137 }
1138 } else {
1139 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
1140 formats = tegra_cursor_plane_formats;
1141 }
1142
1143 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1144 &tegra_plane_funcs, formats,
1145 num_formats, linear_modifiers,
1146 DRM_PLANE_TYPE_CURSOR, NULL);
1147 if (err < 0) {
1148 kfree(plane);
1149 return ERR_PTR(err);
1150 }
1151
1152 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1153 drm_plane_create_zpos_immutable_property(&plane->base, 255);
1154
1155 return &plane->base;
1156}
1157
1158static const u32 tegra20_overlay_formats[] = {
1159 DRM_FORMAT_ARGB4444,
1160 DRM_FORMAT_ARGB1555,
1161 DRM_FORMAT_RGB565,
1162 DRM_FORMAT_RGBA5551,
1163 DRM_FORMAT_ABGR8888,
1164 DRM_FORMAT_ARGB8888,
1165 /* non-native formats */
1166 DRM_FORMAT_XRGB1555,
1167 DRM_FORMAT_RGBX5551,
1168 DRM_FORMAT_XBGR8888,
1169 DRM_FORMAT_XRGB8888,
1170 /* planar formats */
1171 DRM_FORMAT_UYVY,
1172 DRM_FORMAT_YUYV,
1173 DRM_FORMAT_YUV420,
1174 DRM_FORMAT_YUV422,
1175};
1176
1177static const u32 tegra114_overlay_formats[] = {
1178 DRM_FORMAT_ARGB4444,
1179 DRM_FORMAT_ARGB1555,
1180 DRM_FORMAT_RGB565,
1181 DRM_FORMAT_RGBA5551,
1182 DRM_FORMAT_ABGR8888,
1183 DRM_FORMAT_ARGB8888,
1184 /* new on Tegra114 */
1185 DRM_FORMAT_ABGR4444,
1186 DRM_FORMAT_ABGR1555,
1187 DRM_FORMAT_BGRA5551,
1188 DRM_FORMAT_XRGB1555,
1189 DRM_FORMAT_RGBX5551,
1190 DRM_FORMAT_XBGR1555,
1191 DRM_FORMAT_BGRX5551,
1192 DRM_FORMAT_BGR565,
1193 DRM_FORMAT_BGRA8888,
1194 DRM_FORMAT_RGBA8888,
1195 DRM_FORMAT_XRGB8888,
1196 DRM_FORMAT_XBGR8888,
1197 /* planar formats */
1198 DRM_FORMAT_UYVY,
1199 DRM_FORMAT_YUYV,
1200 DRM_FORMAT_YUV420,
1201 DRM_FORMAT_YUV422,
1202 /* semi-planar formats */
1203 DRM_FORMAT_NV12,
1204 DRM_FORMAT_NV21,
1205 DRM_FORMAT_NV16,
1206 DRM_FORMAT_NV61,
1207 DRM_FORMAT_NV24,
1208 DRM_FORMAT_NV42,
1209};
1210
1211static const u32 tegra124_overlay_formats[] = {
1212 DRM_FORMAT_ARGB4444,
1213 DRM_FORMAT_ARGB1555,
1214 DRM_FORMAT_RGB565,
1215 DRM_FORMAT_RGBA5551,
1216 DRM_FORMAT_ABGR8888,
1217 DRM_FORMAT_ARGB8888,
1218 /* new on Tegra114 */
1219 DRM_FORMAT_ABGR4444,
1220 DRM_FORMAT_ABGR1555,
1221 DRM_FORMAT_BGRA5551,
1222 DRM_FORMAT_XRGB1555,
1223 DRM_FORMAT_RGBX5551,
1224 DRM_FORMAT_XBGR1555,
1225 DRM_FORMAT_BGRX5551,
1226 DRM_FORMAT_BGR565,
1227 DRM_FORMAT_BGRA8888,
1228 DRM_FORMAT_RGBA8888,
1229 DRM_FORMAT_XRGB8888,
1230 DRM_FORMAT_XBGR8888,
1231 /* new on Tegra124 */
1232 DRM_FORMAT_RGBX8888,
1233 DRM_FORMAT_BGRX8888,
1234 /* planar formats */
1235 DRM_FORMAT_UYVY,
1236 DRM_FORMAT_YUYV,
1237 DRM_FORMAT_YVYU,
1238 DRM_FORMAT_VYUY,
1239 DRM_FORMAT_YUV420, /* YU12 */
1240 DRM_FORMAT_YUV422, /* YU16 */
1241 DRM_FORMAT_YUV444, /* YU24 */
1242 /* semi-planar formats */
1243 DRM_FORMAT_NV12,
1244 DRM_FORMAT_NV21,
1245 DRM_FORMAT_NV16,
1246 DRM_FORMAT_NV61,
1247 DRM_FORMAT_NV24,
1248 DRM_FORMAT_NV42,
1249};
1250
1251static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1252 struct tegra_dc *dc,
1253 unsigned int index,
1254 bool cursor)
1255{
1256 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1257 struct tegra_plane *plane;
1258 unsigned int num_formats;
1259 enum drm_plane_type type;
1260 const u32 *formats;
1261 int err;
1262
1263 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1264 if (!plane)
1265 return ERR_PTR(-ENOMEM);
1266
1267 plane->offset = 0xa00 + 0x200 * index;
1268 plane->index = index;
1269 plane->dc = dc;
1270
1271 num_formats = dc->soc->num_overlay_formats;
1272 formats = dc->soc->overlay_formats;
1273
1274 err = tegra_plane_interconnect_init(plane);
1275 if (err) {
1276 kfree(plane);
1277 return ERR_PTR(err);
1278 }
1279
1280 if (!cursor)
1281 type = DRM_PLANE_TYPE_OVERLAY;
1282 else
1283 type = DRM_PLANE_TYPE_CURSOR;
1284
1285 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1286 &tegra_plane_funcs, formats,
1287 num_formats, linear_modifiers,
1288 type, NULL);
1289 if (err < 0) {
1290 kfree(plane);
1291 return ERR_PTR(err);
1292 }
1293
1294 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1295 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1296
1297 err = drm_plane_create_rotation_property(&plane->base,
1298 DRM_MODE_ROTATE_0,
1299 DRM_MODE_ROTATE_0 |
1300 DRM_MODE_ROTATE_180 |
1301 DRM_MODE_REFLECT_X |
1302 DRM_MODE_REFLECT_Y);
1303 if (err < 0)
1304 dev_err(dc->dev, "failed to create rotation property: %d\n",
1305 err);
1306
1307 return &plane->base;
1308}
1309
1310static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1311 struct tegra_dc *dc)
1312{
1313 struct drm_plane *plane, *primary = NULL;
1314 unsigned int i, j;
1315
1316 for (i = 0; i < dc->soc->num_wgrps; i++) {
1317 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1318
1319 if (wgrp->dc == dc->pipe) {
1320 for (j = 0; j < wgrp->num_windows; j++) {
1321 unsigned int index = wgrp->windows[j];
1322
1323 plane = tegra_shared_plane_create(drm, dc,
1324 wgrp->index,
1325 index);
1326 if (IS_ERR(plane))
1327 return plane;
1328
1329 /*
1330 * Choose the first shared plane owned by this
1331 * head as the primary plane.
1332 */
1333 if (!primary) {
1334 plane->type = DRM_PLANE_TYPE_PRIMARY;
1335 primary = plane;
1336 }
1337 }
1338 }
1339 }
1340
1341 return primary;
1342}
1343
1344static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1345 struct tegra_dc *dc)
1346{
1347 struct drm_plane *planes[2], *primary;
1348 unsigned int planes_num;
1349 unsigned int i;
1350 int err;
1351
1352 primary = tegra_primary_plane_create(drm, dc);
1353 if (IS_ERR(primary))
1354 return primary;
1355
1356 if (dc->soc->supports_cursor)
1357 planes_num = 2;
1358 else
1359 planes_num = 1;
1360
1361 for (i = 0; i < planes_num; i++) {
1362 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1363 false);
1364 if (IS_ERR(planes[i])) {
1365 err = PTR_ERR(planes[i]);
1366
1367 while (i--)
1368 planes[i]->funcs->destroy(planes[i]);
1369
1370 primary->funcs->destroy(primary);
1371 return ERR_PTR(err);
1372 }
1373 }
1374
1375 return primary;
1376}
1377
1378static void tegra_dc_destroy(struct drm_crtc *crtc)
1379{
1380 drm_crtc_cleanup(crtc);
1381}
1382
1383static void tegra_crtc_reset(struct drm_crtc *crtc)
1384{
1385 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1386
1387 if (crtc->state)
1388 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1389
1390 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1391}
1392
1393static struct drm_crtc_state *
1394tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1395{
1396 struct tegra_dc_state *state = to_dc_state(crtc->state);
1397 struct tegra_dc_state *copy;
1398
1399 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1400 if (!copy)
1401 return NULL;
1402
1403 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1404 copy->clk = state->clk;
1405 copy->pclk = state->pclk;
1406 copy->div = state->div;
1407 copy->planes = state->planes;
1408
1409 return ©->base;
1410}
1411
1412static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1413 struct drm_crtc_state *state)
1414{
1415 __drm_atomic_helper_crtc_destroy_state(state);
1416 kfree(state);
1417}
1418
1419#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1420
1421static const struct debugfs_reg32 tegra_dc_regs[] = {
1422 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1423 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1424 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1425 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1426 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1427 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1428 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1429 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1430 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1431 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1432 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1433 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1434 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1435 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1436 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1437 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1438 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1439 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1440 DEBUGFS_REG32(DC_CMD_INT_MASK),
1441 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1442 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1443 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1444 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1445 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1446 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1447 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1448 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1449 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1450 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1451 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1452 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1453 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1454 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1455 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1456 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1457 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1458 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1459 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1460 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1461 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1462 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1463 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1464 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1465 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1466 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1467 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1468 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1469 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1470 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1471 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1472 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1473 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1474 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1475 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1476 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1477 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1478 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1479 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1480 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1481 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1482 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1483 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1484 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1485 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1486 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1487 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1488 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1489 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1490 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1491 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1492 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1493 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1494 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1495 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1496 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1497 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1498 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1499 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1500 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1501 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1502 DEBUGFS_REG32(DC_DISP_ACTIVE),
1503 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1504 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1505 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1506 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1507 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1508 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1509 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1510 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1511 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1512 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1513 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1514 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1515 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1516 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1517 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1518 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1519 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1520 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1521 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1522 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1523 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1524 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1525 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1526 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1527 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1528 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1529 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1530 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1531 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1532 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1533 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1534 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1535 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1536 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1537 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1538 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1539 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1540 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1541 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1542 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1543 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1544 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1545 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1546 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1547 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1548 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1549 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1550 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1551 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1552 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1553 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1554 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1555 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1556 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1557 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1558 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1559 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1560 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1561 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1562 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1563 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1564 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1565 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1566 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1567 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1568 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1569 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1570 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1571 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1572 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1573 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1574 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1575 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1576 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1577 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1578 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1579 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1580 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1581 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1582 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1583 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1584 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1585 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1586 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1587 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1588 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1589 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1590 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1591 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1592 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1593 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1594 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1595 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1596 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1597 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1598 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1599 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1600 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1601 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1602 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1603 DEBUGFS_REG32(DC_WIN_POSITION),
1604 DEBUGFS_REG32(DC_WIN_SIZE),
1605 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1606 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1607 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1608 DEBUGFS_REG32(DC_WIN_DDA_INC),
1609 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1610 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1611 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1612 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1613 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1614 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1615 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1616 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1617 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1618 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1619 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1620 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1621 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1622 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1623 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1624 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1625 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1626 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1627 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1628 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1629 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1630 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1631 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1632 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1633 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1634};
1635
1636static int tegra_dc_show_regs(struct seq_file *s, void *data)
1637{
1638 struct drm_info_node *node = s->private;
1639 struct tegra_dc *dc = node->info_ent->data;
1640 unsigned int i;
1641 int err = 0;
1642
1643 drm_modeset_lock(&dc->base.mutex, NULL);
1644
1645 if (!dc->base.state->active) {
1646 err = -EBUSY;
1647 goto unlock;
1648 }
1649
1650 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1651 unsigned int offset = tegra_dc_regs[i].offset;
1652
1653 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1654 offset, tegra_dc_readl(dc, offset));
1655 }
1656
1657unlock:
1658 drm_modeset_unlock(&dc->base.mutex);
1659 return err;
1660}
1661
1662static int tegra_dc_show_crc(struct seq_file *s, void *data)
1663{
1664 struct drm_info_node *node = s->private;
1665 struct tegra_dc *dc = node->info_ent->data;
1666 int err = 0;
1667 u32 value;
1668
1669 drm_modeset_lock(&dc->base.mutex, NULL);
1670
1671 if (!dc->base.state->active) {
1672 err = -EBUSY;
1673 goto unlock;
1674 }
1675
1676 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1677 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1678 tegra_dc_commit(dc);
1679
1680 drm_crtc_wait_one_vblank(&dc->base);
1681 drm_crtc_wait_one_vblank(&dc->base);
1682
1683 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1684 seq_printf(s, "%08x\n", value);
1685
1686 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1687
1688unlock:
1689 drm_modeset_unlock(&dc->base.mutex);
1690 return err;
1691}
1692
1693static int tegra_dc_show_stats(struct seq_file *s, void *data)
1694{
1695 struct drm_info_node *node = s->private;
1696 struct tegra_dc *dc = node->info_ent->data;
1697
1698 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1699 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1700 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1701 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1702
1703 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);
1704 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);
1705 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);
1706 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);
1707
1708 return 0;
1709}
1710
1711static struct drm_info_list debugfs_files[] = {
1712 { "regs", tegra_dc_show_regs, 0, NULL },
1713 { "crc", tegra_dc_show_crc, 0, NULL },
1714 { "stats", tegra_dc_show_stats, 0, NULL },
1715};
1716
1717static int tegra_dc_late_register(struct drm_crtc *crtc)
1718{
1719 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1720 struct drm_minor *minor = crtc->dev->primary;
1721 struct dentry *root;
1722 struct tegra_dc *dc = to_tegra_dc(crtc);
1723
1724#ifdef CONFIG_DEBUG_FS
1725 root = crtc->debugfs_entry;
1726#else
1727 root = NULL;
1728#endif
1729
1730 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1731 GFP_KERNEL);
1732 if (!dc->debugfs_files)
1733 return -ENOMEM;
1734
1735 for (i = 0; i < count; i++)
1736 dc->debugfs_files[i].data = dc;
1737
1738 drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1739
1740 return 0;
1741}
1742
1743static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1744{
1745 unsigned int count = ARRAY_SIZE(debugfs_files);
1746 struct drm_minor *minor = crtc->dev->primary;
1747 struct tegra_dc *dc = to_tegra_dc(crtc);
1748
1749 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1750 kfree(dc->debugfs_files);
1751 dc->debugfs_files = NULL;
1752}
1753
1754static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1755{
1756 struct tegra_dc *dc = to_tegra_dc(crtc);
1757
1758 /* XXX vblank syncpoints don't work with nvdisplay yet */
1759 if (dc->syncpt && !dc->soc->has_nvdisplay)
1760 return host1x_syncpt_read(dc->syncpt);
1761
1762 /* fallback to software emulated VBLANK counter */
1763 return (u32)drm_crtc_vblank_count(&dc->base);
1764}
1765
1766static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1767{
1768 struct tegra_dc *dc = to_tegra_dc(crtc);
1769 u32 value;
1770
1771 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1772 value |= VBLANK_INT;
1773 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1774
1775 return 0;
1776}
1777
1778static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1779{
1780 struct tegra_dc *dc = to_tegra_dc(crtc);
1781 u32 value;
1782
1783 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1784 value &= ~VBLANK_INT;
1785 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1786}
1787
1788static const struct drm_crtc_funcs tegra_crtc_funcs = {
1789 .page_flip = drm_atomic_helper_page_flip,
1790 .set_config = drm_atomic_helper_set_config,
1791 .destroy = tegra_dc_destroy,
1792 .reset = tegra_crtc_reset,
1793 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1794 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1795 .late_register = tegra_dc_late_register,
1796 .early_unregister = tegra_dc_early_unregister,
1797 .get_vblank_counter = tegra_dc_get_vblank_counter,
1798 .enable_vblank = tegra_dc_enable_vblank,
1799 .disable_vblank = tegra_dc_disable_vblank,
1800};
1801
1802static int tegra_dc_set_timings(struct tegra_dc *dc,
1803 struct drm_display_mode *mode)
1804{
1805 unsigned int h_ref_to_sync = 1;
1806 unsigned int v_ref_to_sync = 1;
1807 unsigned long value;
1808
1809 if (!dc->soc->has_nvdisplay) {
1810 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1811
1812 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1813 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1814 }
1815
1816 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1817 ((mode->hsync_end - mode->hsync_start) << 0);
1818 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1819
1820 value = ((mode->vtotal - mode->vsync_end) << 16) |
1821 ((mode->htotal - mode->hsync_end) << 0);
1822 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1823
1824 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1825 ((mode->hsync_start - mode->hdisplay) << 0);
1826 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1827
1828 value = (mode->vdisplay << 16) | mode->hdisplay;
1829 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1830
1831 return 0;
1832}
1833
1834/**
1835 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1836 * state
1837 * @dc: display controller
1838 * @crtc_state: CRTC atomic state
1839 * @clk: parent clock for display controller
1840 * @pclk: pixel clock
1841 * @div: shift clock divider
1842 *
1843 * Returns:
1844 * 0 on success or a negative error-code on failure.
1845 */
1846int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1847 struct drm_crtc_state *crtc_state,
1848 struct clk *clk, unsigned long pclk,
1849 unsigned int div)
1850{
1851 struct tegra_dc_state *state = to_dc_state(crtc_state);
1852
1853 if (!clk_has_parent(dc->clk, clk))
1854 return -EINVAL;
1855
1856 state->clk = clk;
1857 state->pclk = pclk;
1858 state->div = div;
1859
1860 return 0;
1861}
1862
1863static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
1864 struct tegra_dc_state *state)
1865{
1866 unsigned long rate, pstate;
1867 struct dev_pm_opp *opp;
1868 int err;
1869
1870 if (!dc->has_opp_table)
1871 return;
1872
1873 /* calculate actual pixel clock rate which depends on internal divider */
1874 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
1875
1876 /* find suitable OPP for the rate */
1877 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
1878
1879 /*
1880 * Very high resolution modes may results in a clock rate that is
1881 * above the characterized maximum. In this case it's okay to fall
1882 * back to the characterized maximum.
1883 */
1884 if (opp == ERR_PTR(-ERANGE))
1885 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
1886
1887 if (IS_ERR(opp)) {
1888 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",
1889 rate, opp);
1890 return;
1891 }
1892
1893 pstate = dev_pm_opp_get_required_pstate(opp, 0);
1894 dev_pm_opp_put(opp);
1895
1896 /*
1897 * The minimum core voltage depends on the pixel clock rate (which
1898 * depends on internal clock divider of the CRTC) and not on the
1899 * rate of the display controller clock. This is why we're not using
1900 * dev_pm_opp_set_rate() API and instead controlling the power domain
1901 * directly.
1902 */
1903 err = dev_pm_genpd_set_performance_state(dc->dev, pstate);
1904 if (err)
1905 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",
1906 pstate, err);
1907}
1908
1909static void tegra_dc_set_clock_rate(struct tegra_dc *dc,
1910 struct tegra_dc_state *state)
1911{
1912 int err;
1913
1914 err = clk_set_parent(dc->clk, state->clk);
1915 if (err < 0)
1916 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1917
1918 /*
1919 * Outputs may not want to change the parent clock rate. This is only
1920 * relevant to Tegra20 where only a single display PLL is available.
1921 * Since that PLL would typically be used for HDMI, an internal LVDS
1922 * panel would need to be driven by some other clock such as PLL_P
1923 * which is shared with other peripherals. Changing the clock rate
1924 * should therefore be avoided.
1925 */
1926 if (state->pclk > 0) {
1927 err = clk_set_rate(state->clk, state->pclk);
1928 if (err < 0)
1929 dev_err(dc->dev,
1930 "failed to set clock rate to %lu Hz\n",
1931 state->pclk);
1932
1933 err = clk_set_rate(dc->clk, state->pclk);
1934 if (err < 0)
1935 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1936 dc->clk, state->pclk, err);
1937 }
1938
1939 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1940 state->div);
1941 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1942
1943 tegra_dc_update_voltage_state(dc, state);
1944}
1945
1946static void tegra_dc_stop(struct tegra_dc *dc)
1947{
1948 u32 value;
1949
1950 /* stop the display controller */
1951 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1952 value &= ~DISP_CTRL_MODE_MASK;
1953 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1954
1955 tegra_dc_commit(dc);
1956}
1957
1958static bool tegra_dc_idle(struct tegra_dc *dc)
1959{
1960 u32 value;
1961
1962 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1963
1964 return (value & DISP_CTRL_MODE_MASK) == 0;
1965}
1966
1967static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1968{
1969 timeout = jiffies + msecs_to_jiffies(timeout);
1970
1971 while (time_before(jiffies, timeout)) {
1972 if (tegra_dc_idle(dc))
1973 return 0;
1974
1975 usleep_range(1000, 2000);
1976 }
1977
1978 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1979 return -ETIMEDOUT;
1980}
1981
1982static void
1983tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc,
1984 struct drm_atomic_state *state,
1985 bool prepare_bandwidth_transition)
1986{
1987 const struct tegra_plane_state *old_tegra_state, *new_tegra_state;
1988 u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw;
1989 const struct drm_plane_state *old_plane_state;
1990 const struct drm_crtc_state *old_crtc_state;
1991 struct tegra_dc_window window, old_window;
1992 struct tegra_dc *dc = to_tegra_dc(crtc);
1993 struct tegra_plane *tegra;
1994 struct drm_plane *plane;
1995
1996 if (dc->soc->has_nvdisplay)
1997 return;
1998
1999 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
2000
2001 if (!crtc->state->active) {
2002 if (!old_crtc_state->active)
2003 return;
2004
2005 /*
2006 * When CRTC is disabled on DPMS, the state of attached planes
2007 * is kept unchanged. Hence we need to enforce removal of the
2008 * bandwidths from the ICC paths.
2009 */
2010 drm_atomic_crtc_for_each_plane(plane, crtc) {
2011 tegra = to_tegra_plane(plane);
2012
2013 icc_set_bw(tegra->icc_mem, 0, 0);
2014 icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2015 }
2016
2017 return;
2018 }
2019
2020 for_each_old_plane_in_state(old_crtc_state->state, plane,
2021 old_plane_state, i) {
2022 old_tegra_state = to_const_tegra_plane_state(old_plane_state);
2023 new_tegra_state = to_const_tegra_plane_state(plane->state);
2024 tegra = to_tegra_plane(plane);
2025
2026 /*
2027 * We're iterating over the global atomic state and it contains
2028 * planes from another CRTC, hence we need to filter out the
2029 * planes unrelated to this CRTC.
2030 */
2031 if (tegra->dc != dc)
2032 continue;
2033
2034 new_avg_bw = new_tegra_state->avg_memory_bandwidth;
2035 old_avg_bw = old_tegra_state->avg_memory_bandwidth;
2036
2037 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth;
2038 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth;
2039
2040 /*
2041 * See the comment related to !crtc->state->active above,
2042 * which explains why bandwidths need to be updated when
2043 * CRTC is turning ON.
2044 */
2045 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw &&
2046 old_crtc_state->active)
2047 continue;
2048
2049 window.src.h = drm_rect_height(&plane->state->src) >> 16;
2050 window.dst.h = drm_rect_height(&plane->state->dst);
2051
2052 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16;
2053 old_window.dst.h = drm_rect_height(&old_plane_state->dst);
2054
2055 /*
2056 * During the preparation phase (atomic_begin), the memory
2057 * freq should go high before the DC changes are committed
2058 * if bandwidth requirement goes up, otherwise memory freq
2059 * should to stay high if BW requirement goes down. The
2060 * opposite applies to the completion phase (post_commit).
2061 */
2062 if (prepare_bandwidth_transition) {
2063 new_avg_bw = max(old_avg_bw, new_avg_bw);
2064 new_peak_bw = max(old_peak_bw, new_peak_bw);
2065
2066 if (tegra_plane_use_vertical_filtering(tegra, &old_window))
2067 window = old_window;
2068 }
2069
2070 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw);
2071
2072 if (tegra_plane_use_vertical_filtering(tegra, &window))
2073 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw);
2074 else
2075 icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2076 }
2077}
2078
2079static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
2080 struct drm_atomic_state *state)
2081{
2082 struct tegra_dc *dc = to_tegra_dc(crtc);
2083 u32 value;
2084 int err;
2085
2086 if (!tegra_dc_idle(dc)) {
2087 tegra_dc_stop(dc);
2088
2089 /*
2090 * Ignore the return value, there isn't anything useful to do
2091 * in case this fails.
2092 */
2093 tegra_dc_wait_idle(dc, 100);
2094 }
2095
2096 /*
2097 * This should really be part of the RGB encoder driver, but clearing
2098 * these bits has the side-effect of stopping the display controller.
2099 * When that happens no VBLANK interrupts will be raised. At the same
2100 * time the encoder is disabled before the display controller, so the
2101 * above code is always going to timeout waiting for the controller
2102 * to go idle.
2103 *
2104 * Given the close coupling between the RGB encoder and the display
2105 * controller doing it here is still kind of okay. None of the other
2106 * encoder drivers require these bits to be cleared.
2107 *
2108 * XXX: Perhaps given that the display controller is switched off at
2109 * this point anyway maybe clearing these bits isn't even useful for
2110 * the RGB encoder?
2111 */
2112 if (dc->rgb) {
2113 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2114 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2115 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
2116 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2117 }
2118
2119 tegra_dc_stats_reset(&dc->stats);
2120 drm_crtc_vblank_off(crtc);
2121
2122 spin_lock_irq(&crtc->dev->event_lock);
2123
2124 if (crtc->state->event) {
2125 drm_crtc_send_vblank_event(crtc, crtc->state->event);
2126 crtc->state->event = NULL;
2127 }
2128
2129 spin_unlock_irq(&crtc->dev->event_lock);
2130
2131 err = host1x_client_suspend(&dc->client);
2132 if (err < 0)
2133 dev_err(dc->dev, "failed to suspend: %d\n", err);
2134
2135 if (dc->has_opp_table) {
2136 err = dev_pm_genpd_set_performance_state(dc->dev, 0);
2137 if (err)
2138 dev_err(dc->dev,
2139 "failed to clear power domain state: %d\n", err);
2140 }
2141}
2142
2143static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
2144 struct drm_atomic_state *state)
2145{
2146 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2147 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
2148 struct tegra_dc *dc = to_tegra_dc(crtc);
2149 u32 value;
2150 int err;
2151
2152 /* apply PLL changes */
2153 tegra_dc_set_clock_rate(dc, crtc_state);
2154
2155 err = host1x_client_resume(&dc->client);
2156 if (err < 0) {
2157 dev_err(dc->dev, "failed to resume: %d\n", err);
2158 return;
2159 }
2160
2161 /* initialize display controller */
2162 if (dc->syncpt) {
2163 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
2164
2165 if (dc->soc->has_nvdisplay)
2166 enable = 1 << 31;
2167 else
2168 enable = 1 << 8;
2169
2170 value = SYNCPT_CNTRL_NO_STALL;
2171 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2172
2173 value = enable | syncpt;
2174 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
2175 }
2176
2177 if (dc->soc->has_nvdisplay) {
2178 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2179 DSC_OBUF_UF_INT;
2180 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2181
2182 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2183 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
2184 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
2185 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
2186 VBLANK_INT | FRAME_END_INT;
2187 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2188
2189 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
2190 FRAME_END_INT;
2191 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2192
2193 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
2194 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2195
2196 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
2197 } else {
2198 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2199 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2200 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2201
2202 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2203 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2204 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2205
2206 /* initialize timer */
2207 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
2208 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
2209 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
2210
2211 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
2212 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
2213 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
2214
2215 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2216 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2217 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2218
2219 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2220 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2221 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2222 }
2223
2224 if (dc->soc->supports_background_color)
2225 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
2226 else
2227 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
2228
2229 /* apply pixel clock changes */
2230 if (!dc->soc->has_nvdisplay) {
2231 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1;
2232 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
2233 }
2234
2235 /* program display mode */
2236 tegra_dc_set_timings(dc, mode);
2237
2238 /* interlacing isn't supported yet, so disable it */
2239 if (dc->soc->supports_interlacing) {
2240 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
2241 value &= ~INTERLACE_ENABLE;
2242 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
2243 }
2244
2245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
2246 value &= ~DISP_CTRL_MODE_MASK;
2247 value |= DISP_CTRL_MODE_C_DISPLAY;
2248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
2249
2250 if (!dc->soc->has_nvdisplay) {
2251 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2252 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2253 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
2254 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2255 }
2256
2257 /* enable underflow reporting and display red for missing pixels */
2258 if (dc->soc->has_nvdisplay) {
2259 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
2260 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
2261 }
2262
2263 if (dc->rgb) {
2264 /* XXX: parameterize? */
2265 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
2266 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
2267 }
2268
2269 tegra_dc_commit(dc);
2270
2271 drm_crtc_vblank_on(crtc);
2272}
2273
2274static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
2275 struct drm_atomic_state *state)
2276{
2277 unsigned long flags;
2278
2279 tegra_crtc_update_memory_bandwidth(crtc, state, true);
2280
2281 if (crtc->state->event) {
2282 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2283
2284 if (drm_crtc_vblank_get(crtc) != 0)
2285 drm_crtc_send_vblank_event(crtc, crtc->state->event);
2286 else
2287 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
2288
2289 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2290
2291 crtc->state->event = NULL;
2292 }
2293}
2294
2295static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
2296 struct drm_atomic_state *state)
2297{
2298 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
2299 crtc);
2300 struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
2301 struct tegra_dc *dc = to_tegra_dc(crtc);
2302 u32 value;
2303
2304 value = dc_state->planes << 8 | GENERAL_UPDATE;
2305 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2306 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2307
2308 value = dc_state->planes | GENERAL_ACT_REQ;
2309 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2310 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2311}
2312
2313static bool tegra_plane_is_cursor(const struct drm_plane_state *state)
2314{
2315 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc;
2316 const struct drm_format_info *fmt = state->fb->format;
2317 unsigned int src_w = drm_rect_width(&state->src) >> 16;
2318 unsigned int dst_w = drm_rect_width(&state->dst);
2319
2320 if (state->plane->type != DRM_PLANE_TYPE_CURSOR)
2321 return false;
2322
2323 if (soc->supports_cursor)
2324 return true;
2325
2326 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256)
2327 return false;
2328
2329 return true;
2330}
2331
2332static unsigned long
2333tegra_plane_overlap_mask(struct drm_crtc_state *state,
2334 const struct drm_plane_state *plane_state)
2335{
2336 const struct drm_plane_state *other_state;
2337 const struct tegra_plane *tegra;
2338 unsigned long overlap_mask = 0;
2339 struct drm_plane *plane;
2340 struct drm_rect rect;
2341
2342 if (!plane_state->visible || !plane_state->fb)
2343 return 0;
2344
2345 /*
2346 * Data-prefetch FIFO will easily help to overcome temporal memory
2347 * pressure if other plane overlaps with the cursor plane.
2348 */
2349 if (tegra_plane_is_cursor(plane_state))
2350 return 0;
2351
2352 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) {
2353 rect = plane_state->dst;
2354
2355 tegra = to_tegra_plane(other_state->plane);
2356
2357 if (!other_state->visible || !other_state->fb)
2358 continue;
2359
2360 /*
2361 * Ignore cursor plane overlaps because it's not practical to
2362 * assume that it contributes to the bandwidth in overlapping
2363 * area if window width is small.
2364 */
2365 if (tegra_plane_is_cursor(other_state))
2366 continue;
2367
2368 if (drm_rect_intersect(&rect, &other_state->dst))
2369 overlap_mask |= BIT(tegra->index);
2370 }
2371
2372 return overlap_mask;
2373}
2374
2375static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc,
2376 struct drm_atomic_state *state)
2377{
2378 ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask;
2379 u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {};
2380 bool all_planes_overlap_simultaneously = true;
2381 const struct tegra_plane_state *tegra_state;
2382 const struct drm_plane_state *plane_state;
2383 struct tegra_dc *dc = to_tegra_dc(crtc);
2384 const struct drm_crtc_state *old_state;
2385 struct drm_crtc_state *new_state;
2386 struct tegra_plane *tegra;
2387 struct drm_plane *plane;
2388
2389 /*
2390 * The nv-display uses shared planes. The algorithm below assumes
2391 * maximum 3 planes per-CRTC, this assumption isn't applicable to
2392 * the nv-display. Note that T124 support has additional windows,
2393 * but currently they aren't supported by the driver.
2394 */
2395 if (dc->soc->has_nvdisplay)
2396 return 0;
2397
2398 new_state = drm_atomic_get_new_crtc_state(state, crtc);
2399 old_state = drm_atomic_get_old_crtc_state(state, crtc);
2400
2401 /*
2402 * For overlapping planes pixel's data is fetched for each plane at
2403 * the same time, hence bandwidths are accumulated in this case.
2404 * This needs to be taken into account for calculating total bandwidth
2405 * consumed by all planes.
2406 *
2407 * Here we get the overlapping state of each plane, which is a
2408 * bitmask of plane indices telling with what planes there is an
2409 * overlap. Note that bitmask[plane] includes BIT(plane) in order
2410 * to make further code nicer and simpler.
2411 */
2412 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2413 tegra_state = to_const_tegra_plane_state(plane_state);
2414 tegra = to_tegra_plane(plane);
2415
2416 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM))
2417 return -EINVAL;
2418
2419 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth;
2420 mask = tegra_plane_overlap_mask(new_state, plane_state);
2421 overlap_mask[tegra->index] = mask;
2422
2423 if (hweight_long(mask) != 3)
2424 all_planes_overlap_simultaneously = false;
2425 }
2426
2427 /*
2428 * Then we calculate maximum bandwidth of each plane state.
2429 * The bandwidth includes the plane BW + BW of the "simultaneously"
2430 * overlapping planes, where "simultaneously" means areas where DC
2431 * fetches from the planes simultaneously during of scan-out process.
2432 *
2433 * For example, if plane A overlaps with planes B and C, but B and C
2434 * don't overlap, then the peak bandwidth will be either in area where
2435 * A-and-B or A-and-C planes overlap.
2436 *
2437 * The plane_peak_bw[] contains peak memory bandwidth values of
2438 * each plane, this information is needed by interconnect provider
2439 * in order to set up latency allowance based on the peak BW, see
2440 * tegra_crtc_update_memory_bandwidth().
2441 */
2442 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2443 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0;
2444
2445 /*
2446 * Note that plane's atomic check doesn't touch the
2447 * total_peak_memory_bandwidth of enabled plane, hence the
2448 * current state contains the old bandwidth state from the
2449 * previous CRTC commit.
2450 */
2451 tegra_state = to_const_tegra_plane_state(plane_state);
2452 tegra = to_tegra_plane(plane);
2453
2454 for_each_set_bit(i, &overlap_mask[tegra->index], 3) {
2455 if (i == tegra->index)
2456 continue;
2457
2458 if (all_planes_overlap_simultaneously)
2459 overlap_bw += plane_peak_bw[i];
2460 else
2461 overlap_bw = max(overlap_bw, plane_peak_bw[i]);
2462 }
2463
2464 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw;
2465 old_peak_bw = tegra_state->total_peak_memory_bandwidth;
2466
2467 /*
2468 * If plane's peak bandwidth changed (for example plane isn't
2469 * overlapped anymore) and plane isn't in the atomic state,
2470 * then add plane to the state in order to have the bandwidth
2471 * updated.
2472 */
2473 if (old_peak_bw != new_peak_bw) {
2474 struct tegra_plane_state *new_tegra_state;
2475 struct drm_plane_state *new_plane_state;
2476
2477 new_plane_state = drm_atomic_get_plane_state(state, plane);
2478 if (IS_ERR(new_plane_state))
2479 return PTR_ERR(new_plane_state);
2480
2481 new_tegra_state = to_tegra_plane_state(new_plane_state);
2482 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw;
2483 }
2484 }
2485
2486 return 0;
2487}
2488
2489static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
2490 struct drm_atomic_state *state)
2491{
2492 int err;
2493
2494 err = tegra_crtc_calculate_memory_bandwidth(crtc, state);
2495 if (err)
2496 return err;
2497
2498 return 0;
2499}
2500
2501void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc,
2502 struct drm_atomic_state *state)
2503{
2504 /*
2505 * Display bandwidth is allowed to go down only once hardware state
2506 * is known to be armed, i.e. state was committed and VBLANK event
2507 * received.
2508 */
2509 tegra_crtc_update_memory_bandwidth(crtc, state, false);
2510}
2511
2512static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
2513 .atomic_check = tegra_crtc_atomic_check,
2514 .atomic_begin = tegra_crtc_atomic_begin,
2515 .atomic_flush = tegra_crtc_atomic_flush,
2516 .atomic_enable = tegra_crtc_atomic_enable,
2517 .atomic_disable = tegra_crtc_atomic_disable,
2518};
2519
2520static irqreturn_t tegra_dc_irq(int irq, void *data)
2521{
2522 struct tegra_dc *dc = data;
2523 unsigned long status;
2524
2525 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2526 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2527
2528 if (status & FRAME_END_INT) {
2529 /*
2530 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
2531 */
2532 dc->stats.frames_total++;
2533 dc->stats.frames++;
2534 }
2535
2536 if (status & VBLANK_INT) {
2537 /*
2538 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
2539 */
2540 drm_crtc_handle_vblank(&dc->base);
2541 dc->stats.vblank_total++;
2542 dc->stats.vblank++;
2543 }
2544
2545 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2546 /*
2547 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2548 */
2549 dc->stats.underflow_total++;
2550 dc->stats.underflow++;
2551 }
2552
2553 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2554 /*
2555 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2556 */
2557 dc->stats.overflow_total++;
2558 dc->stats.overflow++;
2559 }
2560
2561 if (status & HEAD_UF_INT) {
2562 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2563 dc->stats.underflow_total++;
2564 dc->stats.underflow++;
2565 }
2566
2567 return IRQ_HANDLED;
2568}
2569
2570static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2571{
2572 unsigned int i;
2573
2574 if (!dc->soc->wgrps)
2575 return true;
2576
2577 for (i = 0; i < dc->soc->num_wgrps; i++) {
2578 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2579
2580 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2581 return true;
2582 }
2583
2584 return false;
2585}
2586
2587static int tegra_dc_early_init(struct host1x_client *client)
2588{
2589 struct drm_device *drm = dev_get_drvdata(client->host);
2590 struct tegra_drm *tegra = drm->dev_private;
2591
2592 tegra->num_crtcs++;
2593
2594 return 0;
2595}
2596
2597static int tegra_dc_init(struct host1x_client *client)
2598{
2599 struct drm_device *drm = dev_get_drvdata(client->host);
2600 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2601 struct tegra_dc *dc = host1x_client_to_dc(client);
2602 struct tegra_drm *tegra = drm->dev_private;
2603 struct drm_plane *primary = NULL;
2604 struct drm_plane *cursor = NULL;
2605 int err;
2606
2607 /*
2608 * DC has been reset by now, so VBLANK syncpoint can be released
2609 * for general use.
2610 */
2611 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
2612
2613 /*
2614 * XXX do not register DCs with no window groups because we cannot
2615 * assign a primary plane to them, which in turn will cause KMS to
2616 * crash.
2617 */
2618 if (!tegra_dc_has_window_groups(dc))
2619 return 0;
2620
2621 /*
2622 * Set the display hub as the host1x client parent for the display
2623 * controller. This is needed for the runtime reference counting that
2624 * ensures the display hub is always powered when any of the display
2625 * controllers are.
2626 */
2627 if (dc->soc->has_nvdisplay)
2628 client->parent = &tegra->hub->client;
2629
2630 dc->syncpt = host1x_syncpt_request(client, flags);
2631 if (!dc->syncpt)
2632 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2633
2634 err = host1x_client_iommu_attach(client);
2635 if (err < 0 && err != -ENODEV) {
2636 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2637 return err;
2638 }
2639
2640 if (dc->soc->wgrps)
2641 primary = tegra_dc_add_shared_planes(drm, dc);
2642 else
2643 primary = tegra_dc_add_planes(drm, dc);
2644
2645 if (IS_ERR(primary)) {
2646 err = PTR_ERR(primary);
2647 goto cleanup;
2648 }
2649
2650 if (dc->soc->supports_cursor) {
2651 cursor = tegra_dc_cursor_plane_create(drm, dc);
2652 if (IS_ERR(cursor)) {
2653 err = PTR_ERR(cursor);
2654 goto cleanup;
2655 }
2656 } else {
2657 /* dedicate one overlay to mouse cursor */
2658 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2659 if (IS_ERR(cursor)) {
2660 err = PTR_ERR(cursor);
2661 goto cleanup;
2662 }
2663 }
2664
2665 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2666 &tegra_crtc_funcs, NULL);
2667 if (err < 0)
2668 goto cleanup;
2669
2670 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2671
2672 /*
2673 * Keep track of the minimum pitch alignment across all display
2674 * controllers.
2675 */
2676 if (dc->soc->pitch_align > tegra->pitch_align)
2677 tegra->pitch_align = dc->soc->pitch_align;
2678
2679 /* track maximum resolution */
2680 if (dc->soc->has_nvdisplay)
2681 drm->mode_config.max_width = drm->mode_config.max_height = 16384;
2682 else
2683 drm->mode_config.max_width = drm->mode_config.max_height = 4096;
2684
2685 err = tegra_dc_rgb_init(drm, dc);
2686 if (err < 0 && err != -ENODEV) {
2687 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2688 goto cleanup;
2689 }
2690
2691 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2692 dev_name(dc->dev), dc);
2693 if (err < 0) {
2694 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2695 err);
2696 goto cleanup;
2697 }
2698
2699 /*
2700 * Inherit the DMA parameters (such as maximum segment size) from the
2701 * parent host1x device.
2702 */
2703 client->dev->dma_parms = client->host->dma_parms;
2704
2705 return 0;
2706
2707cleanup:
2708 if (!IS_ERR_OR_NULL(cursor))
2709 drm_plane_cleanup(cursor);
2710
2711 if (!IS_ERR(primary))
2712 drm_plane_cleanup(primary);
2713
2714 host1x_client_iommu_detach(client);
2715 host1x_syncpt_put(dc->syncpt);
2716
2717 return err;
2718}
2719
2720static int tegra_dc_exit(struct host1x_client *client)
2721{
2722 struct tegra_dc *dc = host1x_client_to_dc(client);
2723 int err;
2724
2725 if (!tegra_dc_has_window_groups(dc))
2726 return 0;
2727
2728 /* avoid a dangling pointer just in case this disappears */
2729 client->dev->dma_parms = NULL;
2730
2731 devm_free_irq(dc->dev, dc->irq, dc);
2732
2733 err = tegra_dc_rgb_exit(dc);
2734 if (err) {
2735 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2736 return err;
2737 }
2738
2739 host1x_client_iommu_detach(client);
2740 host1x_syncpt_put(dc->syncpt);
2741
2742 return 0;
2743}
2744
2745static int tegra_dc_late_exit(struct host1x_client *client)
2746{
2747 struct drm_device *drm = dev_get_drvdata(client->host);
2748 struct tegra_drm *tegra = drm->dev_private;
2749
2750 tegra->num_crtcs--;
2751
2752 return 0;
2753}
2754
2755static int tegra_dc_runtime_suspend(struct host1x_client *client)
2756{
2757 struct tegra_dc *dc = host1x_client_to_dc(client);
2758 struct device *dev = client->dev;
2759 int err;
2760
2761 err = reset_control_assert(dc->rst);
2762 if (err < 0) {
2763 dev_err(dev, "failed to assert reset: %d\n", err);
2764 return err;
2765 }
2766
2767 if (dc->soc->has_powergate)
2768 tegra_powergate_power_off(dc->powergate);
2769
2770 clk_disable_unprepare(dc->clk);
2771 pm_runtime_put_sync(dev);
2772
2773 return 0;
2774}
2775
2776static int tegra_dc_runtime_resume(struct host1x_client *client)
2777{
2778 struct tegra_dc *dc = host1x_client_to_dc(client);
2779 struct device *dev = client->dev;
2780 int err;
2781
2782 err = pm_runtime_resume_and_get(dev);
2783 if (err < 0) {
2784 dev_err(dev, "failed to get runtime PM: %d\n", err);
2785 return err;
2786 }
2787
2788 if (dc->soc->has_powergate) {
2789 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2790 dc->rst);
2791 if (err < 0) {
2792 dev_err(dev, "failed to power partition: %d\n", err);
2793 goto put_rpm;
2794 }
2795 } else {
2796 err = clk_prepare_enable(dc->clk);
2797 if (err < 0) {
2798 dev_err(dev, "failed to enable clock: %d\n", err);
2799 goto put_rpm;
2800 }
2801
2802 err = reset_control_deassert(dc->rst);
2803 if (err < 0) {
2804 dev_err(dev, "failed to deassert reset: %d\n", err);
2805 goto disable_clk;
2806 }
2807 }
2808
2809 return 0;
2810
2811disable_clk:
2812 clk_disable_unprepare(dc->clk);
2813put_rpm:
2814 pm_runtime_put_sync(dev);
2815 return err;
2816}
2817
2818static const struct host1x_client_ops dc_client_ops = {
2819 .early_init = tegra_dc_early_init,
2820 .init = tegra_dc_init,
2821 .exit = tegra_dc_exit,
2822 .late_exit = tegra_dc_late_exit,
2823 .suspend = tegra_dc_runtime_suspend,
2824 .resume = tegra_dc_runtime_resume,
2825};
2826
2827static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2828 .supports_background_color = false,
2829 .supports_interlacing = false,
2830 .supports_cursor = false,
2831 .supports_block_linear = false,
2832 .supports_sector_layout = false,
2833 .has_legacy_blending = true,
2834 .pitch_align = 8,
2835 .has_powergate = false,
2836 .coupled_pm = true,
2837 .has_nvdisplay = false,
2838 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2839 .primary_formats = tegra20_primary_formats,
2840 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2841 .overlay_formats = tegra20_overlay_formats,
2842 .modifiers = tegra20_modifiers,
2843 .has_win_a_without_filters = true,
2844 .has_win_b_vfilter_mem_client = true,
2845 .has_win_c_without_vert_filter = true,
2846 .plane_tiled_memory_bandwidth_x2 = false,
2847 .has_pll_d2_out0 = false,
2848};
2849
2850static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2851 .supports_background_color = false,
2852 .supports_interlacing = false,
2853 .supports_cursor = false,
2854 .supports_block_linear = false,
2855 .supports_sector_layout = false,
2856 .has_legacy_blending = true,
2857 .pitch_align = 8,
2858 .has_powergate = false,
2859 .coupled_pm = false,
2860 .has_nvdisplay = false,
2861 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2862 .primary_formats = tegra20_primary_formats,
2863 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2864 .overlay_formats = tegra20_overlay_formats,
2865 .modifiers = tegra20_modifiers,
2866 .has_win_a_without_filters = false,
2867 .has_win_b_vfilter_mem_client = true,
2868 .has_win_c_without_vert_filter = false,
2869 .plane_tiled_memory_bandwidth_x2 = true,
2870 .has_pll_d2_out0 = true,
2871};
2872
2873static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2874 .supports_background_color = false,
2875 .supports_interlacing = false,
2876 .supports_cursor = false,
2877 .supports_block_linear = false,
2878 .supports_sector_layout = false,
2879 .has_legacy_blending = true,
2880 .pitch_align = 64,
2881 .has_powergate = true,
2882 .coupled_pm = false,
2883 .has_nvdisplay = false,
2884 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2885 .primary_formats = tegra114_primary_formats,
2886 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2887 .overlay_formats = tegra114_overlay_formats,
2888 .modifiers = tegra20_modifiers,
2889 .has_win_a_without_filters = false,
2890 .has_win_b_vfilter_mem_client = false,
2891 .has_win_c_without_vert_filter = false,
2892 .plane_tiled_memory_bandwidth_x2 = true,
2893 .has_pll_d2_out0 = true,
2894};
2895
2896static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2897 .supports_background_color = true,
2898 .supports_interlacing = true,
2899 .supports_cursor = true,
2900 .supports_block_linear = true,
2901 .supports_sector_layout = false,
2902 .has_legacy_blending = false,
2903 .pitch_align = 64,
2904 .has_powergate = true,
2905 .coupled_pm = false,
2906 .has_nvdisplay = false,
2907 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2908 .primary_formats = tegra124_primary_formats,
2909 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2910 .overlay_formats = tegra124_overlay_formats,
2911 .modifiers = tegra124_modifiers,
2912 .has_win_a_without_filters = false,
2913 .has_win_b_vfilter_mem_client = false,
2914 .has_win_c_without_vert_filter = false,
2915 .plane_tiled_memory_bandwidth_x2 = false,
2916 .has_pll_d2_out0 = true,
2917};
2918
2919static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2920 .supports_background_color = true,
2921 .supports_interlacing = true,
2922 .supports_cursor = true,
2923 .supports_block_linear = true,
2924 .supports_sector_layout = false,
2925 .has_legacy_blending = false,
2926 .pitch_align = 64,
2927 .has_powergate = true,
2928 .coupled_pm = false,
2929 .has_nvdisplay = false,
2930 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2931 .primary_formats = tegra114_primary_formats,
2932 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2933 .overlay_formats = tegra114_overlay_formats,
2934 .modifiers = tegra124_modifiers,
2935 .has_win_a_without_filters = false,
2936 .has_win_b_vfilter_mem_client = false,
2937 .has_win_c_without_vert_filter = false,
2938 .plane_tiled_memory_bandwidth_x2 = false,
2939 .has_pll_d2_out0 = true,
2940};
2941
2942static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2943 {
2944 .index = 0,
2945 .dc = 0,
2946 .windows = (const unsigned int[]) { 0 },
2947 .num_windows = 1,
2948 }, {
2949 .index = 1,
2950 .dc = 1,
2951 .windows = (const unsigned int[]) { 1 },
2952 .num_windows = 1,
2953 }, {
2954 .index = 2,
2955 .dc = 1,
2956 .windows = (const unsigned int[]) { 2 },
2957 .num_windows = 1,
2958 }, {
2959 .index = 3,
2960 .dc = 2,
2961 .windows = (const unsigned int[]) { 3 },
2962 .num_windows = 1,
2963 }, {
2964 .index = 4,
2965 .dc = 2,
2966 .windows = (const unsigned int[]) { 4 },
2967 .num_windows = 1,
2968 }, {
2969 .index = 5,
2970 .dc = 2,
2971 .windows = (const unsigned int[]) { 5 },
2972 .num_windows = 1,
2973 },
2974};
2975
2976static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2977 .supports_background_color = true,
2978 .supports_interlacing = true,
2979 .supports_cursor = true,
2980 .supports_block_linear = true,
2981 .supports_sector_layout = false,
2982 .has_legacy_blending = false,
2983 .pitch_align = 64,
2984 .has_powergate = false,
2985 .coupled_pm = false,
2986 .has_nvdisplay = true,
2987 .wgrps = tegra186_dc_wgrps,
2988 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2989 .plane_tiled_memory_bandwidth_x2 = false,
2990 .has_pll_d2_out0 = false,
2991};
2992
2993static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2994 {
2995 .index = 0,
2996 .dc = 0,
2997 .windows = (const unsigned int[]) { 0 },
2998 .num_windows = 1,
2999 }, {
3000 .index = 1,
3001 .dc = 1,
3002 .windows = (const unsigned int[]) { 1 },
3003 .num_windows = 1,
3004 }, {
3005 .index = 2,
3006 .dc = 1,
3007 .windows = (const unsigned int[]) { 2 },
3008 .num_windows = 1,
3009 }, {
3010 .index = 3,
3011 .dc = 2,
3012 .windows = (const unsigned int[]) { 3 },
3013 .num_windows = 1,
3014 }, {
3015 .index = 4,
3016 .dc = 2,
3017 .windows = (const unsigned int[]) { 4 },
3018 .num_windows = 1,
3019 }, {
3020 .index = 5,
3021 .dc = 2,
3022 .windows = (const unsigned int[]) { 5 },
3023 .num_windows = 1,
3024 },
3025};
3026
3027static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
3028 .supports_background_color = true,
3029 .supports_interlacing = true,
3030 .supports_cursor = true,
3031 .supports_block_linear = true,
3032 .supports_sector_layout = true,
3033 .has_legacy_blending = false,
3034 .pitch_align = 64,
3035 .has_powergate = false,
3036 .coupled_pm = false,
3037 .has_nvdisplay = true,
3038 .wgrps = tegra194_dc_wgrps,
3039 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
3040 .plane_tiled_memory_bandwidth_x2 = false,
3041 .has_pll_d2_out0 = false,
3042};
3043
3044static const struct of_device_id tegra_dc_of_match[] = {
3045 {
3046 .compatible = "nvidia,tegra194-dc",
3047 .data = &tegra194_dc_soc_info,
3048 }, {
3049 .compatible = "nvidia,tegra186-dc",
3050 .data = &tegra186_dc_soc_info,
3051 }, {
3052 .compatible = "nvidia,tegra210-dc",
3053 .data = &tegra210_dc_soc_info,
3054 }, {
3055 .compatible = "nvidia,tegra124-dc",
3056 .data = &tegra124_dc_soc_info,
3057 }, {
3058 .compatible = "nvidia,tegra114-dc",
3059 .data = &tegra114_dc_soc_info,
3060 }, {
3061 .compatible = "nvidia,tegra30-dc",
3062 .data = &tegra30_dc_soc_info,
3063 }, {
3064 .compatible = "nvidia,tegra20-dc",
3065 .data = &tegra20_dc_soc_info,
3066 }, {
3067 /* sentinel */
3068 }
3069};
3070MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
3071
3072static int tegra_dc_parse_dt(struct tegra_dc *dc)
3073{
3074 struct device_node *np;
3075 u32 value = 0;
3076 int err;
3077
3078 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
3079 if (err < 0) {
3080 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
3081
3082 /*
3083 * If the nvidia,head property isn't present, try to find the
3084 * correct head number by looking up the position of this
3085 * display controller's node within the device tree. Assuming
3086 * that the nodes are ordered properly in the DTS file and
3087 * that the translation into a flattened device tree blob
3088 * preserves that ordering this will actually yield the right
3089 * head number.
3090 *
3091 * If those assumptions don't hold, this will still work for
3092 * cases where only a single display controller is used.
3093 */
3094 for_each_matching_node(np, tegra_dc_of_match) {
3095 if (np == dc->dev->of_node) {
3096 of_node_put(np);
3097 break;
3098 }
3099
3100 value++;
3101 }
3102 }
3103
3104 dc->pipe = value;
3105
3106 return 0;
3107}
3108
3109static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
3110{
3111 struct tegra_dc *dc = dev_get_drvdata(dev);
3112 unsigned int pipe = (unsigned long)(void *)data;
3113
3114 return dc->pipe == pipe;
3115}
3116
3117static int tegra_dc_couple(struct tegra_dc *dc)
3118{
3119 /*
3120 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
3121 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
3122 * POWER_CONTROL registers during CRTC enabling.
3123 */
3124 if (dc->soc->coupled_pm && dc->pipe == 1) {
3125 struct device *companion;
3126 struct tegra_dc *parent;
3127
3128 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
3129 tegra_dc_match_by_pipe);
3130 if (!companion)
3131 return -EPROBE_DEFER;
3132
3133 parent = dev_get_drvdata(companion);
3134 dc->client.parent = &parent->client;
3135
3136 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
3137 }
3138
3139 return 0;
3140}
3141
3142static int tegra_dc_init_opp_table(struct tegra_dc *dc)
3143{
3144 struct tegra_core_opp_params opp_params = {};
3145 int err;
3146
3147 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);
3148 if (err && err != -ENODEV)
3149 return err;
3150
3151 if (err)
3152 dc->has_opp_table = false;
3153 else
3154 dc->has_opp_table = true;
3155
3156 return 0;
3157}
3158
3159static int tegra_dc_probe(struct platform_device *pdev)
3160{
3161 u64 dma_mask = dma_get_mask(pdev->dev.parent);
3162 struct tegra_dc *dc;
3163 int err;
3164
3165 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask);
3166 if (err < 0) {
3167 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
3168 return err;
3169 }
3170
3171 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
3172 if (!dc)
3173 return -ENOMEM;
3174
3175 dc->soc = of_device_get_match_data(&pdev->dev);
3176
3177 INIT_LIST_HEAD(&dc->list);
3178 dc->dev = &pdev->dev;
3179
3180 err = tegra_dc_parse_dt(dc);
3181 if (err < 0)
3182 return err;
3183
3184 err = tegra_dc_couple(dc);
3185 if (err < 0)
3186 return err;
3187
3188 dc->clk = devm_clk_get(&pdev->dev, NULL);
3189 if (IS_ERR(dc->clk)) {
3190 dev_err(&pdev->dev, "failed to get clock\n");
3191 return PTR_ERR(dc->clk);
3192 }
3193
3194 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
3195 if (IS_ERR(dc->rst)) {
3196 dev_err(&pdev->dev, "failed to get reset\n");
3197 return PTR_ERR(dc->rst);
3198 }
3199
3200 /* assert reset and disable clock */
3201 err = clk_prepare_enable(dc->clk);
3202 if (err < 0)
3203 return err;
3204
3205 usleep_range(2000, 4000);
3206
3207 err = reset_control_assert(dc->rst);
3208 if (err < 0) {
3209 clk_disable_unprepare(dc->clk);
3210 return err;
3211 }
3212
3213 usleep_range(2000, 4000);
3214
3215 clk_disable_unprepare(dc->clk);
3216
3217 if (dc->soc->has_powergate) {
3218 if (dc->pipe == 0)
3219 dc->powergate = TEGRA_POWERGATE_DIS;
3220 else
3221 dc->powergate = TEGRA_POWERGATE_DISB;
3222
3223 tegra_powergate_power_off(dc->powergate);
3224 }
3225
3226 err = tegra_dc_init_opp_table(dc);
3227 if (err < 0)
3228 return err;
3229
3230 dc->regs = devm_platform_ioremap_resource(pdev, 0);
3231 if (IS_ERR(dc->regs))
3232 return PTR_ERR(dc->regs);
3233
3234 dc->irq = platform_get_irq(pdev, 0);
3235 if (dc->irq < 0)
3236 return -ENXIO;
3237
3238 err = tegra_dc_rgb_probe(dc);
3239 if (err < 0 && err != -ENODEV)
3240 return dev_err_probe(&pdev->dev, err,
3241 "failed to probe RGB output\n");
3242
3243 platform_set_drvdata(pdev, dc);
3244 pm_runtime_enable(&pdev->dev);
3245
3246 INIT_LIST_HEAD(&dc->client.list);
3247 dc->client.ops = &dc_client_ops;
3248 dc->client.dev = &pdev->dev;
3249
3250 err = host1x_client_register(&dc->client);
3251 if (err < 0) {
3252 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3253 err);
3254 goto disable_pm;
3255 }
3256
3257 return 0;
3258
3259disable_pm:
3260 pm_runtime_disable(&pdev->dev);
3261 tegra_dc_rgb_remove(dc);
3262
3263 return err;
3264}
3265
3266static int tegra_dc_remove(struct platform_device *pdev)
3267{
3268 struct tegra_dc *dc = platform_get_drvdata(pdev);
3269 int err;
3270
3271 err = host1x_client_unregister(&dc->client);
3272 if (err < 0) {
3273 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3274 err);
3275 return err;
3276 }
3277
3278 err = tegra_dc_rgb_remove(dc);
3279 if (err < 0) {
3280 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
3281 return err;
3282 }
3283
3284 pm_runtime_disable(&pdev->dev);
3285
3286 return 0;
3287}
3288
3289struct platform_driver tegra_dc_driver = {
3290 .driver = {
3291 .name = "tegra-dc",
3292 .of_match_table = tegra_dc_of_match,
3293 },
3294 .probe = tegra_dc_probe,
3295 .remove = tegra_dc_remove,
3296};