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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/iommu.h>
13#include <linux/reset.h>
14
15#include <soc/tegra/pmc.h>
16
17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
20
21#include <drm/drm_atomic.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_plane_helper.h>
24
25struct tegra_dc_soc_info {
26 bool supports_border_color;
27 bool supports_interlacing;
28 bool supports_cursor;
29 bool supports_block_linear;
30 unsigned int pitch_align;
31 bool has_powergate;
32};
33
34struct tegra_plane {
35 struct drm_plane base;
36 unsigned int index;
37};
38
39static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
40{
41 return container_of(plane, struct tegra_plane, base);
42}
43
44struct tegra_dc_state {
45 struct drm_crtc_state base;
46
47 struct clk *clk;
48 unsigned long pclk;
49 unsigned int div;
50
51 u32 planes;
52};
53
54static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
55{
56 if (state)
57 return container_of(state, struct tegra_dc_state, base);
58
59 return NULL;
60}
61
62struct tegra_plane_state {
63 struct drm_plane_state base;
64
65 struct tegra_bo_tiling tiling;
66 u32 format;
67 u32 swap;
68};
69
70static inline struct tegra_plane_state *
71to_tegra_plane_state(struct drm_plane_state *state)
72{
73 if (state)
74 return container_of(state, struct tegra_plane_state, base);
75
76 return NULL;
77}
78
79static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
80{
81 stats->frames = 0;
82 stats->vblank = 0;
83 stats->underflow = 0;
84 stats->overflow = 0;
85}
86
87/*
88 * Reads the active copy of a register. This takes the dc->lock spinlock to
89 * prevent races with the VBLANK processing which also needs access to the
90 * active copy of some registers.
91 */
92static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
93{
94 unsigned long flags;
95 u32 value;
96
97 spin_lock_irqsave(&dc->lock, flags);
98
99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
100 value = tegra_dc_readl(dc, offset);
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
102
103 spin_unlock_irqrestore(&dc->lock, flags);
104 return value;
105}
106
107/*
108 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
109 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
110 * Latching happens mmediately if the display controller is in STOP mode or
111 * on the next frame boundary otherwise.
112 *
113 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
114 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
115 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
116 * into the ACTIVE copy, either immediately if the display controller is in
117 * STOP mode, or at the next frame boundary otherwise.
118 */
119void tegra_dc_commit(struct tegra_dc *dc)
120{
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
123}
124
125static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
126{
127 /* assume no swapping of fetched data */
128 if (swap)
129 *swap = BYTE_SWAP_NOSWAP;
130
131 switch (fourcc) {
132 case DRM_FORMAT_XBGR8888:
133 *format = WIN_COLOR_DEPTH_R8G8B8A8;
134 break;
135
136 case DRM_FORMAT_XRGB8888:
137 *format = WIN_COLOR_DEPTH_B8G8R8A8;
138 break;
139
140 case DRM_FORMAT_RGB565:
141 *format = WIN_COLOR_DEPTH_B5G6R5;
142 break;
143
144 case DRM_FORMAT_UYVY:
145 *format = WIN_COLOR_DEPTH_YCbCr422;
146 break;
147
148 case DRM_FORMAT_YUYV:
149 if (swap)
150 *swap = BYTE_SWAP_SWAP2;
151
152 *format = WIN_COLOR_DEPTH_YCbCr422;
153 break;
154
155 case DRM_FORMAT_YUV420:
156 *format = WIN_COLOR_DEPTH_YCbCr420P;
157 break;
158
159 case DRM_FORMAT_YUV422:
160 *format = WIN_COLOR_DEPTH_YCbCr422P;
161 break;
162
163 default:
164 return -EINVAL;
165 }
166
167 return 0;
168}
169
170static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
171{
172 switch (format) {
173 case WIN_COLOR_DEPTH_YCbCr422:
174 case WIN_COLOR_DEPTH_YUV422:
175 if (planar)
176 *planar = false;
177
178 return true;
179
180 case WIN_COLOR_DEPTH_YCbCr420P:
181 case WIN_COLOR_DEPTH_YUV420P:
182 case WIN_COLOR_DEPTH_YCbCr422P:
183 case WIN_COLOR_DEPTH_YUV422P:
184 case WIN_COLOR_DEPTH_YCbCr422R:
185 case WIN_COLOR_DEPTH_YUV422R:
186 case WIN_COLOR_DEPTH_YCbCr422RA:
187 case WIN_COLOR_DEPTH_YUV422RA:
188 if (planar)
189 *planar = true;
190
191 return true;
192 }
193
194 if (planar)
195 *planar = false;
196
197 return false;
198}
199
200static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
201 unsigned int bpp)
202{
203 fixed20_12 outf = dfixed_init(out);
204 fixed20_12 inf = dfixed_init(in);
205 u32 dda_inc;
206 int max;
207
208 if (v)
209 max = 15;
210 else {
211 switch (bpp) {
212 case 2:
213 max = 8;
214 break;
215
216 default:
217 WARN_ON_ONCE(1);
218 /* fallthrough */
219 case 4:
220 max = 4;
221 break;
222 }
223 }
224
225 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
226 inf.full -= dfixed_const(1);
227
228 dda_inc = dfixed_div(inf, outf);
229 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
230
231 return dda_inc;
232}
233
234static inline u32 compute_initial_dda(unsigned int in)
235{
236 fixed20_12 inf = dfixed_init(in);
237 return dfixed_frac(inf);
238}
239
240static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
241 const struct tegra_dc_window *window)
242{
243 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
244 unsigned long value, flags;
245 bool yuv, planar;
246
247 /*
248 * For YUV planar modes, the number of bytes per pixel takes into
249 * account only the luma component and therefore is 1.
250 */
251 yuv = tegra_dc_format_is_yuv(window->format, &planar);
252 if (!yuv)
253 bpp = window->bits_per_pixel / 8;
254 else
255 bpp = planar ? 1 : 2;
256
257 spin_lock_irqsave(&dc->lock, flags);
258
259 value = WINDOW_A_SELECT << index;
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
261
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
264
265 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
266 tegra_dc_writel(dc, value, DC_WIN_POSITION);
267
268 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
269 tegra_dc_writel(dc, value, DC_WIN_SIZE);
270
271 h_offset = window->src.x * bpp;
272 v_offset = window->src.y;
273 h_size = window->src.w * bpp;
274 v_size = window->src.h;
275
276 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
278
279 /*
280 * For DDA computations the number of bytes per pixel for YUV planar
281 * modes needs to take into account all Y, U and V components.
282 */
283 if (yuv && planar)
284 bpp = 2;
285
286 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
287 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
288
289 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
290 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
291
292 h_dda = compute_initial_dda(window->src.x);
293 v_dda = compute_initial_dda(window->src.y);
294
295 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
296 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
297
298 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
299 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
300
301 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
302
303 if (yuv && planar) {
304 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
305 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
306 value = window->stride[1] << 16 | window->stride[0];
307 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
308 } else {
309 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
310 }
311
312 if (window->bottom_up)
313 v_offset += window->src.h - 1;
314
315 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
316 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
317
318 if (dc->soc->supports_block_linear) {
319 unsigned long height = window->tiling.value;
320
321 switch (window->tiling.mode) {
322 case TEGRA_BO_TILING_MODE_PITCH:
323 value = DC_WINBUF_SURFACE_KIND_PITCH;
324 break;
325
326 case TEGRA_BO_TILING_MODE_TILED:
327 value = DC_WINBUF_SURFACE_KIND_TILED;
328 break;
329
330 case TEGRA_BO_TILING_MODE_BLOCK:
331 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
332 DC_WINBUF_SURFACE_KIND_BLOCK;
333 break;
334 }
335
336 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
337 } else {
338 switch (window->tiling.mode) {
339 case TEGRA_BO_TILING_MODE_PITCH:
340 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
341 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
342 break;
343
344 case TEGRA_BO_TILING_MODE_TILED:
345 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
346 DC_WIN_BUFFER_ADDR_MODE_TILE;
347 break;
348
349 case TEGRA_BO_TILING_MODE_BLOCK:
350 /*
351 * No need to handle this here because ->atomic_check
352 * will already have filtered it out.
353 */
354 break;
355 }
356
357 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
358 }
359
360 value = WIN_ENABLE;
361
362 if (yuv) {
363 /* setup default colorspace conversion coefficients */
364 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
365 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
366 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
367 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
368 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
369 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
370 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
371 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
372
373 value |= CSC_ENABLE;
374 } else if (window->bits_per_pixel < 24) {
375 value |= COLOR_EXPAND;
376 }
377
378 if (window->bottom_up)
379 value |= V_DIRECTION;
380
381 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
382
383 /*
384 * Disable blending and assume Window A is the bottom-most window,
385 * Window C is the top-most window and Window B is in the middle.
386 */
387 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
389
390 switch (index) {
391 case 0:
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
395 break;
396
397 case 1:
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
399 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
401 break;
402
403 case 2:
404 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
407 break;
408 }
409
410 spin_unlock_irqrestore(&dc->lock, flags);
411}
412
413static void tegra_plane_destroy(struct drm_plane *plane)
414{
415 struct tegra_plane *p = to_tegra_plane(plane);
416
417 drm_plane_cleanup(plane);
418 kfree(p);
419}
420
421static const u32 tegra_primary_plane_formats[] = {
422 DRM_FORMAT_XBGR8888,
423 DRM_FORMAT_XRGB8888,
424 DRM_FORMAT_RGB565,
425};
426
427static void tegra_primary_plane_destroy(struct drm_plane *plane)
428{
429 tegra_plane_destroy(plane);
430}
431
432static void tegra_plane_reset(struct drm_plane *plane)
433{
434 struct tegra_plane_state *state;
435
436 if (plane->state)
437 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
438
439 kfree(plane->state);
440 plane->state = NULL;
441
442 state = kzalloc(sizeof(*state), GFP_KERNEL);
443 if (state) {
444 plane->state = &state->base;
445 plane->state->plane = plane;
446 }
447}
448
449static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
450{
451 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
452 struct tegra_plane_state *copy;
453
454 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
455 if (!copy)
456 return NULL;
457
458 __drm_atomic_helper_plane_duplicate_state(plane, ©->base);
459 copy->tiling = state->tiling;
460 copy->format = state->format;
461 copy->swap = state->swap;
462
463 return ©->base;
464}
465
466static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
467 struct drm_plane_state *state)
468{
469 __drm_atomic_helper_plane_destroy_state(plane, state);
470 kfree(state);
471}
472
473static const struct drm_plane_funcs tegra_primary_plane_funcs = {
474 .update_plane = drm_atomic_helper_update_plane,
475 .disable_plane = drm_atomic_helper_disable_plane,
476 .destroy = tegra_primary_plane_destroy,
477 .reset = tegra_plane_reset,
478 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
479 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
480};
481
482static int tegra_plane_prepare_fb(struct drm_plane *plane,
483 const struct drm_plane_state *new_state)
484{
485 return 0;
486}
487
488static void tegra_plane_cleanup_fb(struct drm_plane *plane,
489 const struct drm_plane_state *old_fb)
490{
491}
492
493static int tegra_plane_state_add(struct tegra_plane *plane,
494 struct drm_plane_state *state)
495{
496 struct drm_crtc_state *crtc_state;
497 struct tegra_dc_state *tegra;
498
499 /* Propagate errors from allocation or locking failures. */
500 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
501 if (IS_ERR(crtc_state))
502 return PTR_ERR(crtc_state);
503
504 tegra = to_dc_state(crtc_state);
505
506 tegra->planes |= WIN_A_ACT_REQ << plane->index;
507
508 return 0;
509}
510
511static int tegra_plane_atomic_check(struct drm_plane *plane,
512 struct drm_plane_state *state)
513{
514 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
515 struct tegra_bo_tiling *tiling = &plane_state->tiling;
516 struct tegra_plane *tegra = to_tegra_plane(plane);
517 struct tegra_dc *dc = to_tegra_dc(state->crtc);
518 int err;
519
520 /* no need for further checks if the plane is being disabled */
521 if (!state->crtc)
522 return 0;
523
524 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
525 &plane_state->swap);
526 if (err < 0)
527 return err;
528
529 err = tegra_fb_get_tiling(state->fb, tiling);
530 if (err < 0)
531 return err;
532
533 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
534 !dc->soc->supports_block_linear) {
535 DRM_ERROR("hardware doesn't support block linear mode\n");
536 return -EINVAL;
537 }
538
539 /*
540 * Tegra doesn't support different strides for U and V planes so we
541 * error out if the user tries to display a framebuffer with such a
542 * configuration.
543 */
544 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
545 if (state->fb->pitches[2] != state->fb->pitches[1]) {
546 DRM_ERROR("unsupported UV-plane configuration\n");
547 return -EINVAL;
548 }
549 }
550
551 err = tegra_plane_state_add(tegra, state);
552 if (err < 0)
553 return err;
554
555 return 0;
556}
557
558static void tegra_plane_atomic_update(struct drm_plane *plane,
559 struct drm_plane_state *old_state)
560{
561 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
562 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
563 struct drm_framebuffer *fb = plane->state->fb;
564 struct tegra_plane *p = to_tegra_plane(plane);
565 struct tegra_dc_window window;
566 unsigned int i;
567
568 /* rien ne va plus */
569 if (!plane->state->crtc || !plane->state->fb)
570 return;
571
572 memset(&window, 0, sizeof(window));
573 window.src.x = plane->state->src_x >> 16;
574 window.src.y = plane->state->src_y >> 16;
575 window.src.w = plane->state->src_w >> 16;
576 window.src.h = plane->state->src_h >> 16;
577 window.dst.x = plane->state->crtc_x;
578 window.dst.y = plane->state->crtc_y;
579 window.dst.w = plane->state->crtc_w;
580 window.dst.h = plane->state->crtc_h;
581 window.bits_per_pixel = fb->bits_per_pixel;
582 window.bottom_up = tegra_fb_is_bottom_up(fb);
583
584 /* copy from state */
585 window.tiling = state->tiling;
586 window.format = state->format;
587 window.swap = state->swap;
588
589 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
590 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
591
592 window.base[i] = bo->paddr + fb->offsets[i];
593 window.stride[i] = fb->pitches[i];
594 }
595
596 tegra_dc_setup_window(dc, p->index, &window);
597}
598
599static void tegra_plane_atomic_disable(struct drm_plane *plane,
600 struct drm_plane_state *old_state)
601{
602 struct tegra_plane *p = to_tegra_plane(plane);
603 struct tegra_dc *dc;
604 unsigned long flags;
605 u32 value;
606
607 /* rien ne va plus */
608 if (!old_state || !old_state->crtc)
609 return;
610
611 dc = to_tegra_dc(old_state->crtc);
612
613 spin_lock_irqsave(&dc->lock, flags);
614
615 value = WINDOW_A_SELECT << p->index;
616 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
617
618 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
619 value &= ~WIN_ENABLE;
620 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
621
622 spin_unlock_irqrestore(&dc->lock, flags);
623}
624
625static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
626 .prepare_fb = tegra_plane_prepare_fb,
627 .cleanup_fb = tegra_plane_cleanup_fb,
628 .atomic_check = tegra_plane_atomic_check,
629 .atomic_update = tegra_plane_atomic_update,
630 .atomic_disable = tegra_plane_atomic_disable,
631};
632
633static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
634 struct tegra_dc *dc)
635{
636 /*
637 * Ideally this would use drm_crtc_mask(), but that would require the
638 * CRTC to already be in the mode_config's list of CRTCs. However, it
639 * will only be added to that list in the drm_crtc_init_with_planes()
640 * (in tegra_dc_init()), which in turn requires registration of these
641 * planes. So we have ourselves a nice little chicken and egg problem
642 * here.
643 *
644 * We work around this by manually creating the mask from the number
645 * of CRTCs that have been registered, and should therefore always be
646 * the same as drm_crtc_index() after registration.
647 */
648 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
649 struct tegra_plane *plane;
650 unsigned int num_formats;
651 const u32 *formats;
652 int err;
653
654 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
655 if (!plane)
656 return ERR_PTR(-ENOMEM);
657
658 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
659 formats = tegra_primary_plane_formats;
660
661 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
662 &tegra_primary_plane_funcs, formats,
663 num_formats, DRM_PLANE_TYPE_PRIMARY,
664 NULL);
665 if (err < 0) {
666 kfree(plane);
667 return ERR_PTR(err);
668 }
669
670 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
671
672 return &plane->base;
673}
674
675static const u32 tegra_cursor_plane_formats[] = {
676 DRM_FORMAT_RGBA8888,
677};
678
679static int tegra_cursor_atomic_check(struct drm_plane *plane,
680 struct drm_plane_state *state)
681{
682 struct tegra_plane *tegra = to_tegra_plane(plane);
683 int err;
684
685 /* no need for further checks if the plane is being disabled */
686 if (!state->crtc)
687 return 0;
688
689 /* scaling not supported for cursor */
690 if ((state->src_w >> 16 != state->crtc_w) ||
691 (state->src_h >> 16 != state->crtc_h))
692 return -EINVAL;
693
694 /* only square cursors supported */
695 if (state->src_w != state->src_h)
696 return -EINVAL;
697
698 if (state->crtc_w != 32 && state->crtc_w != 64 &&
699 state->crtc_w != 128 && state->crtc_w != 256)
700 return -EINVAL;
701
702 err = tegra_plane_state_add(tegra, state);
703 if (err < 0)
704 return err;
705
706 return 0;
707}
708
709static void tegra_cursor_atomic_update(struct drm_plane *plane,
710 struct drm_plane_state *old_state)
711{
712 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
713 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
714 struct drm_plane_state *state = plane->state;
715 u32 value = CURSOR_CLIP_DISPLAY;
716
717 /* rien ne va plus */
718 if (!plane->state->crtc || !plane->state->fb)
719 return;
720
721 switch (state->crtc_w) {
722 case 32:
723 value |= CURSOR_SIZE_32x32;
724 break;
725
726 case 64:
727 value |= CURSOR_SIZE_64x64;
728 break;
729
730 case 128:
731 value |= CURSOR_SIZE_128x128;
732 break;
733
734 case 256:
735 value |= CURSOR_SIZE_256x256;
736 break;
737
738 default:
739 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
740 state->crtc_h);
741 return;
742 }
743
744 value |= (bo->paddr >> 10) & 0x3fffff;
745 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
746
747#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
748 value = (bo->paddr >> 32) & 0x3;
749 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
750#endif
751
752 /* enable cursor and set blend mode */
753 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
754 value |= CURSOR_ENABLE;
755 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
756
757 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
758 value &= ~CURSOR_DST_BLEND_MASK;
759 value &= ~CURSOR_SRC_BLEND_MASK;
760 value |= CURSOR_MODE_NORMAL;
761 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
762 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
763 value |= CURSOR_ALPHA;
764 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
765
766 /* position the cursor */
767 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
768 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
769}
770
771static void tegra_cursor_atomic_disable(struct drm_plane *plane,
772 struct drm_plane_state *old_state)
773{
774 struct tegra_dc *dc;
775 u32 value;
776
777 /* rien ne va plus */
778 if (!old_state || !old_state->crtc)
779 return;
780
781 dc = to_tegra_dc(old_state->crtc);
782
783 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
784 value &= ~CURSOR_ENABLE;
785 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
786}
787
788static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
789 .update_plane = drm_atomic_helper_update_plane,
790 .disable_plane = drm_atomic_helper_disable_plane,
791 .destroy = tegra_plane_destroy,
792 .reset = tegra_plane_reset,
793 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
794 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
795};
796
797static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
798 .prepare_fb = tegra_plane_prepare_fb,
799 .cleanup_fb = tegra_plane_cleanup_fb,
800 .atomic_check = tegra_cursor_atomic_check,
801 .atomic_update = tegra_cursor_atomic_update,
802 .atomic_disable = tegra_cursor_atomic_disable,
803};
804
805static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
806 struct tegra_dc *dc)
807{
808 struct tegra_plane *plane;
809 unsigned int num_formats;
810 const u32 *formats;
811 int err;
812
813 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
814 if (!plane)
815 return ERR_PTR(-ENOMEM);
816
817 /*
818 * This index is kind of fake. The cursor isn't a regular plane, but
819 * its update and activation request bits in DC_CMD_STATE_CONTROL do
820 * use the same programming. Setting this fake index here allows the
821 * code in tegra_add_plane_state() to do the right thing without the
822 * need to special-casing the cursor plane.
823 */
824 plane->index = 6;
825
826 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
827 formats = tegra_cursor_plane_formats;
828
829 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
830 &tegra_cursor_plane_funcs, formats,
831 num_formats, DRM_PLANE_TYPE_CURSOR,
832 NULL);
833 if (err < 0) {
834 kfree(plane);
835 return ERR_PTR(err);
836 }
837
838 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
839
840 return &plane->base;
841}
842
843static void tegra_overlay_plane_destroy(struct drm_plane *plane)
844{
845 tegra_plane_destroy(plane);
846}
847
848static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
849 .update_plane = drm_atomic_helper_update_plane,
850 .disable_plane = drm_atomic_helper_disable_plane,
851 .destroy = tegra_overlay_plane_destroy,
852 .reset = tegra_plane_reset,
853 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
854 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
855};
856
857static const uint32_t tegra_overlay_plane_formats[] = {
858 DRM_FORMAT_XBGR8888,
859 DRM_FORMAT_XRGB8888,
860 DRM_FORMAT_RGB565,
861 DRM_FORMAT_UYVY,
862 DRM_FORMAT_YUYV,
863 DRM_FORMAT_YUV420,
864 DRM_FORMAT_YUV422,
865};
866
867static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
868 .prepare_fb = tegra_plane_prepare_fb,
869 .cleanup_fb = tegra_plane_cleanup_fb,
870 .atomic_check = tegra_plane_atomic_check,
871 .atomic_update = tegra_plane_atomic_update,
872 .atomic_disable = tegra_plane_atomic_disable,
873};
874
875static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
876 struct tegra_dc *dc,
877 unsigned int index)
878{
879 struct tegra_plane *plane;
880 unsigned int num_formats;
881 const u32 *formats;
882 int err;
883
884 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
885 if (!plane)
886 return ERR_PTR(-ENOMEM);
887
888 plane->index = index;
889
890 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
891 formats = tegra_overlay_plane_formats;
892
893 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
894 &tegra_overlay_plane_funcs, formats,
895 num_formats, DRM_PLANE_TYPE_OVERLAY,
896 NULL);
897 if (err < 0) {
898 kfree(plane);
899 return ERR_PTR(err);
900 }
901
902 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
903
904 return &plane->base;
905}
906
907static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
908{
909 struct drm_plane *plane;
910 unsigned int i;
911
912 for (i = 0; i < 2; i++) {
913 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
914 if (IS_ERR(plane))
915 return PTR_ERR(plane);
916 }
917
918 return 0;
919}
920
921u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
922{
923 if (dc->syncpt)
924 return host1x_syncpt_read(dc->syncpt);
925
926 /* fallback to software emulated VBLANK counter */
927 return drm_crtc_vblank_count(&dc->base);
928}
929
930void tegra_dc_enable_vblank(struct tegra_dc *dc)
931{
932 unsigned long value, flags;
933
934 spin_lock_irqsave(&dc->lock, flags);
935
936 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
937 value |= VBLANK_INT;
938 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
939
940 spin_unlock_irqrestore(&dc->lock, flags);
941}
942
943void tegra_dc_disable_vblank(struct tegra_dc *dc)
944{
945 unsigned long value, flags;
946
947 spin_lock_irqsave(&dc->lock, flags);
948
949 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
950 value &= ~VBLANK_INT;
951 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
952
953 spin_unlock_irqrestore(&dc->lock, flags);
954}
955
956static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
957{
958 struct drm_device *drm = dc->base.dev;
959 struct drm_crtc *crtc = &dc->base;
960 unsigned long flags, base;
961 struct tegra_bo *bo;
962
963 spin_lock_irqsave(&drm->event_lock, flags);
964
965 if (!dc->event) {
966 spin_unlock_irqrestore(&drm->event_lock, flags);
967 return;
968 }
969
970 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
971
972 spin_lock(&dc->lock);
973
974 /* check if new start address has been latched */
975 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
976 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
977 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
978 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
979
980 spin_unlock(&dc->lock);
981
982 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
983 drm_crtc_send_vblank_event(crtc, dc->event);
984 drm_crtc_vblank_put(crtc);
985 dc->event = NULL;
986 }
987
988 spin_unlock_irqrestore(&drm->event_lock, flags);
989}
990
991static void tegra_dc_destroy(struct drm_crtc *crtc)
992{
993 drm_crtc_cleanup(crtc);
994}
995
996static void tegra_crtc_reset(struct drm_crtc *crtc)
997{
998 struct tegra_dc_state *state;
999
1000 if (crtc->state)
1001 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1002
1003 kfree(crtc->state);
1004 crtc->state = NULL;
1005
1006 state = kzalloc(sizeof(*state), GFP_KERNEL);
1007 if (state) {
1008 crtc->state = &state->base;
1009 crtc->state->crtc = crtc;
1010 }
1011
1012 drm_crtc_vblank_reset(crtc);
1013}
1014
1015static struct drm_crtc_state *
1016tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1017{
1018 struct tegra_dc_state *state = to_dc_state(crtc->state);
1019 struct tegra_dc_state *copy;
1020
1021 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1022 if (!copy)
1023 return NULL;
1024
1025 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1026 copy->clk = state->clk;
1027 copy->pclk = state->pclk;
1028 copy->div = state->div;
1029 copy->planes = state->planes;
1030
1031 return ©->base;
1032}
1033
1034static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1035 struct drm_crtc_state *state)
1036{
1037 __drm_atomic_helper_crtc_destroy_state(crtc, state);
1038 kfree(state);
1039}
1040
1041static const struct drm_crtc_funcs tegra_crtc_funcs = {
1042 .page_flip = drm_atomic_helper_page_flip,
1043 .set_config = drm_atomic_helper_set_config,
1044 .destroy = tegra_dc_destroy,
1045 .reset = tegra_crtc_reset,
1046 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1047 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1048};
1049
1050static int tegra_dc_set_timings(struct tegra_dc *dc,
1051 struct drm_display_mode *mode)
1052{
1053 unsigned int h_ref_to_sync = 1;
1054 unsigned int v_ref_to_sync = 1;
1055 unsigned long value;
1056
1057 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058
1059 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1061
1062 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063 ((mode->hsync_end - mode->hsync_start) << 0);
1064 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1065
1066 value = ((mode->vtotal - mode->vsync_end) << 16) |
1067 ((mode->htotal - mode->hsync_end) << 0);
1068 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1069
1070 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071 ((mode->hsync_start - mode->hdisplay) << 0);
1072 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1073
1074 value = (mode->vdisplay << 16) | mode->hdisplay;
1075 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1076
1077 return 0;
1078}
1079
1080/**
1081 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1082 * state
1083 * @dc: display controller
1084 * @crtc_state: CRTC atomic state
1085 * @clk: parent clock for display controller
1086 * @pclk: pixel clock
1087 * @div: shift clock divider
1088 *
1089 * Returns:
1090 * 0 on success or a negative error-code on failure.
1091 */
1092int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093 struct drm_crtc_state *crtc_state,
1094 struct clk *clk, unsigned long pclk,
1095 unsigned int div)
1096{
1097 struct tegra_dc_state *state = to_dc_state(crtc_state);
1098
1099 if (!clk_has_parent(dc->clk, clk))
1100 return -EINVAL;
1101
1102 state->clk = clk;
1103 state->pclk = pclk;
1104 state->div = div;
1105
1106 return 0;
1107}
1108
1109static void tegra_dc_commit_state(struct tegra_dc *dc,
1110 struct tegra_dc_state *state)
1111{
1112 u32 value;
1113 int err;
1114
1115 err = clk_set_parent(dc->clk, state->clk);
1116 if (err < 0)
1117 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1118
1119 /*
1120 * Outputs may not want to change the parent clock rate. This is only
1121 * relevant to Tegra20 where only a single display PLL is available.
1122 * Since that PLL would typically be used for HDMI, an internal LVDS
1123 * panel would need to be driven by some other clock such as PLL_P
1124 * which is shared with other peripherals. Changing the clock rate
1125 * should therefore be avoided.
1126 */
1127 if (state->pclk > 0) {
1128 err = clk_set_rate(state->clk, state->pclk);
1129 if (err < 0)
1130 dev_err(dc->dev,
1131 "failed to set clock rate to %lu Hz\n",
1132 state->pclk);
1133 }
1134
1135 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1136 state->div);
1137 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138
1139 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1141}
1142
1143static void tegra_dc_stop(struct tegra_dc *dc)
1144{
1145 u32 value;
1146
1147 /* stop the display controller */
1148 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1149 value &= ~DISP_CTRL_MODE_MASK;
1150 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1151
1152 tegra_dc_commit(dc);
1153}
1154
1155static bool tegra_dc_idle(struct tegra_dc *dc)
1156{
1157 u32 value;
1158
1159 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1160
1161 return (value & DISP_CTRL_MODE_MASK) == 0;
1162}
1163
1164static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1165{
1166 timeout = jiffies + msecs_to_jiffies(timeout);
1167
1168 while (time_before(jiffies, timeout)) {
1169 if (tegra_dc_idle(dc))
1170 return 0;
1171
1172 usleep_range(1000, 2000);
1173 }
1174
1175 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1176 return -ETIMEDOUT;
1177}
1178
1179static void tegra_crtc_disable(struct drm_crtc *crtc)
1180{
1181 struct tegra_dc *dc = to_tegra_dc(crtc);
1182 u32 value;
1183
1184 if (!tegra_dc_idle(dc)) {
1185 tegra_dc_stop(dc);
1186
1187 /*
1188 * Ignore the return value, there isn't anything useful to do
1189 * in case this fails.
1190 */
1191 tegra_dc_wait_idle(dc, 100);
1192 }
1193
1194 /*
1195 * This should really be part of the RGB encoder driver, but clearing
1196 * these bits has the side-effect of stopping the display controller.
1197 * When that happens no VBLANK interrupts will be raised. At the same
1198 * time the encoder is disabled before the display controller, so the
1199 * above code is always going to timeout waiting for the controller
1200 * to go idle.
1201 *
1202 * Given the close coupling between the RGB encoder and the display
1203 * controller doing it here is still kind of okay. None of the other
1204 * encoder drivers require these bits to be cleared.
1205 *
1206 * XXX: Perhaps given that the display controller is switched off at
1207 * this point anyway maybe clearing these bits isn't even useful for
1208 * the RGB encoder?
1209 */
1210 if (dc->rgb) {
1211 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1212 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1213 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1214 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1215 }
1216
1217 tegra_dc_stats_reset(&dc->stats);
1218 drm_crtc_vblank_off(crtc);
1219}
1220
1221static void tegra_crtc_enable(struct drm_crtc *crtc)
1222{
1223 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1224 struct tegra_dc_state *state = to_dc_state(crtc->state);
1225 struct tegra_dc *dc = to_tegra_dc(crtc);
1226 u32 value;
1227
1228 tegra_dc_commit_state(dc, state);
1229
1230 /* program display mode */
1231 tegra_dc_set_timings(dc, mode);
1232
1233 /* interlacing isn't supported yet, so disable it */
1234 if (dc->soc->supports_interlacing) {
1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1236 value &= ~INTERLACE_ENABLE;
1237 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1238 }
1239
1240 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1241 value &= ~DISP_CTRL_MODE_MASK;
1242 value |= DISP_CTRL_MODE_C_DISPLAY;
1243 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1244
1245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1246 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1247 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1249
1250 tegra_dc_commit(dc);
1251
1252 drm_crtc_vblank_on(crtc);
1253}
1254
1255static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1256 struct drm_crtc_state *state)
1257{
1258 return 0;
1259}
1260
1261static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1262 struct drm_crtc_state *old_crtc_state)
1263{
1264 struct tegra_dc *dc = to_tegra_dc(crtc);
1265
1266 if (crtc->state->event) {
1267 crtc->state->event->pipe = drm_crtc_index(crtc);
1268
1269 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1270
1271 dc->event = crtc->state->event;
1272 crtc->state->event = NULL;
1273 }
1274}
1275
1276static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1277 struct drm_crtc_state *old_crtc_state)
1278{
1279 struct tegra_dc_state *state = to_dc_state(crtc->state);
1280 struct tegra_dc *dc = to_tegra_dc(crtc);
1281
1282 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1283 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1284}
1285
1286static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1287 .disable = tegra_crtc_disable,
1288 .enable = tegra_crtc_enable,
1289 .atomic_check = tegra_crtc_atomic_check,
1290 .atomic_begin = tegra_crtc_atomic_begin,
1291 .atomic_flush = tegra_crtc_atomic_flush,
1292};
1293
1294static irqreturn_t tegra_dc_irq(int irq, void *data)
1295{
1296 struct tegra_dc *dc = data;
1297 unsigned long status;
1298
1299 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1300 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1301
1302 if (status & FRAME_END_INT) {
1303 /*
1304 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1305 */
1306 dc->stats.frames++;
1307 }
1308
1309 if (status & VBLANK_INT) {
1310 /*
1311 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1312 */
1313 drm_crtc_handle_vblank(&dc->base);
1314 tegra_dc_finish_page_flip(dc);
1315 dc->stats.vblank++;
1316 }
1317
1318 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1319 /*
1320 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1321 */
1322 dc->stats.underflow++;
1323 }
1324
1325 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1326 /*
1327 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1328 */
1329 dc->stats.overflow++;
1330 }
1331
1332 return IRQ_HANDLED;
1333}
1334
1335static int tegra_dc_show_regs(struct seq_file *s, void *data)
1336{
1337 struct drm_info_node *node = s->private;
1338 struct tegra_dc *dc = node->info_ent->data;
1339 int err = 0;
1340
1341 drm_modeset_lock_crtc(&dc->base, NULL);
1342
1343 if (!dc->base.state->active) {
1344 err = -EBUSY;
1345 goto unlock;
1346 }
1347
1348#define DUMP_REG(name) \
1349 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1350 tegra_dc_readl(dc, name))
1351
1352 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1353 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1354 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1355 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1356 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1357 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1358 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1359 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1360 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1361 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1362 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1363 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1364 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1365 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1366 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1367 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1368 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1369 DUMP_REG(DC_CMD_INT_STATUS);
1370 DUMP_REG(DC_CMD_INT_MASK);
1371 DUMP_REG(DC_CMD_INT_ENABLE);
1372 DUMP_REG(DC_CMD_INT_TYPE);
1373 DUMP_REG(DC_CMD_INT_POLARITY);
1374 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1375 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1376 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1377 DUMP_REG(DC_CMD_STATE_ACCESS);
1378 DUMP_REG(DC_CMD_STATE_CONTROL);
1379 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1380 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1381 DUMP_REG(DC_COM_CRC_CONTROL);
1382 DUMP_REG(DC_COM_CRC_CHECKSUM);
1383 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1384 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1385 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1386 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1387 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1388 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1389 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1390 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1391 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1392 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1393 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1394 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1395 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1396 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1397 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1398 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1399 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1400 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1401 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1402 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1403 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1404 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1405 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1406 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1407 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1408 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1409 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1410 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1411 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1412 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1413 DUMP_REG(DC_COM_SPI_CONTROL);
1414 DUMP_REG(DC_COM_SPI_START_BYTE);
1415 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1416 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1417 DUMP_REG(DC_COM_HSPI_CS_DC);
1418 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1419 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1420 DUMP_REG(DC_COM_GPIO_CTRL);
1421 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1422 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1423 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1424 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1425 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1426 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1427 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1428 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1429 DUMP_REG(DC_DISP_REF_TO_SYNC);
1430 DUMP_REG(DC_DISP_SYNC_WIDTH);
1431 DUMP_REG(DC_DISP_BACK_PORCH);
1432 DUMP_REG(DC_DISP_ACTIVE);
1433 DUMP_REG(DC_DISP_FRONT_PORCH);
1434 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1435 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1436 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1437 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1438 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1439 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1440 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1441 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1442 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1443 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1444 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1445 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1446 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1447 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1448 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1449 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1450 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1451 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1452 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1453 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1454 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1455 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1456 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1457 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1458 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1459 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1460 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1461 DUMP_REG(DC_DISP_M0_CONTROL);
1462 DUMP_REG(DC_DISP_M1_CONTROL);
1463 DUMP_REG(DC_DISP_DI_CONTROL);
1464 DUMP_REG(DC_DISP_PP_CONTROL);
1465 DUMP_REG(DC_DISP_PP_SELECT_A);
1466 DUMP_REG(DC_DISP_PP_SELECT_B);
1467 DUMP_REG(DC_DISP_PP_SELECT_C);
1468 DUMP_REG(DC_DISP_PP_SELECT_D);
1469 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1470 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1471 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1472 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1473 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1474 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1475 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1476 DUMP_REG(DC_DISP_BORDER_COLOR);
1477 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1478 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1479 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1480 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1481 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1482 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1483 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1484 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1485 DUMP_REG(DC_DISP_CURSOR_POSITION);
1486 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1487 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1488 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1489 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1490 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1491 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1492 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1493 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1494 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1495 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1496 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1497 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1498 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1499 DUMP_REG(DC_DISP_SD_CONTROL);
1500 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1501 DUMP_REG(DC_DISP_SD_LUT(0));
1502 DUMP_REG(DC_DISP_SD_LUT(1));
1503 DUMP_REG(DC_DISP_SD_LUT(2));
1504 DUMP_REG(DC_DISP_SD_LUT(3));
1505 DUMP_REG(DC_DISP_SD_LUT(4));
1506 DUMP_REG(DC_DISP_SD_LUT(5));
1507 DUMP_REG(DC_DISP_SD_LUT(6));
1508 DUMP_REG(DC_DISP_SD_LUT(7));
1509 DUMP_REG(DC_DISP_SD_LUT(8));
1510 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1511 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1512 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1513 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1514 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1515 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1516 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1517 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1518 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1519 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1520 DUMP_REG(DC_DISP_SD_BL_TF(0));
1521 DUMP_REG(DC_DISP_SD_BL_TF(1));
1522 DUMP_REG(DC_DISP_SD_BL_TF(2));
1523 DUMP_REG(DC_DISP_SD_BL_TF(3));
1524 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1525 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1526 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1527 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1528 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1529 DUMP_REG(DC_WIN_WIN_OPTIONS);
1530 DUMP_REG(DC_WIN_BYTE_SWAP);
1531 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1532 DUMP_REG(DC_WIN_COLOR_DEPTH);
1533 DUMP_REG(DC_WIN_POSITION);
1534 DUMP_REG(DC_WIN_SIZE);
1535 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1536 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1537 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1538 DUMP_REG(DC_WIN_DDA_INC);
1539 DUMP_REG(DC_WIN_LINE_STRIDE);
1540 DUMP_REG(DC_WIN_BUF_STRIDE);
1541 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1542 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1543 DUMP_REG(DC_WIN_DV_CONTROL);
1544 DUMP_REG(DC_WIN_BLEND_NOKEY);
1545 DUMP_REG(DC_WIN_BLEND_1WIN);
1546 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1547 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1548 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1549 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1550 DUMP_REG(DC_WINBUF_START_ADDR);
1551 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1552 DUMP_REG(DC_WINBUF_START_ADDR_U);
1553 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1554 DUMP_REG(DC_WINBUF_START_ADDR_V);
1555 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1556 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1557 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1558 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1559 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1560 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1561 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1562 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1563 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1564
1565#undef DUMP_REG
1566
1567unlock:
1568 drm_modeset_unlock_crtc(&dc->base);
1569 return err;
1570}
1571
1572static int tegra_dc_show_crc(struct seq_file *s, void *data)
1573{
1574 struct drm_info_node *node = s->private;
1575 struct tegra_dc *dc = node->info_ent->data;
1576 int err = 0;
1577 u32 value;
1578
1579 drm_modeset_lock_crtc(&dc->base, NULL);
1580
1581 if (!dc->base.state->active) {
1582 err = -EBUSY;
1583 goto unlock;
1584 }
1585
1586 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1587 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1588 tegra_dc_commit(dc);
1589
1590 drm_crtc_wait_one_vblank(&dc->base);
1591 drm_crtc_wait_one_vblank(&dc->base);
1592
1593 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1594 seq_printf(s, "%08x\n", value);
1595
1596 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1597
1598unlock:
1599 drm_modeset_unlock_crtc(&dc->base);
1600 return err;
1601}
1602
1603static int tegra_dc_show_stats(struct seq_file *s, void *data)
1604{
1605 struct drm_info_node *node = s->private;
1606 struct tegra_dc *dc = node->info_ent->data;
1607
1608 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1609 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1610 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1611 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1612
1613 return 0;
1614}
1615
1616static struct drm_info_list debugfs_files[] = {
1617 { "regs", tegra_dc_show_regs, 0, NULL },
1618 { "crc", tegra_dc_show_crc, 0, NULL },
1619 { "stats", tegra_dc_show_stats, 0, NULL },
1620};
1621
1622static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1623{
1624 unsigned int i;
1625 char *name;
1626 int err;
1627
1628 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1629 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1630 kfree(name);
1631
1632 if (!dc->debugfs)
1633 return -ENOMEM;
1634
1635 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1636 GFP_KERNEL);
1637 if (!dc->debugfs_files) {
1638 err = -ENOMEM;
1639 goto remove;
1640 }
1641
1642 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1643 dc->debugfs_files[i].data = dc;
1644
1645 err = drm_debugfs_create_files(dc->debugfs_files,
1646 ARRAY_SIZE(debugfs_files),
1647 dc->debugfs, minor);
1648 if (err < 0)
1649 goto free;
1650
1651 dc->minor = minor;
1652
1653 return 0;
1654
1655free:
1656 kfree(dc->debugfs_files);
1657 dc->debugfs_files = NULL;
1658remove:
1659 debugfs_remove(dc->debugfs);
1660 dc->debugfs = NULL;
1661
1662 return err;
1663}
1664
1665static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1666{
1667 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1668 dc->minor);
1669 dc->minor = NULL;
1670
1671 kfree(dc->debugfs_files);
1672 dc->debugfs_files = NULL;
1673
1674 debugfs_remove(dc->debugfs);
1675 dc->debugfs = NULL;
1676
1677 return 0;
1678}
1679
1680static int tegra_dc_init(struct host1x_client *client)
1681{
1682 struct drm_device *drm = dev_get_drvdata(client->parent);
1683 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1684 struct tegra_dc *dc = host1x_client_to_dc(client);
1685 struct tegra_drm *tegra = drm->dev_private;
1686 struct drm_plane *primary = NULL;
1687 struct drm_plane *cursor = NULL;
1688 u32 value;
1689 int err;
1690
1691 dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1692 if (!dc->syncpt)
1693 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1694
1695 if (tegra->domain) {
1696 err = iommu_attach_device(tegra->domain, dc->dev);
1697 if (err < 0) {
1698 dev_err(dc->dev, "failed to attach to domain: %d\n",
1699 err);
1700 return err;
1701 }
1702
1703 dc->domain = tegra->domain;
1704 }
1705
1706 primary = tegra_dc_primary_plane_create(drm, dc);
1707 if (IS_ERR(primary)) {
1708 err = PTR_ERR(primary);
1709 goto cleanup;
1710 }
1711
1712 if (dc->soc->supports_cursor) {
1713 cursor = tegra_dc_cursor_plane_create(drm, dc);
1714 if (IS_ERR(cursor)) {
1715 err = PTR_ERR(cursor);
1716 goto cleanup;
1717 }
1718 }
1719
1720 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1721 &tegra_crtc_funcs, NULL);
1722 if (err < 0)
1723 goto cleanup;
1724
1725 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1726 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1727
1728 /*
1729 * Keep track of the minimum pitch alignment across all display
1730 * controllers.
1731 */
1732 if (dc->soc->pitch_align > tegra->pitch_align)
1733 tegra->pitch_align = dc->soc->pitch_align;
1734
1735 err = tegra_dc_rgb_init(drm, dc);
1736 if (err < 0 && err != -ENODEV) {
1737 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1738 goto cleanup;
1739 }
1740
1741 err = tegra_dc_add_planes(drm, dc);
1742 if (err < 0)
1743 goto cleanup;
1744
1745 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1746 err = tegra_dc_debugfs_init(dc, drm->primary);
1747 if (err < 0)
1748 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1749 }
1750
1751 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1752 dev_name(dc->dev), dc);
1753 if (err < 0) {
1754 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1755 err);
1756 goto cleanup;
1757 }
1758
1759 /* initialize display controller */
1760 if (dc->syncpt) {
1761 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1762
1763 value = SYNCPT_CNTRL_NO_STALL;
1764 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1765
1766 value = SYNCPT_VSYNC_ENABLE | syncpt;
1767 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1768 }
1769
1770 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1771 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1772 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1773
1774 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1775 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1776 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1777
1778 /* initialize timer */
1779 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1780 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1781 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1782
1783 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1784 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1785 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1786
1787 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1788 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1789 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1790
1791 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1792 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1793 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1794
1795 if (dc->soc->supports_border_color)
1796 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1797
1798 tegra_dc_stats_reset(&dc->stats);
1799
1800 return 0;
1801
1802cleanup:
1803 if (cursor)
1804 drm_plane_cleanup(cursor);
1805
1806 if (primary)
1807 drm_plane_cleanup(primary);
1808
1809 if (tegra->domain) {
1810 iommu_detach_device(tegra->domain, dc->dev);
1811 dc->domain = NULL;
1812 }
1813
1814 return err;
1815}
1816
1817static int tegra_dc_exit(struct host1x_client *client)
1818{
1819 struct tegra_dc *dc = host1x_client_to_dc(client);
1820 int err;
1821
1822 devm_free_irq(dc->dev, dc->irq, dc);
1823
1824 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1825 err = tegra_dc_debugfs_exit(dc);
1826 if (err < 0)
1827 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1828 }
1829
1830 err = tegra_dc_rgb_exit(dc);
1831 if (err) {
1832 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1833 return err;
1834 }
1835
1836 if (dc->domain) {
1837 iommu_detach_device(dc->domain, dc->dev);
1838 dc->domain = NULL;
1839 }
1840
1841 host1x_syncpt_free(dc->syncpt);
1842
1843 return 0;
1844}
1845
1846static const struct host1x_client_ops dc_client_ops = {
1847 .init = tegra_dc_init,
1848 .exit = tegra_dc_exit,
1849};
1850
1851static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1852 .supports_border_color = true,
1853 .supports_interlacing = false,
1854 .supports_cursor = false,
1855 .supports_block_linear = false,
1856 .pitch_align = 8,
1857 .has_powergate = false,
1858};
1859
1860static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1861 .supports_border_color = true,
1862 .supports_interlacing = false,
1863 .supports_cursor = false,
1864 .supports_block_linear = false,
1865 .pitch_align = 8,
1866 .has_powergate = false,
1867};
1868
1869static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1870 .supports_border_color = true,
1871 .supports_interlacing = false,
1872 .supports_cursor = false,
1873 .supports_block_linear = false,
1874 .pitch_align = 64,
1875 .has_powergate = true,
1876};
1877
1878static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1879 .supports_border_color = false,
1880 .supports_interlacing = true,
1881 .supports_cursor = true,
1882 .supports_block_linear = true,
1883 .pitch_align = 64,
1884 .has_powergate = true,
1885};
1886
1887static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1888 .supports_border_color = false,
1889 .supports_interlacing = true,
1890 .supports_cursor = true,
1891 .supports_block_linear = true,
1892 .pitch_align = 64,
1893 .has_powergate = true,
1894};
1895
1896static const struct of_device_id tegra_dc_of_match[] = {
1897 {
1898 .compatible = "nvidia,tegra210-dc",
1899 .data = &tegra210_dc_soc_info,
1900 }, {
1901 .compatible = "nvidia,tegra124-dc",
1902 .data = &tegra124_dc_soc_info,
1903 }, {
1904 .compatible = "nvidia,tegra114-dc",
1905 .data = &tegra114_dc_soc_info,
1906 }, {
1907 .compatible = "nvidia,tegra30-dc",
1908 .data = &tegra30_dc_soc_info,
1909 }, {
1910 .compatible = "nvidia,tegra20-dc",
1911 .data = &tegra20_dc_soc_info,
1912 }, {
1913 /* sentinel */
1914 }
1915};
1916MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1917
1918static int tegra_dc_parse_dt(struct tegra_dc *dc)
1919{
1920 struct device_node *np;
1921 u32 value = 0;
1922 int err;
1923
1924 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1925 if (err < 0) {
1926 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1927
1928 /*
1929 * If the nvidia,head property isn't present, try to find the
1930 * correct head number by looking up the position of this
1931 * display controller's node within the device tree. Assuming
1932 * that the nodes are ordered properly in the DTS file and
1933 * that the translation into a flattened device tree blob
1934 * preserves that ordering this will actually yield the right
1935 * head number.
1936 *
1937 * If those assumptions don't hold, this will still work for
1938 * cases where only a single display controller is used.
1939 */
1940 for_each_matching_node(np, tegra_dc_of_match) {
1941 if (np == dc->dev->of_node) {
1942 of_node_put(np);
1943 break;
1944 }
1945
1946 value++;
1947 }
1948 }
1949
1950 dc->pipe = value;
1951
1952 return 0;
1953}
1954
1955static int tegra_dc_probe(struct platform_device *pdev)
1956{
1957 const struct of_device_id *id;
1958 struct resource *regs;
1959 struct tegra_dc *dc;
1960 int err;
1961
1962 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1963 if (!dc)
1964 return -ENOMEM;
1965
1966 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1967 if (!id)
1968 return -ENODEV;
1969
1970 spin_lock_init(&dc->lock);
1971 INIT_LIST_HEAD(&dc->list);
1972 dc->dev = &pdev->dev;
1973 dc->soc = id->data;
1974
1975 err = tegra_dc_parse_dt(dc);
1976 if (err < 0)
1977 return err;
1978
1979 dc->clk = devm_clk_get(&pdev->dev, NULL);
1980 if (IS_ERR(dc->clk)) {
1981 dev_err(&pdev->dev, "failed to get clock\n");
1982 return PTR_ERR(dc->clk);
1983 }
1984
1985 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1986 if (IS_ERR(dc->rst)) {
1987 dev_err(&pdev->dev, "failed to get reset\n");
1988 return PTR_ERR(dc->rst);
1989 }
1990
1991 if (dc->soc->has_powergate) {
1992 if (dc->pipe == 0)
1993 dc->powergate = TEGRA_POWERGATE_DIS;
1994 else
1995 dc->powergate = TEGRA_POWERGATE_DISB;
1996
1997 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1998 dc->rst);
1999 if (err < 0) {
2000 dev_err(&pdev->dev, "failed to power partition: %d\n",
2001 err);
2002 return err;
2003 }
2004 } else {
2005 err = clk_prepare_enable(dc->clk);
2006 if (err < 0) {
2007 dev_err(&pdev->dev, "failed to enable clock: %d\n",
2008 err);
2009 return err;
2010 }
2011
2012 err = reset_control_deassert(dc->rst);
2013 if (err < 0) {
2014 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2015 err);
2016 return err;
2017 }
2018 }
2019
2020 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2022 if (IS_ERR(dc->regs))
2023 return PTR_ERR(dc->regs);
2024
2025 dc->irq = platform_get_irq(pdev, 0);
2026 if (dc->irq < 0) {
2027 dev_err(&pdev->dev, "failed to get IRQ\n");
2028 return -ENXIO;
2029 }
2030
2031 INIT_LIST_HEAD(&dc->client.list);
2032 dc->client.ops = &dc_client_ops;
2033 dc->client.dev = &pdev->dev;
2034
2035 err = tegra_dc_rgb_probe(dc);
2036 if (err < 0 && err != -ENODEV) {
2037 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2038 return err;
2039 }
2040
2041 err = host1x_client_register(&dc->client);
2042 if (err < 0) {
2043 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2044 err);
2045 return err;
2046 }
2047
2048 platform_set_drvdata(pdev, dc);
2049
2050 return 0;
2051}
2052
2053static int tegra_dc_remove(struct platform_device *pdev)
2054{
2055 struct tegra_dc *dc = platform_get_drvdata(pdev);
2056 int err;
2057
2058 err = host1x_client_unregister(&dc->client);
2059 if (err < 0) {
2060 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2061 err);
2062 return err;
2063 }
2064
2065 err = tegra_dc_rgb_remove(dc);
2066 if (err < 0) {
2067 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2068 return err;
2069 }
2070
2071 reset_control_assert(dc->rst);
2072
2073 if (dc->soc->has_powergate)
2074 tegra_powergate_power_off(dc->powergate);
2075
2076 clk_disable_unprepare(dc->clk);
2077
2078 return 0;
2079}
2080
2081struct platform_driver tegra_dc_driver = {
2082 .driver = {
2083 .name = "tegra-dc",
2084 .of_match_table = tegra_dc_of_match,
2085 },
2086 .probe = tegra_dc_probe,
2087 .remove = tegra_dc_remove,
2088};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/reset.h>
15
16#include <soc/tegra/pmc.h>
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_debugfs.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_plane_helper.h>
23#include <drm/drm_vblank.h>
24
25#include "dc.h"
26#include "drm.h"
27#include "gem.h"
28#include "hub.h"
29#include "plane.h"
30
31static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
32 struct drm_crtc_state *state);
33
34static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
35{
36 stats->frames = 0;
37 stats->vblank = 0;
38 stats->underflow = 0;
39 stats->overflow = 0;
40}
41
42/* Reads the active copy of a register. */
43static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
44{
45 u32 value;
46
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
48 value = tegra_dc_readl(dc, offset);
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
50
51 return value;
52}
53
54static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
55 unsigned int offset)
56{
57 if (offset >= 0x500 && offset <= 0x638) {
58 offset = 0x000 + (offset - 0x500);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x700 && offset <= 0x719) {
63 offset = 0x180 + (offset - 0x700);
64 return plane->offset + offset;
65 }
66
67 if (offset >= 0x800 && offset <= 0x839) {
68 offset = 0x1c0 + (offset - 0x800);
69 return plane->offset + offset;
70 }
71
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
73
74 return plane->offset + offset;
75}
76
77static inline u32 tegra_plane_readl(struct tegra_plane *plane,
78 unsigned int offset)
79{
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
81}
82
83static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
84 unsigned int offset)
85{
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
87}
88
89bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
90{
91 struct device_node *np = dc->dev->of_node;
92 struct of_phandle_iterator it;
93 int err;
94
95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
96 if (it.node == dev->of_node)
97 return true;
98
99 return false;
100}
101
102/*
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
105 * Latching happens mmediately if the display controller is in STOP mode or
106 * on the next frame boundary otherwise.
107 *
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
111 * into the ACTIVE copy, either immediately if the display controller is in
112 * STOP mode, or at the next frame boundary otherwise.
113 */
114void tegra_dc_commit(struct tegra_dc *dc)
115{
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
118}
119
120static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
121 unsigned int bpp)
122{
123 fixed20_12 outf = dfixed_init(out);
124 fixed20_12 inf = dfixed_init(in);
125 u32 dda_inc;
126 int max;
127
128 if (v)
129 max = 15;
130 else {
131 switch (bpp) {
132 case 2:
133 max = 8;
134 break;
135
136 default:
137 WARN_ON_ONCE(1);
138 /* fallthrough */
139 case 4:
140 max = 4;
141 break;
142 }
143 }
144
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
146 inf.full -= dfixed_const(1);
147
148 dda_inc = dfixed_div(inf, outf);
149 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
150
151 return dda_inc;
152}
153
154static inline u32 compute_initial_dda(unsigned int in)
155{
156 fixed20_12 inf = dfixed_init(in);
157 return dfixed_frac(inf);
158}
159
160static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
161{
162 u32 background[3] = {
163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
166 };
167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
168 BLEND_COLOR_KEY_NONE;
169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
170 struct tegra_plane_state *state;
171 u32 blending[2];
172 unsigned int i;
173
174 /* disable blending for non-overlapping case */
175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
177
178 state = to_tegra_plane_state(plane->base.state);
179
180 if (state->opaque) {
181 /*
182 * Since custom fix-weight blending isn't utilized and weight
183 * of top window is set to max, we can enforce dependent
184 * blending which in this case results in transparent bottom
185 * window if top window is opaque and if top window enables
186 * alpha blending, then bottom window is getting alpha value
187 * of 1 minus the sum of alpha components of the overlapping
188 * plane.
189 */
190 background[0] |= BLEND_CONTROL_DEPENDENT;
191 background[1] |= BLEND_CONTROL_DEPENDENT;
192
193 /*
194 * The region where three windows overlap is the intersection
195 * of the two regions where two windows overlap. It contributes
196 * to the area if all of the windows on top of it have an alpha
197 * component.
198 */
199 switch (state->base.normalized_zpos) {
200 case 0:
201 if (state->blending[0].alpha &&
202 state->blending[1].alpha)
203 background[2] |= BLEND_CONTROL_DEPENDENT;
204 break;
205
206 case 1:
207 background[2] |= BLEND_CONTROL_DEPENDENT;
208 break;
209 }
210 } else {
211 /*
212 * Enable alpha blending if pixel format has an alpha
213 * component.
214 */
215 foreground |= BLEND_CONTROL_ALPHA;
216
217 /*
218 * If any of the windows on top of this window is opaque, it
219 * will completely conceal this window within that area. If
220 * top window has an alpha component, it is blended over the
221 * bottom window.
222 */
223 for (i = 0; i < 2; i++) {
224 if (state->blending[i].alpha &&
225 state->blending[i].top)
226 background[i] |= BLEND_CONTROL_DEPENDENT;
227 }
228
229 switch (state->base.normalized_zpos) {
230 case 0:
231 if (state->blending[0].alpha &&
232 state->blending[1].alpha)
233 background[2] |= BLEND_CONTROL_DEPENDENT;
234 break;
235
236 case 1:
237 /*
238 * When both middle and topmost windows have an alpha,
239 * these windows a mixed together and then the result
240 * is blended over the bottom window.
241 */
242 if (state->blending[0].alpha &&
243 state->blending[0].top)
244 background[2] |= BLEND_CONTROL_ALPHA;
245
246 if (state->blending[1].alpha &&
247 state->blending[1].top)
248 background[2] |= BLEND_CONTROL_ALPHA;
249 break;
250 }
251 }
252
253 switch (state->base.normalized_zpos) {
254 case 0:
255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
258 break;
259
260 case 1:
261 /*
262 * If window B / C is topmost, then X / Y registers are
263 * matching the order of blending[...] state indices,
264 * otherwise a swap is required.
265 */
266 if (!state->blending[0].top && state->blending[1].top) {
267 blending[0] = foreground;
268 blending[1] = background[1];
269 } else {
270 blending[0] = background[0];
271 blending[1] = foreground;
272 }
273
274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
277 break;
278
279 case 2:
280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
283 break;
284 }
285}
286
287static void tegra_plane_setup_blending(struct tegra_plane *plane,
288 const struct tegra_dc_window *window)
289{
290 u32 value;
291
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
296
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
301
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
304}
305
306static bool
307tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
308 const struct tegra_dc_window *window)
309{
310 struct tegra_dc *dc = plane->dc;
311
312 if (window->src.w == window->dst.w)
313 return false;
314
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
316 return false;
317
318 return true;
319}
320
321static bool
322tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
323 const struct tegra_dc_window *window)
324{
325 struct tegra_dc *dc = plane->dc;
326
327 if (window->src.h == window->dst.h)
328 return false;
329
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
331 return false;
332
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
334 return false;
335
336 return true;
337}
338
339static void tegra_dc_setup_window(struct tegra_plane *plane,
340 const struct tegra_dc_window *window)
341{
342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
343 struct tegra_dc *dc = plane->dc;
344 bool yuv, planar;
345 u32 value;
346
347 /*
348 * For YUV planar modes, the number of bytes per pixel takes into
349 * account only the luma component and therefore is 1.
350 */
351 yuv = tegra_plane_format_is_yuv(window->format, &planar);
352 if (!yuv)
353 bpp = window->bits_per_pixel / 8;
354 else
355 bpp = planar ? 1 : 2;
356
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
359
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
362
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
365
366 h_offset = window->src.x * bpp;
367 v_offset = window->src.y;
368 h_size = window->src.w * bpp;
369 v_size = window->src.h;
370
371 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
372 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
373
374 /*
375 * For DDA computations the number of bytes per pixel for YUV planar
376 * modes needs to take into account all Y, U and V components.
377 */
378 if (yuv && planar)
379 bpp = 2;
380
381 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
382 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
383
384 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
385 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
386
387 h_dda = compute_initial_dda(window->src.x);
388 v_dda = compute_initial_dda(window->src.y);
389
390 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
391 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
392
393 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
394 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
395
396 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
397
398 if (yuv && planar) {
399 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
400 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
401 value = window->stride[1] << 16 | window->stride[0];
402 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
403 } else {
404 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
405 }
406
407 if (window->bottom_up)
408 v_offset += window->src.h - 1;
409
410 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
411 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
412
413 if (dc->soc->supports_block_linear) {
414 unsigned long height = window->tiling.value;
415
416 switch (window->tiling.mode) {
417 case TEGRA_BO_TILING_MODE_PITCH:
418 value = DC_WINBUF_SURFACE_KIND_PITCH;
419 break;
420
421 case TEGRA_BO_TILING_MODE_TILED:
422 value = DC_WINBUF_SURFACE_KIND_TILED;
423 break;
424
425 case TEGRA_BO_TILING_MODE_BLOCK:
426 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
427 DC_WINBUF_SURFACE_KIND_BLOCK;
428 break;
429 }
430
431 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
432 } else {
433 switch (window->tiling.mode) {
434 case TEGRA_BO_TILING_MODE_PITCH:
435 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
436 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
437 break;
438
439 case TEGRA_BO_TILING_MODE_TILED:
440 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
441 DC_WIN_BUFFER_ADDR_MODE_TILE;
442 break;
443
444 case TEGRA_BO_TILING_MODE_BLOCK:
445 /*
446 * No need to handle this here because ->atomic_check
447 * will already have filtered it out.
448 */
449 break;
450 }
451
452 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
453 }
454
455 value = WIN_ENABLE;
456
457 if (yuv) {
458 /* setup default colorspace conversion coefficients */
459 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
460 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
461 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
462 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
463 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
464 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
465 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
466 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
467
468 value |= CSC_ENABLE;
469 } else if (window->bits_per_pixel < 24) {
470 value |= COLOR_EXPAND;
471 }
472
473 if (window->bottom_up)
474 value |= V_DIRECTION;
475
476 if (tegra_plane_use_horizontal_filtering(plane, window)) {
477 /*
478 * Enable horizontal 6-tap filter and set filtering
479 * coefficients to the default values defined in TRM.
480 */
481 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
482 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
483 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
484 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
485 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
486 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
487 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
488 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
489 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
490 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
491 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
492 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
493 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
494 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
495 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
496 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
497
498 value |= H_FILTER;
499 }
500
501 if (tegra_plane_use_vertical_filtering(plane, window)) {
502 unsigned int i, k;
503
504 /*
505 * Enable vertical 2-tap filter and set filtering
506 * coefficients to the default values defined in TRM.
507 */
508 for (i = 0, k = 128; i < 16; i++, k -= 8)
509 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
510
511 value |= V_FILTER;
512 }
513
514 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
515
516 if (dc->soc->has_legacy_blending)
517 tegra_plane_setup_blending_legacy(plane);
518 else
519 tegra_plane_setup_blending(plane, window);
520}
521
522static const u32 tegra20_primary_formats[] = {
523 DRM_FORMAT_ARGB4444,
524 DRM_FORMAT_ARGB1555,
525 DRM_FORMAT_RGB565,
526 DRM_FORMAT_RGBA5551,
527 DRM_FORMAT_ABGR8888,
528 DRM_FORMAT_ARGB8888,
529 /* non-native formats */
530 DRM_FORMAT_XRGB1555,
531 DRM_FORMAT_RGBX5551,
532 DRM_FORMAT_XBGR8888,
533 DRM_FORMAT_XRGB8888,
534};
535
536static const u64 tegra20_modifiers[] = {
537 DRM_FORMAT_MOD_LINEAR,
538 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
539 DRM_FORMAT_MOD_INVALID
540};
541
542static const u32 tegra114_primary_formats[] = {
543 DRM_FORMAT_ARGB4444,
544 DRM_FORMAT_ARGB1555,
545 DRM_FORMAT_RGB565,
546 DRM_FORMAT_RGBA5551,
547 DRM_FORMAT_ABGR8888,
548 DRM_FORMAT_ARGB8888,
549 /* new on Tegra114 */
550 DRM_FORMAT_ABGR4444,
551 DRM_FORMAT_ABGR1555,
552 DRM_FORMAT_BGRA5551,
553 DRM_FORMAT_XRGB1555,
554 DRM_FORMAT_RGBX5551,
555 DRM_FORMAT_XBGR1555,
556 DRM_FORMAT_BGRX5551,
557 DRM_FORMAT_BGR565,
558 DRM_FORMAT_BGRA8888,
559 DRM_FORMAT_RGBA8888,
560 DRM_FORMAT_XRGB8888,
561 DRM_FORMAT_XBGR8888,
562};
563
564static const u32 tegra124_primary_formats[] = {
565 DRM_FORMAT_ARGB4444,
566 DRM_FORMAT_ARGB1555,
567 DRM_FORMAT_RGB565,
568 DRM_FORMAT_RGBA5551,
569 DRM_FORMAT_ABGR8888,
570 DRM_FORMAT_ARGB8888,
571 /* new on Tegra114 */
572 DRM_FORMAT_ABGR4444,
573 DRM_FORMAT_ABGR1555,
574 DRM_FORMAT_BGRA5551,
575 DRM_FORMAT_XRGB1555,
576 DRM_FORMAT_RGBX5551,
577 DRM_FORMAT_XBGR1555,
578 DRM_FORMAT_BGRX5551,
579 DRM_FORMAT_BGR565,
580 DRM_FORMAT_BGRA8888,
581 DRM_FORMAT_RGBA8888,
582 DRM_FORMAT_XRGB8888,
583 DRM_FORMAT_XBGR8888,
584 /* new on Tegra124 */
585 DRM_FORMAT_RGBX8888,
586 DRM_FORMAT_BGRX8888,
587};
588
589static const u64 tegra124_modifiers[] = {
590 DRM_FORMAT_MOD_LINEAR,
591 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
592 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
593 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
594 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
595 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
596 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
597 DRM_FORMAT_MOD_INVALID
598};
599
600static int tegra_plane_atomic_check(struct drm_plane *plane,
601 struct drm_plane_state *state)
602{
603 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
604 unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
605 struct tegra_bo_tiling *tiling = &plane_state->tiling;
606 struct tegra_plane *tegra = to_tegra_plane(plane);
607 struct tegra_dc *dc = to_tegra_dc(state->crtc);
608 int err;
609
610 /* no need for further checks if the plane is being disabled */
611 if (!state->crtc)
612 return 0;
613
614 err = tegra_plane_format(state->fb->format->format,
615 &plane_state->format,
616 &plane_state->swap);
617 if (err < 0)
618 return err;
619
620 /*
621 * Tegra20 and Tegra30 are special cases here because they support
622 * only variants of specific formats with an alpha component, but not
623 * the corresponding opaque formats. However, the opaque formats can
624 * be emulated by disabling alpha blending for the plane.
625 */
626 if (dc->soc->has_legacy_blending) {
627 err = tegra_plane_setup_legacy_state(tegra, plane_state);
628 if (err < 0)
629 return err;
630 }
631
632 err = tegra_fb_get_tiling(state->fb, tiling);
633 if (err < 0)
634 return err;
635
636 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
637 !dc->soc->supports_block_linear) {
638 DRM_ERROR("hardware doesn't support block linear mode\n");
639 return -EINVAL;
640 }
641
642 rotation = drm_rotation_simplify(state->rotation, rotation);
643
644 if (rotation & DRM_MODE_REFLECT_Y)
645 plane_state->bottom_up = true;
646 else
647 plane_state->bottom_up = false;
648
649 /*
650 * Tegra doesn't support different strides for U and V planes so we
651 * error out if the user tries to display a framebuffer with such a
652 * configuration.
653 */
654 if (state->fb->format->num_planes > 2) {
655 if (state->fb->pitches[2] != state->fb->pitches[1]) {
656 DRM_ERROR("unsupported UV-plane configuration\n");
657 return -EINVAL;
658 }
659 }
660
661 err = tegra_plane_state_add(tegra, state);
662 if (err < 0)
663 return err;
664
665 return 0;
666}
667
668static void tegra_plane_atomic_disable(struct drm_plane *plane,
669 struct drm_plane_state *old_state)
670{
671 struct tegra_plane *p = to_tegra_plane(plane);
672 u32 value;
673
674 /* rien ne va plus */
675 if (!old_state || !old_state->crtc)
676 return;
677
678 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
679 value &= ~WIN_ENABLE;
680 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
681}
682
683static void tegra_plane_atomic_update(struct drm_plane *plane,
684 struct drm_plane_state *old_state)
685{
686 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
687 struct drm_framebuffer *fb = plane->state->fb;
688 struct tegra_plane *p = to_tegra_plane(plane);
689 struct tegra_dc_window window;
690 unsigned int i;
691
692 /* rien ne va plus */
693 if (!plane->state->crtc || !plane->state->fb)
694 return;
695
696 if (!plane->state->visible)
697 return tegra_plane_atomic_disable(plane, old_state);
698
699 memset(&window, 0, sizeof(window));
700 window.src.x = plane->state->src.x1 >> 16;
701 window.src.y = plane->state->src.y1 >> 16;
702 window.src.w = drm_rect_width(&plane->state->src) >> 16;
703 window.src.h = drm_rect_height(&plane->state->src) >> 16;
704 window.dst.x = plane->state->dst.x1;
705 window.dst.y = plane->state->dst.y1;
706 window.dst.w = drm_rect_width(&plane->state->dst);
707 window.dst.h = drm_rect_height(&plane->state->dst);
708 window.bits_per_pixel = fb->format->cpp[0] * 8;
709 window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
710
711 /* copy from state */
712 window.zpos = plane->state->normalized_zpos;
713 window.tiling = state->tiling;
714 window.format = state->format;
715 window.swap = state->swap;
716
717 for (i = 0; i < fb->format->num_planes; i++) {
718 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
719
720 window.base[i] = bo->paddr + fb->offsets[i];
721
722 /*
723 * Tegra uses a shared stride for UV planes. Framebuffers are
724 * already checked for this in the tegra_plane_atomic_check()
725 * function, so it's safe to ignore the V-plane pitch here.
726 */
727 if (i < 2)
728 window.stride[i] = fb->pitches[i];
729 }
730
731 tegra_dc_setup_window(p, &window);
732}
733
734static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
735 .atomic_check = tegra_plane_atomic_check,
736 .atomic_disable = tegra_plane_atomic_disable,
737 .atomic_update = tegra_plane_atomic_update,
738};
739
740static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
741{
742 /*
743 * Ideally this would use drm_crtc_mask(), but that would require the
744 * CRTC to already be in the mode_config's list of CRTCs. However, it
745 * will only be added to that list in the drm_crtc_init_with_planes()
746 * (in tegra_dc_init()), which in turn requires registration of these
747 * planes. So we have ourselves a nice little chicken and egg problem
748 * here.
749 *
750 * We work around this by manually creating the mask from the number
751 * of CRTCs that have been registered, and should therefore always be
752 * the same as drm_crtc_index() after registration.
753 */
754 return 1 << drm->mode_config.num_crtc;
755}
756
757static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
758 struct tegra_dc *dc)
759{
760 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
761 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
762 struct tegra_plane *plane;
763 unsigned int num_formats;
764 const u64 *modifiers;
765 const u32 *formats;
766 int err;
767
768 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
769 if (!plane)
770 return ERR_PTR(-ENOMEM);
771
772 /* Always use window A as primary window */
773 plane->offset = 0xa00;
774 plane->index = 0;
775 plane->dc = dc;
776
777 num_formats = dc->soc->num_primary_formats;
778 formats = dc->soc->primary_formats;
779 modifiers = dc->soc->modifiers;
780
781 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
782 &tegra_plane_funcs, formats,
783 num_formats, modifiers, type, NULL);
784 if (err < 0) {
785 kfree(plane);
786 return ERR_PTR(err);
787 }
788
789 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
790 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
791
792 err = drm_plane_create_rotation_property(&plane->base,
793 DRM_MODE_ROTATE_0,
794 DRM_MODE_ROTATE_0 |
795 DRM_MODE_REFLECT_Y);
796 if (err < 0)
797 dev_err(dc->dev, "failed to create rotation property: %d\n",
798 err);
799
800 return &plane->base;
801}
802
803static const u32 tegra_cursor_plane_formats[] = {
804 DRM_FORMAT_RGBA8888,
805};
806
807static int tegra_cursor_atomic_check(struct drm_plane *plane,
808 struct drm_plane_state *state)
809{
810 struct tegra_plane *tegra = to_tegra_plane(plane);
811 int err;
812
813 /* no need for further checks if the plane is being disabled */
814 if (!state->crtc)
815 return 0;
816
817 /* scaling not supported for cursor */
818 if ((state->src_w >> 16 != state->crtc_w) ||
819 (state->src_h >> 16 != state->crtc_h))
820 return -EINVAL;
821
822 /* only square cursors supported */
823 if (state->src_w != state->src_h)
824 return -EINVAL;
825
826 if (state->crtc_w != 32 && state->crtc_w != 64 &&
827 state->crtc_w != 128 && state->crtc_w != 256)
828 return -EINVAL;
829
830 err = tegra_plane_state_add(tegra, state);
831 if (err < 0)
832 return err;
833
834 return 0;
835}
836
837static void tegra_cursor_atomic_update(struct drm_plane *plane,
838 struct drm_plane_state *old_state)
839{
840 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
841 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
842 struct drm_plane_state *state = plane->state;
843 u32 value = CURSOR_CLIP_DISPLAY;
844
845 /* rien ne va plus */
846 if (!plane->state->crtc || !plane->state->fb)
847 return;
848
849 switch (state->crtc_w) {
850 case 32:
851 value |= CURSOR_SIZE_32x32;
852 break;
853
854 case 64:
855 value |= CURSOR_SIZE_64x64;
856 break;
857
858 case 128:
859 value |= CURSOR_SIZE_128x128;
860 break;
861
862 case 256:
863 value |= CURSOR_SIZE_256x256;
864 break;
865
866 default:
867 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
868 state->crtc_h);
869 return;
870 }
871
872 value |= (bo->paddr >> 10) & 0x3fffff;
873 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
874
875#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
876 value = (bo->paddr >> 32) & 0x3;
877 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
878#endif
879
880 /* enable cursor and set blend mode */
881 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
882 value |= CURSOR_ENABLE;
883 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
884
885 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
886 value &= ~CURSOR_DST_BLEND_MASK;
887 value &= ~CURSOR_SRC_BLEND_MASK;
888 value |= CURSOR_MODE_NORMAL;
889 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
890 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
891 value |= CURSOR_ALPHA;
892 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
893
894 /* position the cursor */
895 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
896 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
897}
898
899static void tegra_cursor_atomic_disable(struct drm_plane *plane,
900 struct drm_plane_state *old_state)
901{
902 struct tegra_dc *dc;
903 u32 value;
904
905 /* rien ne va plus */
906 if (!old_state || !old_state->crtc)
907 return;
908
909 dc = to_tegra_dc(old_state->crtc);
910
911 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
912 value &= ~CURSOR_ENABLE;
913 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
914}
915
916static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
917 .atomic_check = tegra_cursor_atomic_check,
918 .atomic_update = tegra_cursor_atomic_update,
919 .atomic_disable = tegra_cursor_atomic_disable,
920};
921
922static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
923 struct tegra_dc *dc)
924{
925 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
926 struct tegra_plane *plane;
927 unsigned int num_formats;
928 const u32 *formats;
929 int err;
930
931 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
932 if (!plane)
933 return ERR_PTR(-ENOMEM);
934
935 /*
936 * This index is kind of fake. The cursor isn't a regular plane, but
937 * its update and activation request bits in DC_CMD_STATE_CONTROL do
938 * use the same programming. Setting this fake index here allows the
939 * code in tegra_add_plane_state() to do the right thing without the
940 * need to special-casing the cursor plane.
941 */
942 plane->index = 6;
943 plane->dc = dc;
944
945 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
946 formats = tegra_cursor_plane_formats;
947
948 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
949 &tegra_plane_funcs, formats,
950 num_formats, NULL,
951 DRM_PLANE_TYPE_CURSOR, NULL);
952 if (err < 0) {
953 kfree(plane);
954 return ERR_PTR(err);
955 }
956
957 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
958
959 return &plane->base;
960}
961
962static const u32 tegra20_overlay_formats[] = {
963 DRM_FORMAT_ARGB4444,
964 DRM_FORMAT_ARGB1555,
965 DRM_FORMAT_RGB565,
966 DRM_FORMAT_RGBA5551,
967 DRM_FORMAT_ABGR8888,
968 DRM_FORMAT_ARGB8888,
969 /* non-native formats */
970 DRM_FORMAT_XRGB1555,
971 DRM_FORMAT_RGBX5551,
972 DRM_FORMAT_XBGR8888,
973 DRM_FORMAT_XRGB8888,
974 /* planar formats */
975 DRM_FORMAT_UYVY,
976 DRM_FORMAT_YUYV,
977 DRM_FORMAT_YUV420,
978 DRM_FORMAT_YUV422,
979};
980
981static const u32 tegra114_overlay_formats[] = {
982 DRM_FORMAT_ARGB4444,
983 DRM_FORMAT_ARGB1555,
984 DRM_FORMAT_RGB565,
985 DRM_FORMAT_RGBA5551,
986 DRM_FORMAT_ABGR8888,
987 DRM_FORMAT_ARGB8888,
988 /* new on Tegra114 */
989 DRM_FORMAT_ABGR4444,
990 DRM_FORMAT_ABGR1555,
991 DRM_FORMAT_BGRA5551,
992 DRM_FORMAT_XRGB1555,
993 DRM_FORMAT_RGBX5551,
994 DRM_FORMAT_XBGR1555,
995 DRM_FORMAT_BGRX5551,
996 DRM_FORMAT_BGR565,
997 DRM_FORMAT_BGRA8888,
998 DRM_FORMAT_RGBA8888,
999 DRM_FORMAT_XRGB8888,
1000 DRM_FORMAT_XBGR8888,
1001 /* planar formats */
1002 DRM_FORMAT_UYVY,
1003 DRM_FORMAT_YUYV,
1004 DRM_FORMAT_YUV420,
1005 DRM_FORMAT_YUV422,
1006};
1007
1008static const u32 tegra124_overlay_formats[] = {
1009 DRM_FORMAT_ARGB4444,
1010 DRM_FORMAT_ARGB1555,
1011 DRM_FORMAT_RGB565,
1012 DRM_FORMAT_RGBA5551,
1013 DRM_FORMAT_ABGR8888,
1014 DRM_FORMAT_ARGB8888,
1015 /* new on Tegra114 */
1016 DRM_FORMAT_ABGR4444,
1017 DRM_FORMAT_ABGR1555,
1018 DRM_FORMAT_BGRA5551,
1019 DRM_FORMAT_XRGB1555,
1020 DRM_FORMAT_RGBX5551,
1021 DRM_FORMAT_XBGR1555,
1022 DRM_FORMAT_BGRX5551,
1023 DRM_FORMAT_BGR565,
1024 DRM_FORMAT_BGRA8888,
1025 DRM_FORMAT_RGBA8888,
1026 DRM_FORMAT_XRGB8888,
1027 DRM_FORMAT_XBGR8888,
1028 /* new on Tegra124 */
1029 DRM_FORMAT_RGBX8888,
1030 DRM_FORMAT_BGRX8888,
1031 /* planar formats */
1032 DRM_FORMAT_UYVY,
1033 DRM_FORMAT_YUYV,
1034 DRM_FORMAT_YUV420,
1035 DRM_FORMAT_YUV422,
1036};
1037
1038static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1039 struct tegra_dc *dc,
1040 unsigned int index,
1041 bool cursor)
1042{
1043 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1044 struct tegra_plane *plane;
1045 unsigned int num_formats;
1046 enum drm_plane_type type;
1047 const u32 *formats;
1048 int err;
1049
1050 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1051 if (!plane)
1052 return ERR_PTR(-ENOMEM);
1053
1054 plane->offset = 0xa00 + 0x200 * index;
1055 plane->index = index;
1056 plane->dc = dc;
1057
1058 num_formats = dc->soc->num_overlay_formats;
1059 formats = dc->soc->overlay_formats;
1060
1061 if (!cursor)
1062 type = DRM_PLANE_TYPE_OVERLAY;
1063 else
1064 type = DRM_PLANE_TYPE_CURSOR;
1065
1066 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1067 &tegra_plane_funcs, formats,
1068 num_formats, NULL, type, NULL);
1069 if (err < 0) {
1070 kfree(plane);
1071 return ERR_PTR(err);
1072 }
1073
1074 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1075 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1076
1077 err = drm_plane_create_rotation_property(&plane->base,
1078 DRM_MODE_ROTATE_0,
1079 DRM_MODE_ROTATE_0 |
1080 DRM_MODE_REFLECT_Y);
1081 if (err < 0)
1082 dev_err(dc->dev, "failed to create rotation property: %d\n",
1083 err);
1084
1085 return &plane->base;
1086}
1087
1088static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1089 struct tegra_dc *dc)
1090{
1091 struct drm_plane *plane, *primary = NULL;
1092 unsigned int i, j;
1093
1094 for (i = 0; i < dc->soc->num_wgrps; i++) {
1095 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1096
1097 if (wgrp->dc == dc->pipe) {
1098 for (j = 0; j < wgrp->num_windows; j++) {
1099 unsigned int index = wgrp->windows[j];
1100
1101 plane = tegra_shared_plane_create(drm, dc,
1102 wgrp->index,
1103 index);
1104 if (IS_ERR(plane))
1105 return plane;
1106
1107 /*
1108 * Choose the first shared plane owned by this
1109 * head as the primary plane.
1110 */
1111 if (!primary) {
1112 plane->type = DRM_PLANE_TYPE_PRIMARY;
1113 primary = plane;
1114 }
1115 }
1116 }
1117 }
1118
1119 return primary;
1120}
1121
1122static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1123 struct tegra_dc *dc)
1124{
1125 struct drm_plane *planes[2], *primary;
1126 unsigned int planes_num;
1127 unsigned int i;
1128 int err;
1129
1130 primary = tegra_primary_plane_create(drm, dc);
1131 if (IS_ERR(primary))
1132 return primary;
1133
1134 if (dc->soc->supports_cursor)
1135 planes_num = 2;
1136 else
1137 planes_num = 1;
1138
1139 for (i = 0; i < planes_num; i++) {
1140 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1141 false);
1142 if (IS_ERR(planes[i])) {
1143 err = PTR_ERR(planes[i]);
1144
1145 while (i--)
1146 tegra_plane_funcs.destroy(planes[i]);
1147
1148 tegra_plane_funcs.destroy(primary);
1149 return ERR_PTR(err);
1150 }
1151 }
1152
1153 return primary;
1154}
1155
1156static void tegra_dc_destroy(struct drm_crtc *crtc)
1157{
1158 drm_crtc_cleanup(crtc);
1159}
1160
1161static void tegra_crtc_reset(struct drm_crtc *crtc)
1162{
1163 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1164
1165 if (crtc->state)
1166 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1167
1168 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1169 drm_crtc_vblank_reset(crtc);
1170}
1171
1172static struct drm_crtc_state *
1173tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1174{
1175 struct tegra_dc_state *state = to_dc_state(crtc->state);
1176 struct tegra_dc_state *copy;
1177
1178 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1179 if (!copy)
1180 return NULL;
1181
1182 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1183 copy->clk = state->clk;
1184 copy->pclk = state->pclk;
1185 copy->div = state->div;
1186 copy->planes = state->planes;
1187
1188 return ©->base;
1189}
1190
1191static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1192 struct drm_crtc_state *state)
1193{
1194 __drm_atomic_helper_crtc_destroy_state(state);
1195 kfree(state);
1196}
1197
1198#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1199
1200static const struct debugfs_reg32 tegra_dc_regs[] = {
1201 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1202 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1203 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1204 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1205 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1206 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1207 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1208 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1209 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1210 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1211 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1212 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1213 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1214 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1215 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1216 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1217 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1218 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1219 DEBUGFS_REG32(DC_CMD_INT_MASK),
1220 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1221 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1222 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1223 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1224 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1225 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1226 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1227 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1228 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1229 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1230 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1231 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1232 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1233 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1234 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1235 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1236 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1237 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1238 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1239 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1240 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1241 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1242 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1243 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1244 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1245 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1246 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1247 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1248 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1249 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1250 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1251 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1252 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1253 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1254 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1255 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1256 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1257 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1258 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1259 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1260 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1261 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1262 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1263 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1264 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1265 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1266 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1267 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1268 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1269 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1270 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1271 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1272 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1273 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1274 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1275 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1276 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1277 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1278 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1279 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1280 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1281 DEBUGFS_REG32(DC_DISP_ACTIVE),
1282 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1283 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1284 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1285 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1286 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1287 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1288 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1289 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1290 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1291 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1292 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1293 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1294 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1295 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1296 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1297 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1298 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1299 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1300 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1301 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1302 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1303 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1304 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1305 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1306 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1307 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1308 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1309 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1310 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1311 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1312 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1313 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1314 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1315 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1316 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1317 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1318 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1319 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1320 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1321 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1322 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1323 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1324 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1325 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1326 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1327 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1328 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1329 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1330 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1331 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1332 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1333 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1334 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1335 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1336 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1337 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1338 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1339 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1340 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1341 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1342 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1343 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1344 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1345 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1346 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1347 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1348 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1349 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1350 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1351 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1352 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1353 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1354 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1355 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1356 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1357 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1358 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1359 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1360 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1361 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1362 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1363 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1364 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1365 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1366 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1367 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1368 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1369 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1370 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1371 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1372 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1373 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1374 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1375 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1376 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1377 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1378 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1379 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1380 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1381 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1382 DEBUGFS_REG32(DC_WIN_POSITION),
1383 DEBUGFS_REG32(DC_WIN_SIZE),
1384 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1385 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1386 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1387 DEBUGFS_REG32(DC_WIN_DDA_INC),
1388 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1389 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1390 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1391 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1392 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1393 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1394 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1395 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1396 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1397 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1398 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1399 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1400 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1401 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1402 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1403 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1404 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1405 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1406 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1407 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1408 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1409 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1410 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1411 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1412 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1413};
1414
1415static int tegra_dc_show_regs(struct seq_file *s, void *data)
1416{
1417 struct drm_info_node *node = s->private;
1418 struct tegra_dc *dc = node->info_ent->data;
1419 unsigned int i;
1420 int err = 0;
1421
1422 drm_modeset_lock(&dc->base.mutex, NULL);
1423
1424 if (!dc->base.state->active) {
1425 err = -EBUSY;
1426 goto unlock;
1427 }
1428
1429 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1430 unsigned int offset = tegra_dc_regs[i].offset;
1431
1432 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1433 offset, tegra_dc_readl(dc, offset));
1434 }
1435
1436unlock:
1437 drm_modeset_unlock(&dc->base.mutex);
1438 return err;
1439}
1440
1441static int tegra_dc_show_crc(struct seq_file *s, void *data)
1442{
1443 struct drm_info_node *node = s->private;
1444 struct tegra_dc *dc = node->info_ent->data;
1445 int err = 0;
1446 u32 value;
1447
1448 drm_modeset_lock(&dc->base.mutex, NULL);
1449
1450 if (!dc->base.state->active) {
1451 err = -EBUSY;
1452 goto unlock;
1453 }
1454
1455 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1456 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1457 tegra_dc_commit(dc);
1458
1459 drm_crtc_wait_one_vblank(&dc->base);
1460 drm_crtc_wait_one_vblank(&dc->base);
1461
1462 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1463 seq_printf(s, "%08x\n", value);
1464
1465 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1466
1467unlock:
1468 drm_modeset_unlock(&dc->base.mutex);
1469 return err;
1470}
1471
1472static int tegra_dc_show_stats(struct seq_file *s, void *data)
1473{
1474 struct drm_info_node *node = s->private;
1475 struct tegra_dc *dc = node->info_ent->data;
1476
1477 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1478 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1479 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1480 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1481
1482 return 0;
1483}
1484
1485static struct drm_info_list debugfs_files[] = {
1486 { "regs", tegra_dc_show_regs, 0, NULL },
1487 { "crc", tegra_dc_show_crc, 0, NULL },
1488 { "stats", tegra_dc_show_stats, 0, NULL },
1489};
1490
1491static int tegra_dc_late_register(struct drm_crtc *crtc)
1492{
1493 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1494 struct drm_minor *minor = crtc->dev->primary;
1495 struct dentry *root;
1496 struct tegra_dc *dc = to_tegra_dc(crtc);
1497 int err;
1498
1499#ifdef CONFIG_DEBUG_FS
1500 root = crtc->debugfs_entry;
1501#else
1502 root = NULL;
1503#endif
1504
1505 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1506 GFP_KERNEL);
1507 if (!dc->debugfs_files)
1508 return -ENOMEM;
1509
1510 for (i = 0; i < count; i++)
1511 dc->debugfs_files[i].data = dc;
1512
1513 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1514 if (err < 0)
1515 goto free;
1516
1517 return 0;
1518
1519free:
1520 kfree(dc->debugfs_files);
1521 dc->debugfs_files = NULL;
1522
1523 return err;
1524}
1525
1526static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1527{
1528 unsigned int count = ARRAY_SIZE(debugfs_files);
1529 struct drm_minor *minor = crtc->dev->primary;
1530 struct tegra_dc *dc = to_tegra_dc(crtc);
1531
1532 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1533 kfree(dc->debugfs_files);
1534 dc->debugfs_files = NULL;
1535}
1536
1537static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1538{
1539 struct tegra_dc *dc = to_tegra_dc(crtc);
1540
1541 /* XXX vblank syncpoints don't work with nvdisplay yet */
1542 if (dc->syncpt && !dc->soc->has_nvdisplay)
1543 return host1x_syncpt_read(dc->syncpt);
1544
1545 /* fallback to software emulated VBLANK counter */
1546 return (u32)drm_crtc_vblank_count(&dc->base);
1547}
1548
1549static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1550{
1551 struct tegra_dc *dc = to_tegra_dc(crtc);
1552 u32 value;
1553
1554 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1555 value |= VBLANK_INT;
1556 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1557
1558 return 0;
1559}
1560
1561static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1562{
1563 struct tegra_dc *dc = to_tegra_dc(crtc);
1564 u32 value;
1565
1566 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1567 value &= ~VBLANK_INT;
1568 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1569}
1570
1571static const struct drm_crtc_funcs tegra_crtc_funcs = {
1572 .page_flip = drm_atomic_helper_page_flip,
1573 .set_config = drm_atomic_helper_set_config,
1574 .destroy = tegra_dc_destroy,
1575 .reset = tegra_crtc_reset,
1576 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1577 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1578 .late_register = tegra_dc_late_register,
1579 .early_unregister = tegra_dc_early_unregister,
1580 .get_vblank_counter = tegra_dc_get_vblank_counter,
1581 .enable_vblank = tegra_dc_enable_vblank,
1582 .disable_vblank = tegra_dc_disable_vblank,
1583};
1584
1585static int tegra_dc_set_timings(struct tegra_dc *dc,
1586 struct drm_display_mode *mode)
1587{
1588 unsigned int h_ref_to_sync = 1;
1589 unsigned int v_ref_to_sync = 1;
1590 unsigned long value;
1591
1592 if (!dc->soc->has_nvdisplay) {
1593 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1594
1595 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1596 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1597 }
1598
1599 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1600 ((mode->hsync_end - mode->hsync_start) << 0);
1601 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1602
1603 value = ((mode->vtotal - mode->vsync_end) << 16) |
1604 ((mode->htotal - mode->hsync_end) << 0);
1605 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1606
1607 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1608 ((mode->hsync_start - mode->hdisplay) << 0);
1609 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1610
1611 value = (mode->vdisplay << 16) | mode->hdisplay;
1612 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1613
1614 return 0;
1615}
1616
1617/**
1618 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1619 * state
1620 * @dc: display controller
1621 * @crtc_state: CRTC atomic state
1622 * @clk: parent clock for display controller
1623 * @pclk: pixel clock
1624 * @div: shift clock divider
1625 *
1626 * Returns:
1627 * 0 on success or a negative error-code on failure.
1628 */
1629int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1630 struct drm_crtc_state *crtc_state,
1631 struct clk *clk, unsigned long pclk,
1632 unsigned int div)
1633{
1634 struct tegra_dc_state *state = to_dc_state(crtc_state);
1635
1636 if (!clk_has_parent(dc->clk, clk))
1637 return -EINVAL;
1638
1639 state->clk = clk;
1640 state->pclk = pclk;
1641 state->div = div;
1642
1643 return 0;
1644}
1645
1646static void tegra_dc_commit_state(struct tegra_dc *dc,
1647 struct tegra_dc_state *state)
1648{
1649 u32 value;
1650 int err;
1651
1652 err = clk_set_parent(dc->clk, state->clk);
1653 if (err < 0)
1654 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1655
1656 /*
1657 * Outputs may not want to change the parent clock rate. This is only
1658 * relevant to Tegra20 where only a single display PLL is available.
1659 * Since that PLL would typically be used for HDMI, an internal LVDS
1660 * panel would need to be driven by some other clock such as PLL_P
1661 * which is shared with other peripherals. Changing the clock rate
1662 * should therefore be avoided.
1663 */
1664 if (state->pclk > 0) {
1665 err = clk_set_rate(state->clk, state->pclk);
1666 if (err < 0)
1667 dev_err(dc->dev,
1668 "failed to set clock rate to %lu Hz\n",
1669 state->pclk);
1670 }
1671
1672 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1673 state->div);
1674 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1675
1676 if (!dc->soc->has_nvdisplay) {
1677 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1678 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1679 }
1680
1681 err = clk_set_rate(dc->clk, state->pclk);
1682 if (err < 0)
1683 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1684 dc->clk, state->pclk, err);
1685}
1686
1687static void tegra_dc_stop(struct tegra_dc *dc)
1688{
1689 u32 value;
1690
1691 /* stop the display controller */
1692 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1693 value &= ~DISP_CTRL_MODE_MASK;
1694 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1695
1696 tegra_dc_commit(dc);
1697}
1698
1699static bool tegra_dc_idle(struct tegra_dc *dc)
1700{
1701 u32 value;
1702
1703 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1704
1705 return (value & DISP_CTRL_MODE_MASK) == 0;
1706}
1707
1708static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1709{
1710 timeout = jiffies + msecs_to_jiffies(timeout);
1711
1712 while (time_before(jiffies, timeout)) {
1713 if (tegra_dc_idle(dc))
1714 return 0;
1715
1716 usleep_range(1000, 2000);
1717 }
1718
1719 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1720 return -ETIMEDOUT;
1721}
1722
1723static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1724 struct drm_crtc_state *old_state)
1725{
1726 struct tegra_dc *dc = to_tegra_dc(crtc);
1727 u32 value;
1728
1729 if (!tegra_dc_idle(dc)) {
1730 tegra_dc_stop(dc);
1731
1732 /*
1733 * Ignore the return value, there isn't anything useful to do
1734 * in case this fails.
1735 */
1736 tegra_dc_wait_idle(dc, 100);
1737 }
1738
1739 /*
1740 * This should really be part of the RGB encoder driver, but clearing
1741 * these bits has the side-effect of stopping the display controller.
1742 * When that happens no VBLANK interrupts will be raised. At the same
1743 * time the encoder is disabled before the display controller, so the
1744 * above code is always going to timeout waiting for the controller
1745 * to go idle.
1746 *
1747 * Given the close coupling between the RGB encoder and the display
1748 * controller doing it here is still kind of okay. None of the other
1749 * encoder drivers require these bits to be cleared.
1750 *
1751 * XXX: Perhaps given that the display controller is switched off at
1752 * this point anyway maybe clearing these bits isn't even useful for
1753 * the RGB encoder?
1754 */
1755 if (dc->rgb) {
1756 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1757 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1758 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1759 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1760 }
1761
1762 tegra_dc_stats_reset(&dc->stats);
1763 drm_crtc_vblank_off(crtc);
1764
1765 spin_lock_irq(&crtc->dev->event_lock);
1766
1767 if (crtc->state->event) {
1768 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1769 crtc->state->event = NULL;
1770 }
1771
1772 spin_unlock_irq(&crtc->dev->event_lock);
1773
1774 pm_runtime_put_sync(dc->dev);
1775}
1776
1777static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1778 struct drm_crtc_state *old_state)
1779{
1780 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1781 struct tegra_dc_state *state = to_dc_state(crtc->state);
1782 struct tegra_dc *dc = to_tegra_dc(crtc);
1783 u32 value;
1784
1785 pm_runtime_get_sync(dc->dev);
1786
1787 /* initialize display controller */
1788 if (dc->syncpt) {
1789 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1790
1791 if (dc->soc->has_nvdisplay)
1792 enable = 1 << 31;
1793 else
1794 enable = 1 << 8;
1795
1796 value = SYNCPT_CNTRL_NO_STALL;
1797 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1798
1799 value = enable | syncpt;
1800 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1801 }
1802
1803 if (dc->soc->has_nvdisplay) {
1804 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1805 DSC_OBUF_UF_INT;
1806 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1807
1808 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1809 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1810 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1811 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1812 VBLANK_INT | FRAME_END_INT;
1813 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1814
1815 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1816 FRAME_END_INT;
1817 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1818
1819 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1820 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1821
1822 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1823 } else {
1824 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1825 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1826 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1827
1828 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1829 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1830 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1831
1832 /* initialize timer */
1833 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1834 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1835 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1836
1837 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1838 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1839 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1840
1841 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1842 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1843 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1844
1845 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1846 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1847 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1848 }
1849
1850 if (dc->soc->supports_background_color)
1851 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1852 else
1853 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1854
1855 /* apply PLL and pixel clock changes */
1856 tegra_dc_commit_state(dc, state);
1857
1858 /* program display mode */
1859 tegra_dc_set_timings(dc, mode);
1860
1861 /* interlacing isn't supported yet, so disable it */
1862 if (dc->soc->supports_interlacing) {
1863 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1864 value &= ~INTERLACE_ENABLE;
1865 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1866 }
1867
1868 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1869 value &= ~DISP_CTRL_MODE_MASK;
1870 value |= DISP_CTRL_MODE_C_DISPLAY;
1871 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1872
1873 if (!dc->soc->has_nvdisplay) {
1874 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1875 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1876 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1877 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1878 }
1879
1880 /* enable underflow reporting and display red for missing pixels */
1881 if (dc->soc->has_nvdisplay) {
1882 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1883 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1884 }
1885
1886 tegra_dc_commit(dc);
1887
1888 drm_crtc_vblank_on(crtc);
1889}
1890
1891static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1892 struct drm_crtc_state *old_crtc_state)
1893{
1894 unsigned long flags;
1895
1896 if (crtc->state->event) {
1897 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1898
1899 if (drm_crtc_vblank_get(crtc) != 0)
1900 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1901 else
1902 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1903
1904 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1905
1906 crtc->state->event = NULL;
1907 }
1908}
1909
1910static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1911 struct drm_crtc_state *old_crtc_state)
1912{
1913 struct tegra_dc_state *state = to_dc_state(crtc->state);
1914 struct tegra_dc *dc = to_tegra_dc(crtc);
1915 u32 value;
1916
1917 value = state->planes << 8 | GENERAL_UPDATE;
1918 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1919 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1920
1921 value = state->planes | GENERAL_ACT_REQ;
1922 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1923 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1924}
1925
1926static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1927 .atomic_begin = tegra_crtc_atomic_begin,
1928 .atomic_flush = tegra_crtc_atomic_flush,
1929 .atomic_enable = tegra_crtc_atomic_enable,
1930 .atomic_disable = tegra_crtc_atomic_disable,
1931};
1932
1933static irqreturn_t tegra_dc_irq(int irq, void *data)
1934{
1935 struct tegra_dc *dc = data;
1936 unsigned long status;
1937
1938 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1939 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1940
1941 if (status & FRAME_END_INT) {
1942 /*
1943 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1944 */
1945 dc->stats.frames++;
1946 }
1947
1948 if (status & VBLANK_INT) {
1949 /*
1950 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1951 */
1952 drm_crtc_handle_vblank(&dc->base);
1953 dc->stats.vblank++;
1954 }
1955
1956 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1957 /*
1958 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1959 */
1960 dc->stats.underflow++;
1961 }
1962
1963 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1964 /*
1965 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1966 */
1967 dc->stats.overflow++;
1968 }
1969
1970 if (status & HEAD_UF_INT) {
1971 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1972 dc->stats.underflow++;
1973 }
1974
1975 return IRQ_HANDLED;
1976}
1977
1978static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
1979{
1980 unsigned int i;
1981
1982 if (!dc->soc->wgrps)
1983 return true;
1984
1985 for (i = 0; i < dc->soc->num_wgrps; i++) {
1986 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1987
1988 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
1989 return true;
1990 }
1991
1992 return false;
1993}
1994
1995static int tegra_dc_init(struct host1x_client *client)
1996{
1997 struct drm_device *drm = dev_get_drvdata(client->parent);
1998 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1999 struct tegra_dc *dc = host1x_client_to_dc(client);
2000 struct tegra_drm *tegra = drm->dev_private;
2001 struct drm_plane *primary = NULL;
2002 struct drm_plane *cursor = NULL;
2003 int err;
2004
2005 /*
2006 * XXX do not register DCs with no window groups because we cannot
2007 * assign a primary plane to them, which in turn will cause KMS to
2008 * crash.
2009 */
2010 if (!tegra_dc_has_window_groups(dc))
2011 return 0;
2012
2013 dc->syncpt = host1x_syncpt_request(client, flags);
2014 if (!dc->syncpt)
2015 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2016
2017 dc->group = host1x_client_iommu_attach(client, true);
2018 if (IS_ERR(dc->group)) {
2019 err = PTR_ERR(dc->group);
2020 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2021 return err;
2022 }
2023
2024 if (dc->soc->wgrps)
2025 primary = tegra_dc_add_shared_planes(drm, dc);
2026 else
2027 primary = tegra_dc_add_planes(drm, dc);
2028
2029 if (IS_ERR(primary)) {
2030 err = PTR_ERR(primary);
2031 goto cleanup;
2032 }
2033
2034 if (dc->soc->supports_cursor) {
2035 cursor = tegra_dc_cursor_plane_create(drm, dc);
2036 if (IS_ERR(cursor)) {
2037 err = PTR_ERR(cursor);
2038 goto cleanup;
2039 }
2040 } else {
2041 /* dedicate one overlay to mouse cursor */
2042 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2043 if (IS_ERR(cursor)) {
2044 err = PTR_ERR(cursor);
2045 goto cleanup;
2046 }
2047 }
2048
2049 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2050 &tegra_crtc_funcs, NULL);
2051 if (err < 0)
2052 goto cleanup;
2053
2054 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2055
2056 /*
2057 * Keep track of the minimum pitch alignment across all display
2058 * controllers.
2059 */
2060 if (dc->soc->pitch_align > tegra->pitch_align)
2061 tegra->pitch_align = dc->soc->pitch_align;
2062
2063 err = tegra_dc_rgb_init(drm, dc);
2064 if (err < 0 && err != -ENODEV) {
2065 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2066 goto cleanup;
2067 }
2068
2069 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2070 dev_name(dc->dev), dc);
2071 if (err < 0) {
2072 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2073 err);
2074 goto cleanup;
2075 }
2076
2077 return 0;
2078
2079cleanup:
2080 if (!IS_ERR_OR_NULL(cursor))
2081 drm_plane_cleanup(cursor);
2082
2083 if (!IS_ERR(primary))
2084 drm_plane_cleanup(primary);
2085
2086 host1x_client_iommu_detach(client, dc->group);
2087 host1x_syncpt_free(dc->syncpt);
2088
2089 return err;
2090}
2091
2092static int tegra_dc_exit(struct host1x_client *client)
2093{
2094 struct tegra_dc *dc = host1x_client_to_dc(client);
2095 int err;
2096
2097 if (!tegra_dc_has_window_groups(dc))
2098 return 0;
2099
2100 devm_free_irq(dc->dev, dc->irq, dc);
2101
2102 err = tegra_dc_rgb_exit(dc);
2103 if (err) {
2104 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2105 return err;
2106 }
2107
2108 host1x_client_iommu_detach(client, dc->group);
2109 host1x_syncpt_free(dc->syncpt);
2110
2111 return 0;
2112}
2113
2114static const struct host1x_client_ops dc_client_ops = {
2115 .init = tegra_dc_init,
2116 .exit = tegra_dc_exit,
2117};
2118
2119static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2120 .supports_background_color = false,
2121 .supports_interlacing = false,
2122 .supports_cursor = false,
2123 .supports_block_linear = false,
2124 .has_legacy_blending = true,
2125 .pitch_align = 8,
2126 .has_powergate = false,
2127 .coupled_pm = true,
2128 .has_nvdisplay = false,
2129 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2130 .primary_formats = tegra20_primary_formats,
2131 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2132 .overlay_formats = tegra20_overlay_formats,
2133 .modifiers = tegra20_modifiers,
2134 .has_win_a_without_filters = true,
2135 .has_win_c_without_vert_filter = true,
2136};
2137
2138static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2139 .supports_background_color = false,
2140 .supports_interlacing = false,
2141 .supports_cursor = false,
2142 .supports_block_linear = false,
2143 .has_legacy_blending = true,
2144 .pitch_align = 8,
2145 .has_powergate = false,
2146 .coupled_pm = false,
2147 .has_nvdisplay = false,
2148 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2149 .primary_formats = tegra20_primary_formats,
2150 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2151 .overlay_formats = tegra20_overlay_formats,
2152 .modifiers = tegra20_modifiers,
2153 .has_win_a_without_filters = false,
2154 .has_win_c_without_vert_filter = false,
2155};
2156
2157static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2158 .supports_background_color = false,
2159 .supports_interlacing = false,
2160 .supports_cursor = false,
2161 .supports_block_linear = false,
2162 .has_legacy_blending = true,
2163 .pitch_align = 64,
2164 .has_powergate = true,
2165 .coupled_pm = false,
2166 .has_nvdisplay = false,
2167 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2168 .primary_formats = tegra114_primary_formats,
2169 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2170 .overlay_formats = tegra114_overlay_formats,
2171 .modifiers = tegra20_modifiers,
2172 .has_win_a_without_filters = false,
2173 .has_win_c_without_vert_filter = false,
2174};
2175
2176static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2177 .supports_background_color = true,
2178 .supports_interlacing = true,
2179 .supports_cursor = true,
2180 .supports_block_linear = true,
2181 .has_legacy_blending = false,
2182 .pitch_align = 64,
2183 .has_powergate = true,
2184 .coupled_pm = false,
2185 .has_nvdisplay = false,
2186 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2187 .primary_formats = tegra124_primary_formats,
2188 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2189 .overlay_formats = tegra124_overlay_formats,
2190 .modifiers = tegra124_modifiers,
2191 .has_win_a_without_filters = false,
2192 .has_win_c_without_vert_filter = false,
2193};
2194
2195static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2196 .supports_background_color = true,
2197 .supports_interlacing = true,
2198 .supports_cursor = true,
2199 .supports_block_linear = true,
2200 .has_legacy_blending = false,
2201 .pitch_align = 64,
2202 .has_powergate = true,
2203 .coupled_pm = false,
2204 .has_nvdisplay = false,
2205 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2206 .primary_formats = tegra114_primary_formats,
2207 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2208 .overlay_formats = tegra114_overlay_formats,
2209 .modifiers = tegra124_modifiers,
2210 .has_win_a_without_filters = false,
2211 .has_win_c_without_vert_filter = false,
2212};
2213
2214static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2215 {
2216 .index = 0,
2217 .dc = 0,
2218 .windows = (const unsigned int[]) { 0 },
2219 .num_windows = 1,
2220 }, {
2221 .index = 1,
2222 .dc = 1,
2223 .windows = (const unsigned int[]) { 1 },
2224 .num_windows = 1,
2225 }, {
2226 .index = 2,
2227 .dc = 1,
2228 .windows = (const unsigned int[]) { 2 },
2229 .num_windows = 1,
2230 }, {
2231 .index = 3,
2232 .dc = 2,
2233 .windows = (const unsigned int[]) { 3 },
2234 .num_windows = 1,
2235 }, {
2236 .index = 4,
2237 .dc = 2,
2238 .windows = (const unsigned int[]) { 4 },
2239 .num_windows = 1,
2240 }, {
2241 .index = 5,
2242 .dc = 2,
2243 .windows = (const unsigned int[]) { 5 },
2244 .num_windows = 1,
2245 },
2246};
2247
2248static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2249 .supports_background_color = true,
2250 .supports_interlacing = true,
2251 .supports_cursor = true,
2252 .supports_block_linear = true,
2253 .has_legacy_blending = false,
2254 .pitch_align = 64,
2255 .has_powergate = false,
2256 .coupled_pm = false,
2257 .has_nvdisplay = true,
2258 .wgrps = tegra186_dc_wgrps,
2259 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2260};
2261
2262static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2263 {
2264 .index = 0,
2265 .dc = 0,
2266 .windows = (const unsigned int[]) { 0 },
2267 .num_windows = 1,
2268 }, {
2269 .index = 1,
2270 .dc = 1,
2271 .windows = (const unsigned int[]) { 1 },
2272 .num_windows = 1,
2273 }, {
2274 .index = 2,
2275 .dc = 1,
2276 .windows = (const unsigned int[]) { 2 },
2277 .num_windows = 1,
2278 }, {
2279 .index = 3,
2280 .dc = 2,
2281 .windows = (const unsigned int[]) { 3 },
2282 .num_windows = 1,
2283 }, {
2284 .index = 4,
2285 .dc = 2,
2286 .windows = (const unsigned int[]) { 4 },
2287 .num_windows = 1,
2288 }, {
2289 .index = 5,
2290 .dc = 2,
2291 .windows = (const unsigned int[]) { 5 },
2292 .num_windows = 1,
2293 },
2294};
2295
2296static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2297 .supports_background_color = true,
2298 .supports_interlacing = true,
2299 .supports_cursor = true,
2300 .supports_block_linear = true,
2301 .has_legacy_blending = false,
2302 .pitch_align = 64,
2303 .has_powergate = false,
2304 .coupled_pm = false,
2305 .has_nvdisplay = true,
2306 .wgrps = tegra194_dc_wgrps,
2307 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2308};
2309
2310static const struct of_device_id tegra_dc_of_match[] = {
2311 {
2312 .compatible = "nvidia,tegra194-dc",
2313 .data = &tegra194_dc_soc_info,
2314 }, {
2315 .compatible = "nvidia,tegra186-dc",
2316 .data = &tegra186_dc_soc_info,
2317 }, {
2318 .compatible = "nvidia,tegra210-dc",
2319 .data = &tegra210_dc_soc_info,
2320 }, {
2321 .compatible = "nvidia,tegra124-dc",
2322 .data = &tegra124_dc_soc_info,
2323 }, {
2324 .compatible = "nvidia,tegra114-dc",
2325 .data = &tegra114_dc_soc_info,
2326 }, {
2327 .compatible = "nvidia,tegra30-dc",
2328 .data = &tegra30_dc_soc_info,
2329 }, {
2330 .compatible = "nvidia,tegra20-dc",
2331 .data = &tegra20_dc_soc_info,
2332 }, {
2333 /* sentinel */
2334 }
2335};
2336MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2337
2338static int tegra_dc_parse_dt(struct tegra_dc *dc)
2339{
2340 struct device_node *np;
2341 u32 value = 0;
2342 int err;
2343
2344 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2345 if (err < 0) {
2346 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2347
2348 /*
2349 * If the nvidia,head property isn't present, try to find the
2350 * correct head number by looking up the position of this
2351 * display controller's node within the device tree. Assuming
2352 * that the nodes are ordered properly in the DTS file and
2353 * that the translation into a flattened device tree blob
2354 * preserves that ordering this will actually yield the right
2355 * head number.
2356 *
2357 * If those assumptions don't hold, this will still work for
2358 * cases where only a single display controller is used.
2359 */
2360 for_each_matching_node(np, tegra_dc_of_match) {
2361 if (np == dc->dev->of_node) {
2362 of_node_put(np);
2363 break;
2364 }
2365
2366 value++;
2367 }
2368 }
2369
2370 dc->pipe = value;
2371
2372 return 0;
2373}
2374
2375static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2376{
2377 struct tegra_dc *dc = dev_get_drvdata(dev);
2378 unsigned int pipe = (unsigned long)(void *)data;
2379
2380 return dc->pipe == pipe;
2381}
2382
2383static int tegra_dc_couple(struct tegra_dc *dc)
2384{
2385 /*
2386 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2387 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2388 * POWER_CONTROL registers during CRTC enabling.
2389 */
2390 if (dc->soc->coupled_pm && dc->pipe == 1) {
2391 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2392 struct device_link *link;
2393 struct device *partner;
2394
2395 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2396 tegra_dc_match_by_pipe);
2397 if (!partner)
2398 return -EPROBE_DEFER;
2399
2400 link = device_link_add(dc->dev, partner, flags);
2401 if (!link) {
2402 dev_err(dc->dev, "failed to link controllers\n");
2403 return -EINVAL;
2404 }
2405
2406 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2407 }
2408
2409 return 0;
2410}
2411
2412static int tegra_dc_probe(struct platform_device *pdev)
2413{
2414 struct resource *regs;
2415 struct tegra_dc *dc;
2416 int err;
2417
2418 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2419 if (!dc)
2420 return -ENOMEM;
2421
2422 dc->soc = of_device_get_match_data(&pdev->dev);
2423
2424 INIT_LIST_HEAD(&dc->list);
2425 dc->dev = &pdev->dev;
2426
2427 err = tegra_dc_parse_dt(dc);
2428 if (err < 0)
2429 return err;
2430
2431 err = tegra_dc_couple(dc);
2432 if (err < 0)
2433 return err;
2434
2435 dc->clk = devm_clk_get(&pdev->dev, NULL);
2436 if (IS_ERR(dc->clk)) {
2437 dev_err(&pdev->dev, "failed to get clock\n");
2438 return PTR_ERR(dc->clk);
2439 }
2440
2441 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2442 if (IS_ERR(dc->rst)) {
2443 dev_err(&pdev->dev, "failed to get reset\n");
2444 return PTR_ERR(dc->rst);
2445 }
2446
2447 /* assert reset and disable clock */
2448 err = clk_prepare_enable(dc->clk);
2449 if (err < 0)
2450 return err;
2451
2452 usleep_range(2000, 4000);
2453
2454 err = reset_control_assert(dc->rst);
2455 if (err < 0)
2456 return err;
2457
2458 usleep_range(2000, 4000);
2459
2460 clk_disable_unprepare(dc->clk);
2461
2462 if (dc->soc->has_powergate) {
2463 if (dc->pipe == 0)
2464 dc->powergate = TEGRA_POWERGATE_DIS;
2465 else
2466 dc->powergate = TEGRA_POWERGATE_DISB;
2467
2468 tegra_powergate_power_off(dc->powergate);
2469 }
2470
2471 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2472 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2473 if (IS_ERR(dc->regs))
2474 return PTR_ERR(dc->regs);
2475
2476 dc->irq = platform_get_irq(pdev, 0);
2477 if (dc->irq < 0) {
2478 dev_err(&pdev->dev, "failed to get IRQ\n");
2479 return -ENXIO;
2480 }
2481
2482 err = tegra_dc_rgb_probe(dc);
2483 if (err < 0 && err != -ENODEV) {
2484 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2485 return err;
2486 }
2487
2488 platform_set_drvdata(pdev, dc);
2489 pm_runtime_enable(&pdev->dev);
2490
2491 INIT_LIST_HEAD(&dc->client.list);
2492 dc->client.ops = &dc_client_ops;
2493 dc->client.dev = &pdev->dev;
2494
2495 err = host1x_client_register(&dc->client);
2496 if (err < 0) {
2497 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2498 err);
2499 return err;
2500 }
2501
2502 return 0;
2503}
2504
2505static int tegra_dc_remove(struct platform_device *pdev)
2506{
2507 struct tegra_dc *dc = platform_get_drvdata(pdev);
2508 int err;
2509
2510 err = host1x_client_unregister(&dc->client);
2511 if (err < 0) {
2512 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2513 err);
2514 return err;
2515 }
2516
2517 err = tegra_dc_rgb_remove(dc);
2518 if (err < 0) {
2519 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2520 return err;
2521 }
2522
2523 pm_runtime_disable(&pdev->dev);
2524
2525 return 0;
2526}
2527
2528#ifdef CONFIG_PM
2529static int tegra_dc_suspend(struct device *dev)
2530{
2531 struct tegra_dc *dc = dev_get_drvdata(dev);
2532 int err;
2533
2534 err = reset_control_assert(dc->rst);
2535 if (err < 0) {
2536 dev_err(dev, "failed to assert reset: %d\n", err);
2537 return err;
2538 }
2539
2540 if (dc->soc->has_powergate)
2541 tegra_powergate_power_off(dc->powergate);
2542
2543 clk_disable_unprepare(dc->clk);
2544
2545 return 0;
2546}
2547
2548static int tegra_dc_resume(struct device *dev)
2549{
2550 struct tegra_dc *dc = dev_get_drvdata(dev);
2551 int err;
2552
2553 if (dc->soc->has_powergate) {
2554 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2555 dc->rst);
2556 if (err < 0) {
2557 dev_err(dev, "failed to power partition: %d\n", err);
2558 return err;
2559 }
2560 } else {
2561 err = clk_prepare_enable(dc->clk);
2562 if (err < 0) {
2563 dev_err(dev, "failed to enable clock: %d\n", err);
2564 return err;
2565 }
2566
2567 err = reset_control_deassert(dc->rst);
2568 if (err < 0) {
2569 dev_err(dev, "failed to deassert reset: %d\n", err);
2570 return err;
2571 }
2572 }
2573
2574 return 0;
2575}
2576#endif
2577
2578static const struct dev_pm_ops tegra_dc_pm_ops = {
2579 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2580};
2581
2582struct platform_driver tegra_dc_driver = {
2583 .driver = {
2584 .name = "tegra-dc",
2585 .of_match_table = tegra_dc_of_match,
2586 .pm = &tegra_dc_pm_ops,
2587 },
2588 .probe = tegra_dc_probe,
2589 .remove = tegra_dc_remove,
2590};