1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2 */
   3/*
   4 *
   5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6 * All Rights Reserved.
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a
   9 * copy of this software and associated documentation files (the
  10 * "Software"), to deal in the Software without restriction, including
  11 * without limitation the rights to use, copy, modify, merge, publish,
  12 * distribute, sub license, and/or sell copies of the Software, and to
  13 * permit persons to whom the Software is furnished to do so, subject to
  14 * the following conditions:
  15 *
  16 * The above copyright notice and this permission notice (including the
  17 * next paragraph) shall be included in all copies or substantial portions
  18 * of the Software.
  19 *
  20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27 *
  28 */
  29
  30#ifndef _I915_DRV_H_
  31#define _I915_DRV_H_
  32
  33#include <uapi/drm/i915_drm.h>
  34#include <uapi/drm/drm_fourcc.h>
  35
  36#include <drm/drmP.h>
  37#include "i915_params.h"
  38#include "i915_reg.h"
  39#include "intel_bios.h"
  40#include "intel_ringbuffer.h"
  41#include "intel_lrc.h"
  42#include "i915_gem_gtt.h"
  43#include "i915_gem_render_state.h"
  44#include <linux/io-mapping.h>
  45#include <linux/i2c.h>
  46#include <linux/i2c-algo-bit.h>
  47#include <drm/intel-gtt.h>
  48#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  49#include <drm/drm_gem.h>
  50#include <linux/backlight.h>
  51#include <linux/hashtable.h>
  52#include <linux/intel-iommu.h>
  53#include <linux/kref.h>
  54#include <linux/pm_qos.h>
  55#include "intel_guc.h"
  56
  57/* General customization:
  58 */
  59
  60#define DRIVER_NAME		"i915"
  61#define DRIVER_DESC		"Intel Graphics"
  62#define DRIVER_DATE		"20160229"
  63
  64#undef WARN_ON
  65/* Many gcc seem to no see through this and fall over :( */
  66#if 0
  67#define WARN_ON(x) ({ \
  68	bool __i915_warn_cond = (x); \
  69	if (__builtin_constant_p(__i915_warn_cond)) \
  70		BUILD_BUG_ON(__i915_warn_cond); \
  71	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
  72#else
  73#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
  74#endif
  75
  76#undef WARN_ON_ONCE
  77#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
  78
  79#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
  80			     (long) (x), __func__);
  81
  82/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
  83 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
  84 * which may not necessarily be a user visible problem.  This will either
  85 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
  86 * enable distros and users to tailor their preferred amount of i915 abrt
  87 * spam.
  88 */
  89#define I915_STATE_WARN(condition, format...) ({			\
  90	int __ret_warn_on = !!(condition);				\
  91	if (unlikely(__ret_warn_on))					\
  92		if (!WARN(i915.verbose_state_checks, format))		\
  93			DRM_ERROR(format);				\
  94	unlikely(__ret_warn_on);					\
  95})
  96
  97#define I915_STATE_WARN_ON(x)						\
  98	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
  99
 100static inline const char *yesno(bool v)
 101{
 102	return v ? "yes" : "no";
 103}
 104
 105static inline const char *onoff(bool v)
 106{
 107	return v ? "on" : "off";
 108}
 109
 110enum pipe {
 111	INVALID_PIPE = -1,
 112	PIPE_A = 0,
 113	PIPE_B,
 114	PIPE_C,
 115	_PIPE_EDP,
 116	I915_MAX_PIPES = _PIPE_EDP
 117};
 118#define pipe_name(p) ((p) + 'A')
 119
 120enum transcoder {
 121	TRANSCODER_A = 0,
 122	TRANSCODER_B,
 123	TRANSCODER_C,
 124	TRANSCODER_EDP,
 125	I915_MAX_TRANSCODERS
 126};
 127#define transcoder_name(t) ((t) + 'A')
 128
 129/*
 130 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 131 * number of planes per CRTC.  Not all platforms really have this many planes,
 132 * which means some arrays of size I915_MAX_PLANES may have unused entries
 133 * between the topmost sprite plane and the cursor plane.
 134 */
 135enum plane {
 136	PLANE_A = 0,
 137	PLANE_B,
 138	PLANE_C,
 139	PLANE_CURSOR,
 140	I915_MAX_PLANES,
 141};
 142#define plane_name(p) ((p) + 'A')
 143
 144#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
 145
 146enum port {
 147	PORT_A = 0,
 148	PORT_B,
 149	PORT_C,
 150	PORT_D,
 151	PORT_E,
 152	I915_MAX_PORTS
 153};
 154#define port_name(p) ((p) + 'A')
 155
 156#define I915_NUM_PHYS_VLV 2
 157
 158enum dpio_channel {
 159	DPIO_CH0,
 160	DPIO_CH1
 161};
 162
 163enum dpio_phy {
 164	DPIO_PHY0,
 165	DPIO_PHY1
 166};
 167
 168enum intel_display_power_domain {
 169	POWER_DOMAIN_PIPE_A,
 170	POWER_DOMAIN_PIPE_B,
 171	POWER_DOMAIN_PIPE_C,
 172	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 173	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 174	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 175	POWER_DOMAIN_TRANSCODER_A,
 176	POWER_DOMAIN_TRANSCODER_B,
 177	POWER_DOMAIN_TRANSCODER_C,
 178	POWER_DOMAIN_TRANSCODER_EDP,
 179	POWER_DOMAIN_PORT_DDI_A_LANES,
 180	POWER_DOMAIN_PORT_DDI_B_LANES,
 181	POWER_DOMAIN_PORT_DDI_C_LANES,
 182	POWER_DOMAIN_PORT_DDI_D_LANES,
 183	POWER_DOMAIN_PORT_DDI_E_LANES,
 184	POWER_DOMAIN_PORT_DSI,
 185	POWER_DOMAIN_PORT_CRT,
 186	POWER_DOMAIN_PORT_OTHER,
 187	POWER_DOMAIN_VGA,
 188	POWER_DOMAIN_AUDIO,
 189	POWER_DOMAIN_PLLS,
 190	POWER_DOMAIN_AUX_A,
 191	POWER_DOMAIN_AUX_B,
 192	POWER_DOMAIN_AUX_C,
 193	POWER_DOMAIN_AUX_D,
 194	POWER_DOMAIN_GMBUS,
 195	POWER_DOMAIN_MODESET,
 196	POWER_DOMAIN_INIT,
 197
 198	POWER_DOMAIN_NUM,
 199};
 200
 201#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 202#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 203		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 204#define POWER_DOMAIN_TRANSCODER(tran) \
 205	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 206	 (tran) + POWER_DOMAIN_TRANSCODER_A)
 207
 208enum hpd_pin {
 209	HPD_NONE = 0,
 210	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 211	HPD_CRT,
 212	HPD_SDVO_B,
 213	HPD_SDVO_C,
 214	HPD_PORT_A,
 215	HPD_PORT_B,
 216	HPD_PORT_C,
 217	HPD_PORT_D,
 218	HPD_PORT_E,
 219	HPD_NUM_PINS
 220};
 221
 222#define for_each_hpd_pin(__pin) \
 223	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
 224
 225struct i915_hotplug {
 226	struct work_struct hotplug_work;
 227
 228	struct {
 229		unsigned long last_jiffies;
 230		int count;
 231		enum {
 232			HPD_ENABLED = 0,
 233			HPD_DISABLED = 1,
 234			HPD_MARK_DISABLED = 2
 235		} state;
 236	} stats[HPD_NUM_PINS];
 237	u32 event_bits;
 238	struct delayed_work reenable_work;
 239
 240	struct intel_digital_port *irq_port[I915_MAX_PORTS];
 241	u32 long_port_mask;
 242	u32 short_port_mask;
 243	struct work_struct dig_port_work;
 244
 245	/*
 246	 * if we get a HPD irq from DP and a HPD irq from non-DP
 247	 * the non-DP HPD could block the workqueue on a mode config
 248	 * mutex getting, that userspace may have taken. However
 249	 * userspace is waiting on the DP workqueue to run which is
 250	 * blocked behind the non-DP one.
 251	 */
 252	struct workqueue_struct *dp_wq;
 253};
 254
 255#define I915_GEM_GPU_DOMAINS \
 256	(I915_GEM_DOMAIN_RENDER | \
 257	 I915_GEM_DOMAIN_SAMPLER | \
 258	 I915_GEM_DOMAIN_COMMAND | \
 259	 I915_GEM_DOMAIN_INSTRUCTION | \
 260	 I915_GEM_DOMAIN_VERTEX)
 261
 262#define for_each_pipe(__dev_priv, __p) \
 263	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 264#define for_each_pipe_masked(__dev_priv, __p, __mask) \
 265	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
 266		for_each_if ((__mask) & (1 << (__p)))
 267#define for_each_plane(__dev_priv, __pipe, __p)				\
 268	for ((__p) = 0;							\
 269	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
 270	     (__p)++)
 271#define for_each_sprite(__dev_priv, __p, __s)				\
 272	for ((__s) = 0;							\
 273	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
 274	     (__s)++)
 275
 276#define for_each_crtc(dev, crtc) \
 277	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 278
 279#define for_each_intel_plane(dev, intel_plane) \
 280	list_for_each_entry(intel_plane,			\
 281			    &dev->mode_config.plane_list,	\
 282			    base.head)
 283
 284#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
 285	list_for_each_entry(intel_plane,				\
 286			    &(dev)->mode_config.plane_list,		\
 287			    base.head)					\
 288		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
 289
 290#define for_each_intel_crtc(dev, intel_crtc) \
 291	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
 292
 293#define for_each_intel_encoder(dev, intel_encoder)		\
 294	list_for_each_entry(intel_encoder,			\
 295			    &(dev)->mode_config.encoder_list,	\
 296			    base.head)
 297
 298#define for_each_intel_connector(dev, intel_connector)		\
 299	list_for_each_entry(intel_connector,			\
 300			    &dev->mode_config.connector_list,	\
 301			    base.head)
 302
 303#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 304	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 305		for_each_if ((intel_encoder)->base.crtc == (__crtc))
 306
 307#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 308	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 309		for_each_if ((intel_connector)->base.encoder == (__encoder))
 310
 311#define for_each_power_domain(domain, mask)				\
 312	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
 313		for_each_if ((1 << (domain)) & (mask))
 314
 315struct drm_i915_private;
 316struct i915_mm_struct;
 317struct i915_mmu_object;
 318
 319struct drm_i915_file_private {
 320	struct drm_i915_private *dev_priv;
 321	struct drm_file *file;
 322
 323	struct {
 324		spinlock_t lock;
 325		struct list_head request_list;
 326/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 327 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 328 * (when using lax throttling for the frontbuffer). We also use it to
 329 * offer free GPU waitboosts for severely congested workloads.
 330 */
 331#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
 332	} mm;
 333	struct idr context_idr;
 334
 335	struct intel_rps_client {
 336		struct list_head link;
 337		unsigned boosts;
 338	} rps;
 339
 340	unsigned int bsd_ring;
 341};
 342
 343enum intel_dpll_id {
 344	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 345	/* real shared dpll ids must be >= 0 */
 346	DPLL_ID_PCH_PLL_A = 0,
 347	DPLL_ID_PCH_PLL_B = 1,
 348	/* hsw/bdw */
 349	DPLL_ID_WRPLL1 = 0,
 350	DPLL_ID_WRPLL2 = 1,
 351	DPLL_ID_SPLL = 2,
 352
 353	/* skl */
 354	DPLL_ID_SKL_DPLL1 = 0,
 355	DPLL_ID_SKL_DPLL2 = 1,
 356	DPLL_ID_SKL_DPLL3 = 2,
 357};
 358#define I915_NUM_PLLS 3
 359
 360struct intel_dpll_hw_state {
 361	/* i9xx, pch plls */
 362	uint32_t dpll;
 363	uint32_t dpll_md;
 364	uint32_t fp0;
 365	uint32_t fp1;
 366
 367	/* hsw, bdw */
 368	uint32_t wrpll;
 369	uint32_t spll;
 370
 371	/* skl */
 372	/*
 373	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
 374	 * lower part of ctrl1 and they get shifted into position when writing
 375	 * the register.  This allows us to easily compare the state to share
 376	 * the DPLL.
 377	 */
 378	uint32_t ctrl1;
 379	/* HDMI only, 0 when used for DP */
 380	uint32_t cfgcr1, cfgcr2;
 381
 382	/* bxt */
 383	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
 384		 pcsdw12;
 385};
 386
 387struct intel_shared_dpll_config {
 388	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
 389	struct intel_dpll_hw_state hw_state;
 390};
 391
 392struct intel_shared_dpll {
 393	struct intel_shared_dpll_config config;
 394
 395	int active; /* count of number of active CRTCs (i.e. DPMS on) */
 396	bool on; /* is the PLL actually active? Disabled during modeset */
 397	const char *name;
 398	/* should match the index in the dev_priv->shared_dplls array */
 399	enum intel_dpll_id id;
 400	/* The mode_set hook is optional and should be used together with the
 401	 * intel_prepare_shared_dpll function. */
 402	void (*mode_set)(struct drm_i915_private *dev_priv,
 403			 struct intel_shared_dpll *pll);
 404	void (*enable)(struct drm_i915_private *dev_priv,
 405		       struct intel_shared_dpll *pll);
 406	void (*disable)(struct drm_i915_private *dev_priv,
 407			struct intel_shared_dpll *pll);
 408	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 409			     struct intel_shared_dpll *pll,
 410			     struct intel_dpll_hw_state *hw_state);
 411};
 412
 413#define SKL_DPLL0 0
 414#define SKL_DPLL1 1
 415#define SKL_DPLL2 2
 416#define SKL_DPLL3 3
 417
 418/* Used by dp and fdi links */
 419struct intel_link_m_n {
 420	uint32_t	tu;
 421	uint32_t	gmch_m;
 422	uint32_t	gmch_n;
 423	uint32_t	link_m;
 424	uint32_t	link_n;
 425};
 426
 427void intel_link_compute_m_n(int bpp, int nlanes,
 428			    int pixel_clock, int link_clock,
 429			    struct intel_link_m_n *m_n);
 430
 431/* Interface history:
 432 *
 433 * 1.1: Original.
 434 * 1.2: Add Power Management
 435 * 1.3: Add vblank support
 436 * 1.4: Fix cmdbuffer path, add heap destroy
 437 * 1.5: Add vblank pipe configuration
 438 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 439 *      - Support vertical blank on secondary display pipe
 440 */
 441#define DRIVER_MAJOR		1
 442#define DRIVER_MINOR		6
 443#define DRIVER_PATCHLEVEL	0
 444
 445#define WATCH_LISTS	0
 446
 447struct opregion_header;
 448struct opregion_acpi;
 449struct opregion_swsci;
 450struct opregion_asle;
 451
 452struct intel_opregion {
 453	struct opregion_header *header;
 454	struct opregion_acpi *acpi;
 455	struct opregion_swsci *swsci;
 456	u32 swsci_gbda_sub_functions;
 457	u32 swsci_sbcb_sub_functions;
 458	struct opregion_asle *asle;
 459	void *rvda;
 460	const void *vbt;
 461	u32 vbt_size;
 462	u32 *lid_state;
 463	struct work_struct asle_work;
 464};
 465#define OPREGION_SIZE            (8*1024)
 466
 467struct intel_overlay;
 468struct intel_overlay_error_state;
 469
 470#define I915_FENCE_REG_NONE -1
 471#define I915_MAX_NUM_FENCES 32
 472/* 32 fences + sign bit for FENCE_REG_NONE */
 473#define I915_MAX_NUM_FENCE_BITS 6
 474
 475struct drm_i915_fence_reg {
 476	struct list_head lru_list;
 477	struct drm_i915_gem_object *obj;
 478	int pin_count;
 479};
 480
 481struct sdvo_device_mapping {
 482	u8 initialized;
 483	u8 dvo_port;
 484	u8 slave_addr;
 485	u8 dvo_wiring;
 486	u8 i2c_pin;
 487	u8 ddc_pin;
 488};
 489
 490struct intel_display_error_state;
 491
 492struct drm_i915_error_state {
 493	struct kref ref;
 494	struct timeval time;
 495
 496	char error_msg[128];
 497	int iommu;
 498	u32 reset_count;
 499	u32 suspend_count;
 500
 501	/* Generic register state */
 502	u32 eir;
 503	u32 pgtbl_er;
 504	u32 ier;
 505	u32 gtier[4];
 506	u32 ccid;
 507	u32 derrmr;
 508	u32 forcewake;
 509	u32 error; /* gen6+ */
 510	u32 err_int; /* gen7 */
 511	u32 fault_data0; /* gen8, gen9 */
 512	u32 fault_data1; /* gen8, gen9 */
 513	u32 done_reg;
 514	u32 gac_eco;
 515	u32 gam_ecochk;
 516	u32 gab_ctl;
 517	u32 gfx_mode;
 518	u32 extra_instdone[I915_NUM_INSTDONE_REG];
 519	u64 fence[I915_MAX_NUM_FENCES];
 520	struct intel_overlay_error_state *overlay;
 521	struct intel_display_error_state *display;
 522	struct drm_i915_error_object *semaphore_obj;
 523
 524	struct drm_i915_error_ring {
 525		bool valid;
 526		/* Software tracked state */
 527		bool waiting;
 528		int hangcheck_score;
 529		enum intel_ring_hangcheck_action hangcheck_action;
 530		int num_requests;
 531
 532		/* our own tracking of ring head and tail */
 533		u32 cpu_ring_head;
 534		u32 cpu_ring_tail;
 535
 536		u32 semaphore_seqno[I915_NUM_RINGS - 1];
 537
 538		/* Register state */
 539		u32 start;
 540		u32 tail;
 541		u32 head;
 542		u32 ctl;
 543		u32 hws;
 544		u32 ipeir;
 545		u32 ipehr;
 546		u32 instdone;
 547		u32 bbstate;
 548		u32 instpm;
 549		u32 instps;
 550		u32 seqno;
 551		u64 bbaddr;
 552		u64 acthd;
 553		u32 fault_reg;
 554		u64 faddr;
 555		u32 rc_psmi; /* sleep state */
 556		u32 semaphore_mboxes[I915_NUM_RINGS - 1];
 557
 558		struct drm_i915_error_object {
 559			int page_count;
 560			u64 gtt_offset;
 561			u32 *pages[0];
 562		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 563
 564		struct drm_i915_error_request {
 565			long jiffies;
 566			u32 seqno;
 567			u32 tail;
 568		} *requests;
 569
 570		struct {
 571			u32 gfx_mode;
 572			union {
 573				u64 pdp[4];
 574				u32 pp_dir_base;
 575			};
 576		} vm_info;
 577
 578		pid_t pid;
 579		char comm[TASK_COMM_LEN];
 580	} ring[I915_NUM_RINGS];
 581
 582	struct drm_i915_error_buffer {
 583		u32 size;
 584		u32 name;
 585		u32 rseqno[I915_NUM_RINGS], wseqno;
 586		u64 gtt_offset;
 587		u32 read_domains;
 588		u32 write_domain;
 589		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 590		s32 pinned:2;
 591		u32 tiling:2;
 592		u32 dirty:1;
 593		u32 purgeable:1;
 594		u32 userptr:1;
 595		s32 ring:4;
 596		u32 cache_level:3;
 597	} **active_bo, **pinned_bo;
 598
 599	u32 *active_bo_count, *pinned_bo_count;
 600	u32 vm_count;
 601};
 602
 603struct intel_connector;
 604struct intel_encoder;
 605struct intel_crtc_state;
 606struct intel_initial_plane_config;
 607struct intel_crtc;
 608struct intel_limit;
 609struct dpll;
 610
 611struct drm_i915_display_funcs {
 612	int (*get_display_clock_speed)(struct drm_device *dev);
 613	int (*get_fifo_size)(struct drm_device *dev, int plane);
 614	/**
 615	 * find_dpll() - Find the best values for the PLL
 616	 * @limit: limits for the PLL
 617	 * @crtc: current CRTC
 618	 * @target: target frequency in kHz
 619	 * @refclk: reference clock frequency in kHz
 620	 * @match_clock: if provided, @best_clock P divider must
 621	 *               match the P divider from @match_clock
 622	 *               used for LVDS downclocking
 623	 * @best_clock: best PLL values found
 624	 *
 625	 * Returns true on success, false on failure.
 626	 */
 627	bool (*find_dpll)(const struct intel_limit *limit,
 628			  struct intel_crtc_state *crtc_state,
 629			  int target, int refclk,
 630			  struct dpll *match_clock,
 631			  struct dpll *best_clock);
 632	int (*compute_pipe_wm)(struct intel_crtc *crtc,
 633			       struct drm_atomic_state *state);
 634	void (*program_watermarks)(struct intel_crtc_state *cstate);
 635	void (*update_wm)(struct drm_crtc *crtc);
 636	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
 637	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
 638	/* Returns the active state of the crtc, and if the crtc is active,
 639	 * fills out the pipe-config with the hw state. */
 640	bool (*get_pipe_config)(struct intel_crtc *,
 641				struct intel_crtc_state *);
 642	void (*get_initial_plane_config)(struct intel_crtc *,
 643					 struct intel_initial_plane_config *);
 644	int (*crtc_compute_clock)(struct intel_crtc *crtc,
 645				  struct intel_crtc_state *crtc_state);
 646	void (*crtc_enable)(struct drm_crtc *crtc);
 647	void (*crtc_disable)(struct drm_crtc *crtc);
 648	void (*audio_codec_enable)(struct drm_connector *connector,
 649				   struct intel_encoder *encoder,
 650				   const struct drm_display_mode *adjusted_mode);
 651	void (*audio_codec_disable)(struct intel_encoder *encoder);
 652	void (*fdi_link_train)(struct drm_crtc *crtc);
 653	void (*init_clock_gating)(struct drm_device *dev);
 654	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 655			  struct drm_framebuffer *fb,
 656			  struct drm_i915_gem_object *obj,
 657			  struct drm_i915_gem_request *req,
 658			  uint32_t flags);
 659	void (*hpd_irq_setup)(struct drm_device *dev);
 660	/* clock updates for mode set */
 661	/* cursor updates */
 662	/* render clock increase/decrease */
 663	/* display clock increase/decrease */
 664	/* pll clock increase/decrease */
 665};
 666
 667enum forcewake_domain_id {
 668	FW_DOMAIN_ID_RENDER = 0,
 669	FW_DOMAIN_ID_BLITTER,
 670	FW_DOMAIN_ID_MEDIA,
 671
 672	FW_DOMAIN_ID_COUNT
 673};
 674
 675enum forcewake_domains {
 676	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
 677	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
 678	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
 679	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
 680			 FORCEWAKE_BLITTER |
 681			 FORCEWAKE_MEDIA)
 682};
 683
 684struct intel_uncore_funcs {
 685	void (*force_wake_get)(struct drm_i915_private *dev_priv,
 686							enum forcewake_domains domains);
 687	void (*force_wake_put)(struct drm_i915_private *dev_priv,
 688							enum forcewake_domains domains);
 689
 690	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 691	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 692	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 693	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
 694
 695	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
 696				uint8_t val, bool trace);
 697	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
 698				uint16_t val, bool trace);
 699	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
 700				uint32_t val, bool trace);
 701	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
 702				uint64_t val, bool trace);
 703};
 704
 705struct intel_uncore {
 706	spinlock_t lock; /** lock is also taken in irq contexts. */
 707
 708	struct intel_uncore_funcs funcs;
 709
 710	unsigned fifo_count;
 711	enum forcewake_domains fw_domains;
 712
 713	struct intel_uncore_forcewake_domain {
 714		struct drm_i915_private *i915;
 715		enum forcewake_domain_id id;
 716		unsigned wake_count;
 717		struct timer_list timer;
 718		i915_reg_t reg_set;
 719		u32 val_set;
 720		u32 val_clear;
 721		i915_reg_t reg_ack;
 722		i915_reg_t reg_post;
 723		u32 val_reset;
 724	} fw_domain[FW_DOMAIN_ID_COUNT];
 725
 726	int unclaimed_mmio_check;
 727};
 728
 729/* Iterate over initialised fw domains */
 730#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
 731	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
 732	     (i__) < FW_DOMAIN_ID_COUNT; \
 733	     (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
 734		for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
 735
 736#define for_each_fw_domain(domain__, dev_priv__, i__) \
 737	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
 738
 739#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
 740#define CSR_VERSION_MAJOR(version)	((version) >> 16)
 741#define CSR_VERSION_MINOR(version)	((version) & 0xffff)
 742
 743struct intel_csr {
 744	struct work_struct work;
 745	const char *fw_path;
 746	uint32_t *dmc_payload;
 747	uint32_t dmc_fw_size;
 748	uint32_t version;
 749	uint32_t mmio_count;
 750	i915_reg_t mmioaddr[8];
 751	uint32_t mmiodata[8];
 752	uint32_t dc_state;
 753};
 754
 755#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
 756	func(is_mobile) sep \
 757	func(is_i85x) sep \
 758	func(is_i915g) sep \
 759	func(is_i945gm) sep \
 760	func(is_g33) sep \
 761	func(need_gfx_hws) sep \
 762	func(is_g4x) sep \
 763	func(is_pineview) sep \
 764	func(is_broadwater) sep \
 765	func(is_crestline) sep \
 766	func(is_ivybridge) sep \
 767	func(is_valleyview) sep \
 768	func(is_cherryview) sep \
 769	func(is_haswell) sep \
 770	func(is_skylake) sep \
 771	func(is_broxton) sep \
 772	func(is_kabylake) sep \
 773	func(is_preliminary) sep \
 774	func(has_fbc) sep \
 775	func(has_pipe_cxsr) sep \
 776	func(has_hotplug) sep \
 777	func(cursor_needs_physical) sep \
 778	func(has_overlay) sep \
 779	func(overlay_needs_physical) sep \
 780	func(supports_tv) sep \
 781	func(has_llc) sep \
 782	func(has_ddi) sep \
 783	func(has_fpga_dbg)
 784
 785#define DEFINE_FLAG(name) u8 name:1
 786#define SEP_SEMICOLON ;
 787
 788struct intel_device_info {
 789	u32 display_mmio_offset;
 790	u16 device_id;
 791	u8 num_pipes:3;
 792	u8 num_sprites[I915_MAX_PIPES];
 793	u8 gen;
 794	u8 ring_mask; /* Rings supported by the HW */
 795	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 796	/* Register offsets for the various display pipes and transcoders */
 797	int pipe_offsets[I915_MAX_TRANSCODERS];
 798	int trans_offsets[I915_MAX_TRANSCODERS];
 799	int palette_offsets[I915_MAX_PIPES];
 800	int cursor_offsets[I915_MAX_PIPES];
 801
 802	/* Slice/subslice/EU info */
 803	u8 slice_total;
 804	u8 subslice_total;
 805	u8 subslice_per_slice;
 806	u8 eu_total;
 807	u8 eu_per_subslice;
 808	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
 809	u8 subslice_7eu[3];
 810	u8 has_slice_pg:1;
 811	u8 has_subslice_pg:1;
 812	u8 has_eu_pg:1;
 813};
 814
 815#undef DEFINE_FLAG
 816#undef SEP_SEMICOLON
 817
 818enum i915_cache_level {
 819	I915_CACHE_NONE = 0,
 820	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 821	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 822			      caches, eg sampler/render caches, and the
 823			      large Last-Level-Cache. LLC is coherent with
 824			      the CPU, but L3 is only visible to the GPU. */
 825	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 826};
 827
 828struct i915_ctx_hang_stats {
 829	/* This context had batch pending when hang was declared */
 830	unsigned batch_pending;
 831
 832	/* This context had batch active when hang was declared */
 833	unsigned batch_active;
 834
 835	/* Time when this context was last blamed for a GPU reset */
 836	unsigned long guilty_ts;
 837
 838	/* If the contexts causes a second GPU hang within this time,
 839	 * it is permanently banned from submitting any more work.
 840	 */
 841	unsigned long ban_period_seconds;
 842
 843	/* This context is banned to submit more work */
 844	bool banned;
 845};
 846
 847/* This must match up with the value previously used for execbuf2.rsvd1. */
 848#define DEFAULT_CONTEXT_HANDLE 0
 849
 850#define CONTEXT_NO_ZEROMAP (1<<0)
 851/**
 852 * struct intel_context - as the name implies, represents a context.
 853 * @ref: reference count.
 854 * @user_handle: userspace tracking identity for this context.
 855 * @remap_slice: l3 row remapping information.
 856 * @flags: context specific flags:
 857 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
 858 * @file_priv: filp associated with this context (NULL for global default
 859 *	       context).
 860 * @hang_stats: information about the role of this context in possible GPU
 861 *		hangs.
 862 * @ppgtt: virtual memory space used by this context.
 863 * @legacy_hw_ctx: render context backing object and whether it is correctly
 864 *                initialized (legacy ring submission mechanism only).
 865 * @link: link in the global list of contexts.
 866 *
 867 * Contexts are memory images used by the hardware to store copies of their
 868 * internal state.
 869 */
 870struct intel_context {
 871	struct kref ref;
 872	int user_handle;
 873	uint8_t remap_slice;
 874	struct drm_i915_private *i915;
 875	int flags;
 876	struct drm_i915_file_private *file_priv;
 877	struct i915_ctx_hang_stats hang_stats;
 878	struct i915_hw_ppgtt *ppgtt;
 879
 880	/* Legacy ring buffer submission */
 881	struct {
 882		struct drm_i915_gem_object *rcs_state;
 883		bool initialized;
 884	} legacy_hw_ctx;
 885
 886	/* Execlists */
 887	struct {
 888		struct drm_i915_gem_object *state;
 889		struct intel_ringbuffer *ringbuf;
 890		int pin_count;
 891		struct i915_vma *lrc_vma;
 892		u64 lrc_desc;
 893		uint32_t *lrc_reg_state;
 894	} engine[I915_NUM_RINGS];
 895
 896	struct list_head link;
 897};
 898
 899enum fb_op_origin {
 900	ORIGIN_GTT,
 901	ORIGIN_CPU,
 902	ORIGIN_CS,
 903	ORIGIN_FLIP,
 904	ORIGIN_DIRTYFB,
 905};
 906
 907struct intel_fbc {
 908	/* This is always the inner lock when overlapping with struct_mutex and
 909	 * it's the outer lock when overlapping with stolen_lock. */
 910	struct mutex lock;
 911	unsigned threshold;
 912	unsigned int possible_framebuffer_bits;
 913	unsigned int busy_bits;
 914	unsigned int visible_pipes_mask;
 915	struct intel_crtc *crtc;
 916
 917	struct drm_mm_node compressed_fb;
 918	struct drm_mm_node *compressed_llb;
 919
 920	bool false_color;
 921
 922	bool enabled;
 923	bool active;
 924
 925	struct intel_fbc_state_cache {
 926		struct {
 927			unsigned int mode_flags;
 928			uint32_t hsw_bdw_pixel_rate;
 929		} crtc;
 930
 931		struct {
 932			unsigned int rotation;
 933			int src_w;
 934			int src_h;
 935			bool visible;
 936		} plane;
 937
 938		struct {
 939			u64 ilk_ggtt_offset;
 940			uint32_t pixel_format;
 941			unsigned int stride;
 942			int fence_reg;
 943			unsigned int tiling_mode;
 944		} fb;
 945	} state_cache;
 946
 947	struct intel_fbc_reg_params {
 948		struct {
 949			enum pipe pipe;
 950			enum plane plane;
 951			unsigned int fence_y_offset;
 952		} crtc;
 953
 954		struct {
 955			u64 ggtt_offset;
 956			uint32_t pixel_format;
 957			unsigned int stride;
 958			int fence_reg;
 959		} fb;
 960
 961		int cfb_size;
 962	} params;
 963
 964	struct intel_fbc_work {
 965		bool scheduled;
 966		u32 scheduled_vblank;
 967		struct work_struct work;
 968	} work;
 969
 970	const char *no_fbc_reason;
 971};
 972
 973/**
 974 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 975 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 976 * parsing for same resolution.
 977 */
 978enum drrs_refresh_rate_type {
 979	DRRS_HIGH_RR,
 980	DRRS_LOW_RR,
 981	DRRS_MAX_RR, /* RR count */
 982};
 983
 984enum drrs_support_type {
 985	DRRS_NOT_SUPPORTED = 0,
 986	STATIC_DRRS_SUPPORT = 1,
 987	SEAMLESS_DRRS_SUPPORT = 2
 988};
 989
 990struct intel_dp;
 991struct i915_drrs {
 992	struct mutex mutex;
 993	struct delayed_work work;
 994	struct intel_dp *dp;
 995	unsigned busy_frontbuffer_bits;
 996	enum drrs_refresh_rate_type refresh_rate_type;
 997	enum drrs_support_type type;
 998};
 999
1000struct i915_psr {
1001	struct mutex lock;
1002	bool sink_support;
1003	bool source_ok;
1004	struct intel_dp *enabled;
1005	bool active;
1006	struct delayed_work work;
1007	unsigned busy_frontbuffer_bits;
1008	bool psr2_support;
1009	bool aux_frame_sync;
1010	bool link_standby;
1011};
1012
1013enum intel_pch {
1014	PCH_NONE = 0,	/* No PCH present */
1015	PCH_IBX,	/* Ibexpeak PCH */
1016	PCH_CPT,	/* Cougarpoint PCH */
1017	PCH_LPT,	/* Lynxpoint PCH */
1018	PCH_SPT,        /* Sunrisepoint PCH */
1019	PCH_NOP,
1020};
1021
1022enum intel_sbi_destination {
1023	SBI_ICLK,
1024	SBI_MPHY,
1025};
1026
1027#define QUIRK_PIPEA_FORCE (1<<0)
1028#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1029#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1030#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1031#define QUIRK_PIPEB_FORCE (1<<4)
1032#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1033
1034struct intel_fbdev;
1035struct intel_fbc_work;
1036
1037struct intel_gmbus {
1038	struct i2c_adapter adapter;
1039	u32 force_bit;
1040	u32 reg0;
1041	i915_reg_t gpio_reg;
1042	struct i2c_algo_bit_data bit_algo;
1043	struct drm_i915_private *dev_priv;
1044};
1045
1046struct i915_suspend_saved_registers {
1047	u32 saveDSPARB;
1048	u32 saveLVDS;
1049	u32 savePP_ON_DELAYS;
1050	u32 savePP_OFF_DELAYS;
1051	u32 savePP_ON;
1052	u32 savePP_OFF;
1053	u32 savePP_CONTROL;
1054	u32 savePP_DIVISOR;
1055	u32 saveFBC_CONTROL;
1056	u32 saveCACHE_MODE_0;
1057	u32 saveMI_ARB_STATE;
1058	u32 saveSWF0[16];
1059	u32 saveSWF1[16];
1060	u32 saveSWF3[3];
1061	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1062	u32 savePCH_PORT_HOTPLUG;
1063	u16 saveGCDGMBUS;
1064};
1065
1066struct vlv_s0ix_state {
1067	/* GAM */
1068	u32 wr_watermark;
1069	u32 gfx_prio_ctrl;
1070	u32 arb_mode;
1071	u32 gfx_pend_tlb0;
1072	u32 gfx_pend_tlb1;
1073	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1074	u32 media_max_req_count;
1075	u32 gfx_max_req_count;
1076	u32 render_hwsp;
1077	u32 ecochk;
1078	u32 bsd_hwsp;
1079	u32 blt_hwsp;
1080	u32 tlb_rd_addr;
1081
1082	/* MBC */
1083	u32 g3dctl;
1084	u32 gsckgctl;
1085	u32 mbctl;
1086
1087	/* GCP */
1088	u32 ucgctl1;
1089	u32 ucgctl3;
1090	u32 rcgctl1;
1091	u32 rcgctl2;
1092	u32 rstctl;
1093	u32 misccpctl;
1094
1095	/* GPM */
1096	u32 gfxpause;
1097	u32 rpdeuhwtc;
1098	u32 rpdeuc;
1099	u32 ecobus;
1100	u32 pwrdwnupctl;
1101	u32 rp_down_timeout;
1102	u32 rp_deucsw;
1103	u32 rcubmabdtmr;
1104	u32 rcedata;
1105	u32 spare2gh;
1106
1107	/* Display 1 CZ domain */
1108	u32 gt_imr;
1109	u32 gt_ier;
1110	u32 pm_imr;
1111	u32 pm_ier;
1112	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1113
1114	/* GT SA CZ domain */
1115	u32 tilectl;
1116	u32 gt_fifoctl;
1117	u32 gtlc_wake_ctrl;
1118	u32 gtlc_survive;
1119	u32 pmwgicz;
1120
1121	/* Display 2 CZ domain */
1122	u32 gu_ctl0;
1123	u32 gu_ctl1;
1124	u32 pcbr;
1125	u32 clock_gate_dis2;
1126};
1127
1128struct intel_rps_ei {
1129	u32 cz_clock;
1130	u32 render_c0;
1131	u32 media_c0;
1132};
1133
1134struct intel_gen6_power_mgmt {
1135	/*
1136	 * work, interrupts_enabled and pm_iir are protected by
1137	 * dev_priv->irq_lock
1138	 */
1139	struct work_struct work;
1140	bool interrupts_enabled;
1141	u32 pm_iir;
1142
1143	/* Frequencies are stored in potentially platform dependent multiples.
1144	 * In other words, *_freq needs to be multiplied by X to be interesting.
1145	 * Soft limits are those which are used for the dynamic reclocking done
1146	 * by the driver (raise frequencies under heavy loads, and lower for
1147	 * lighter loads). Hard limits are those imposed by the hardware.
1148	 *
1149	 * A distinction is made for overclocking, which is never enabled by
1150	 * default, and is considered to be above the hard limit if it's
1151	 * possible at all.
1152	 */
1153	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
1154	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
1155	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
1156	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
1157	u8 min_freq;		/* AKA RPn. Minimum frequency */
1158	u8 idle_freq;		/* Frequency to request when we are idle */
1159	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
1160	u8 rp1_freq;		/* "less than" RP0 power/freqency */
1161	u8 rp0_freq;		/* Non-overclocked max frequency. */
1162
1163	u8 up_threshold; /* Current %busy required to uplock */
1164	u8 down_threshold; /* Current %busy required to downclock */
1165
1166	int last_adj;
1167	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1168
1169	spinlock_t client_lock;
1170	struct list_head clients;
1171	bool client_boost;
1172
1173	bool enabled;
1174	struct delayed_work delayed_resume_work;
1175	unsigned boosts;
1176
1177	struct intel_rps_client semaphores, mmioflips;
1178
1179	/* manual wa residency calculations */
1180	struct intel_rps_ei up_ei, down_ei;
1181
1182	/*
1183	 * Protects RPS/RC6 register access and PCU communication.
1184	 * Must be taken after struct_mutex if nested. Note that
1185	 * this lock may be held for long periods of time when
1186	 * talking to hw - so only take it when talking to hw!
1187	 */
1188	struct mutex hw_lock;
1189};
1190
1191/* defined intel_pm.c */
1192extern spinlock_t mchdev_lock;
1193
1194struct intel_ilk_power_mgmt {
1195	u8 cur_delay;
1196	u8 min_delay;
1197	u8 max_delay;
1198	u8 fmax;
1199	u8 fstart;
1200
1201	u64 last_count1;
1202	unsigned long last_time1;
1203	unsigned long chipset_power;
1204	u64 last_count2;
1205	u64 last_time2;
1206	unsigned long gfx_power;
1207	u8 corr;
1208
1209	int c_m;
1210	int r_t;
1211};
1212
1213struct drm_i915_private;
1214struct i915_power_well;
1215
1216struct i915_power_well_ops {
1217	/*
1218	 * Synchronize the well's hw state to match the current sw state, for
1219	 * example enable/disable it based on the current refcount. Called
1220	 * during driver init and resume time, possibly after first calling
1221	 * the enable/disable handlers.
1222	 */
1223	void (*sync_hw)(struct drm_i915_private *dev_priv,
1224			struct i915_power_well *power_well);
1225	/*
1226	 * Enable the well and resources that depend on it (for example
1227	 * interrupts located on the well). Called after the 0->1 refcount
1228	 * transition.
1229	 */
1230	void (*enable)(struct drm_i915_private *dev_priv,
1231		       struct i915_power_well *power_well);
1232	/*
1233	 * Disable the well and resources that depend on it. Called after
1234	 * the 1->0 refcount transition.
1235	 */
1236	void (*disable)(struct drm_i915_private *dev_priv,
1237			struct i915_power_well *power_well);
1238	/* Returns the hw enabled state. */
1239	bool (*is_enabled)(struct drm_i915_private *dev_priv,
1240			   struct i915_power_well *power_well);
1241};
1242
1243/* Power well structure for haswell */
1244struct i915_power_well {
1245	const char *name;
1246	bool always_on;
1247	/* power well enable/disable usage count */
1248	int count;
1249	/* cached hw enabled state */
1250	bool hw_enabled;
1251	unsigned long domains;
1252	unsigned long data;
1253	const struct i915_power_well_ops *ops;
1254};
1255
1256struct i915_power_domains {
1257	/*
1258	 * Power wells needed for initialization at driver init and suspend
1259	 * time are on. They are kept on until after the first modeset.
1260	 */
1261	bool init_power_on;
1262	bool initializing;
1263	int power_well_count;
1264
1265	struct mutex lock;
1266	int domain_use_count[POWER_DOMAIN_NUM];
1267	struct i915_power_well *power_wells;
1268};
1269
1270#define MAX_L3_SLICES 2
1271struct intel_l3_parity {
1272	u32 *remap_info[MAX_L3_SLICES];
1273	struct work_struct error_work;
1274	int which_slice;
1275};
1276
1277struct i915_gem_mm {
 
 
 
 
 
 
 
1278	/** Memory allocator for GTT stolen memory */
1279	struct drm_mm stolen;
1280	/** Protects the usage of the GTT stolen memory allocator. This is
1281	 * always the inner lock when overlapping with struct_mutex. */
1282	struct mutex stolen_lock;
1283
1284	/** List of all objects in gtt_space. Used to restore gtt
1285	 * mappings on resume */
1286	struct list_head bound_list;
1287	/**
1288	 * List of objects which are not bound to the GTT (thus
1289	 * are idle and not used by the GPU) but still have
1290	 * (presumably uncached) pages still attached.
1291	 */
1292	struct list_head unbound_list;
1293
1294	/** Usable portion of the GTT for GEM */
1295	unsigned long stolen_base; /* limited to low memory (32-bit) */
1296
1297	/** PPGTT used for aliasing the PPGTT with the GTT */
1298	struct i915_hw_ppgtt *aliasing_ppgtt;
1299
1300	struct notifier_block oom_notifier;
1301	struct shrinker shrinker;
1302	bool shrinker_no_lock_stealing;
1303
1304	/** LRU list of objects with fence regs on them. */
1305	struct list_head fence_list;
1306
1307	/**
1308	 * We leave the user IRQ off as much as possible,
1309	 * but this means that requests will finish and never
1310	 * be retired once the system goes idle. Set a timer to
1311	 * fire periodically while the ring is running. When it
1312	 * fires, go retire requests.
1313	 */
1314	struct delayed_work retire_work;
1315
1316	/**
1317	 * When we detect an idle GPU, we want to turn on
1318	 * powersaving features. So once we see that there
1319	 * are no more requests outstanding and no more
1320	 * arrive within a small period of time, we fire
1321	 * off the idle_work.
1322	 */
1323	struct delayed_work idle_work;
1324
1325	/**
1326	 * Are we in a non-interruptible section of code like
1327	 * modesetting?
1328	 */
1329	bool interruptible;
1330
1331	/**
1332	 * Is the GPU currently considered idle, or busy executing userspace
1333	 * requests?  Whilst idle, we attempt to power down the hardware and
1334	 * display clocks. In order to reduce the effect on performance, there
1335	 * is a slight delay before we do so.
1336	 */
1337	bool busy;
1338
1339	/* the indicator for dispatch video commands on two BSD rings */
1340	unsigned int bsd_ring_dispatch_index;
1341
1342	/** Bit 6 swizzling required for X tiling */
1343	uint32_t bit_6_swizzle_x;
1344	/** Bit 6 swizzling required for Y tiling */
1345	uint32_t bit_6_swizzle_y;
1346
1347	/* accounting, useful for userland debugging */
1348	spinlock_t object_stat_lock;
1349	size_t object_memory;
1350	u32 object_count;
1351};
1352
1353struct drm_i915_error_state_buf {
1354	struct drm_i915_private *i915;
1355	unsigned bytes;
1356	unsigned size;
1357	int err;
1358	u8 *buf;
1359	loff_t start;
1360	loff_t pos;
1361};
1362
1363struct i915_error_state_file_priv {
1364	struct drm_device *dev;
1365	struct drm_i915_error_state *error;
1366};
1367
1368struct i915_gpu_error {
1369	/* For hangcheck timer */
1370#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1371#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1372	/* Hang gpu twice in this window and your context gets banned */
1373#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1374
1375	struct workqueue_struct *hangcheck_wq;
1376	struct delayed_work hangcheck_work;
1377
1378	/* For reset and error_state handling. */
1379	spinlock_t lock;
1380	/* Protected by the above dev->gpu_error.lock. */
1381	struct drm_i915_error_state *first_error;
1382
1383	unsigned long missed_irq_rings;
1384
1385	/**
1386	 * State variable controlling the reset flow and count
1387	 *
1388	 * This is a counter which gets incremented when reset is triggered,
1389	 * and again when reset has been handled. So odd values (lowest bit set)
1390	 * means that reset is in progress and even values that
1391	 * (reset_counter >> 1):th reset was successfully completed.
1392	 *
1393	 * If reset is not completed succesfully, the I915_WEDGE bit is
1394	 * set meaning that hardware is terminally sour and there is no
1395	 * recovery. All waiters on the reset_queue will be woken when
1396	 * that happens.
1397	 *
1398	 * This counter is used by the wait_seqno code to notice that reset
1399	 * event happened and it needs to restart the entire ioctl (since most
1400	 * likely the seqno it waited for won't ever signal anytime soon).
1401	 *
1402	 * This is important for lock-free wait paths, where no contended lock
1403	 * naturally enforces the correct ordering between the bail-out of the
1404	 * waiter and the gpu reset work code.
1405	 */
1406	atomic_t reset_counter;
1407
1408#define I915_RESET_IN_PROGRESS_FLAG	1
1409#define I915_WEDGED			(1 << 31)
1410
1411	/**
1412	 * Waitqueue to signal when the reset has completed. Used by clients
1413	 * that wait for dev_priv->mm.wedged to settle.
1414	 */
1415	wait_queue_head_t reset_queue;
1416
1417	/* Userspace knobs for gpu hang simulation;
1418	 * combines both a ring mask, and extra flags
1419	 */
1420	u32 stop_rings;
1421#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
1422#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1423
1424	/* For missed irq/seqno simulation. */
1425	unsigned int test_irq_rings;
1426
1427	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
1428	bool reload_in_reset;
1429};
1430
1431enum modeset_restore {
1432	MODESET_ON_LID_OPEN,
1433	MODESET_DONE,
1434	MODESET_SUSPENDED,
1435};
1436
1437#define DP_AUX_A 0x40
1438#define DP_AUX_B 0x10
1439#define DP_AUX_C 0x20
1440#define DP_AUX_D 0x30
1441
1442#define DDC_PIN_B  0x05
1443#define DDC_PIN_C  0x04
1444#define DDC_PIN_D  0x06
1445
1446struct ddi_vbt_port_info {
1447	/*
1448	 * This is an index in the HDMI/DVI DDI buffer translation table.
1449	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1450	 * populate this field.
1451	 */
1452#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1453	uint8_t hdmi_level_shift;
1454
1455	uint8_t supports_dvi:1;
1456	uint8_t supports_hdmi:1;
1457	uint8_t supports_dp:1;
1458
1459	uint8_t alternate_aux_channel;
1460	uint8_t alternate_ddc_pin;
1461
1462	uint8_t dp_boost_level;
1463	uint8_t hdmi_boost_level;
1464};
1465
1466enum psr_lines_to_wait {
1467	PSR_0_LINES_TO_WAIT = 0,
1468	PSR_1_LINE_TO_WAIT,
1469	PSR_4_LINES_TO_WAIT,
1470	PSR_8_LINES_TO_WAIT
1471};
1472
1473struct intel_vbt_data {
1474	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1475	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1476
1477	/* Feature bits */
1478	unsigned int int_tv_support:1;
1479	unsigned int lvds_dither:1;
1480	unsigned int lvds_vbt:1;
1481	unsigned int int_crt_support:1;
1482	unsigned int lvds_use_ssc:1;
1483	unsigned int display_clock_mode:1;
1484	unsigned int fdi_rx_polarity_inverted:1;
1485	unsigned int has_mipi:1;
1486	int lvds_ssc_freq;
1487	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1488
1489	enum drrs_support_type drrs_type;
1490
1491	/* eDP */
1492	int edp_rate;
1493	int edp_lanes;
1494	int edp_preemphasis;
1495	int edp_vswing;
1496	bool edp_initialized;
1497	bool edp_support;
1498	int edp_bpp;
1499	struct edp_power_seq edp_pps;
1500
1501	struct {
1502		bool full_link;
1503		bool require_aux_wakeup;
1504		int idle_frames;
1505		enum psr_lines_to_wait lines_to_wait;
1506		int tp1_wakeup_time;
1507		int tp2_tp3_wakeup_time;
1508	} psr;
1509
1510	struct {
1511		u16 pwm_freq_hz;
1512		bool present;
1513		bool active_low_pwm;
1514		u8 min_brightness;	/* min_brightness/255 of max */
1515	} backlight;
1516
1517	/* MIPI DSI */
1518	struct {
1519		u16 port;
1520		u16 panel_id;
1521		struct mipi_config *config;
1522		struct mipi_pps_data *pps;
1523		u8 seq_version;
1524		u32 size;
1525		u8 *data;
1526		const u8 *sequence[MIPI_SEQ_MAX];
1527	} dsi;
1528
1529	int crt_ddc_pin;
1530
1531	int child_dev_num;
1532	union child_device_config *child_dev;
1533
1534	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1535};
1536
1537enum intel_ddb_partitioning {
1538	INTEL_DDB_PART_1_2,
1539	INTEL_DDB_PART_5_6, /* IVB+ */
1540};
1541
1542struct intel_wm_level {
1543	bool enable;
1544	uint32_t pri_val;
1545	uint32_t spr_val;
1546	uint32_t cur_val;
1547	uint32_t fbc_val;
1548};
1549
1550struct ilk_wm_values {
1551	uint32_t wm_pipe[3];
1552	uint32_t wm_lp[3];
1553	uint32_t wm_lp_spr[3];
1554	uint32_t wm_linetime[3];
1555	bool enable_fbc_wm;
1556	enum intel_ddb_partitioning partitioning;
1557};
1558
1559struct vlv_pipe_wm {
1560	uint16_t primary;
1561	uint16_t sprite[2];
1562	uint8_t cursor;
1563};
1564
1565struct vlv_sr_wm {
1566	uint16_t plane;
1567	uint8_t cursor;
1568};
1569
1570struct vlv_wm_values {
1571	struct vlv_pipe_wm pipe[3];
1572	struct vlv_sr_wm sr;
1573	struct {
1574		uint8_t cursor;
1575		uint8_t sprite[2];
1576		uint8_t primary;
1577	} ddl[3];
1578	uint8_t level;
1579	bool cxsr;
1580};
1581
1582struct skl_ddb_entry {
1583	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1584};
1585
1586static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1587{
1588	return entry->end - entry->start;
1589}
1590
1591static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1592				       const struct skl_ddb_entry *e2)
1593{
1594	if (e1->start == e2->start && e1->end == e2->end)
1595		return true;
1596
1597	return false;
1598}
1599
1600struct skl_ddb_allocation {
1601	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1602	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1603	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1604};
1605
1606struct skl_wm_values {
1607	bool dirty[I915_MAX_PIPES];
1608	struct skl_ddb_allocation ddb;
1609	uint32_t wm_linetime[I915_MAX_PIPES];
1610	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1611	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1612};
1613
1614struct skl_wm_level {
1615	bool plane_en[I915_MAX_PLANES];
1616	uint16_t plane_res_b[I915_MAX_PLANES];
1617	uint8_t plane_res_l[I915_MAX_PLANES];
1618};
1619
1620/*
1621 * This struct helps tracking the state needed for runtime PM, which puts the
1622 * device in PCI D3 state. Notice that when this happens, nothing on the
1623 * graphics device works, even register access, so we don't get interrupts nor
1624 * anything else.
1625 *
1626 * Every piece of our code that needs to actually touch the hardware needs to
1627 * either call intel_runtime_pm_get or call intel_display_power_get with the
1628 * appropriate power domain.
1629 *
1630 * Our driver uses the autosuspend delay feature, which means we'll only really
1631 * suspend if we stay with zero refcount for a certain amount of time. The
1632 * default value is currently very conservative (see intel_runtime_pm_enable), but
1633 * it can be changed with the standard runtime PM files from sysfs.
1634 *
1635 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1636 * goes back to false exactly before we reenable the IRQs. We use this variable
1637 * to check if someone is trying to enable/disable IRQs while they're supposed
1638 * to be disabled. This shouldn't happen and we'll print some error messages in
1639 * case it happens.
1640 *
1641 * For more, read the Documentation/power/runtime_pm.txt.
1642 */
1643struct i915_runtime_pm {
1644	atomic_t wakeref_count;
1645	atomic_t atomic_seq;
1646	bool suspended;
1647	bool irqs_enabled;
1648};
1649
1650enum intel_pipe_crc_source {
1651	INTEL_PIPE_CRC_SOURCE_NONE,
1652	INTEL_PIPE_CRC_SOURCE_PLANE1,
1653	INTEL_PIPE_CRC_SOURCE_PLANE2,
1654	INTEL_PIPE_CRC_SOURCE_PF,
1655	INTEL_PIPE_CRC_SOURCE_PIPE,
1656	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
1657	INTEL_PIPE_CRC_SOURCE_TV,
1658	INTEL_PIPE_CRC_SOURCE_DP_B,
1659	INTEL_PIPE_CRC_SOURCE_DP_C,
1660	INTEL_PIPE_CRC_SOURCE_DP_D,
1661	INTEL_PIPE_CRC_SOURCE_AUTO,
1662	INTEL_PIPE_CRC_SOURCE_MAX,
1663};
1664
1665struct intel_pipe_crc_entry {
1666	uint32_t frame;
1667	uint32_t crc[5];
1668};
1669
1670#define INTEL_PIPE_CRC_ENTRIES_NR	128
1671struct intel_pipe_crc {
1672	spinlock_t lock;
1673	bool opened;		/* exclusive access to the result file */
1674	struct intel_pipe_crc_entry *entries;
1675	enum intel_pipe_crc_source source;
1676	int head, tail;
1677	wait_queue_head_t wq;
1678};
1679
1680struct i915_frontbuffer_tracking {
1681	struct mutex lock;
1682
1683	/*
1684	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1685	 * scheduled flips.
1686	 */
1687	unsigned busy_bits;
1688	unsigned flip_bits;
1689};
1690
1691struct i915_wa_reg {
1692	i915_reg_t addr;
1693	u32 value;
1694	/* bitmask representing WA bits */
1695	u32 mask;
1696};
1697
1698/*
1699 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1700 * allowing it for RCS as we don't foresee any requirement of having
1701 * a whitelist for other engines. When it is really required for
1702 * other engines then the limit need to be increased.
1703 */
1704#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1705
1706struct i915_workarounds {
1707	struct i915_wa_reg reg[I915_MAX_WA_REGS];
1708	u32 count;
1709	u32 hw_whitelist_count[I915_NUM_RINGS];
1710};
1711
1712struct i915_virtual_gpu {
 
1713	bool active;
 
 
 
 
1714};
1715
1716struct i915_execbuffer_params {
1717	struct drm_device               *dev;
1718	struct drm_file                 *file;
1719	uint32_t                        dispatch_flags;
1720	uint32_t                        args_batch_start_offset;
1721	uint64_t                        batch_obj_vm_offset;
1722	struct intel_engine_cs          *ring;
1723	struct drm_i915_gem_object      *batch_obj;
1724	struct intel_context            *ctx;
1725	struct drm_i915_gem_request     *request;
1726};
1727
1728/* used in computing the new watermarks state */
1729struct intel_wm_config {
1730	unsigned int num_pipes_active;
1731	bool sprites_enabled;
1732	bool sprites_scaled;
1733};
1734
1735struct drm_i915_private {
1736	struct drm_device *dev;
1737	struct kmem_cache *objects;
1738	struct kmem_cache *vmas;
1739	struct kmem_cache *requests;
1740
1741	const struct intel_device_info info;
1742
1743	int relative_constants_mode;
1744
1745	void __iomem *regs;
 
1746
1747	struct intel_uncore uncore;
1748
1749	struct i915_virtual_gpu vgpu;
1750
1751	struct intel_guc guc;
1752
1753	struct intel_csr csr;
1754
1755	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1756
1757	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
1758	 * controller on different i2c buses. */
1759	struct mutex gmbus_mutex;
1760
1761	/**
1762	 * Base address of the gmbus and gpio block.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1763	 */
1764	uint32_t gpio_mmio_base;
1765
1766	/* MMIO base address for MIPI regs */
1767	uint32_t mipi_mmio_base;
1768
1769	uint32_t psr_mmio_base;
1770
1771	wait_queue_head_t gmbus_wait_queue;
1772
1773	struct pci_dev *bridge_dev;
1774	struct intel_engine_cs ring[I915_NUM_RINGS];
1775	struct drm_i915_gem_object *semaphore_obj;
1776	uint32_t last_seqno, next_seqno;
1777
1778	struct drm_dma_handle *status_page_dmah;
 
 
1779	struct resource mch_res;
1780
1781	/* protects the irq masks */
1782	spinlock_t irq_lock;
1783
1784	/* protects the mmio flip data */
1785	spinlock_t mmio_flip_lock;
1786
1787	bool display_irqs_enabled;
1788
1789	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1790	struct pm_qos_request pm_qos;
1791
1792	/* Sideband mailbox protection */
1793	struct mutex sb_lock;
 
1794
1795	/** Cached value of IMR to avoid reads in updating the bitfield */
1796	union {
1797		u32 irq_mask;
1798		u32 de_irq_mask[I915_MAX_PIPES];
1799	};
1800	u32 gt_irq_mask;
1801	u32 pm_irq_mask;
1802	u32 pm_rps_events;
1803	u32 pipestat_irq_mask[I915_MAX_PIPES];
1804
1805	struct i915_hotplug hotplug;
1806	struct intel_fbc fbc;
1807	struct i915_drrs drrs;
1808	struct intel_opregion opregion;
1809	struct intel_vbt_data vbt;
1810
1811	bool preserve_bios_swizzle;
1812
1813	/* overlay */
1814	struct intel_overlay *overlay;
1815
1816	/* backlight registers and fields in struct intel_panel */
1817	struct mutex backlight_lock;
1818
1819	/* LVDS info */
1820	bool no_aux_handshake;
1821
1822	/* protects panel power sequencer state */
1823	struct mutex pps_mutex;
1824
1825	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1826	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1827
1828	unsigned int fsb_freq, mem_freq, is_ddr3;
1829	unsigned int skl_boot_cdclk;
1830	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1831	unsigned int max_dotclk_freq;
1832	unsigned int hpll_freq;
1833	unsigned int czclk_freq;
1834
1835	/**
1836	 * wq - Driver workqueue for GEM.
1837	 *
1838	 * NOTE: Work items scheduled here are not allowed to grab any modeset
1839	 * locks, for otherwise the flushing done in the pageflip code will
1840	 * result in deadlocks.
1841	 */
1842	struct workqueue_struct *wq;
1843
1844	/* Display functions */
1845	struct drm_i915_display_funcs display;
1846
1847	/* PCH chipset type */
1848	enum intel_pch pch_type;
1849	unsigned short pch_id;
1850
1851	unsigned long quirks;
1852
1853	enum modeset_restore modeset_restore;
1854	struct mutex modeset_restore_lock;
1855	struct drm_atomic_state *modeset_restore_state;
1856
1857	struct list_head vm_list; /* Global list of all address spaces */
1858	struct i915_gtt gtt; /* VM representing the global address space */
1859
1860	struct i915_gem_mm mm;
1861	DECLARE_HASHTABLE(mm_structs, 7);
1862	struct mutex mm_lock;
1863
1864	/* Kernel Modesetting */
1865
1866	struct sdvo_device_mapping sdvo_mappings[2];
1867
1868	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1869	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1870	wait_queue_head_t pending_flip_queue;
1871
1872#ifdef CONFIG_DEBUG_FS
1873	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1874#endif
1875
1876	/* dpll and cdclk state is protected by connection_mutex */
1877	int num_shared_dpll;
1878	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1879
1880	unsigned int active_crtcs;
1881	unsigned int min_pixclk[I915_MAX_PIPES];
1882
1883	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1884
1885	struct i915_workarounds workarounds;
1886
1887	/* Reclocking support */
1888	bool render_reclock_avail;
1889
1890	struct i915_frontbuffer_tracking fb_tracking;
1891
1892	u16 orig_clock;
1893
1894	bool mchbar_need_disable;
1895
1896	struct intel_l3_parity l3_parity;
1897
1898	/* Cannot be determined by PCIID. You must always read a register. */
1899	size_t ellc_size;
 
 
 
1900
1901	/* gen6+ rps state */
1902	struct intel_gen6_power_mgmt rps;
1903
1904	/* ilk-only ips/rps state. Everything in here is protected by the global
1905	 * mchdev_lock in intel_pm.c */
1906	struct intel_ilk_power_mgmt ips;
 
 
 
 
1907
1908	struct i915_power_domains power_domains;
 
 
1909
1910	struct i915_psr psr;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1911
1912	struct i915_gpu_error gpu_error;
1913
1914	struct drm_i915_gem_object *vlv_pctx;
1915
1916#ifdef CONFIG_DRM_FBDEV_EMULATION
1917	/* list of fbdev register on this device */
1918	struct intel_fbdev *fbdev;
1919	struct work_struct fbdev_suspend_work;
1920#endif
1921
1922	struct drm_property *broadcast_rgb_property;
1923	struct drm_property *force_audio_property;
1924
1925	/* hda/i915 audio component */
1926	struct i915_audio_component *audio_component;
1927	bool audio_component_registered;
1928	/**
1929	 * av_mutex - mutex for audio/video sync
1930	 *
1931	 */
1932	struct mutex av_mutex;
 
1933
1934	uint32_t hw_context_size;
1935	struct list_head context_list;
1936
1937	u32 fdi_rx_config;
1938
1939	u32 chv_phy_control;
1940
1941	u32 suspend_count;
1942	bool suspended_to_idle;
1943	struct i915_suspend_saved_registers regfile;
1944	struct vlv_s0ix_state vlv_s0ix_state;
1945
1946	struct {
1947		/*
1948		 * Raw watermark latency values:
1949		 * in 0.1us units for WM0,
1950		 * in 0.5us units for WM1+.
1951		 */
1952		/* primary */
1953		uint16_t pri_latency[5];
1954		/* sprite */
1955		uint16_t spr_latency[5];
1956		/* cursor */
1957		uint16_t cur_latency[5];
1958		/*
1959		 * Raw watermark memory latency values
1960		 * for SKL for all 8 levels
1961		 * in 1us units.
1962		 */
1963		uint16_t skl_latency[8];
1964
1965		/* Committed wm config */
1966		struct intel_wm_config config;
1967
1968		/*
1969		 * The skl_wm_values structure is a bit too big for stack
1970		 * allocation, so we keep the staging struct where we store
1971		 * intermediate results here instead.
 
 
 
1972		 */
1973		struct skl_wm_values skl_results;
 
1974
1975		/* current hardware state */
1976		union {
1977			struct ilk_wm_values hw;
1978			struct skl_wm_values skl_hw;
1979			struct vlv_wm_values vlv;
1980		};
1981
1982		uint8_t max_level;
1983	} wm;
1984
1985	struct i915_runtime_pm pm;
1986
1987	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1988	struct {
1989		int (*execbuf_submit)(struct i915_execbuffer_params *params,
1990				      struct drm_i915_gem_execbuffer2 *args,
1991				      struct list_head *vmas);
1992		int (*init_rings)(struct drm_device *dev);
1993		void (*cleanup_ring)(struct intel_engine_cs *ring);
1994		void (*stop_ring)(struct intel_engine_cs *ring);
1995	} gt;
1996
1997	struct intel_context *kernel_context;
1998
1999	bool edp_low_vswing;
2000
2001	/* perform PHY state sanity checks? */
2002	bool chv_phy_assert[2];
2003
2004	struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2005
2006	/*
2007	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2008	 * will be rejected. Instead look for a better place.
2009	 */
2010};
2011
2012static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2013{
2014	return dev->dev_private;
2015}
2016
2017static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2018{
2019	return to_i915(dev_get_drvdata(dev));
2020}
2021
2022static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2023{
2024	return container_of(guc, struct drm_i915_private, guc);
2025}
2026
2027/* Iterate over initialised rings */
2028#define for_each_ring(ring__, dev_priv__, i__) \
2029	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2030		for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
2031
2032enum hdmi_force_audio {
2033	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
2034	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
2035	HDMI_AUDIO_AUTO,		/* trust EDID */
2036	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
2037};
2038
2039#define I915_GTT_OFFSET_NONE ((u32)-1)
2040
2041struct drm_i915_gem_object_ops {
2042	unsigned int flags;
2043#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2044
2045	/* Interface between the GEM object and its backing storage.
2046	 * get_pages() is called once prior to the use of the associated set
2047	 * of pages before to binding them into the GTT, and put_pages() is
2048	 * called after we no longer need them. As we expect there to be
2049	 * associated cost with migrating pages between the backing storage
2050	 * and making them available for the GPU (e.g. clflush), we may hold
2051	 * onto the pages after they are no longer referenced by the GPU
2052	 * in case they may be used again shortly (for example migrating the
2053	 * pages to a different memory domain within the GTT). put_pages()
2054	 * will therefore most likely be called when the object itself is
2055	 * being released or under memory pressure (where we attempt to
2056	 * reap pages for the shrinker).
2057	 */
2058	int (*get_pages)(struct drm_i915_gem_object *);
2059	void (*put_pages)(struct drm_i915_gem_object *);
2060
2061	int (*dmabuf_export)(struct drm_i915_gem_object *);
2062	void (*release)(struct drm_i915_gem_object *);
2063};
2064
2065/*
2066 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2067 * considered to be the frontbuffer for the given plane interface-wise. This
2068 * doesn't mean that the hw necessarily already scans it out, but that any
2069 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2070 *
2071 * We have one bit per pipe and per scanout plane type.
2072 */
2073#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2074#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2075#define INTEL_FRONTBUFFER_BITS \
2076	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2077#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2078	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2079#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2080	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2081#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2082	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2083#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2084	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2085#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2086	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2087
2088struct drm_i915_gem_object {
2089	struct drm_gem_object base;
2090
2091	const struct drm_i915_gem_object_ops *ops;
2092
2093	/** List of VMAs backed by this object */
2094	struct list_head vma_list;
2095
2096	/** Stolen memory for this object, instead of being backed by shmem. */
2097	struct drm_mm_node *stolen;
2098	struct list_head global_list;
2099
2100	struct list_head ring_list[I915_NUM_RINGS];
2101	/** Used in execbuf to temporarily hold a ref */
2102	struct list_head obj_exec_link;
2103
2104	struct list_head batch_pool_link;
2105
2106	/**
2107	 * This is set if the object is on the active lists (has pending
2108	 * rendering and so a non-zero seqno), and is not set if it i s on
2109	 * inactive (ready to be unbound) list.
2110	 */
2111	unsigned int active:I915_NUM_RINGS;
2112
2113	/**
2114	 * This is set if the object has been written to since last bound
2115	 * to the GTT
2116	 */
2117	unsigned int dirty:1;
2118
2119	/**
2120	 * Fence register bits (if any) for this object.  Will be set
2121	 * as needed when mapped into the GTT.
2122	 * Protected by dev->struct_mutex.
2123	 */
2124	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2125
2126	/**
2127	 * Advice: are the backing pages purgeable?
2128	 */
2129	unsigned int madv:2;
2130
2131	/**
2132	 * Current tiling mode for the object.
2133	 */
2134	unsigned int tiling_mode:2;
2135	/**
2136	 * Whether the tiling parameters for the currently associated fence
2137	 * register have changed. Note that for the purposes of tracking
2138	 * tiling changes we also treat the unfenced register, the register
2139	 * slot that the object occupies whilst it executes a fenced
2140	 * command (such as BLT on gen2/3), as a "fence".
2141	 */
2142	unsigned int fence_dirty:1;
2143
2144	/**
2145	 * Is the object at the current location in the gtt mappable and
2146	 * fenceable? Used to avoid costly recalculations.
2147	 */
2148	unsigned int map_and_fenceable:1;
2149
2150	/**
2151	 * Whether the current gtt mapping needs to be mappable (and isn't just
2152	 * mappable by accident). Track pin and fault separate for a more
2153	 * accurate mappable working set.
2154	 */
2155	unsigned int fault_mappable:1;
2156
2157	/*
2158	 * Is the object to be mapped as read-only to the GPU
2159	 * Only honoured if hardware has relevant pte bit
2160	 */
2161	unsigned long gt_ro:1;
2162	unsigned int cache_level:3;
2163	unsigned int cache_dirty:1;
2164
2165	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2166
2167	unsigned int pin_display;
2168
2169	struct sg_table *pages;
2170	int pages_pin_count;
2171	struct get_page {
2172		struct scatterlist *sg;
2173		int last;
2174	} get_page;
2175
2176	/* prime dma-buf support */
2177	void *dma_buf_vmapping;
2178	int vmapping_count;
2179
2180	/** Breadcrumb of last rendering to the buffer.
2181	 * There can only be one writer, but we allow for multiple readers.
2182	 * If there is a writer that necessarily implies that all other
2183	 * read requests are complete - but we may only be lazily clearing
2184	 * the read requests. A read request is naturally the most recent
2185	 * request on a ring, so we may have two different write and read
2186	 * requests on one ring where the write request is older than the
2187	 * read request. This allows for the CPU to read from an active
2188	 * buffer by only waiting for the write to complete.
2189	 * */
2190	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2191	struct drm_i915_gem_request *last_write_req;
2192	/** Breadcrumb of last fenced GPU access to the buffer. */
2193	struct drm_i915_gem_request *last_fenced_req;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2194
2195	/** Current tiling stride for the object, if it's tiled. */
2196	uint32_t stride;
2197
2198	/** References from framebuffers, locks out tiling changes. */
2199	unsigned long framebuffer_references;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2200
2201	/** Record of address bit 17 of each page at last unbind. */
2202	unsigned long *bit_17;
 
2203
2204	union {
2205		/** for phy allocated objects */
2206		struct drm_dma_handle *phys_handle;
2207
2208		struct i915_gem_userptr {
2209			uintptr_t ptr;
2210			unsigned read_only :1;
2211			unsigned workers :4;
2212#define I915_GEM_USERPTR_MAX_WORKERS 15
2213
2214			struct i915_mm_struct *mm;
2215			struct i915_mmu_object *mmu_object;
2216			struct work_struct *work;
2217		} userptr;
2218	};
2219};
2220#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2221
2222void i915_gem_track_fb(struct drm_i915_gem_object *old,
2223		       struct drm_i915_gem_object *new,
2224		       unsigned frontbuffer_bits);
 
 
 
 
 
2225
2226/**
2227 * Request queue structure.
2228 *
2229 * The request queue allows us to note sequence numbers that have been emitted
2230 * and may be associated with active buffers to be retired.
2231 *
2232 * By keeping this list, we can avoid having to do questionable sequence
2233 * number comparisons on buffer last_read|write_seqno. It also allows an
2234 * emission time to be associated with the request for tracking how far ahead
2235 * of the GPU the submission is.
2236 *
2237 * The requests are reference counted, so upon creation they should have an
2238 * initial reference taken using kref_init
2239 */
2240struct drm_i915_gem_request {
2241	struct kref ref;
2242
2243	/** On Which ring this request was generated */
2244	struct drm_i915_private *i915;
2245	struct intel_engine_cs *ring;
2246
2247	 /** GEM sequence number associated with the previous request,
2248	  * when the HWS breadcrumb is equal to this the GPU is processing
2249	  * this request.
2250	  */
2251	u32 previous_seqno;
2252
2253	 /** GEM sequence number associated with this request,
2254	  * when the HWS breadcrumb is equal or greater than this the GPU
2255	  * has finished processing this request.
2256	  */
2257	u32 seqno;
2258
2259	/** Position in the ringbuffer of the start of the request */
2260	u32 head;
2261
2262	/**
2263	 * Position in the ringbuffer of the start of the postfix.
2264	 * This is required to calculate the maximum available ringbuffer
2265	 * space without overwriting the postfix.
2266	 */
2267	 u32 postfix;
2268
2269	/** Position in the ringbuffer of the end of the whole request */
2270	u32 tail;
 
2271
2272	/**
2273	 * Context and ring buffer related to this request
2274	 * Contexts are refcounted, so when this request is associated with a
2275	 * context, we must increment the context's refcount, to guarantee that
2276	 * it persists while any request is linked to it. Requests themselves
2277	 * are also refcounted, so the request will only be freed when the last
2278	 * reference to it is dismissed, and the code in
2279	 * i915_gem_request_free() will then decrement the refcount on the
2280	 * context.
2281	 */
2282	struct intel_context *ctx;
2283	struct intel_ringbuffer *ringbuf;
2284
2285	/** Batch buffer related to this request if any (used for
2286	    error state dump only) */
2287	struct drm_i915_gem_object *batch_obj;
2288
2289	/** Time at which this request was emitted, in jiffies. */
2290	unsigned long emitted_jiffies;
2291
2292	/** global list entry for this request */
2293	struct list_head list;
2294
2295	struct drm_i915_file_private *file_priv;
2296	/** file_priv list entry for this request */
2297	struct list_head client_list;
2298
2299	/** process identifier submitting this request */
2300	struct pid *pid;
2301
2302	/**
2303	 * The ELSP only accepts two elements at a time, so we queue
2304	 * context/tail pairs on a given queue (ring->execlist_queue) until the
2305	 * hardware is available. The queue serves a double purpose: we also use
2306	 * it to keep track of the up to 2 contexts currently in the hardware
2307	 * (usually one in execution and the other queued up by the GPU): We
2308	 * only remove elements from the head of the queue when the hardware
2309	 * informs us that an element has been completed.
2310	 *
2311	 * All accesses to the queue are mediated by a spinlock
2312	 * (ring->execlist_lock).
2313	 */
2314
2315	/** Execlist link in the submission queue.*/
2316	struct list_head execlist_link;
2317
2318	/** Execlists no. of times this request has been sent to the ELSP */
2319	int elsp_submitted;
2320
2321};
2322
2323struct drm_i915_gem_request * __must_check
2324i915_gem_request_alloc(struct intel_engine_cs *engine,
2325		       struct intel_context *ctx);
2326void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2327void i915_gem_request_free(struct kref *req_ref);
2328int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2329				   struct drm_file *file);
2330
2331static inline uint32_t
2332i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2333{
2334	return req ? req->seqno : 0;
2335}
2336
2337static inline struct intel_engine_cs *
2338i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2339{
2340	return req ? req->ring : NULL;
2341}
 
 
 
 
2342
2343static inline struct drm_i915_gem_request *
2344i915_gem_request_reference(struct drm_i915_gem_request *req)
2345{
2346	if (req)
2347		kref_get(&req->ref);
2348	return req;
2349}
2350
2351static inline void
2352i915_gem_request_unreference(struct drm_i915_gem_request *req)
2353{
2354	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2355	kref_put(&req->ref, i915_gem_request_free);
2356}
2357
2358static inline void
2359i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2360{
2361	struct drm_device *dev;
2362
2363	if (!req)
2364		return;
2365
2366	dev = req->ring->dev;
2367	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2368		mutex_unlock(&dev->struct_mutex);
2369}
2370
2371static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2372					   struct drm_i915_gem_request *src)
2373{
2374	if (src)
2375		i915_gem_request_reference(src);
2376
2377	if (*pdst)
2378		i915_gem_request_unreference(*pdst);
2379
2380	*pdst = src;
2381}
2382
2383/*
2384 * XXX: i915_gem_request_completed should be here but currently needs the
2385 * definition of i915_seqno_passed() which is below. It will be moved in
2386 * a later patch when the call to i915_seqno_passed() is obsoleted...
2387 */
2388
2389/*
2390 * A command that requires special handling by the command parser.
 
2391 */
2392struct drm_i915_cmd_descriptor {
2393	/*
2394	 * Flags describing how the command parser processes the command.
2395	 *
2396	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2397	 *                 a length mask if not set
2398	 * CMD_DESC_SKIP: The command is allowed but does not follow the
2399	 *                standard length encoding for the opcode range in
2400	 *                which it falls
2401	 * CMD_DESC_REJECT: The command is never allowed
2402	 * CMD_DESC_REGISTER: The command should be checked against the
2403	 *                    register whitelist for the appropriate ring
2404	 * CMD_DESC_MASTER: The command is allowed if the submitting process
2405	 *                  is the DRM master
2406	 */
2407	u32 flags;
2408#define CMD_DESC_FIXED    (1<<0)
2409#define CMD_DESC_SKIP     (1<<1)
2410#define CMD_DESC_REJECT   (1<<2)
2411#define CMD_DESC_REGISTER (1<<3)
2412#define CMD_DESC_BITMASK  (1<<4)
2413#define CMD_DESC_MASTER   (1<<5)
2414
2415	/*
2416	 * The command's unique identification bits and the bitmask to get them.
2417	 * This isn't strictly the opcode field as defined in the spec and may
2418	 * also include type, subtype, and/or subop fields.
2419	 */
2420	struct {
2421		u32 value;
2422		u32 mask;
2423	} cmd;
2424
2425	/*
2426	 * The command's length. The command is either fixed length (i.e. does
2427	 * not include a length field) or has a length field mask. The flag
2428	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2429	 * a length mask. All command entries in a command table must include
2430	 * length information.
2431	 */
2432	union {
2433		u32 fixed;
2434		u32 mask;
2435	} length;
2436
2437	/*
2438	 * Describes where to find a register address in the command to check
2439	 * against the ring's register whitelist. Only valid if flags has the
2440	 * CMD_DESC_REGISTER bit set.
2441	 *
2442	 * A non-zero step value implies that the command may access multiple
2443	 * registers in sequence (e.g. LRI), in that case step gives the
2444	 * distance in dwords between individual offset fields.
2445	 */
2446	struct {
2447		u32 offset;
2448		u32 mask;
2449		u32 step;
2450	} reg;
2451
2452#define MAX_CMD_DESC_BITMASKS 3
2453	/*
2454	 * Describes command checks where a particular dword is masked and
2455	 * compared against an expected value. If the command does not match
2456	 * the expected value, the parser rejects it. Only valid if flags has
2457	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2458	 * are valid.
2459	 *
2460	 * If the check specifies a non-zero condition_mask then the parser
2461	 * only performs the check when the bits specified by condition_mask
2462	 * are non-zero.
2463	 */
2464	struct {
2465		u32 offset;
2466		u32 mask;
2467		u32 expected;
2468		u32 condition_offset;
2469		u32 condition_mask;
2470	} bits[MAX_CMD_DESC_BITMASKS];
2471};
2472
2473/*
2474 * A table of commands requiring special handling by the command parser.
2475 *
2476 * Each ring has an array of tables. Each table consists of an array of command
2477 * descriptors, which must be sorted with command opcodes in ascending order.
2478 */
2479struct drm_i915_cmd_table {
2480	const struct drm_i915_cmd_descriptor *table;
2481	int count;
2482};
2483
2484/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2485#define __I915__(p) ({ \
2486	struct drm_i915_private *__p; \
2487	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2488		__p = (struct drm_i915_private *)p; \
2489	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2490		__p = to_i915((struct drm_device *)p); \
2491	else \
2492		BUILD_BUG(); \
2493	__p; \
2494})
2495#define INTEL_INFO(p) 	(&__I915__(p)->info)
2496#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2497#define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
2498
2499#define REVID_FOREVER		0xff
2500/*
2501 * Return true if revision is in range [since,until] inclusive.
2502 *
2503 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2504 */
2505#define IS_REVID(p, since, until) \
2506	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2507
2508#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
2509#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2510#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2511#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2512#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2513#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
2514#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2515#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
2516#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
2517#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2518#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2519#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2520#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
2521#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2522#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
2523#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2524#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2525#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2526#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
2527				 INTEL_DEVID(dev) == 0x0152 || \
2528				 INTEL_DEVID(dev) == 0x015a)
2529#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2530#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2531#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2532#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2533#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2534#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2535#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2536#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2537#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2538				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2539#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2540				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2541				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2542				 (INTEL_DEVID(dev) & 0xf) == 0xe))
2543/* ULX machines are also considered ULT. */
2544#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
2545				 (INTEL_DEVID(dev) & 0xf) == 0xe)
2546#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
2547				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2548#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2549				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2550#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2551				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2552/* ULX machines are also considered ULT. */
2553#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
2554				 INTEL_DEVID(dev) == 0x0A1E)
2555#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
2556				 INTEL_DEVID(dev) == 0x1913 || \
2557				 INTEL_DEVID(dev) == 0x1916 || \
2558				 INTEL_DEVID(dev) == 0x1921 || \
2559				 INTEL_DEVID(dev) == 0x1926)
2560#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
2561				 INTEL_DEVID(dev) == 0x1915 || \
2562				 INTEL_DEVID(dev) == 0x191E)
2563#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
2564				 INTEL_DEVID(dev) == 0x5913 || \
2565				 INTEL_DEVID(dev) == 0x5916 || \
2566				 INTEL_DEVID(dev) == 0x5921 || \
2567				 INTEL_DEVID(dev) == 0x5926)
2568#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
2569				 INTEL_DEVID(dev) == 0x5915 || \
2570				 INTEL_DEVID(dev) == 0x591E)
2571#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
2572				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2573#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
2574				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2575
2576#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2577
2578#define SKL_REVID_A0		0x0
2579#define SKL_REVID_B0		0x1
2580#define SKL_REVID_C0		0x2
2581#define SKL_REVID_D0		0x3
2582#define SKL_REVID_E0		0x4
2583#define SKL_REVID_F0		0x5
2584
2585#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2586
2587#define BXT_REVID_A0		0x0
2588#define BXT_REVID_A1		0x1
2589#define BXT_REVID_B0		0x3
2590#define BXT_REVID_C0		0x9
2591
2592#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
 
 
2593
2594/*
2595 * The genX designation typically refers to the render engine, so render
2596 * capability related checks should use IS_GEN, while display and other checks
2597 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2598 * chips, etc.).
2599 */
2600#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
2601#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
2602#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
2603#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
2604#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2605#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
2606#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2607#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
2608
2609#define RENDER_RING		(1<<RCS)
2610#define BSD_RING		(1<<VCS)
2611#define BLT_RING		(1<<BCS)
2612#define VEBOX_RING		(1<<VECS)
2613#define BSD2_RING		(1<<VCS2)
2614#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2615#define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2616#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
2617#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2618#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
2619#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2620				 __I915__(dev)->ellc_size)
2621#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
2622
2623#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2624#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2625#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2626#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
2627#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2628
2629#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2630#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
2631
2632/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2633#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2634
2635/* WaRsDisableCoarsePowerGating:skl,bxt */
2636#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2637						 IS_SKL_GT3(dev) || \
2638						 IS_SKL_GT4(dev))
2639
2640/*
2641 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2642 * even when in MSI mode. This results in spurious interrupt warnings if the
2643 * legacy irq no. is shared with another device. The kernel then disables that
2644 * interrupt source and so prevents the other device from working properly.
2645 */
2646#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2647#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2648
2649/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2650 * rows, which changed the alignment requirements and fence programming.
2651 */
2652#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2653						      IS_I915GM(dev)))
2654#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
2655#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
2656
2657#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2658#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2659#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2660
2661#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2662
2663#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2664				 INTEL_INFO(dev)->gen >= 9)
2665
2666#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2667#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2668#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2669				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2670				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2671#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
2672				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2673				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2674				 IS_KABYLAKE(dev))
2675#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
2676#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2677
2678#define HAS_CSR(dev)	(IS_GEN9(dev))
2679
2680#define HAS_GUC_UCODE(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
2681#define HAS_GUC_SCHED(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
2682
2683#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2684				    INTEL_INFO(dev)->gen >= 8)
2685
2686#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2687				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2688				 !IS_BROXTON(dev))
2689
2690#define INTEL_PCH_DEVICE_ID_MASK		0xff00
2691#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
2692#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
2693#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
2694#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
2695#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2696#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
2697#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2698#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2699#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2700
2701#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2702#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2703#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2704#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2705#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2706#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2707#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2708#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2709#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2710
2711#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2712			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2713
2714/* DPF == dynamic parity feature */
2715#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2716#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
 
2717
2718#define GT_FREQUENCY_MULTIPLIER 50
2719#define GEN9_FREQ_SCALER 3
2720
2721#include "i915_trace.h"
2722
2723extern const struct drm_ioctl_desc i915_ioctls[];
2724extern int i915_max_ioctl;
2725
2726extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2727extern int i915_resume_switcheroo(struct drm_device *dev);
2728
2729/* i915_dma.c */
2730extern int i915_driver_load(struct drm_device *, unsigned long flags);
2731extern int i915_driver_unload(struct drm_device *);
2732extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2733extern void i915_driver_lastclose(struct drm_device * dev);
2734extern void i915_driver_preclose(struct drm_device *dev,
2735				 struct drm_file *file);
2736extern void i915_driver_postclose(struct drm_device *dev,
2737				  struct drm_file *file);
2738#ifdef CONFIG_COMPAT
2739extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2740			      unsigned long arg);
2741#endif
2742extern int intel_gpu_reset(struct drm_device *dev);
2743extern bool intel_has_gpu_reset(struct drm_device *dev);
2744extern int i915_reset(struct drm_device *dev);
2745extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2746extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2747extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2748extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2749int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2750
2751/* intel_hotplug.c */
2752void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2753void intel_hpd_init(struct drm_i915_private *dev_priv);
2754void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2755void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2756bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2757
2758/* i915_irq.c */
2759void i915_queue_hangcheck(struct drm_device *dev);
2760__printf(3, 4)
2761void i915_handle_error(struct drm_device *dev, bool wedged,
2762		       const char *fmt, ...);
2763
2764extern void intel_irq_init(struct drm_i915_private *dev_priv);
2765int intel_irq_install(struct drm_i915_private *dev_priv);
2766void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2767
2768extern void intel_uncore_sanitize(struct drm_device *dev);
2769extern void intel_uncore_early_sanitize(struct drm_device *dev,
2770					bool restore_forcewake);
2771extern void intel_uncore_init(struct drm_device *dev);
2772extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2773extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2774extern void intel_uncore_fini(struct drm_device *dev);
2775extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2776const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2777void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2778				enum forcewake_domains domains);
2779void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2780				enum forcewake_domains domains);
2781/* Like above but the caller must manage the uncore.lock itself.
2782 * Must be used with I915_READ_FW and friends.
2783 */
2784void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2785					enum forcewake_domains domains);
2786void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2787					enum forcewake_domains domains);
2788void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2789static inline bool intel_vgpu_active(struct drm_device *dev)
2790{
2791	return to_i915(dev)->vgpu.active;
2792}
2793
2794void
2795i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2796		     u32 status_mask);
2797
2798void
2799i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2800		      u32 status_mask);
2801
2802void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2803void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2804void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2805				   uint32_t mask,
2806				   uint32_t bits);
2807void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2808			    uint32_t interrupt_mask,
2809			    uint32_t enabled_irq_mask);
2810static inline void
2811ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2812{
2813	ilk_update_display_irq(dev_priv, bits, bits);
2814}
2815static inline void
2816ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2817{
2818	ilk_update_display_irq(dev_priv, bits, 0);
2819}
2820void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2821			 enum pipe pipe,
2822			 uint32_t interrupt_mask,
2823			 uint32_t enabled_irq_mask);
2824static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2825				       enum pipe pipe, uint32_t bits)
2826{
2827	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2828}
2829static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2830					enum pipe pipe, uint32_t bits)
2831{
2832	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2833}
2834void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2835				  uint32_t interrupt_mask,
2836				  uint32_t enabled_irq_mask);
2837static inline void
2838ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2839{
2840	ibx_display_interrupt_update(dev_priv, bits, bits);
2841}
2842static inline void
2843ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2844{
2845	ibx_display_interrupt_update(dev_priv, bits, 0);
2846}
2847
2848
2849/* i915_gem.c */
2850int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2851			  struct drm_file *file_priv);
2852int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2853			 struct drm_file *file_priv);
2854int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2855			  struct drm_file *file_priv);
2856int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2857			struct drm_file *file_priv);
2858int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2859			struct drm_file *file_priv);
2860int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2861			      struct drm_file *file_priv);
2862int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2863			     struct drm_file *file_priv);
2864void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2865					struct drm_i915_gem_request *req);
2866void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2867int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2868				   struct drm_i915_gem_execbuffer2 *args,
2869				   struct list_head *vmas);
2870int i915_gem_execbuffer(struct drm_device *dev, void *data,
2871			struct drm_file *file_priv);
2872int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2873			 struct drm_file *file_priv);
2874int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2875			struct drm_file *file_priv);
2876int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2877			       struct drm_file *file);
2878int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2879			       struct drm_file *file);
2880int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2881			    struct drm_file *file_priv);
2882int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2883			   struct drm_file *file_priv);
2884int i915_gem_set_tiling(struct drm_device *dev, void *data,
2885			struct drm_file *file_priv);
2886int i915_gem_get_tiling(struct drm_device *dev, void *data,
2887			struct drm_file *file_priv);
2888int i915_gem_init_userptr(struct drm_device *dev);
2889int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2890			   struct drm_file *file);
2891int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2892				struct drm_file *file_priv);
2893int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2894			struct drm_file *file_priv);
2895void i915_gem_load_init(struct drm_device *dev);
2896void i915_gem_load_cleanup(struct drm_device *dev);
2897void *i915_gem_object_alloc(struct drm_device *dev);
2898void i915_gem_object_free(struct drm_i915_gem_object *obj);
2899void i915_gem_object_init(struct drm_i915_gem_object *obj,
2900			 const struct drm_i915_gem_object_ops *ops);
2901struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2902						  size_t size);
2903struct drm_i915_gem_object *i915_gem_object_create_from_data(
2904		struct drm_device *dev, const void *data, size_t size);
2905void i915_gem_free_object(struct drm_gem_object *obj);
2906void i915_gem_vma_destroy(struct i915_vma *vma);
2907
2908/* Flags used by pin/bind&friends. */
2909#define PIN_MAPPABLE	(1<<0)
2910#define PIN_NONBLOCK	(1<<1)
2911#define PIN_GLOBAL	(1<<2)
2912#define PIN_OFFSET_BIAS	(1<<3)
2913#define PIN_USER	(1<<4)
2914#define PIN_UPDATE	(1<<5)
2915#define PIN_ZONE_4G	(1<<6)
2916#define PIN_HIGH	(1<<7)
2917#define PIN_OFFSET_FIXED	(1<<8)
2918#define PIN_OFFSET_MASK (~4095)
2919int __must_check
2920i915_gem_object_pin(struct drm_i915_gem_object *obj,
2921		    struct i915_address_space *vm,
2922		    uint32_t alignment,
2923		    uint64_t flags);
2924int __must_check
2925i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2926			 const struct i915_ggtt_view *view,
2927			 uint32_t alignment,
2928			 uint64_t flags);
2929
2930int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2931		  u32 flags);
2932void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2933int __must_check i915_vma_unbind(struct i915_vma *vma);
2934/*
2935 * BEWARE: Do not use the function below unless you can _absolutely_
2936 * _guarantee_ VMA in question is _not in use_ anywhere.
2937 */
2938int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2939int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2940void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2941void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2942
2943int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2944				    int *needs_clflush);
2945
2946int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2947
2948static inline int __sg_page_count(struct scatterlist *sg)
2949{
2950	return sg->length >> PAGE_SHIFT;
2951}
2952
2953struct page *
2954i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2955
2956static inline struct page *
2957i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2958{
2959	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2960		return NULL;
2961
2962	if (n < obj->get_page.last) {
2963		obj->get_page.sg = obj->pages->sgl;
2964		obj->get_page.last = 0;
2965	}
2966
2967	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2968		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2969		if (unlikely(sg_is_chain(obj->get_page.sg)))
2970			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2971	}
2972
2973	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2974}
2975
2976static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2977{
2978	BUG_ON(obj->pages == NULL);
2979	obj->pages_pin_count++;
2980}
2981static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2982{
2983	BUG_ON(obj->pages_pin_count == 0);
2984	obj->pages_pin_count--;
2985}
2986
2987int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2988int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2989			 struct intel_engine_cs *to,
2990			 struct drm_i915_gem_request **to_req);
2991void i915_vma_move_to_active(struct i915_vma *vma,
2992			     struct drm_i915_gem_request *req);
2993int i915_gem_dumb_create(struct drm_file *file_priv,
2994			 struct drm_device *dev,
2995			 struct drm_mode_create_dumb *args);
2996int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2997		      uint32_t handle, uint64_t *offset);
2998/**
2999 * Returns true if seq1 is later than seq2.
3000 */
3001static inline bool
3002i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3003{
3004	return (int32_t)(seq1 - seq2) >= 0;
3005}
3006
3007static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3008					   bool lazy_coherency)
3009{
3010	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3011	return i915_seqno_passed(seqno, req->previous_seqno);
3012}
3013
3014static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3015					      bool lazy_coherency)
3016{
3017	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3018	return i915_seqno_passed(seqno, req->seqno);
3019}
3020
3021int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3022int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3023
3024struct drm_i915_gem_request *
3025i915_gem_find_active_request(struct intel_engine_cs *ring);
3026
3027bool i915_gem_retire_requests(struct drm_device *dev);
3028void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3029int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3030				      bool interruptible);
3031
3032static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3033{
3034	return unlikely(atomic_read(&error->reset_counter)
3035			& (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3036}
3037
3038static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3039{
3040	return atomic_read(&error->reset_counter) & I915_WEDGED;
3041}
3042
3043static inline u32 i915_reset_count(struct i915_gpu_error *error)
3044{
3045	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3046}
3047
3048static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3049{
3050	return dev_priv->gpu_error.stop_rings == 0 ||
3051		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3052}
3053
3054static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3055{
3056	return dev_priv->gpu_error.stop_rings == 0 ||
3057		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3058}
3059
3060void i915_gem_reset(struct drm_device *dev);
3061bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3062int __must_check i915_gem_init(struct drm_device *dev);
3063int i915_gem_init_rings(struct drm_device *dev);
3064int __must_check i915_gem_init_hw(struct drm_device *dev);
3065int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3066void i915_gem_init_swizzling(struct drm_device *dev);
3067void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3068int __must_check i915_gpu_idle(struct drm_device *dev);
3069int __must_check i915_gem_suspend(struct drm_device *dev);
3070void __i915_add_request(struct drm_i915_gem_request *req,
3071			struct drm_i915_gem_object *batch_obj,
3072			bool flush_caches);
3073#define i915_add_request(req) \
3074	__i915_add_request(req, NULL, true)
3075#define i915_add_request_no_flush(req) \
3076	__i915_add_request(req, NULL, false)
3077int __i915_wait_request(struct drm_i915_gem_request *req,
3078			unsigned reset_counter,
3079			bool interruptible,
3080			s64 *timeout,
3081			struct intel_rps_client *rps);
3082int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3083int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3084int __must_check
3085i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3086			       bool readonly);
3087int __must_check
3088i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3089				  bool write);
3090int __must_check
3091i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3092int __must_check
3093i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3094				     u32 alignment,
3095				     const struct i915_ggtt_view *view);
3096void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3097					      const struct i915_ggtt_view *view);
3098int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3099				int align);
3100int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3101void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3102
3103uint32_t
3104i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3105uint32_t
3106i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3107			    int tiling_mode, bool fenced);
3108
3109int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3110				    enum i915_cache_level cache_level);
3111
3112struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3113				struct dma_buf *dma_buf);
3114
3115struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3116				struct drm_gem_object *gem_obj, int flags);
3117
3118u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3119				  const struct i915_ggtt_view *view);
3120u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3121			struct i915_address_space *vm);
3122static inline u64
3123i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3124{
3125	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3126}
3127
3128bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3129bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3130				  const struct i915_ggtt_view *view);
3131bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3132			struct i915_address_space *vm);
3133
3134unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3135				struct i915_address_space *vm);
3136struct i915_vma *
3137i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3138		    struct i915_address_space *vm);
3139struct i915_vma *
3140i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3141			  const struct i915_ggtt_view *view);
3142
3143struct i915_vma *
3144i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3145				  struct i915_address_space *vm);
3146struct i915_vma *
3147i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3148				       const struct i915_ggtt_view *view);
3149
3150static inline struct i915_vma *
3151i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3152{
3153	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3154}
3155bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3156
3157/* Some GGTT VM helpers */
3158#define i915_obj_to_ggtt(obj) \
3159	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3160
3161static inline struct i915_hw_ppgtt *
3162i915_vm_to_ppgtt(struct i915_address_space *vm)
3163{
3164	WARN_ON(i915_is_ggtt(vm));
3165	return container_of(vm, struct i915_hw_ppgtt, base);
3166}
3167
3168
3169static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3170{
3171	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3172}
3173
3174static inline unsigned long
3175i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3176{
3177	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3178}
3179
3180static inline int __must_check
3181i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3182		      uint32_t alignment,
3183		      unsigned flags)
3184{
3185	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3186				   alignment, flags | PIN_GLOBAL);
3187}
3188
3189static inline int
3190i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3191{
3192	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3193}
3194
3195void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3196				     const struct i915_ggtt_view *view);
3197static inline void
3198i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3199{
3200	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3201}
3202
3203/* i915_gem_fence.c */
3204int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3205int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3206
3207bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3208void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3209
3210void i915_gem_restore_fences(struct drm_device *dev);
3211
3212void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3213void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3214void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3215
3216/* i915_gem_context.c */
3217int __must_check i915_gem_context_init(struct drm_device *dev);
3218void i915_gem_context_fini(struct drm_device *dev);
3219void i915_gem_context_reset(struct drm_device *dev);
3220int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3221int i915_gem_context_enable(struct drm_i915_gem_request *req);
3222void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3223int i915_switch_context(struct drm_i915_gem_request *req);
3224struct intel_context *
3225i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3226void i915_gem_context_free(struct kref *ctx_ref);
3227struct drm_i915_gem_object *
3228i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3229static inline void i915_gem_context_reference(struct intel_context *ctx)
3230{
3231	kref_get(&ctx->ref);
3232}
3233
3234static inline void i915_gem_context_unreference(struct intel_context *ctx)
3235{
3236	kref_put(&ctx->ref, i915_gem_context_free);
3237}
3238
3239static inline bool i915_gem_context_is_default(const struct intel_context *c)
3240{
3241	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3242}
3243
3244int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3245				  struct drm_file *file);
3246int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3247				   struct drm_file *file);
3248int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3249				    struct drm_file *file_priv);
3250int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3251				    struct drm_file *file_priv);
3252
3253/* i915_gem_evict.c */
3254int __must_check i915_gem_evict_something(struct drm_device *dev,
3255					  struct i915_address_space *vm,
3256					  int min_size,
3257					  unsigned alignment,
3258					  unsigned cache_level,
3259					  unsigned long start,
3260					  unsigned long end,
3261					  unsigned flags);
3262int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3263int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3264
3265/* belongs in i915_gem_gtt.h */
3266static inline void i915_gem_chipset_flush(struct drm_device *dev)
3267{
3268	if (INTEL_INFO(dev)->gen < 6)
3269		intel_gtt_chipset_flush();
3270}
3271
3272/* i915_gem_stolen.c */
3273int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3274				struct drm_mm_node *node, u64 size,
3275				unsigned alignment);
3276int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3277					 struct drm_mm_node *node, u64 size,
3278					 unsigned alignment, u64 start,
3279					 u64 end);
3280void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3281				 struct drm_mm_node *node);
3282int i915_gem_init_stolen(struct drm_device *dev);
3283void i915_gem_cleanup_stolen(struct drm_device *dev);
3284struct drm_i915_gem_object *
3285i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3286struct drm_i915_gem_object *
3287i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3288					       u32 stolen_offset,
3289					       u32 gtt_offset,
3290					       u32 size);
3291
3292/* i915_gem_shrinker.c */
3293unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3294			      unsigned long target,
3295			      unsigned flags);
3296#define I915_SHRINK_PURGEABLE 0x1
3297#define I915_SHRINK_UNBOUND 0x2
3298#define I915_SHRINK_BOUND 0x4
3299#define I915_SHRINK_ACTIVE 0x8
3300unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3301void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3302void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3303
3304
3305/* i915_gem_tiling.c */
3306static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3307{
3308	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3309
3310	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3311		obj->tiling_mode != I915_TILING_NONE;
3312}
3313
3314/* i915_gem_debug.c */
3315#if WATCH_LISTS
3316int i915_verify_lists(struct drm_device *dev);
3317#else
3318#define i915_verify_lists(dev) 0
3319#endif
3320
3321/* i915_debugfs.c */
3322int i915_debugfs_init(struct drm_minor *minor);
3323void i915_debugfs_cleanup(struct drm_minor *minor);
3324#ifdef CONFIG_DEBUG_FS
3325int i915_debugfs_connector_add(struct drm_connector *connector);
3326void intel_display_crc_init(struct drm_device *dev);
3327#else
3328static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3329{ return 0; }
3330static inline void intel_display_crc_init(struct drm_device *dev) {}
3331#endif
3332
3333/* i915_gpu_error.c */
3334__printf(2, 3)
3335void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3336int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3337			    const struct i915_error_state_file_priv *error);
3338int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3339			      struct drm_i915_private *i915,
3340			      size_t count, loff_t pos);
3341static inline void i915_error_state_buf_release(
3342	struct drm_i915_error_state_buf *eb)
3343{
3344	kfree(eb->buf);
3345}
3346void i915_capture_error_state(struct drm_device *dev, bool wedge,
3347			      const char *error_msg);
3348void i915_error_state_get(struct drm_device *dev,
3349			  struct i915_error_state_file_priv *error_priv);
3350void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3351void i915_destroy_error_state(struct drm_device *dev);
3352
3353void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3354const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3355
3356/* i915_cmd_parser.c */
3357int i915_cmd_parser_get_version(void);
3358int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3359void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3360bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3361int i915_parse_cmds(struct intel_engine_cs *ring,
3362		    struct drm_i915_gem_object *batch_obj,
3363		    struct drm_i915_gem_object *shadow_batch_obj,
3364		    u32 batch_start_offset,
3365		    u32 batch_len,
3366		    bool is_master);
3367
3368/* i915_suspend.c */
3369extern int i915_save_state(struct drm_device *dev);
3370extern int i915_restore_state(struct drm_device *dev);
3371
3372/* i915_sysfs.c */
3373void i915_setup_sysfs(struct drm_device *dev_priv);
3374void i915_teardown_sysfs(struct drm_device *dev_priv);
3375
3376/* intel_i2c.c */
3377extern int intel_setup_gmbus(struct drm_device *dev);
3378extern void intel_teardown_gmbus(struct drm_device *dev);
3379extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3380				     unsigned int pin);
3381
3382extern struct i2c_adapter *
3383intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3384extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3385extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3386static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3387{
3388	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3389}
3390extern void intel_i2c_reset(struct drm_device *dev);
3391
3392/* intel_bios.c */
3393int intel_bios_init(struct drm_i915_private *dev_priv);
3394bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3395
3396/* intel_opregion.c */
3397#ifdef CONFIG_ACPI
3398extern int intel_opregion_setup(struct drm_device *dev);
3399extern void intel_opregion_init(struct drm_device *dev);
3400extern void intel_opregion_fini(struct drm_device *dev);
3401extern void intel_opregion_asle_intr(struct drm_device *dev);
3402extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3403					 bool enable);
3404extern int intel_opregion_notify_adapter(struct drm_device *dev,
3405					 pci_power_t state);
3406#else
3407static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3408static inline void intel_opregion_init(struct drm_device *dev) { return; }
3409static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3410static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3411static inline int
3412intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3413{
3414	return 0;
3415}
3416static inline int
3417intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3418{
3419	return 0;
3420}
3421#endif
3422
3423/* intel_acpi.c */
3424#ifdef CONFIG_ACPI
3425extern void intel_register_dsm_handler(void);
3426extern void intel_unregister_dsm_handler(void);
3427#else
3428static inline void intel_register_dsm_handler(void) { return; }
3429static inline void intel_unregister_dsm_handler(void) { return; }
3430#endif /* CONFIG_ACPI */
3431
3432/* modesetting */
3433extern void intel_modeset_init_hw(struct drm_device *dev);
3434extern void intel_modeset_init(struct drm_device *dev);
3435extern void intel_modeset_gem_init(struct drm_device *dev);
3436extern void intel_modeset_cleanup(struct drm_device *dev);
3437extern void intel_connector_unregister(struct intel_connector *);
3438extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3439extern void intel_display_resume(struct drm_device *dev);
3440extern void i915_redisable_vga(struct drm_device *dev);
3441extern void i915_redisable_vga_power_on(struct drm_device *dev);
3442extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3443extern void intel_init_pch_refclk(struct drm_device *dev);
3444extern void intel_set_rps(struct drm_device *dev, u8 val);
3445extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3446				  bool enable);
3447extern void intel_detect_pch(struct drm_device *dev);
3448extern int intel_enable_rc6(const struct drm_device *dev);
3449
3450extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3451int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3452			struct drm_file *file);
3453int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3454			       struct drm_file *file);
3455
3456/* overlay */
3457extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3458extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3459					    struct intel_overlay_error_state *error);
3460
3461extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3462extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3463					    struct drm_device *dev,
3464					    struct intel_display_error_state *error);
3465
3466int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3467int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3468
3469/* intel_sideband.c */
3470u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3471void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3472u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3473u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3474void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3475u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3476void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3477u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3478void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3479u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3480void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3481u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3482void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3483u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3484		   enum intel_sbi_destination destination);
3485void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3486		     enum intel_sbi_destination destination);
3487u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3488void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3489
3490int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3491int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3492
3493#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3494#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3495
3496#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3497#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3498#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3499#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3500
3501#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3502#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3503#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3504#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3505
3506/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3507 * will be implemented using 2 32-bit writes in an arbitrary order with
3508 * an arbitrary delay between them. This can cause the hardware to
3509 * act upon the intermediate value, possibly leading to corruption and
3510 * machine death. You have been warned.
3511 */
3512#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3513#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3514
3515#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3516	u32 upper, lower, old_upper, loop = 0;				\
3517	upper = I915_READ(upper_reg);					\
3518	do {								\
3519		old_upper = upper;					\
3520		lower = I915_READ(lower_reg);				\
3521		upper = I915_READ(upper_reg);				\
3522	} while (upper != old_upper && loop++ < 2);			\
3523	(u64)upper << 32 | lower; })
3524
3525#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
3526#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)
3527
3528#define __raw_read(x, s) \
3529static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3530					     i915_reg_t reg) \
3531{ \
3532	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3533}
3534
3535#define __raw_write(x, s) \
3536static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3537				       i915_reg_t reg, uint##x##_t val) \
3538{ \
3539	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3540}
3541__raw_read(8, b)
3542__raw_read(16, w)
3543__raw_read(32, l)
3544__raw_read(64, q)
3545
3546__raw_write(8, b)
3547__raw_write(16, w)
3548__raw_write(32, l)
3549__raw_write(64, q)
3550
3551#undef __raw_read
3552#undef __raw_write
3553
3554/* These are untraced mmio-accessors that are only valid to be used inside
3555 * criticial sections inside IRQ handlers where forcewake is explicitly
3556 * controlled.
3557 * Think twice, and think again, before using these.
3558 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3559 * intel_uncore_forcewake_irqunlock().
3560 */
3561#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3562#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3563#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3564
3565/* "Broadcast RGB" property */
3566#define INTEL_BROADCAST_RGB_AUTO 0
3567#define INTEL_BROADCAST_RGB_FULL 1
3568#define INTEL_BROADCAST_RGB_LIMITED 2
3569
3570static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3571{
3572	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3573		return VLV_VGACNTRL;
3574	else if (INTEL_INFO(dev)->gen >= 5)
3575		return CPU_VGACNTRL;
3576	else
3577		return VGACNTRL;
3578}
3579
3580static inline void __user *to_user_ptr(u64 address)
3581{
3582	return (void __user *)(uintptr_t)address;
3583}
3584
3585static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3586{
3587	unsigned long j = msecs_to_jiffies(m);
 
 
3588
3589	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3590}
3591
3592static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3593{
3594        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3595}
3596
3597static inline unsigned long
3598timespec_to_jiffies_timeout(const struct timespec *value)
3599{
3600	unsigned long j = timespec_to_jiffies(value);
3601
3602	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3603}
3604
3605/*
3606 * If you need to wait X milliseconds between events A and B, but event B
3607 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3608 * when event A happened, then just before event B you call this function and
3609 * pass the timestamp as the first argument, and X as the second argument.
3610 */
3611static inline void
3612wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3613{
3614	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3615
3616	/*
3617	 * Don't re-read the value of "jiffies" every time since it may change
3618	 * behind our back and break the math.
3619	 */
3620	tmp_jiffies = jiffies;
3621	target_jiffies = timestamp_jiffies +
3622			 msecs_to_jiffies_timeout(to_wait_ms);
3623
3624	if (time_after(target_jiffies, tmp_jiffies)) {
3625		remaining_jiffies = target_jiffies - tmp_jiffies;
3626		while (remaining_jiffies)
3627			remaining_jiffies =
3628			    schedule_timeout_uninterruptible(remaining_jiffies);
3629	}
3630}
3631
3632static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3633				      struct drm_i915_gem_request *req)
 
3634{
3635	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3636		i915_gem_request_assign(&ring->trace_irq_req, req);
3637}
3638
3639#endif