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1/**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 **************************************************************************/
18#include <drm/drmP.h>
19#include "psb_drv.h"
20#include "psb_reg.h"
21#include "mmu.h"
22
23/*
24 * Code for the SGX MMU:
25 */
26
27/*
28 * clflush on one processor only:
29 * clflush should apparently flush the cache line on all processors in an
30 * SMP system.
31 */
32
33/*
34 * kmap atomic:
35 * The usage of the slots must be completely encapsulated within a spinlock, and
36 * no other functions that may be using the locks for other purposed may be
37 * called from within the locked region.
38 * Since the slots are per processor, this will guarantee that we are the only
39 * user.
40 */
41
42/*
43 * TODO: Inserting ptes from an interrupt handler:
44 * This may be desirable for some SGX functionality where the GPU can fault in
45 * needed pages. For that, we need to make an atomic insert_pages function, that
46 * may fail.
47 * If it fails, the caller need to insert the page using a workqueue function,
48 * but on average it should be fast.
49 */
50
51static inline uint32_t psb_mmu_pt_index(uint32_t offset)
52{
53 return (offset >> PSB_PTE_SHIFT) & 0x3FF;
54}
55
56static inline uint32_t psb_mmu_pd_index(uint32_t offset)
57{
58 return offset >> PSB_PDE_SHIFT;
59}
60
61#if defined(CONFIG_X86)
62static inline void psb_clflush(void *addr)
63{
64 __asm__ __volatile__("clflush (%0)\n" : : "r"(addr) : "memory");
65}
66
67static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
68{
69 if (!driver->has_clflush)
70 return;
71
72 mb();
73 psb_clflush(addr);
74 mb();
75}
76#else
77
78static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
79{;
80}
81
82#endif
83
84static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
85{
86 struct drm_device *dev = driver->dev;
87 struct drm_psb_private *dev_priv = dev->dev_private;
88
89 if (atomic_read(&driver->needs_tlbflush) || force) {
90 uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL);
91 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
92
93 /* Make sure data cache is turned off before enabling it */
94 wmb();
95 PSB_WSGX32(val & ~_PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
96 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
97 if (driver->msvdx_mmu_invaldc)
98 atomic_set(driver->msvdx_mmu_invaldc, 1);
99 }
100 atomic_set(&driver->needs_tlbflush, 0);
101}
102
103#if 0
104static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
105{
106 down_write(&driver->sem);
107 psb_mmu_flush_pd_locked(driver, force);
108 up_write(&driver->sem);
109}
110#endif
111
112void psb_mmu_flush(struct psb_mmu_driver *driver)
113{
114 struct drm_device *dev = driver->dev;
115 struct drm_psb_private *dev_priv = dev->dev_private;
116 uint32_t val;
117
118 down_write(&driver->sem);
119 val = PSB_RSGX32(PSB_CR_BIF_CTRL);
120 if (atomic_read(&driver->needs_tlbflush))
121 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
122 else
123 PSB_WSGX32(val | _PSB_CB_CTRL_FLUSH, PSB_CR_BIF_CTRL);
124
125 /* Make sure data cache is turned off and MMU is flushed before
126 restoring bank interface control register */
127 wmb();
128 PSB_WSGX32(val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
129 PSB_CR_BIF_CTRL);
130 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
131
132 atomic_set(&driver->needs_tlbflush, 0);
133 if (driver->msvdx_mmu_invaldc)
134 atomic_set(driver->msvdx_mmu_invaldc, 1);
135 up_write(&driver->sem);
136}
137
138void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
139{
140 struct drm_device *dev = pd->driver->dev;
141 struct drm_psb_private *dev_priv = dev->dev_private;
142 uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
143 PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
144
145 down_write(&pd->driver->sem);
146 PSB_WSGX32(page_to_pfn(pd->p) << PAGE_SHIFT, offset);
147 wmb();
148 psb_mmu_flush_pd_locked(pd->driver, 1);
149 pd->hw_context = hw_context;
150 up_write(&pd->driver->sem);
151
152}
153
154static inline unsigned long psb_pd_addr_end(unsigned long addr,
155 unsigned long end)
156{
157 addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
158 return (addr < end) ? addr : end;
159}
160
161static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
162{
163 uint32_t mask = PSB_PTE_VALID;
164
165 if (type & PSB_MMU_CACHED_MEMORY)
166 mask |= PSB_PTE_CACHED;
167 if (type & PSB_MMU_RO_MEMORY)
168 mask |= PSB_PTE_RO;
169 if (type & PSB_MMU_WO_MEMORY)
170 mask |= PSB_PTE_WO;
171
172 return (pfn << PAGE_SHIFT) | mask;
173}
174
175struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
176 int trap_pagefaults, int invalid_type)
177{
178 struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
179 uint32_t *v;
180 int i;
181
182 if (!pd)
183 return NULL;
184
185 pd->p = alloc_page(GFP_DMA32);
186 if (!pd->p)
187 goto out_err1;
188 pd->dummy_pt = alloc_page(GFP_DMA32);
189 if (!pd->dummy_pt)
190 goto out_err2;
191 pd->dummy_page = alloc_page(GFP_DMA32);
192 if (!pd->dummy_page)
193 goto out_err3;
194
195 if (!trap_pagefaults) {
196 pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
197 invalid_type);
198 pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
199 invalid_type);
200 } else {
201 pd->invalid_pde = 0;
202 pd->invalid_pte = 0;
203 }
204
205 v = kmap(pd->dummy_pt);
206 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
207 v[i] = pd->invalid_pte;
208
209 kunmap(pd->dummy_pt);
210
211 v = kmap(pd->p);
212 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
213 v[i] = pd->invalid_pde;
214
215 kunmap(pd->p);
216
217 clear_page(kmap(pd->dummy_page));
218 kunmap(pd->dummy_page);
219
220 pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
221 if (!pd->tables)
222 goto out_err4;
223
224 pd->hw_context = -1;
225 pd->pd_mask = PSB_PTE_VALID;
226 pd->driver = driver;
227
228 return pd;
229
230out_err4:
231 __free_page(pd->dummy_page);
232out_err3:
233 __free_page(pd->dummy_pt);
234out_err2:
235 __free_page(pd->p);
236out_err1:
237 kfree(pd);
238 return NULL;
239}
240
241static void psb_mmu_free_pt(struct psb_mmu_pt *pt)
242{
243 __free_page(pt->p);
244 kfree(pt);
245}
246
247void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
248{
249 struct psb_mmu_driver *driver = pd->driver;
250 struct drm_device *dev = driver->dev;
251 struct drm_psb_private *dev_priv = dev->dev_private;
252 struct psb_mmu_pt *pt;
253 int i;
254
255 down_write(&driver->sem);
256 if (pd->hw_context != -1) {
257 PSB_WSGX32(0, PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
258 psb_mmu_flush_pd_locked(driver, 1);
259 }
260
261 /* Should take the spinlock here, but we don't need to do that
262 since we have the semaphore in write mode. */
263
264 for (i = 0; i < 1024; ++i) {
265 pt = pd->tables[i];
266 if (pt)
267 psb_mmu_free_pt(pt);
268 }
269
270 vfree(pd->tables);
271 __free_page(pd->dummy_page);
272 __free_page(pd->dummy_pt);
273 __free_page(pd->p);
274 kfree(pd);
275 up_write(&driver->sem);
276}
277
278static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
279{
280 struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
281 void *v;
282 uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
283 uint32_t clflush_count = PAGE_SIZE / clflush_add;
284 spinlock_t *lock = &pd->driver->lock;
285 uint8_t *clf;
286 uint32_t *ptes;
287 int i;
288
289 if (!pt)
290 return NULL;
291
292 pt->p = alloc_page(GFP_DMA32);
293 if (!pt->p) {
294 kfree(pt);
295 return NULL;
296 }
297
298 spin_lock(lock);
299
300 v = kmap_atomic(pt->p);
301 clf = (uint8_t *) v;
302 ptes = (uint32_t *) v;
303 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
304 *ptes++ = pd->invalid_pte;
305
306#if defined(CONFIG_X86)
307 if (pd->driver->has_clflush && pd->hw_context != -1) {
308 mb();
309 for (i = 0; i < clflush_count; ++i) {
310 psb_clflush(clf);
311 clf += clflush_add;
312 }
313 mb();
314 }
315#endif
316 kunmap_atomic(v);
317 spin_unlock(lock);
318
319 pt->count = 0;
320 pt->pd = pd;
321 pt->index = 0;
322
323 return pt;
324}
325
326struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
327 unsigned long addr)
328{
329 uint32_t index = psb_mmu_pd_index(addr);
330 struct psb_mmu_pt *pt;
331 uint32_t *v;
332 spinlock_t *lock = &pd->driver->lock;
333
334 spin_lock(lock);
335 pt = pd->tables[index];
336 while (!pt) {
337 spin_unlock(lock);
338 pt = psb_mmu_alloc_pt(pd);
339 if (!pt)
340 return NULL;
341 spin_lock(lock);
342
343 if (pd->tables[index]) {
344 spin_unlock(lock);
345 psb_mmu_free_pt(pt);
346 spin_lock(lock);
347 pt = pd->tables[index];
348 continue;
349 }
350
351 v = kmap_atomic(pd->p);
352 pd->tables[index] = pt;
353 v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
354 pt->index = index;
355 kunmap_atomic((void *) v);
356
357 if (pd->hw_context != -1) {
358 psb_mmu_clflush(pd->driver, (void *)&v[index]);
359 atomic_set(&pd->driver->needs_tlbflush, 1);
360 }
361 }
362 pt->v = kmap_atomic(pt->p);
363 return pt;
364}
365
366static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
367 unsigned long addr)
368{
369 uint32_t index = psb_mmu_pd_index(addr);
370 struct psb_mmu_pt *pt;
371 spinlock_t *lock = &pd->driver->lock;
372
373 spin_lock(lock);
374 pt = pd->tables[index];
375 if (!pt) {
376 spin_unlock(lock);
377 return NULL;
378 }
379 pt->v = kmap_atomic(pt->p);
380 return pt;
381}
382
383static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
384{
385 struct psb_mmu_pd *pd = pt->pd;
386 uint32_t *v;
387
388 kunmap_atomic(pt->v);
389 if (pt->count == 0) {
390 v = kmap_atomic(pd->p);
391 v[pt->index] = pd->invalid_pde;
392 pd->tables[pt->index] = NULL;
393
394 if (pd->hw_context != -1) {
395 psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
396 atomic_set(&pd->driver->needs_tlbflush, 1);
397 }
398 kunmap_atomic(pt->v);
399 spin_unlock(&pd->driver->lock);
400 psb_mmu_free_pt(pt);
401 return;
402 }
403 spin_unlock(&pd->driver->lock);
404}
405
406static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
407 uint32_t pte)
408{
409 pt->v[psb_mmu_pt_index(addr)] = pte;
410}
411
412static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
413 unsigned long addr)
414{
415 pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
416}
417
418struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
419{
420 struct psb_mmu_pd *pd;
421
422 down_read(&driver->sem);
423 pd = driver->default_pd;
424 up_read(&driver->sem);
425
426 return pd;
427}
428
429/* Returns the physical address of the PD shared by sgx/msvdx */
430uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver)
431{
432 struct psb_mmu_pd *pd;
433
434 pd = psb_mmu_get_default_pd(driver);
435 return page_to_pfn(pd->p) << PAGE_SHIFT;
436}
437
438void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
439{
440 struct drm_device *dev = driver->dev;
441 struct drm_psb_private *dev_priv = dev->dev_private;
442
443 PSB_WSGX32(driver->bif_ctrl, PSB_CR_BIF_CTRL);
444 psb_mmu_free_pagedir(driver->default_pd);
445 kfree(driver);
446}
447
448struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev,
449 int trap_pagefaults,
450 int invalid_type,
451 atomic_t *msvdx_mmu_invaldc)
452{
453 struct psb_mmu_driver *driver;
454 struct drm_psb_private *dev_priv = dev->dev_private;
455
456 driver = kmalloc(sizeof(*driver), GFP_KERNEL);
457
458 if (!driver)
459 return NULL;
460
461 driver->dev = dev;
462 driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
463 invalid_type);
464 if (!driver->default_pd)
465 goto out_err1;
466
467 spin_lock_init(&driver->lock);
468 init_rwsem(&driver->sem);
469 down_write(&driver->sem);
470 atomic_set(&driver->needs_tlbflush, 1);
471 driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
472
473 driver->bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
474 PSB_WSGX32(driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
475 PSB_CR_BIF_CTRL);
476 PSB_WSGX32(driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
477 PSB_CR_BIF_CTRL);
478
479 driver->has_clflush = 0;
480
481#if defined(CONFIG_X86)
482 if (boot_cpu_has(X86_FEATURE_CLFLUSH)) {
483 uint32_t tfms, misc, cap0, cap4, clflush_size;
484
485 /*
486 * clflush size is determined at kernel setup for x86_64 but not
487 * for i386. We have to do it here.
488 */
489
490 cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
491 clflush_size = ((misc >> 8) & 0xff) * 8;
492 driver->has_clflush = 1;
493 driver->clflush_add =
494 PAGE_SIZE * clflush_size / sizeof(uint32_t);
495 driver->clflush_mask = driver->clflush_add - 1;
496 driver->clflush_mask = ~driver->clflush_mask;
497 }
498#endif
499
500 up_write(&driver->sem);
501 return driver;
502
503out_err1:
504 kfree(driver);
505 return NULL;
506}
507
508#if defined(CONFIG_X86)
509static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
510 uint32_t num_pages, uint32_t desired_tile_stride,
511 uint32_t hw_tile_stride)
512{
513 struct psb_mmu_pt *pt;
514 uint32_t rows = 1;
515 uint32_t i;
516 unsigned long addr;
517 unsigned long end;
518 unsigned long next;
519 unsigned long add;
520 unsigned long row_add;
521 unsigned long clflush_add = pd->driver->clflush_add;
522 unsigned long clflush_mask = pd->driver->clflush_mask;
523
524 if (!pd->driver->has_clflush)
525 return;
526
527 if (hw_tile_stride)
528 rows = num_pages / desired_tile_stride;
529 else
530 desired_tile_stride = num_pages;
531
532 add = desired_tile_stride << PAGE_SHIFT;
533 row_add = hw_tile_stride << PAGE_SHIFT;
534 mb();
535 for (i = 0; i < rows; ++i) {
536
537 addr = address;
538 end = addr + add;
539
540 do {
541 next = psb_pd_addr_end(addr, end);
542 pt = psb_mmu_pt_map_lock(pd, addr);
543 if (!pt)
544 continue;
545 do {
546 psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
547 } while (addr += clflush_add,
548 (addr & clflush_mask) < next);
549
550 psb_mmu_pt_unmap_unlock(pt);
551 } while (addr = next, next != end);
552 address += row_add;
553 }
554 mb();
555}
556#else
557static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
558 uint32_t num_pages, uint32_t desired_tile_stride,
559 uint32_t hw_tile_stride)
560{
561 drm_ttm_cache_flush();
562}
563#endif
564
565void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
566 unsigned long address, uint32_t num_pages)
567{
568 struct psb_mmu_pt *pt;
569 unsigned long addr;
570 unsigned long end;
571 unsigned long next;
572 unsigned long f_address = address;
573
574 down_read(&pd->driver->sem);
575
576 addr = address;
577 end = addr + (num_pages << PAGE_SHIFT);
578
579 do {
580 next = psb_pd_addr_end(addr, end);
581 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
582 if (!pt)
583 goto out;
584 do {
585 psb_mmu_invalidate_pte(pt, addr);
586 --pt->count;
587 } while (addr += PAGE_SIZE, addr < next);
588 psb_mmu_pt_unmap_unlock(pt);
589
590 } while (addr = next, next != end);
591
592out:
593 if (pd->hw_context != -1)
594 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
595
596 up_read(&pd->driver->sem);
597
598 if (pd->hw_context != -1)
599 psb_mmu_flush(pd->driver);
600
601 return;
602}
603
604void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
605 uint32_t num_pages, uint32_t desired_tile_stride,
606 uint32_t hw_tile_stride)
607{
608 struct psb_mmu_pt *pt;
609 uint32_t rows = 1;
610 uint32_t i;
611 unsigned long addr;
612 unsigned long end;
613 unsigned long next;
614 unsigned long add;
615 unsigned long row_add;
616 unsigned long f_address = address;
617
618 if (hw_tile_stride)
619 rows = num_pages / desired_tile_stride;
620 else
621 desired_tile_stride = num_pages;
622
623 add = desired_tile_stride << PAGE_SHIFT;
624 row_add = hw_tile_stride << PAGE_SHIFT;
625
626 down_read(&pd->driver->sem);
627
628 /* Make sure we only need to flush this processor's cache */
629
630 for (i = 0; i < rows; ++i) {
631
632 addr = address;
633 end = addr + add;
634
635 do {
636 next = psb_pd_addr_end(addr, end);
637 pt = psb_mmu_pt_map_lock(pd, addr);
638 if (!pt)
639 continue;
640 do {
641 psb_mmu_invalidate_pte(pt, addr);
642 --pt->count;
643
644 } while (addr += PAGE_SIZE, addr < next);
645 psb_mmu_pt_unmap_unlock(pt);
646
647 } while (addr = next, next != end);
648 address += row_add;
649 }
650 if (pd->hw_context != -1)
651 psb_mmu_flush_ptes(pd, f_address, num_pages,
652 desired_tile_stride, hw_tile_stride);
653
654 up_read(&pd->driver->sem);
655
656 if (pd->hw_context != -1)
657 psb_mmu_flush(pd->driver);
658}
659
660int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
661 unsigned long address, uint32_t num_pages,
662 int type)
663{
664 struct psb_mmu_pt *pt;
665 uint32_t pte;
666 unsigned long addr;
667 unsigned long end;
668 unsigned long next;
669 unsigned long f_address = address;
670 int ret = -ENOMEM;
671
672 down_read(&pd->driver->sem);
673
674 addr = address;
675 end = addr + (num_pages << PAGE_SHIFT);
676
677 do {
678 next = psb_pd_addr_end(addr, end);
679 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
680 if (!pt) {
681 ret = -ENOMEM;
682 goto out;
683 }
684 do {
685 pte = psb_mmu_mask_pte(start_pfn++, type);
686 psb_mmu_set_pte(pt, addr, pte);
687 pt->count++;
688 } while (addr += PAGE_SIZE, addr < next);
689 psb_mmu_pt_unmap_unlock(pt);
690
691 } while (addr = next, next != end);
692 ret = 0;
693
694out:
695 if (pd->hw_context != -1)
696 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
697
698 up_read(&pd->driver->sem);
699
700 if (pd->hw_context != -1)
701 psb_mmu_flush(pd->driver);
702
703 return 0;
704}
705
706int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
707 unsigned long address, uint32_t num_pages,
708 uint32_t desired_tile_stride, uint32_t hw_tile_stride,
709 int type)
710{
711 struct psb_mmu_pt *pt;
712 uint32_t rows = 1;
713 uint32_t i;
714 uint32_t pte;
715 unsigned long addr;
716 unsigned long end;
717 unsigned long next;
718 unsigned long add;
719 unsigned long row_add;
720 unsigned long f_address = address;
721 int ret = -ENOMEM;
722
723 if (hw_tile_stride) {
724 if (num_pages % desired_tile_stride != 0)
725 return -EINVAL;
726 rows = num_pages / desired_tile_stride;
727 } else {
728 desired_tile_stride = num_pages;
729 }
730
731 add = desired_tile_stride << PAGE_SHIFT;
732 row_add = hw_tile_stride << PAGE_SHIFT;
733
734 down_read(&pd->driver->sem);
735
736 for (i = 0; i < rows; ++i) {
737
738 addr = address;
739 end = addr + add;
740
741 do {
742 next = psb_pd_addr_end(addr, end);
743 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
744 if (!pt)
745 goto out;
746 do {
747 pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
748 type);
749 psb_mmu_set_pte(pt, addr, pte);
750 pt->count++;
751 } while (addr += PAGE_SIZE, addr < next);
752 psb_mmu_pt_unmap_unlock(pt);
753
754 } while (addr = next, next != end);
755
756 address += row_add;
757 }
758
759 ret = 0;
760out:
761 if (pd->hw_context != -1)
762 psb_mmu_flush_ptes(pd, f_address, num_pages,
763 desired_tile_stride, hw_tile_stride);
764
765 up_read(&pd->driver->sem);
766
767 if (pd->hw_context != -1)
768 psb_mmu_flush(pd->driver);
769
770 return ret;
771}
772
773int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
774 unsigned long *pfn)
775{
776 int ret;
777 struct psb_mmu_pt *pt;
778 uint32_t tmp;
779 spinlock_t *lock = &pd->driver->lock;
780
781 down_read(&pd->driver->sem);
782 pt = psb_mmu_pt_map_lock(pd, virtual);
783 if (!pt) {
784 uint32_t *v;
785
786 spin_lock(lock);
787 v = kmap_atomic(pd->p);
788 tmp = v[psb_mmu_pd_index(virtual)];
789 kunmap_atomic(v);
790 spin_unlock(lock);
791
792 if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
793 !(pd->invalid_pte & PSB_PTE_VALID)) {
794 ret = -EINVAL;
795 goto out;
796 }
797 ret = 0;
798 *pfn = pd->invalid_pte >> PAGE_SHIFT;
799 goto out;
800 }
801 tmp = pt->v[psb_mmu_pt_index(virtual)];
802 if (!(tmp & PSB_PTE_VALID)) {
803 ret = -EINVAL;
804 } else {
805 ret = 0;
806 *pfn = tmp >> PAGE_SHIFT;
807 }
808 psb_mmu_pt_unmap_unlock(pt);
809out:
810 up_read(&pd->driver->sem);
811 return ret;
812}
1// SPDX-License-Identifier: GPL-2.0-only
2/**************************************************************************
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 **************************************************************************/
6
7#include <linux/highmem.h>
8
9#include "mmu.h"
10#include "psb_drv.h"
11#include "psb_reg.h"
12
13/*
14 * Code for the SGX MMU:
15 */
16
17/*
18 * clflush on one processor only:
19 * clflush should apparently flush the cache line on all processors in an
20 * SMP system.
21 */
22
23/*
24 * kmap atomic:
25 * The usage of the slots must be completely encapsulated within a spinlock, and
26 * no other functions that may be using the locks for other purposed may be
27 * called from within the locked region.
28 * Since the slots are per processor, this will guarantee that we are the only
29 * user.
30 */
31
32/*
33 * TODO: Inserting ptes from an interrupt handler:
34 * This may be desirable for some SGX functionality where the GPU can fault in
35 * needed pages. For that, we need to make an atomic insert_pages function, that
36 * may fail.
37 * If it fails, the caller need to insert the page using a workqueue function,
38 * but on average it should be fast.
39 */
40
41static inline uint32_t psb_mmu_pt_index(uint32_t offset)
42{
43 return (offset >> PSB_PTE_SHIFT) & 0x3FF;
44}
45
46static inline uint32_t psb_mmu_pd_index(uint32_t offset)
47{
48 return offset >> PSB_PDE_SHIFT;
49}
50
51static inline void psb_clflush(void *addr)
52{
53 __asm__ __volatile__("clflush (%0)\n" : : "r"(addr) : "memory");
54}
55
56static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
57{
58 if (!driver->has_clflush)
59 return;
60
61 mb();
62 psb_clflush(addr);
63 mb();
64}
65
66static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
67{
68 struct drm_device *dev = driver->dev;
69 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
70
71 if (atomic_read(&driver->needs_tlbflush) || force) {
72 uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL);
73 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
74
75 /* Make sure data cache is turned off before enabling it */
76 wmb();
77 PSB_WSGX32(val & ~_PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
78 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
79 if (driver->msvdx_mmu_invaldc)
80 atomic_set(driver->msvdx_mmu_invaldc, 1);
81 }
82 atomic_set(&driver->needs_tlbflush, 0);
83}
84
85#if 0
86static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
87{
88 down_write(&driver->sem);
89 psb_mmu_flush_pd_locked(driver, force);
90 up_write(&driver->sem);
91}
92#endif
93
94void psb_mmu_flush(struct psb_mmu_driver *driver)
95{
96 struct drm_device *dev = driver->dev;
97 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
98 uint32_t val;
99
100 down_write(&driver->sem);
101 val = PSB_RSGX32(PSB_CR_BIF_CTRL);
102 if (atomic_read(&driver->needs_tlbflush))
103 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
104 else
105 PSB_WSGX32(val | _PSB_CB_CTRL_FLUSH, PSB_CR_BIF_CTRL);
106
107 /* Make sure data cache is turned off and MMU is flushed before
108 restoring bank interface control register */
109 wmb();
110 PSB_WSGX32(val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
111 PSB_CR_BIF_CTRL);
112 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
113
114 atomic_set(&driver->needs_tlbflush, 0);
115 if (driver->msvdx_mmu_invaldc)
116 atomic_set(driver->msvdx_mmu_invaldc, 1);
117 up_write(&driver->sem);
118}
119
120void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
121{
122 struct drm_device *dev = pd->driver->dev;
123 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
124 uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
125 PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
126
127 down_write(&pd->driver->sem);
128 PSB_WSGX32(page_to_pfn(pd->p) << PAGE_SHIFT, offset);
129 wmb();
130 psb_mmu_flush_pd_locked(pd->driver, 1);
131 pd->hw_context = hw_context;
132 up_write(&pd->driver->sem);
133
134}
135
136static inline unsigned long psb_pd_addr_end(unsigned long addr,
137 unsigned long end)
138{
139 addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
140 return (addr < end) ? addr : end;
141}
142
143static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
144{
145 uint32_t mask = PSB_PTE_VALID;
146
147 if (type & PSB_MMU_CACHED_MEMORY)
148 mask |= PSB_PTE_CACHED;
149 if (type & PSB_MMU_RO_MEMORY)
150 mask |= PSB_PTE_RO;
151 if (type & PSB_MMU_WO_MEMORY)
152 mask |= PSB_PTE_WO;
153
154 return (pfn << PAGE_SHIFT) | mask;
155}
156
157struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
158 int trap_pagefaults, int invalid_type)
159{
160 struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
161 uint32_t *v;
162 int i;
163
164 if (!pd)
165 return NULL;
166
167 pd->p = alloc_page(GFP_DMA32);
168 if (!pd->p)
169 goto out_err1;
170 pd->dummy_pt = alloc_page(GFP_DMA32);
171 if (!pd->dummy_pt)
172 goto out_err2;
173 pd->dummy_page = alloc_page(GFP_DMA32);
174 if (!pd->dummy_page)
175 goto out_err3;
176
177 if (!trap_pagefaults) {
178 pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
179 invalid_type);
180 pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
181 invalid_type);
182 } else {
183 pd->invalid_pde = 0;
184 pd->invalid_pte = 0;
185 }
186
187 v = kmap_local_page(pd->dummy_pt);
188 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
189 v[i] = pd->invalid_pte;
190
191 kunmap_local(v);
192
193 v = kmap_local_page(pd->p);
194 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
195 v[i] = pd->invalid_pde;
196
197 kunmap_local(v);
198
199 clear_page(kmap(pd->dummy_page));
200 kunmap(pd->dummy_page);
201
202 pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
203 if (!pd->tables)
204 goto out_err4;
205
206 pd->hw_context = -1;
207 pd->pd_mask = PSB_PTE_VALID;
208 pd->driver = driver;
209
210 return pd;
211
212out_err4:
213 __free_page(pd->dummy_page);
214out_err3:
215 __free_page(pd->dummy_pt);
216out_err2:
217 __free_page(pd->p);
218out_err1:
219 kfree(pd);
220 return NULL;
221}
222
223static void psb_mmu_free_pt(struct psb_mmu_pt *pt)
224{
225 __free_page(pt->p);
226 kfree(pt);
227}
228
229void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
230{
231 struct psb_mmu_driver *driver = pd->driver;
232 struct drm_device *dev = driver->dev;
233 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
234 struct psb_mmu_pt *pt;
235 int i;
236
237 down_write(&driver->sem);
238 if (pd->hw_context != -1) {
239 PSB_WSGX32(0, PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
240 psb_mmu_flush_pd_locked(driver, 1);
241 }
242
243 /* Should take the spinlock here, but we don't need to do that
244 since we have the semaphore in write mode. */
245
246 for (i = 0; i < 1024; ++i) {
247 pt = pd->tables[i];
248 if (pt)
249 psb_mmu_free_pt(pt);
250 }
251
252 vfree(pd->tables);
253 __free_page(pd->dummy_page);
254 __free_page(pd->dummy_pt);
255 __free_page(pd->p);
256 kfree(pd);
257 up_write(&driver->sem);
258}
259
260static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
261{
262 struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
263 void *v;
264 uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
265 uint32_t clflush_count = PAGE_SIZE / clflush_add;
266 spinlock_t *lock = &pd->driver->lock;
267 uint8_t *clf;
268 uint32_t *ptes;
269 int i;
270
271 if (!pt)
272 return NULL;
273
274 pt->p = alloc_page(GFP_DMA32);
275 if (!pt->p) {
276 kfree(pt);
277 return NULL;
278 }
279
280 spin_lock(lock);
281
282 v = kmap_atomic(pt->p);
283 clf = (uint8_t *) v;
284 ptes = (uint32_t *) v;
285 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
286 *ptes++ = pd->invalid_pte;
287
288 if (pd->driver->has_clflush && pd->hw_context != -1) {
289 mb();
290 for (i = 0; i < clflush_count; ++i) {
291 psb_clflush(clf);
292 clf += clflush_add;
293 }
294 mb();
295 }
296 kunmap_atomic(v);
297 spin_unlock(lock);
298
299 pt->count = 0;
300 pt->pd = pd;
301 pt->index = 0;
302
303 return pt;
304}
305
306static struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
307 unsigned long addr)
308{
309 uint32_t index = psb_mmu_pd_index(addr);
310 struct psb_mmu_pt *pt;
311 uint32_t *v;
312 spinlock_t *lock = &pd->driver->lock;
313
314 spin_lock(lock);
315 pt = pd->tables[index];
316 while (!pt) {
317 spin_unlock(lock);
318 pt = psb_mmu_alloc_pt(pd);
319 if (!pt)
320 return NULL;
321 spin_lock(lock);
322
323 if (pd->tables[index]) {
324 spin_unlock(lock);
325 psb_mmu_free_pt(pt);
326 spin_lock(lock);
327 pt = pd->tables[index];
328 continue;
329 }
330
331 v = kmap_atomic(pd->p);
332 pd->tables[index] = pt;
333 v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
334 pt->index = index;
335 kunmap_atomic((void *) v);
336
337 if (pd->hw_context != -1) {
338 psb_mmu_clflush(pd->driver, (void *)&v[index]);
339 atomic_set(&pd->driver->needs_tlbflush, 1);
340 }
341 }
342 pt->v = kmap_atomic(pt->p);
343 return pt;
344}
345
346static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
347 unsigned long addr)
348{
349 uint32_t index = psb_mmu_pd_index(addr);
350 struct psb_mmu_pt *pt;
351 spinlock_t *lock = &pd->driver->lock;
352
353 spin_lock(lock);
354 pt = pd->tables[index];
355 if (!pt) {
356 spin_unlock(lock);
357 return NULL;
358 }
359 pt->v = kmap_atomic(pt->p);
360 return pt;
361}
362
363static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
364{
365 struct psb_mmu_pd *pd = pt->pd;
366 uint32_t *v;
367
368 kunmap_atomic(pt->v);
369 if (pt->count == 0) {
370 v = kmap_atomic(pd->p);
371 v[pt->index] = pd->invalid_pde;
372 pd->tables[pt->index] = NULL;
373
374 if (pd->hw_context != -1) {
375 psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
376 atomic_set(&pd->driver->needs_tlbflush, 1);
377 }
378 kunmap_atomic(v);
379 spin_unlock(&pd->driver->lock);
380 psb_mmu_free_pt(pt);
381 return;
382 }
383 spin_unlock(&pd->driver->lock);
384}
385
386static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
387 uint32_t pte)
388{
389 pt->v[psb_mmu_pt_index(addr)] = pte;
390}
391
392static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
393 unsigned long addr)
394{
395 pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
396}
397
398struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
399{
400 struct psb_mmu_pd *pd;
401
402 down_read(&driver->sem);
403 pd = driver->default_pd;
404 up_read(&driver->sem);
405
406 return pd;
407}
408
409void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
410{
411 struct drm_device *dev = driver->dev;
412 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
413
414 PSB_WSGX32(driver->bif_ctrl, PSB_CR_BIF_CTRL);
415 psb_mmu_free_pagedir(driver->default_pd);
416 kfree(driver);
417}
418
419struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev,
420 int trap_pagefaults,
421 int invalid_type,
422 atomic_t *msvdx_mmu_invaldc)
423{
424 struct psb_mmu_driver *driver;
425 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
426
427 driver = kmalloc(sizeof(*driver), GFP_KERNEL);
428
429 if (!driver)
430 return NULL;
431
432 driver->dev = dev;
433 driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
434 invalid_type);
435 if (!driver->default_pd)
436 goto out_err1;
437
438 spin_lock_init(&driver->lock);
439 init_rwsem(&driver->sem);
440 down_write(&driver->sem);
441 atomic_set(&driver->needs_tlbflush, 1);
442 driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
443
444 driver->bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
445 PSB_WSGX32(driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
446 PSB_CR_BIF_CTRL);
447 PSB_WSGX32(driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
448 PSB_CR_BIF_CTRL);
449
450 driver->has_clflush = 0;
451
452 if (boot_cpu_has(X86_FEATURE_CLFLUSH)) {
453 uint32_t tfms, misc, cap0, cap4, clflush_size;
454
455 /*
456 * clflush size is determined at kernel setup for x86_64 but not
457 * for i386. We have to do it here.
458 */
459
460 cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
461 clflush_size = ((misc >> 8) & 0xff) * 8;
462 driver->has_clflush = 1;
463 driver->clflush_add =
464 PAGE_SIZE * clflush_size / sizeof(uint32_t);
465 driver->clflush_mask = driver->clflush_add - 1;
466 driver->clflush_mask = ~driver->clflush_mask;
467 }
468
469 up_write(&driver->sem);
470 return driver;
471
472out_err1:
473 kfree(driver);
474 return NULL;
475}
476
477static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
478 uint32_t num_pages, uint32_t desired_tile_stride,
479 uint32_t hw_tile_stride)
480{
481 struct psb_mmu_pt *pt;
482 uint32_t rows = 1;
483 uint32_t i;
484 unsigned long addr;
485 unsigned long end;
486 unsigned long next;
487 unsigned long add;
488 unsigned long row_add;
489 unsigned long clflush_add = pd->driver->clflush_add;
490 unsigned long clflush_mask = pd->driver->clflush_mask;
491
492 if (!pd->driver->has_clflush)
493 return;
494
495 if (hw_tile_stride)
496 rows = num_pages / desired_tile_stride;
497 else
498 desired_tile_stride = num_pages;
499
500 add = desired_tile_stride << PAGE_SHIFT;
501 row_add = hw_tile_stride << PAGE_SHIFT;
502 mb();
503 for (i = 0; i < rows; ++i) {
504
505 addr = address;
506 end = addr + add;
507
508 do {
509 next = psb_pd_addr_end(addr, end);
510 pt = psb_mmu_pt_map_lock(pd, addr);
511 if (!pt)
512 continue;
513 do {
514 psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
515 } while (addr += clflush_add,
516 (addr & clflush_mask) < next);
517
518 psb_mmu_pt_unmap_unlock(pt);
519 } while (addr = next, next != end);
520 address += row_add;
521 }
522 mb();
523}
524
525void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
526 unsigned long address, uint32_t num_pages)
527{
528 struct psb_mmu_pt *pt;
529 unsigned long addr;
530 unsigned long end;
531 unsigned long next;
532 unsigned long f_address = address;
533
534 down_read(&pd->driver->sem);
535
536 addr = address;
537 end = addr + (num_pages << PAGE_SHIFT);
538
539 do {
540 next = psb_pd_addr_end(addr, end);
541 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
542 if (!pt)
543 goto out;
544 do {
545 psb_mmu_invalidate_pte(pt, addr);
546 --pt->count;
547 } while (addr += PAGE_SIZE, addr < next);
548 psb_mmu_pt_unmap_unlock(pt);
549
550 } while (addr = next, next != end);
551
552out:
553 if (pd->hw_context != -1)
554 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
555
556 up_read(&pd->driver->sem);
557
558 if (pd->hw_context != -1)
559 psb_mmu_flush(pd->driver);
560
561 return;
562}
563
564void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
565 uint32_t num_pages, uint32_t desired_tile_stride,
566 uint32_t hw_tile_stride)
567{
568 struct psb_mmu_pt *pt;
569 uint32_t rows = 1;
570 uint32_t i;
571 unsigned long addr;
572 unsigned long end;
573 unsigned long next;
574 unsigned long add;
575 unsigned long row_add;
576 unsigned long f_address = address;
577
578 if (hw_tile_stride)
579 rows = num_pages / desired_tile_stride;
580 else
581 desired_tile_stride = num_pages;
582
583 add = desired_tile_stride << PAGE_SHIFT;
584 row_add = hw_tile_stride << PAGE_SHIFT;
585
586 down_read(&pd->driver->sem);
587
588 /* Make sure we only need to flush this processor's cache */
589
590 for (i = 0; i < rows; ++i) {
591
592 addr = address;
593 end = addr + add;
594
595 do {
596 next = psb_pd_addr_end(addr, end);
597 pt = psb_mmu_pt_map_lock(pd, addr);
598 if (!pt)
599 continue;
600 do {
601 psb_mmu_invalidate_pte(pt, addr);
602 --pt->count;
603
604 } while (addr += PAGE_SIZE, addr < next);
605 psb_mmu_pt_unmap_unlock(pt);
606
607 } while (addr = next, next != end);
608 address += row_add;
609 }
610 if (pd->hw_context != -1)
611 psb_mmu_flush_ptes(pd, f_address, num_pages,
612 desired_tile_stride, hw_tile_stride);
613
614 up_read(&pd->driver->sem);
615
616 if (pd->hw_context != -1)
617 psb_mmu_flush(pd->driver);
618}
619
620int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
621 unsigned long address, uint32_t num_pages,
622 int type)
623{
624 struct psb_mmu_pt *pt;
625 uint32_t pte;
626 unsigned long addr;
627 unsigned long end;
628 unsigned long next;
629 unsigned long f_address = address;
630 int ret = -ENOMEM;
631
632 down_read(&pd->driver->sem);
633
634 addr = address;
635 end = addr + (num_pages << PAGE_SHIFT);
636
637 do {
638 next = psb_pd_addr_end(addr, end);
639 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
640 if (!pt) {
641 ret = -ENOMEM;
642 goto out;
643 }
644 do {
645 pte = psb_mmu_mask_pte(start_pfn++, type);
646 psb_mmu_set_pte(pt, addr, pte);
647 pt->count++;
648 } while (addr += PAGE_SIZE, addr < next);
649 psb_mmu_pt_unmap_unlock(pt);
650
651 } while (addr = next, next != end);
652 ret = 0;
653
654out:
655 if (pd->hw_context != -1)
656 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
657
658 up_read(&pd->driver->sem);
659
660 if (pd->hw_context != -1)
661 psb_mmu_flush(pd->driver);
662
663 return ret;
664}
665
666int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
667 unsigned long address, uint32_t num_pages,
668 uint32_t desired_tile_stride, uint32_t hw_tile_stride,
669 int type)
670{
671 struct psb_mmu_pt *pt;
672 uint32_t rows = 1;
673 uint32_t i;
674 uint32_t pte;
675 unsigned long addr;
676 unsigned long end;
677 unsigned long next;
678 unsigned long add;
679 unsigned long row_add;
680 unsigned long f_address = address;
681 int ret = -ENOMEM;
682
683 if (hw_tile_stride) {
684 if (num_pages % desired_tile_stride != 0)
685 return -EINVAL;
686 rows = num_pages / desired_tile_stride;
687 } else {
688 desired_tile_stride = num_pages;
689 }
690
691 add = desired_tile_stride << PAGE_SHIFT;
692 row_add = hw_tile_stride << PAGE_SHIFT;
693
694 down_read(&pd->driver->sem);
695
696 for (i = 0; i < rows; ++i) {
697
698 addr = address;
699 end = addr + add;
700
701 do {
702 next = psb_pd_addr_end(addr, end);
703 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
704 if (!pt)
705 goto out;
706 do {
707 pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
708 type);
709 psb_mmu_set_pte(pt, addr, pte);
710 pt->count++;
711 } while (addr += PAGE_SIZE, addr < next);
712 psb_mmu_pt_unmap_unlock(pt);
713
714 } while (addr = next, next != end);
715
716 address += row_add;
717 }
718
719 ret = 0;
720out:
721 if (pd->hw_context != -1)
722 psb_mmu_flush_ptes(pd, f_address, num_pages,
723 desired_tile_stride, hw_tile_stride);
724
725 up_read(&pd->driver->sem);
726
727 if (pd->hw_context != -1)
728 psb_mmu_flush(pd->driver);
729
730 return ret;
731}
732
733int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
734 unsigned long *pfn)
735{
736 int ret;
737 struct psb_mmu_pt *pt;
738 uint32_t tmp;
739 spinlock_t *lock = &pd->driver->lock;
740
741 down_read(&pd->driver->sem);
742 pt = psb_mmu_pt_map_lock(pd, virtual);
743 if (!pt) {
744 uint32_t *v;
745
746 spin_lock(lock);
747 v = kmap_atomic(pd->p);
748 tmp = v[psb_mmu_pd_index(virtual)];
749 kunmap_atomic(v);
750 spin_unlock(lock);
751
752 if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
753 !(pd->invalid_pte & PSB_PTE_VALID)) {
754 ret = -EINVAL;
755 goto out;
756 }
757 ret = 0;
758 *pfn = pd->invalid_pte >> PAGE_SHIFT;
759 goto out;
760 }
761 tmp = pt->v[psb_mmu_pt_index(virtual)];
762 if (!(tmp & PSB_PTE_VALID)) {
763 ret = -EINVAL;
764 } else {
765 ret = 0;
766 *pfn = tmp >> PAGE_SHIFT;
767 }
768 psb_mmu_pt_unmap_unlock(pt);
769out:
770 up_read(&pd->driver->sem);
771 return ret;
772}