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1/**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 **************************************************************************/
18#include <drm/drmP.h>
19#include "psb_drv.h"
20#include "psb_reg.h"
21#include "mmu.h"
22
23/*
24 * Code for the SGX MMU:
25 */
26
27/*
28 * clflush on one processor only:
29 * clflush should apparently flush the cache line on all processors in an
30 * SMP system.
31 */
32
33/*
34 * kmap atomic:
35 * The usage of the slots must be completely encapsulated within a spinlock, and
36 * no other functions that may be using the locks for other purposed may be
37 * called from within the locked region.
38 * Since the slots are per processor, this will guarantee that we are the only
39 * user.
40 */
41
42/*
43 * TODO: Inserting ptes from an interrupt handler:
44 * This may be desirable for some SGX functionality where the GPU can fault in
45 * needed pages. For that, we need to make an atomic insert_pages function, that
46 * may fail.
47 * If it fails, the caller need to insert the page using a workqueue function,
48 * but on average it should be fast.
49 */
50
51static inline uint32_t psb_mmu_pt_index(uint32_t offset)
52{
53 return (offset >> PSB_PTE_SHIFT) & 0x3FF;
54}
55
56static inline uint32_t psb_mmu_pd_index(uint32_t offset)
57{
58 return offset >> PSB_PDE_SHIFT;
59}
60
61#if defined(CONFIG_X86)
62static inline void psb_clflush(void *addr)
63{
64 __asm__ __volatile__("clflush (%0)\n" : : "r"(addr) : "memory");
65}
66
67static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
68{
69 if (!driver->has_clflush)
70 return;
71
72 mb();
73 psb_clflush(addr);
74 mb();
75}
76#else
77
78static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
79{;
80}
81
82#endif
83
84static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
85{
86 struct drm_device *dev = driver->dev;
87 struct drm_psb_private *dev_priv = dev->dev_private;
88
89 if (atomic_read(&driver->needs_tlbflush) || force) {
90 uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL);
91 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
92
93 /* Make sure data cache is turned off before enabling it */
94 wmb();
95 PSB_WSGX32(val & ~_PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
96 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
97 if (driver->msvdx_mmu_invaldc)
98 atomic_set(driver->msvdx_mmu_invaldc, 1);
99 }
100 atomic_set(&driver->needs_tlbflush, 0);
101}
102
103#if 0
104static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
105{
106 down_write(&driver->sem);
107 psb_mmu_flush_pd_locked(driver, force);
108 up_write(&driver->sem);
109}
110#endif
111
112void psb_mmu_flush(struct psb_mmu_driver *driver)
113{
114 struct drm_device *dev = driver->dev;
115 struct drm_psb_private *dev_priv = dev->dev_private;
116 uint32_t val;
117
118 down_write(&driver->sem);
119 val = PSB_RSGX32(PSB_CR_BIF_CTRL);
120 if (atomic_read(&driver->needs_tlbflush))
121 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
122 else
123 PSB_WSGX32(val | _PSB_CB_CTRL_FLUSH, PSB_CR_BIF_CTRL);
124
125 /* Make sure data cache is turned off and MMU is flushed before
126 restoring bank interface control register */
127 wmb();
128 PSB_WSGX32(val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
129 PSB_CR_BIF_CTRL);
130 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
131
132 atomic_set(&driver->needs_tlbflush, 0);
133 if (driver->msvdx_mmu_invaldc)
134 atomic_set(driver->msvdx_mmu_invaldc, 1);
135 up_write(&driver->sem);
136}
137
138void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
139{
140 struct drm_device *dev = pd->driver->dev;
141 struct drm_psb_private *dev_priv = dev->dev_private;
142 uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
143 PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
144
145 down_write(&pd->driver->sem);
146 PSB_WSGX32(page_to_pfn(pd->p) << PAGE_SHIFT, offset);
147 wmb();
148 psb_mmu_flush_pd_locked(pd->driver, 1);
149 pd->hw_context = hw_context;
150 up_write(&pd->driver->sem);
151
152}
153
154static inline unsigned long psb_pd_addr_end(unsigned long addr,
155 unsigned long end)
156{
157 addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
158 return (addr < end) ? addr : end;
159}
160
161static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
162{
163 uint32_t mask = PSB_PTE_VALID;
164
165 if (type & PSB_MMU_CACHED_MEMORY)
166 mask |= PSB_PTE_CACHED;
167 if (type & PSB_MMU_RO_MEMORY)
168 mask |= PSB_PTE_RO;
169 if (type & PSB_MMU_WO_MEMORY)
170 mask |= PSB_PTE_WO;
171
172 return (pfn << PAGE_SHIFT) | mask;
173}
174
175struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
176 int trap_pagefaults, int invalid_type)
177{
178 struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
179 uint32_t *v;
180 int i;
181
182 if (!pd)
183 return NULL;
184
185 pd->p = alloc_page(GFP_DMA32);
186 if (!pd->p)
187 goto out_err1;
188 pd->dummy_pt = alloc_page(GFP_DMA32);
189 if (!pd->dummy_pt)
190 goto out_err2;
191 pd->dummy_page = alloc_page(GFP_DMA32);
192 if (!pd->dummy_page)
193 goto out_err3;
194
195 if (!trap_pagefaults) {
196 pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
197 invalid_type);
198 pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
199 invalid_type);
200 } else {
201 pd->invalid_pde = 0;
202 pd->invalid_pte = 0;
203 }
204
205 v = kmap(pd->dummy_pt);
206 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
207 v[i] = pd->invalid_pte;
208
209 kunmap(pd->dummy_pt);
210
211 v = kmap(pd->p);
212 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
213 v[i] = pd->invalid_pde;
214
215 kunmap(pd->p);
216
217 clear_page(kmap(pd->dummy_page));
218 kunmap(pd->dummy_page);
219
220 pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
221 if (!pd->tables)
222 goto out_err4;
223
224 pd->hw_context = -1;
225 pd->pd_mask = PSB_PTE_VALID;
226 pd->driver = driver;
227
228 return pd;
229
230out_err4:
231 __free_page(pd->dummy_page);
232out_err3:
233 __free_page(pd->dummy_pt);
234out_err2:
235 __free_page(pd->p);
236out_err1:
237 kfree(pd);
238 return NULL;
239}
240
241static void psb_mmu_free_pt(struct psb_mmu_pt *pt)
242{
243 __free_page(pt->p);
244 kfree(pt);
245}
246
247void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
248{
249 struct psb_mmu_driver *driver = pd->driver;
250 struct drm_device *dev = driver->dev;
251 struct drm_psb_private *dev_priv = dev->dev_private;
252 struct psb_mmu_pt *pt;
253 int i;
254
255 down_write(&driver->sem);
256 if (pd->hw_context != -1) {
257 PSB_WSGX32(0, PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
258 psb_mmu_flush_pd_locked(driver, 1);
259 }
260
261 /* Should take the spinlock here, but we don't need to do that
262 since we have the semaphore in write mode. */
263
264 for (i = 0; i < 1024; ++i) {
265 pt = pd->tables[i];
266 if (pt)
267 psb_mmu_free_pt(pt);
268 }
269
270 vfree(pd->tables);
271 __free_page(pd->dummy_page);
272 __free_page(pd->dummy_pt);
273 __free_page(pd->p);
274 kfree(pd);
275 up_write(&driver->sem);
276}
277
278static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
279{
280 struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
281 void *v;
282 uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
283 uint32_t clflush_count = PAGE_SIZE / clflush_add;
284 spinlock_t *lock = &pd->driver->lock;
285 uint8_t *clf;
286 uint32_t *ptes;
287 int i;
288
289 if (!pt)
290 return NULL;
291
292 pt->p = alloc_page(GFP_DMA32);
293 if (!pt->p) {
294 kfree(pt);
295 return NULL;
296 }
297
298 spin_lock(lock);
299
300 v = kmap_atomic(pt->p);
301 clf = (uint8_t *) v;
302 ptes = (uint32_t *) v;
303 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
304 *ptes++ = pd->invalid_pte;
305
306#if defined(CONFIG_X86)
307 if (pd->driver->has_clflush && pd->hw_context != -1) {
308 mb();
309 for (i = 0; i < clflush_count; ++i) {
310 psb_clflush(clf);
311 clf += clflush_add;
312 }
313 mb();
314 }
315#endif
316 kunmap_atomic(v);
317 spin_unlock(lock);
318
319 pt->count = 0;
320 pt->pd = pd;
321 pt->index = 0;
322
323 return pt;
324}
325
326struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
327 unsigned long addr)
328{
329 uint32_t index = psb_mmu_pd_index(addr);
330 struct psb_mmu_pt *pt;
331 uint32_t *v;
332 spinlock_t *lock = &pd->driver->lock;
333
334 spin_lock(lock);
335 pt = pd->tables[index];
336 while (!pt) {
337 spin_unlock(lock);
338 pt = psb_mmu_alloc_pt(pd);
339 if (!pt)
340 return NULL;
341 spin_lock(lock);
342
343 if (pd->tables[index]) {
344 spin_unlock(lock);
345 psb_mmu_free_pt(pt);
346 spin_lock(lock);
347 pt = pd->tables[index];
348 continue;
349 }
350
351 v = kmap_atomic(pd->p);
352 pd->tables[index] = pt;
353 v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
354 pt->index = index;
355 kunmap_atomic((void *) v);
356
357 if (pd->hw_context != -1) {
358 psb_mmu_clflush(pd->driver, (void *)&v[index]);
359 atomic_set(&pd->driver->needs_tlbflush, 1);
360 }
361 }
362 pt->v = kmap_atomic(pt->p);
363 return pt;
364}
365
366static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
367 unsigned long addr)
368{
369 uint32_t index = psb_mmu_pd_index(addr);
370 struct psb_mmu_pt *pt;
371 spinlock_t *lock = &pd->driver->lock;
372
373 spin_lock(lock);
374 pt = pd->tables[index];
375 if (!pt) {
376 spin_unlock(lock);
377 return NULL;
378 }
379 pt->v = kmap_atomic(pt->p);
380 return pt;
381}
382
383static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
384{
385 struct psb_mmu_pd *pd = pt->pd;
386 uint32_t *v;
387
388 kunmap_atomic(pt->v);
389 if (pt->count == 0) {
390 v = kmap_atomic(pd->p);
391 v[pt->index] = pd->invalid_pde;
392 pd->tables[pt->index] = NULL;
393
394 if (pd->hw_context != -1) {
395 psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
396 atomic_set(&pd->driver->needs_tlbflush, 1);
397 }
398 kunmap_atomic(pt->v);
399 spin_unlock(&pd->driver->lock);
400 psb_mmu_free_pt(pt);
401 return;
402 }
403 spin_unlock(&pd->driver->lock);
404}
405
406static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
407 uint32_t pte)
408{
409 pt->v[psb_mmu_pt_index(addr)] = pte;
410}
411
412static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
413 unsigned long addr)
414{
415 pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
416}
417
418struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
419{
420 struct psb_mmu_pd *pd;
421
422 down_read(&driver->sem);
423 pd = driver->default_pd;
424 up_read(&driver->sem);
425
426 return pd;
427}
428
429/* Returns the physical address of the PD shared by sgx/msvdx */
430uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver)
431{
432 struct psb_mmu_pd *pd;
433
434 pd = psb_mmu_get_default_pd(driver);
435 return page_to_pfn(pd->p) << PAGE_SHIFT;
436}
437
438void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
439{
440 struct drm_device *dev = driver->dev;
441 struct drm_psb_private *dev_priv = dev->dev_private;
442
443 PSB_WSGX32(driver->bif_ctrl, PSB_CR_BIF_CTRL);
444 psb_mmu_free_pagedir(driver->default_pd);
445 kfree(driver);
446}
447
448struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev,
449 int trap_pagefaults,
450 int invalid_type,
451 atomic_t *msvdx_mmu_invaldc)
452{
453 struct psb_mmu_driver *driver;
454 struct drm_psb_private *dev_priv = dev->dev_private;
455
456 driver = kmalloc(sizeof(*driver), GFP_KERNEL);
457
458 if (!driver)
459 return NULL;
460
461 driver->dev = dev;
462 driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
463 invalid_type);
464 if (!driver->default_pd)
465 goto out_err1;
466
467 spin_lock_init(&driver->lock);
468 init_rwsem(&driver->sem);
469 down_write(&driver->sem);
470 atomic_set(&driver->needs_tlbflush, 1);
471 driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
472
473 driver->bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
474 PSB_WSGX32(driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
475 PSB_CR_BIF_CTRL);
476 PSB_WSGX32(driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
477 PSB_CR_BIF_CTRL);
478
479 driver->has_clflush = 0;
480
481#if defined(CONFIG_X86)
482 if (boot_cpu_has(X86_FEATURE_CLFLUSH)) {
483 uint32_t tfms, misc, cap0, cap4, clflush_size;
484
485 /*
486 * clflush size is determined at kernel setup for x86_64 but not
487 * for i386. We have to do it here.
488 */
489
490 cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
491 clflush_size = ((misc >> 8) & 0xff) * 8;
492 driver->has_clflush = 1;
493 driver->clflush_add =
494 PAGE_SIZE * clflush_size / sizeof(uint32_t);
495 driver->clflush_mask = driver->clflush_add - 1;
496 driver->clflush_mask = ~driver->clflush_mask;
497 }
498#endif
499
500 up_write(&driver->sem);
501 return driver;
502
503out_err1:
504 kfree(driver);
505 return NULL;
506}
507
508#if defined(CONFIG_X86)
509static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
510 uint32_t num_pages, uint32_t desired_tile_stride,
511 uint32_t hw_tile_stride)
512{
513 struct psb_mmu_pt *pt;
514 uint32_t rows = 1;
515 uint32_t i;
516 unsigned long addr;
517 unsigned long end;
518 unsigned long next;
519 unsigned long add;
520 unsigned long row_add;
521 unsigned long clflush_add = pd->driver->clflush_add;
522 unsigned long clflush_mask = pd->driver->clflush_mask;
523
524 if (!pd->driver->has_clflush)
525 return;
526
527 if (hw_tile_stride)
528 rows = num_pages / desired_tile_stride;
529 else
530 desired_tile_stride = num_pages;
531
532 add = desired_tile_stride << PAGE_SHIFT;
533 row_add = hw_tile_stride << PAGE_SHIFT;
534 mb();
535 for (i = 0; i < rows; ++i) {
536
537 addr = address;
538 end = addr + add;
539
540 do {
541 next = psb_pd_addr_end(addr, end);
542 pt = psb_mmu_pt_map_lock(pd, addr);
543 if (!pt)
544 continue;
545 do {
546 psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
547 } while (addr += clflush_add,
548 (addr & clflush_mask) < next);
549
550 psb_mmu_pt_unmap_unlock(pt);
551 } while (addr = next, next != end);
552 address += row_add;
553 }
554 mb();
555}
556#else
557static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
558 uint32_t num_pages, uint32_t desired_tile_stride,
559 uint32_t hw_tile_stride)
560{
561 drm_ttm_cache_flush();
562}
563#endif
564
565void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
566 unsigned long address, uint32_t num_pages)
567{
568 struct psb_mmu_pt *pt;
569 unsigned long addr;
570 unsigned long end;
571 unsigned long next;
572 unsigned long f_address = address;
573
574 down_read(&pd->driver->sem);
575
576 addr = address;
577 end = addr + (num_pages << PAGE_SHIFT);
578
579 do {
580 next = psb_pd_addr_end(addr, end);
581 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
582 if (!pt)
583 goto out;
584 do {
585 psb_mmu_invalidate_pte(pt, addr);
586 --pt->count;
587 } while (addr += PAGE_SIZE, addr < next);
588 psb_mmu_pt_unmap_unlock(pt);
589
590 } while (addr = next, next != end);
591
592out:
593 if (pd->hw_context != -1)
594 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
595
596 up_read(&pd->driver->sem);
597
598 if (pd->hw_context != -1)
599 psb_mmu_flush(pd->driver);
600
601 return;
602}
603
604void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
605 uint32_t num_pages, uint32_t desired_tile_stride,
606 uint32_t hw_tile_stride)
607{
608 struct psb_mmu_pt *pt;
609 uint32_t rows = 1;
610 uint32_t i;
611 unsigned long addr;
612 unsigned long end;
613 unsigned long next;
614 unsigned long add;
615 unsigned long row_add;
616 unsigned long f_address = address;
617
618 if (hw_tile_stride)
619 rows = num_pages / desired_tile_stride;
620 else
621 desired_tile_stride = num_pages;
622
623 add = desired_tile_stride << PAGE_SHIFT;
624 row_add = hw_tile_stride << PAGE_SHIFT;
625
626 down_read(&pd->driver->sem);
627
628 /* Make sure we only need to flush this processor's cache */
629
630 for (i = 0; i < rows; ++i) {
631
632 addr = address;
633 end = addr + add;
634
635 do {
636 next = psb_pd_addr_end(addr, end);
637 pt = psb_mmu_pt_map_lock(pd, addr);
638 if (!pt)
639 continue;
640 do {
641 psb_mmu_invalidate_pte(pt, addr);
642 --pt->count;
643
644 } while (addr += PAGE_SIZE, addr < next);
645 psb_mmu_pt_unmap_unlock(pt);
646
647 } while (addr = next, next != end);
648 address += row_add;
649 }
650 if (pd->hw_context != -1)
651 psb_mmu_flush_ptes(pd, f_address, num_pages,
652 desired_tile_stride, hw_tile_stride);
653
654 up_read(&pd->driver->sem);
655
656 if (pd->hw_context != -1)
657 psb_mmu_flush(pd->driver);
658}
659
660int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
661 unsigned long address, uint32_t num_pages,
662 int type)
663{
664 struct psb_mmu_pt *pt;
665 uint32_t pte;
666 unsigned long addr;
667 unsigned long end;
668 unsigned long next;
669 unsigned long f_address = address;
670 int ret = -ENOMEM;
671
672 down_read(&pd->driver->sem);
673
674 addr = address;
675 end = addr + (num_pages << PAGE_SHIFT);
676
677 do {
678 next = psb_pd_addr_end(addr, end);
679 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
680 if (!pt) {
681 ret = -ENOMEM;
682 goto out;
683 }
684 do {
685 pte = psb_mmu_mask_pte(start_pfn++, type);
686 psb_mmu_set_pte(pt, addr, pte);
687 pt->count++;
688 } while (addr += PAGE_SIZE, addr < next);
689 psb_mmu_pt_unmap_unlock(pt);
690
691 } while (addr = next, next != end);
692 ret = 0;
693
694out:
695 if (pd->hw_context != -1)
696 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
697
698 up_read(&pd->driver->sem);
699
700 if (pd->hw_context != -1)
701 psb_mmu_flush(pd->driver);
702
703 return 0;
704}
705
706int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
707 unsigned long address, uint32_t num_pages,
708 uint32_t desired_tile_stride, uint32_t hw_tile_stride,
709 int type)
710{
711 struct psb_mmu_pt *pt;
712 uint32_t rows = 1;
713 uint32_t i;
714 uint32_t pte;
715 unsigned long addr;
716 unsigned long end;
717 unsigned long next;
718 unsigned long add;
719 unsigned long row_add;
720 unsigned long f_address = address;
721 int ret = -ENOMEM;
722
723 if (hw_tile_stride) {
724 if (num_pages % desired_tile_stride != 0)
725 return -EINVAL;
726 rows = num_pages / desired_tile_stride;
727 } else {
728 desired_tile_stride = num_pages;
729 }
730
731 add = desired_tile_stride << PAGE_SHIFT;
732 row_add = hw_tile_stride << PAGE_SHIFT;
733
734 down_read(&pd->driver->sem);
735
736 for (i = 0; i < rows; ++i) {
737
738 addr = address;
739 end = addr + add;
740
741 do {
742 next = psb_pd_addr_end(addr, end);
743 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
744 if (!pt)
745 goto out;
746 do {
747 pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
748 type);
749 psb_mmu_set_pte(pt, addr, pte);
750 pt->count++;
751 } while (addr += PAGE_SIZE, addr < next);
752 psb_mmu_pt_unmap_unlock(pt);
753
754 } while (addr = next, next != end);
755
756 address += row_add;
757 }
758
759 ret = 0;
760out:
761 if (pd->hw_context != -1)
762 psb_mmu_flush_ptes(pd, f_address, num_pages,
763 desired_tile_stride, hw_tile_stride);
764
765 up_read(&pd->driver->sem);
766
767 if (pd->hw_context != -1)
768 psb_mmu_flush(pd->driver);
769
770 return ret;
771}
772
773int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
774 unsigned long *pfn)
775{
776 int ret;
777 struct psb_mmu_pt *pt;
778 uint32_t tmp;
779 spinlock_t *lock = &pd->driver->lock;
780
781 down_read(&pd->driver->sem);
782 pt = psb_mmu_pt_map_lock(pd, virtual);
783 if (!pt) {
784 uint32_t *v;
785
786 spin_lock(lock);
787 v = kmap_atomic(pd->p);
788 tmp = v[psb_mmu_pd_index(virtual)];
789 kunmap_atomic(v);
790 spin_unlock(lock);
791
792 if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
793 !(pd->invalid_pte & PSB_PTE_VALID)) {
794 ret = -EINVAL;
795 goto out;
796 }
797 ret = 0;
798 *pfn = pd->invalid_pte >> PAGE_SHIFT;
799 goto out;
800 }
801 tmp = pt->v[psb_mmu_pt_index(virtual)];
802 if (!(tmp & PSB_PTE_VALID)) {
803 ret = -EINVAL;
804 } else {
805 ret = 0;
806 *pfn = tmp >> PAGE_SHIFT;
807 }
808 psb_mmu_pt_unmap_unlock(pt);
809out:
810 up_read(&pd->driver->sem);
811 return ret;
812}
1// SPDX-License-Identifier: GPL-2.0-only
2/**************************************************************************
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 **************************************************************************/
6
7#include <linux/highmem.h>
8
9#include "mmu.h"
10#include "psb_drv.h"
11#include "psb_reg.h"
12
13/*
14 * Code for the SGX MMU:
15 */
16
17/*
18 * clflush on one processor only:
19 * clflush should apparently flush the cache line on all processors in an
20 * SMP system.
21 */
22
23/*
24 * kmap atomic:
25 * The usage of the slots must be completely encapsulated within a spinlock, and
26 * no other functions that may be using the locks for other purposed may be
27 * called from within the locked region.
28 * Since the slots are per processor, this will guarantee that we are the only
29 * user.
30 */
31
32/*
33 * TODO: Inserting ptes from an interrupt handler:
34 * This may be desirable for some SGX functionality where the GPU can fault in
35 * needed pages. For that, we need to make an atomic insert_pages function, that
36 * may fail.
37 * If it fails, the caller need to insert the page using a workqueue function,
38 * but on average it should be fast.
39 */
40
41static inline uint32_t psb_mmu_pt_index(uint32_t offset)
42{
43 return (offset >> PSB_PTE_SHIFT) & 0x3FF;
44}
45
46static inline uint32_t psb_mmu_pd_index(uint32_t offset)
47{
48 return offset >> PSB_PDE_SHIFT;
49}
50
51#if defined(CONFIG_X86)
52static inline void psb_clflush(void *addr)
53{
54 __asm__ __volatile__("clflush (%0)\n" : : "r"(addr) : "memory");
55}
56
57static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
58{
59 if (!driver->has_clflush)
60 return;
61
62 mb();
63 psb_clflush(addr);
64 mb();
65}
66#else
67
68static inline void psb_mmu_clflush(struct psb_mmu_driver *driver, void *addr)
69{;
70}
71
72#endif
73
74static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver, int force)
75{
76 struct drm_device *dev = driver->dev;
77 struct drm_psb_private *dev_priv = dev->dev_private;
78
79 if (atomic_read(&driver->needs_tlbflush) || force) {
80 uint32_t val = PSB_RSGX32(PSB_CR_BIF_CTRL);
81 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
82
83 /* Make sure data cache is turned off before enabling it */
84 wmb();
85 PSB_WSGX32(val & ~_PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
86 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
87 if (driver->msvdx_mmu_invaldc)
88 atomic_set(driver->msvdx_mmu_invaldc, 1);
89 }
90 atomic_set(&driver->needs_tlbflush, 0);
91}
92
93#if 0
94static void psb_mmu_flush_pd(struct psb_mmu_driver *driver, int force)
95{
96 down_write(&driver->sem);
97 psb_mmu_flush_pd_locked(driver, force);
98 up_write(&driver->sem);
99}
100#endif
101
102void psb_mmu_flush(struct psb_mmu_driver *driver)
103{
104 struct drm_device *dev = driver->dev;
105 struct drm_psb_private *dev_priv = dev->dev_private;
106 uint32_t val;
107
108 down_write(&driver->sem);
109 val = PSB_RSGX32(PSB_CR_BIF_CTRL);
110 if (atomic_read(&driver->needs_tlbflush))
111 PSB_WSGX32(val | _PSB_CB_CTRL_INVALDC, PSB_CR_BIF_CTRL);
112 else
113 PSB_WSGX32(val | _PSB_CB_CTRL_FLUSH, PSB_CR_BIF_CTRL);
114
115 /* Make sure data cache is turned off and MMU is flushed before
116 restoring bank interface control register */
117 wmb();
118 PSB_WSGX32(val & ~(_PSB_CB_CTRL_FLUSH | _PSB_CB_CTRL_INVALDC),
119 PSB_CR_BIF_CTRL);
120 (void)PSB_RSGX32(PSB_CR_BIF_CTRL);
121
122 atomic_set(&driver->needs_tlbflush, 0);
123 if (driver->msvdx_mmu_invaldc)
124 atomic_set(driver->msvdx_mmu_invaldc, 1);
125 up_write(&driver->sem);
126}
127
128void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context)
129{
130 struct drm_device *dev = pd->driver->dev;
131 struct drm_psb_private *dev_priv = dev->dev_private;
132 uint32_t offset = (hw_context == 0) ? PSB_CR_BIF_DIR_LIST_BASE0 :
133 PSB_CR_BIF_DIR_LIST_BASE1 + hw_context * 4;
134
135 down_write(&pd->driver->sem);
136 PSB_WSGX32(page_to_pfn(pd->p) << PAGE_SHIFT, offset);
137 wmb();
138 psb_mmu_flush_pd_locked(pd->driver, 1);
139 pd->hw_context = hw_context;
140 up_write(&pd->driver->sem);
141
142}
143
144static inline unsigned long psb_pd_addr_end(unsigned long addr,
145 unsigned long end)
146{
147 addr = (addr + PSB_PDE_MASK + 1) & ~PSB_PDE_MASK;
148 return (addr < end) ? addr : end;
149}
150
151static inline uint32_t psb_mmu_mask_pte(uint32_t pfn, int type)
152{
153 uint32_t mask = PSB_PTE_VALID;
154
155 if (type & PSB_MMU_CACHED_MEMORY)
156 mask |= PSB_PTE_CACHED;
157 if (type & PSB_MMU_RO_MEMORY)
158 mask |= PSB_PTE_RO;
159 if (type & PSB_MMU_WO_MEMORY)
160 mask |= PSB_PTE_WO;
161
162 return (pfn << PAGE_SHIFT) | mask;
163}
164
165struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
166 int trap_pagefaults, int invalid_type)
167{
168 struct psb_mmu_pd *pd = kmalloc(sizeof(*pd), GFP_KERNEL);
169 uint32_t *v;
170 int i;
171
172 if (!pd)
173 return NULL;
174
175 pd->p = alloc_page(GFP_DMA32);
176 if (!pd->p)
177 goto out_err1;
178 pd->dummy_pt = alloc_page(GFP_DMA32);
179 if (!pd->dummy_pt)
180 goto out_err2;
181 pd->dummy_page = alloc_page(GFP_DMA32);
182 if (!pd->dummy_page)
183 goto out_err3;
184
185 if (!trap_pagefaults) {
186 pd->invalid_pde = psb_mmu_mask_pte(page_to_pfn(pd->dummy_pt),
187 invalid_type);
188 pd->invalid_pte = psb_mmu_mask_pte(page_to_pfn(pd->dummy_page),
189 invalid_type);
190 } else {
191 pd->invalid_pde = 0;
192 pd->invalid_pte = 0;
193 }
194
195 v = kmap(pd->dummy_pt);
196 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
197 v[i] = pd->invalid_pte;
198
199 kunmap(pd->dummy_pt);
200
201 v = kmap(pd->p);
202 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
203 v[i] = pd->invalid_pde;
204
205 kunmap(pd->p);
206
207 clear_page(kmap(pd->dummy_page));
208 kunmap(pd->dummy_page);
209
210 pd->tables = vmalloc_user(sizeof(struct psb_mmu_pt *) * 1024);
211 if (!pd->tables)
212 goto out_err4;
213
214 pd->hw_context = -1;
215 pd->pd_mask = PSB_PTE_VALID;
216 pd->driver = driver;
217
218 return pd;
219
220out_err4:
221 __free_page(pd->dummy_page);
222out_err3:
223 __free_page(pd->dummy_pt);
224out_err2:
225 __free_page(pd->p);
226out_err1:
227 kfree(pd);
228 return NULL;
229}
230
231static void psb_mmu_free_pt(struct psb_mmu_pt *pt)
232{
233 __free_page(pt->p);
234 kfree(pt);
235}
236
237void psb_mmu_free_pagedir(struct psb_mmu_pd *pd)
238{
239 struct psb_mmu_driver *driver = pd->driver;
240 struct drm_device *dev = driver->dev;
241 struct drm_psb_private *dev_priv = dev->dev_private;
242 struct psb_mmu_pt *pt;
243 int i;
244
245 down_write(&driver->sem);
246 if (pd->hw_context != -1) {
247 PSB_WSGX32(0, PSB_CR_BIF_DIR_LIST_BASE0 + pd->hw_context * 4);
248 psb_mmu_flush_pd_locked(driver, 1);
249 }
250
251 /* Should take the spinlock here, but we don't need to do that
252 since we have the semaphore in write mode. */
253
254 for (i = 0; i < 1024; ++i) {
255 pt = pd->tables[i];
256 if (pt)
257 psb_mmu_free_pt(pt);
258 }
259
260 vfree(pd->tables);
261 __free_page(pd->dummy_page);
262 __free_page(pd->dummy_pt);
263 __free_page(pd->p);
264 kfree(pd);
265 up_write(&driver->sem);
266}
267
268static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd)
269{
270 struct psb_mmu_pt *pt = kmalloc(sizeof(*pt), GFP_KERNEL);
271 void *v;
272 uint32_t clflush_add = pd->driver->clflush_add >> PAGE_SHIFT;
273 uint32_t clflush_count = PAGE_SIZE / clflush_add;
274 spinlock_t *lock = &pd->driver->lock;
275 uint8_t *clf;
276 uint32_t *ptes;
277 int i;
278
279 if (!pt)
280 return NULL;
281
282 pt->p = alloc_page(GFP_DMA32);
283 if (!pt->p) {
284 kfree(pt);
285 return NULL;
286 }
287
288 spin_lock(lock);
289
290 v = kmap_atomic(pt->p);
291 clf = (uint8_t *) v;
292 ptes = (uint32_t *) v;
293 for (i = 0; i < (PAGE_SIZE / sizeof(uint32_t)); ++i)
294 *ptes++ = pd->invalid_pte;
295
296#if defined(CONFIG_X86)
297 if (pd->driver->has_clflush && pd->hw_context != -1) {
298 mb();
299 for (i = 0; i < clflush_count; ++i) {
300 psb_clflush(clf);
301 clf += clflush_add;
302 }
303 mb();
304 }
305#endif
306 kunmap_atomic(v);
307 spin_unlock(lock);
308
309 pt->count = 0;
310 pt->pd = pd;
311 pt->index = 0;
312
313 return pt;
314}
315
316struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd,
317 unsigned long addr)
318{
319 uint32_t index = psb_mmu_pd_index(addr);
320 struct psb_mmu_pt *pt;
321 uint32_t *v;
322 spinlock_t *lock = &pd->driver->lock;
323
324 spin_lock(lock);
325 pt = pd->tables[index];
326 while (!pt) {
327 spin_unlock(lock);
328 pt = psb_mmu_alloc_pt(pd);
329 if (!pt)
330 return NULL;
331 spin_lock(lock);
332
333 if (pd->tables[index]) {
334 spin_unlock(lock);
335 psb_mmu_free_pt(pt);
336 spin_lock(lock);
337 pt = pd->tables[index];
338 continue;
339 }
340
341 v = kmap_atomic(pd->p);
342 pd->tables[index] = pt;
343 v[index] = (page_to_pfn(pt->p) << 12) | pd->pd_mask;
344 pt->index = index;
345 kunmap_atomic((void *) v);
346
347 if (pd->hw_context != -1) {
348 psb_mmu_clflush(pd->driver, (void *)&v[index]);
349 atomic_set(&pd->driver->needs_tlbflush, 1);
350 }
351 }
352 pt->v = kmap_atomic(pt->p);
353 return pt;
354}
355
356static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd,
357 unsigned long addr)
358{
359 uint32_t index = psb_mmu_pd_index(addr);
360 struct psb_mmu_pt *pt;
361 spinlock_t *lock = &pd->driver->lock;
362
363 spin_lock(lock);
364 pt = pd->tables[index];
365 if (!pt) {
366 spin_unlock(lock);
367 return NULL;
368 }
369 pt->v = kmap_atomic(pt->p);
370 return pt;
371}
372
373static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt)
374{
375 struct psb_mmu_pd *pd = pt->pd;
376 uint32_t *v;
377
378 kunmap_atomic(pt->v);
379 if (pt->count == 0) {
380 v = kmap_atomic(pd->p);
381 v[pt->index] = pd->invalid_pde;
382 pd->tables[pt->index] = NULL;
383
384 if (pd->hw_context != -1) {
385 psb_mmu_clflush(pd->driver, (void *)&v[pt->index]);
386 atomic_set(&pd->driver->needs_tlbflush, 1);
387 }
388 kunmap_atomic(v);
389 spin_unlock(&pd->driver->lock);
390 psb_mmu_free_pt(pt);
391 return;
392 }
393 spin_unlock(&pd->driver->lock);
394}
395
396static inline void psb_mmu_set_pte(struct psb_mmu_pt *pt, unsigned long addr,
397 uint32_t pte)
398{
399 pt->v[psb_mmu_pt_index(addr)] = pte;
400}
401
402static inline void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt,
403 unsigned long addr)
404{
405 pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
406}
407
408struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver)
409{
410 struct psb_mmu_pd *pd;
411
412 down_read(&driver->sem);
413 pd = driver->default_pd;
414 up_read(&driver->sem);
415
416 return pd;
417}
418
419/* Returns the physical address of the PD shared by sgx/msvdx */
420uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver)
421{
422 struct psb_mmu_pd *pd;
423
424 pd = psb_mmu_get_default_pd(driver);
425 return page_to_pfn(pd->p) << PAGE_SHIFT;
426}
427
428void psb_mmu_driver_takedown(struct psb_mmu_driver *driver)
429{
430 struct drm_device *dev = driver->dev;
431 struct drm_psb_private *dev_priv = dev->dev_private;
432
433 PSB_WSGX32(driver->bif_ctrl, PSB_CR_BIF_CTRL);
434 psb_mmu_free_pagedir(driver->default_pd);
435 kfree(driver);
436}
437
438struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev,
439 int trap_pagefaults,
440 int invalid_type,
441 atomic_t *msvdx_mmu_invaldc)
442{
443 struct psb_mmu_driver *driver;
444 struct drm_psb_private *dev_priv = dev->dev_private;
445
446 driver = kmalloc(sizeof(*driver), GFP_KERNEL);
447
448 if (!driver)
449 return NULL;
450
451 driver->dev = dev;
452 driver->default_pd = psb_mmu_alloc_pd(driver, trap_pagefaults,
453 invalid_type);
454 if (!driver->default_pd)
455 goto out_err1;
456
457 spin_lock_init(&driver->lock);
458 init_rwsem(&driver->sem);
459 down_write(&driver->sem);
460 atomic_set(&driver->needs_tlbflush, 1);
461 driver->msvdx_mmu_invaldc = msvdx_mmu_invaldc;
462
463 driver->bif_ctrl = PSB_RSGX32(PSB_CR_BIF_CTRL);
464 PSB_WSGX32(driver->bif_ctrl | _PSB_CB_CTRL_CLEAR_FAULT,
465 PSB_CR_BIF_CTRL);
466 PSB_WSGX32(driver->bif_ctrl & ~_PSB_CB_CTRL_CLEAR_FAULT,
467 PSB_CR_BIF_CTRL);
468
469 driver->has_clflush = 0;
470
471#if defined(CONFIG_X86)
472 if (boot_cpu_has(X86_FEATURE_CLFLUSH)) {
473 uint32_t tfms, misc, cap0, cap4, clflush_size;
474
475 /*
476 * clflush size is determined at kernel setup for x86_64 but not
477 * for i386. We have to do it here.
478 */
479
480 cpuid(0x00000001, &tfms, &misc, &cap0, &cap4);
481 clflush_size = ((misc >> 8) & 0xff) * 8;
482 driver->has_clflush = 1;
483 driver->clflush_add =
484 PAGE_SIZE * clflush_size / sizeof(uint32_t);
485 driver->clflush_mask = driver->clflush_add - 1;
486 driver->clflush_mask = ~driver->clflush_mask;
487 }
488#endif
489
490 up_write(&driver->sem);
491 return driver;
492
493out_err1:
494 kfree(driver);
495 return NULL;
496}
497
498#if defined(CONFIG_X86)
499static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
500 uint32_t num_pages, uint32_t desired_tile_stride,
501 uint32_t hw_tile_stride)
502{
503 struct psb_mmu_pt *pt;
504 uint32_t rows = 1;
505 uint32_t i;
506 unsigned long addr;
507 unsigned long end;
508 unsigned long next;
509 unsigned long add;
510 unsigned long row_add;
511 unsigned long clflush_add = pd->driver->clflush_add;
512 unsigned long clflush_mask = pd->driver->clflush_mask;
513
514 if (!pd->driver->has_clflush)
515 return;
516
517 if (hw_tile_stride)
518 rows = num_pages / desired_tile_stride;
519 else
520 desired_tile_stride = num_pages;
521
522 add = desired_tile_stride << PAGE_SHIFT;
523 row_add = hw_tile_stride << PAGE_SHIFT;
524 mb();
525 for (i = 0; i < rows; ++i) {
526
527 addr = address;
528 end = addr + add;
529
530 do {
531 next = psb_pd_addr_end(addr, end);
532 pt = psb_mmu_pt_map_lock(pd, addr);
533 if (!pt)
534 continue;
535 do {
536 psb_clflush(&pt->v[psb_mmu_pt_index(addr)]);
537 } while (addr += clflush_add,
538 (addr & clflush_mask) < next);
539
540 psb_mmu_pt_unmap_unlock(pt);
541 } while (addr = next, next != end);
542 address += row_add;
543 }
544 mb();
545}
546#else
547static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd, unsigned long address,
548 uint32_t num_pages, uint32_t desired_tile_stride,
549 uint32_t hw_tile_stride)
550{
551 drm_ttm_cache_flush();
552}
553#endif
554
555void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
556 unsigned long address, uint32_t num_pages)
557{
558 struct psb_mmu_pt *pt;
559 unsigned long addr;
560 unsigned long end;
561 unsigned long next;
562 unsigned long f_address = address;
563
564 down_read(&pd->driver->sem);
565
566 addr = address;
567 end = addr + (num_pages << PAGE_SHIFT);
568
569 do {
570 next = psb_pd_addr_end(addr, end);
571 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
572 if (!pt)
573 goto out;
574 do {
575 psb_mmu_invalidate_pte(pt, addr);
576 --pt->count;
577 } while (addr += PAGE_SIZE, addr < next);
578 psb_mmu_pt_unmap_unlock(pt);
579
580 } while (addr = next, next != end);
581
582out:
583 if (pd->hw_context != -1)
584 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
585
586 up_read(&pd->driver->sem);
587
588 if (pd->hw_context != -1)
589 psb_mmu_flush(pd->driver);
590
591 return;
592}
593
594void psb_mmu_remove_pages(struct psb_mmu_pd *pd, unsigned long address,
595 uint32_t num_pages, uint32_t desired_tile_stride,
596 uint32_t hw_tile_stride)
597{
598 struct psb_mmu_pt *pt;
599 uint32_t rows = 1;
600 uint32_t i;
601 unsigned long addr;
602 unsigned long end;
603 unsigned long next;
604 unsigned long add;
605 unsigned long row_add;
606 unsigned long f_address = address;
607
608 if (hw_tile_stride)
609 rows = num_pages / desired_tile_stride;
610 else
611 desired_tile_stride = num_pages;
612
613 add = desired_tile_stride << PAGE_SHIFT;
614 row_add = hw_tile_stride << PAGE_SHIFT;
615
616 down_read(&pd->driver->sem);
617
618 /* Make sure we only need to flush this processor's cache */
619
620 for (i = 0; i < rows; ++i) {
621
622 addr = address;
623 end = addr + add;
624
625 do {
626 next = psb_pd_addr_end(addr, end);
627 pt = psb_mmu_pt_map_lock(pd, addr);
628 if (!pt)
629 continue;
630 do {
631 psb_mmu_invalidate_pte(pt, addr);
632 --pt->count;
633
634 } while (addr += PAGE_SIZE, addr < next);
635 psb_mmu_pt_unmap_unlock(pt);
636
637 } while (addr = next, next != end);
638 address += row_add;
639 }
640 if (pd->hw_context != -1)
641 psb_mmu_flush_ptes(pd, f_address, num_pages,
642 desired_tile_stride, hw_tile_stride);
643
644 up_read(&pd->driver->sem);
645
646 if (pd->hw_context != -1)
647 psb_mmu_flush(pd->driver);
648}
649
650int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, uint32_t start_pfn,
651 unsigned long address, uint32_t num_pages,
652 int type)
653{
654 struct psb_mmu_pt *pt;
655 uint32_t pte;
656 unsigned long addr;
657 unsigned long end;
658 unsigned long next;
659 unsigned long f_address = address;
660 int ret = -ENOMEM;
661
662 down_read(&pd->driver->sem);
663
664 addr = address;
665 end = addr + (num_pages << PAGE_SHIFT);
666
667 do {
668 next = psb_pd_addr_end(addr, end);
669 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
670 if (!pt) {
671 ret = -ENOMEM;
672 goto out;
673 }
674 do {
675 pte = psb_mmu_mask_pte(start_pfn++, type);
676 psb_mmu_set_pte(pt, addr, pte);
677 pt->count++;
678 } while (addr += PAGE_SIZE, addr < next);
679 psb_mmu_pt_unmap_unlock(pt);
680
681 } while (addr = next, next != end);
682 ret = 0;
683
684out:
685 if (pd->hw_context != -1)
686 psb_mmu_flush_ptes(pd, f_address, num_pages, 1, 1);
687
688 up_read(&pd->driver->sem);
689
690 if (pd->hw_context != -1)
691 psb_mmu_flush(pd->driver);
692
693 return 0;
694}
695
696int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
697 unsigned long address, uint32_t num_pages,
698 uint32_t desired_tile_stride, uint32_t hw_tile_stride,
699 int type)
700{
701 struct psb_mmu_pt *pt;
702 uint32_t rows = 1;
703 uint32_t i;
704 uint32_t pte;
705 unsigned long addr;
706 unsigned long end;
707 unsigned long next;
708 unsigned long add;
709 unsigned long row_add;
710 unsigned long f_address = address;
711 int ret = -ENOMEM;
712
713 if (hw_tile_stride) {
714 if (num_pages % desired_tile_stride != 0)
715 return -EINVAL;
716 rows = num_pages / desired_tile_stride;
717 } else {
718 desired_tile_stride = num_pages;
719 }
720
721 add = desired_tile_stride << PAGE_SHIFT;
722 row_add = hw_tile_stride << PAGE_SHIFT;
723
724 down_read(&pd->driver->sem);
725
726 for (i = 0; i < rows; ++i) {
727
728 addr = address;
729 end = addr + add;
730
731 do {
732 next = psb_pd_addr_end(addr, end);
733 pt = psb_mmu_pt_alloc_map_lock(pd, addr);
734 if (!pt)
735 goto out;
736 do {
737 pte = psb_mmu_mask_pte(page_to_pfn(*pages++),
738 type);
739 psb_mmu_set_pte(pt, addr, pte);
740 pt->count++;
741 } while (addr += PAGE_SIZE, addr < next);
742 psb_mmu_pt_unmap_unlock(pt);
743
744 } while (addr = next, next != end);
745
746 address += row_add;
747 }
748
749 ret = 0;
750out:
751 if (pd->hw_context != -1)
752 psb_mmu_flush_ptes(pd, f_address, num_pages,
753 desired_tile_stride, hw_tile_stride);
754
755 up_read(&pd->driver->sem);
756
757 if (pd->hw_context != -1)
758 psb_mmu_flush(pd->driver);
759
760 return ret;
761}
762
763int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
764 unsigned long *pfn)
765{
766 int ret;
767 struct psb_mmu_pt *pt;
768 uint32_t tmp;
769 spinlock_t *lock = &pd->driver->lock;
770
771 down_read(&pd->driver->sem);
772 pt = psb_mmu_pt_map_lock(pd, virtual);
773 if (!pt) {
774 uint32_t *v;
775
776 spin_lock(lock);
777 v = kmap_atomic(pd->p);
778 tmp = v[psb_mmu_pd_index(virtual)];
779 kunmap_atomic(v);
780 spin_unlock(lock);
781
782 if (tmp != pd->invalid_pde || !(tmp & PSB_PTE_VALID) ||
783 !(pd->invalid_pte & PSB_PTE_VALID)) {
784 ret = -EINVAL;
785 goto out;
786 }
787 ret = 0;
788 *pfn = pd->invalid_pte >> PAGE_SHIFT;
789 goto out;
790 }
791 tmp = pt->v[psb_mmu_pt_index(virtual)];
792 if (!(tmp & PSB_PTE_VALID)) {
793 ret = -EINVAL;
794 } else {
795 ret = 0;
796 *pfn = tmp >> PAGE_SHIFT;
797 }
798 psb_mmu_pt_unmap_unlock(pt);
799out:
800 up_read(&pd->driver->sem);
801 return ret;
802}