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1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/of.h>
22
23#define DRIVER_NAME "zynq-gpio"
24
25/* Maximum banks */
26#define ZYNQ_GPIO_MAX_BANK 4
27#define ZYNQMP_GPIO_MAX_BANK 6
28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
62
63
64/* Register offsets for the GPIO device */
65/* LSW Mask & Data -WO */
66#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
67/* MSW Mask & Data -WO */
68#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
69/* Data Register-RW */
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
99/**
100 * struct zynq_gpio - gpio device private data structure
101 * @chip: instance of the gpio_chip
102 * @base_addr: base address of the GPIO device
103 * @clk: clock resource for this controller
104 * @irq: interrupt for the GPIO device
105 * @p_data: pointer to platform data
106 */
107struct zynq_gpio {
108 struct gpio_chip chip;
109 void __iomem *base_addr;
110 struct clk *clk;
111 int irq;
112 const struct zynq_platform_data *p_data;
113};
114
115/**
116 * struct zynq_platform_data - zynq gpio platform data structure
117 * @label: string to store in gpio->label
118 * @ngpio: max number of gpio pins
119 * @max_bank: maximum number of gpio banks
120 * @bank_min: this array represents bank's min pin
121 * @bank_max: this array represents bank's max pin
122*/
123struct zynq_platform_data {
124 const char *label;
125 u16 ngpio;
126 int max_bank;
127 int bank_min[ZYNQMP_GPIO_MAX_BANK];
128 int bank_max[ZYNQMP_GPIO_MAX_BANK];
129};
130
131static struct irq_chip zynq_gpio_level_irqchip;
132static struct irq_chip zynq_gpio_edge_irqchip;
133
134/**
135 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
136 * for a given pin in the GPIO device
137 * @pin_num: gpio pin number within the device
138 * @bank_num: an output parameter used to return the bank number of the gpio
139 * pin
140 * @bank_pin_num: an output parameter used to return pin number within a bank
141 * for the given gpio pin
142 *
143 * Returns the bank number and pin offset within the bank.
144 */
145static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
146 unsigned int *bank_num,
147 unsigned int *bank_pin_num,
148 struct zynq_gpio *gpio)
149{
150 int bank;
151
152 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
153 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
154 (pin_num <= gpio->p_data->bank_max[bank])) {
155 *bank_num = bank;
156 *bank_pin_num = pin_num -
157 gpio->p_data->bank_min[bank];
158 return;
159 }
160 }
161
162 /* default */
163 WARN(true, "invalid GPIO pin number: %u", pin_num);
164 *bank_num = 0;
165 *bank_pin_num = 0;
166}
167
168/**
169 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
170 * @chip: gpio_chip instance to be worked on
171 * @pin: gpio pin number within the device
172 *
173 * This function reads the state of the specified pin of the GPIO device.
174 *
175 * Return: 0 if the pin is low, 1 if pin is high.
176 */
177static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
178{
179 u32 data;
180 unsigned int bank_num, bank_pin_num;
181 struct zynq_gpio *gpio = gpiochip_get_data(chip);
182
183 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
184
185 data = readl_relaxed(gpio->base_addr +
186 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
187
188 return (data >> bank_pin_num) & 1;
189}
190
191/**
192 * zynq_gpio_set_value - Modify the state of the pin with specified value
193 * @chip: gpio_chip instance to be worked on
194 * @pin: gpio pin number within the device
195 * @state: value used to modify the state of the specified pin
196 *
197 * This function calculates the register offset (i.e to lower 16 bits or
198 * upper 16 bits) based on the given pin number and sets the state of a
199 * gpio pin to the specified value. The state is either 0 or non-zero.
200 */
201static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
202 int state)
203{
204 unsigned int reg_offset, bank_num, bank_pin_num;
205 struct zynq_gpio *gpio = gpiochip_get_data(chip);
206
207 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
208
209 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
210 /* only 16 data bits in bit maskable reg */
211 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
212 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
213 } else {
214 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
215 }
216
217 /*
218 * get the 32 bit value to be written to the mask/data register where
219 * the upper 16 bits is the mask and lower 16 bits is the data
220 */
221 state = !!state;
222 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
223 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
224
225 writel_relaxed(state, gpio->base_addr + reg_offset);
226}
227
228/**
229 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
230 * @chip: gpio_chip instance to be worked on
231 * @pin: gpio pin number within the device
232 *
233 * This function uses the read-modify-write sequence to set the direction of
234 * the gpio pin as input.
235 *
236 * Return: 0 always
237 */
238static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
239{
240 u32 reg;
241 unsigned int bank_num, bank_pin_num;
242 struct zynq_gpio *gpio = gpiochip_get_data(chip);
243
244 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
245
246 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
247 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
248 return -EINVAL;
249
250 /* clear the bit in direction mode reg to set the pin as input */
251 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
252 reg &= ~BIT(bank_pin_num);
253 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
254
255 return 0;
256}
257
258/**
259 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
260 * @chip: gpio_chip instance to be worked on
261 * @pin: gpio pin number within the device
262 * @state: value to be written to specified pin
263 *
264 * This function sets the direction of specified GPIO pin as output, configures
265 * the Output Enable register for the pin and uses zynq_gpio_set to set
266 * the state of the pin to the value specified.
267 *
268 * Return: 0 always
269 */
270static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
271 int state)
272{
273 u32 reg;
274 unsigned int bank_num, bank_pin_num;
275 struct zynq_gpio *gpio = gpiochip_get_data(chip);
276
277 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
278
279 /* set the GPIO pin as output */
280 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
281 reg |= BIT(bank_pin_num);
282 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
283
284 /* configure the output enable reg for the pin */
285 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
286 reg |= BIT(bank_pin_num);
287 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
288
289 /* set the state of the pin */
290 zynq_gpio_set_value(chip, pin, state);
291 return 0;
292}
293
294/**
295 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
296 * @irq_data: per irq and chip data passed down to chip functions
297 *
298 * This function calculates gpio pin number from irq number and sets the
299 * bit in the Interrupt Disable register of the corresponding bank to disable
300 * interrupts for that pin.
301 */
302static void zynq_gpio_irq_mask(struct irq_data *irq_data)
303{
304 unsigned int device_pin_num, bank_num, bank_pin_num;
305 struct zynq_gpio *gpio =
306 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
307
308 device_pin_num = irq_data->hwirq;
309 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
310 writel_relaxed(BIT(bank_pin_num),
311 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
312}
313
314/**
315 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
316 * @irq_data: irq data containing irq number of gpio pin for the interrupt
317 * to enable
318 *
319 * This function calculates the gpio pin number from irq number and sets the
320 * bit in the Interrupt Enable register of the corresponding bank to enable
321 * interrupts for that pin.
322 */
323static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
324{
325 unsigned int device_pin_num, bank_num, bank_pin_num;
326 struct zynq_gpio *gpio =
327 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
328
329 device_pin_num = irq_data->hwirq;
330 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
331 writel_relaxed(BIT(bank_pin_num),
332 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
333}
334
335/**
336 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
337 * @irq_data: irq data containing irq number of gpio pin for the interrupt
338 * to ack
339 *
340 * This function calculates gpio pin number from irq number and sets the bit
341 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
342 */
343static void zynq_gpio_irq_ack(struct irq_data *irq_data)
344{
345 unsigned int device_pin_num, bank_num, bank_pin_num;
346 struct zynq_gpio *gpio =
347 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
348
349 device_pin_num = irq_data->hwirq;
350 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
351 writel_relaxed(BIT(bank_pin_num),
352 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
353}
354
355/**
356 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
357 * @irq_data: irq data containing irq number of gpio pin for the interrupt
358 * to enable
359 *
360 * Clears the INTSTS bit and unmasks the given interrupt.
361 */
362static void zynq_gpio_irq_enable(struct irq_data *irq_data)
363{
364 /*
365 * The Zynq GPIO controller does not disable interrupt detection when
366 * the interrupt is masked and only disables the propagation of the
367 * interrupt. This means when the controller detects an interrupt
368 * condition while the interrupt is logically disabled it will propagate
369 * that interrupt event once the interrupt is enabled. This will cause
370 * the interrupt consumer to see spurious interrupts to prevent this
371 * first make sure that the interrupt is not asserted and then enable
372 * it.
373 */
374 zynq_gpio_irq_ack(irq_data);
375 zynq_gpio_irq_unmask(irq_data);
376}
377
378/**
379 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
380 * @irq_data: irq data containing irq number of gpio pin
381 * @type: interrupt type that is to be set for the gpio pin
382 *
383 * This function gets the gpio pin number and its bank from the gpio pin number
384 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
385 *
386 * Return: 0, negative error otherwise.
387 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
388 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
389 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
390 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
391 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
392 */
393static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
394{
395 u32 int_type, int_pol, int_any;
396 unsigned int device_pin_num, bank_num, bank_pin_num;
397 struct zynq_gpio *gpio =
398 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
399
400 device_pin_num = irq_data->hwirq;
401 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
402
403 int_type = readl_relaxed(gpio->base_addr +
404 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
405 int_pol = readl_relaxed(gpio->base_addr +
406 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
407 int_any = readl_relaxed(gpio->base_addr +
408 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
409
410 /*
411 * based on the type requested, configure the INT_TYPE, INT_POLARITY
412 * and INT_ANY registers
413 */
414 switch (type) {
415 case IRQ_TYPE_EDGE_RISING:
416 int_type |= BIT(bank_pin_num);
417 int_pol |= BIT(bank_pin_num);
418 int_any &= ~BIT(bank_pin_num);
419 break;
420 case IRQ_TYPE_EDGE_FALLING:
421 int_type |= BIT(bank_pin_num);
422 int_pol &= ~BIT(bank_pin_num);
423 int_any &= ~BIT(bank_pin_num);
424 break;
425 case IRQ_TYPE_EDGE_BOTH:
426 int_type |= BIT(bank_pin_num);
427 int_any |= BIT(bank_pin_num);
428 break;
429 case IRQ_TYPE_LEVEL_HIGH:
430 int_type &= ~BIT(bank_pin_num);
431 int_pol |= BIT(bank_pin_num);
432 break;
433 case IRQ_TYPE_LEVEL_LOW:
434 int_type &= ~BIT(bank_pin_num);
435 int_pol &= ~BIT(bank_pin_num);
436 break;
437 default:
438 return -EINVAL;
439 }
440
441 writel_relaxed(int_type,
442 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
443 writel_relaxed(int_pol,
444 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
445 writel_relaxed(int_any,
446 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
447
448 if (type & IRQ_TYPE_LEVEL_MASK) {
449 irq_set_chip_handler_name_locked(irq_data,
450 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
451 } else {
452 irq_set_chip_handler_name_locked(irq_data,
453 &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
454 }
455
456 return 0;
457}
458
459static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
460{
461 struct zynq_gpio *gpio =
462 gpiochip_get_data(irq_data_get_irq_chip_data(data));
463
464 irq_set_irq_wake(gpio->irq, on);
465
466 return 0;
467}
468
469/* irq chip descriptor */
470static struct irq_chip zynq_gpio_level_irqchip = {
471 .name = DRIVER_NAME,
472 .irq_enable = zynq_gpio_irq_enable,
473 .irq_eoi = zynq_gpio_irq_ack,
474 .irq_mask = zynq_gpio_irq_mask,
475 .irq_unmask = zynq_gpio_irq_unmask,
476 .irq_set_type = zynq_gpio_set_irq_type,
477 .irq_set_wake = zynq_gpio_set_wake,
478 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
479 IRQCHIP_MASK_ON_SUSPEND,
480};
481
482static struct irq_chip zynq_gpio_edge_irqchip = {
483 .name = DRIVER_NAME,
484 .irq_enable = zynq_gpio_irq_enable,
485 .irq_ack = zynq_gpio_irq_ack,
486 .irq_mask = zynq_gpio_irq_mask,
487 .irq_unmask = zynq_gpio_irq_unmask,
488 .irq_set_type = zynq_gpio_set_irq_type,
489 .irq_set_wake = zynq_gpio_set_wake,
490 .flags = IRQCHIP_MASK_ON_SUSPEND,
491};
492
493static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
494 unsigned int bank_num,
495 unsigned long pending)
496{
497 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
498 struct irq_domain *irqdomain = gpio->chip.irqdomain;
499 int offset;
500
501 if (!pending)
502 return;
503
504 for_each_set_bit(offset, &pending, 32) {
505 unsigned int gpio_irq;
506
507 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
508 generic_handle_irq(gpio_irq);
509 }
510}
511
512/**
513 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
514 * @irq: irq number of the gpio bank where interrupt has occurred
515 * @desc: irq descriptor instance of the 'irq'
516 *
517 * This function reads the Interrupt Status Register of each bank to get the
518 * gpio pin number which has triggered an interrupt. It then acks the triggered
519 * interrupt and calls the pin specific handler set by the higher layer
520 * application for that pin.
521 * Note: A bug is reported if no handler is set for the gpio pin.
522 */
523static void zynq_gpio_irqhandler(struct irq_desc *desc)
524{
525 u32 int_sts, int_enb;
526 unsigned int bank_num;
527 struct zynq_gpio *gpio =
528 gpiochip_get_data(irq_desc_get_handler_data(desc));
529 struct irq_chip *irqchip = irq_desc_get_chip(desc);
530
531 chained_irq_enter(irqchip, desc);
532
533 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
534 int_sts = readl_relaxed(gpio->base_addr +
535 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
536 int_enb = readl_relaxed(gpio->base_addr +
537 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
538 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
539 }
540
541 chained_irq_exit(irqchip, desc);
542}
543
544static int __maybe_unused zynq_gpio_suspend(struct device *dev)
545{
546 struct platform_device *pdev = to_platform_device(dev);
547 int irq = platform_get_irq(pdev, 0);
548 struct irq_data *data = irq_get_irq_data(irq);
549
550 if (!irqd_is_wakeup_set(data))
551 return pm_runtime_force_suspend(dev);
552
553 return 0;
554}
555
556static int __maybe_unused zynq_gpio_resume(struct device *dev)
557{
558 struct platform_device *pdev = to_platform_device(dev);
559 int irq = platform_get_irq(pdev, 0);
560 struct irq_data *data = irq_get_irq_data(irq);
561
562 if (!irqd_is_wakeup_set(data))
563 return pm_runtime_force_resume(dev);
564
565 return 0;
566}
567
568static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
569{
570 struct platform_device *pdev = to_platform_device(dev);
571 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
572
573 clk_disable_unprepare(gpio->clk);
574
575 return 0;
576}
577
578static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
579{
580 struct platform_device *pdev = to_platform_device(dev);
581 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
582
583 return clk_prepare_enable(gpio->clk);
584}
585
586static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
587{
588 int ret;
589
590 ret = pm_runtime_get_sync(chip->parent);
591
592 /*
593 * If the device is already active pm_runtime_get() will return 1 on
594 * success, but gpio_request still needs to return 0.
595 */
596 return ret < 0 ? ret : 0;
597}
598
599static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
600{
601 pm_runtime_put(chip->parent);
602}
603
604static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
605 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
606 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
607 zynq_gpio_runtime_resume, NULL)
608};
609
610static const struct zynq_platform_data zynqmp_gpio_def = {
611 .label = "zynqmp_gpio",
612 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
613 .max_bank = ZYNQMP_GPIO_MAX_BANK,
614 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
615 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
616 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
617 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
618 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
619 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
620 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
621 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
622 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
623 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
624 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
625 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
626};
627
628static const struct zynq_platform_data zynq_gpio_def = {
629 .label = "zynq_gpio",
630 .ngpio = ZYNQ_GPIO_NR_GPIOS,
631 .max_bank = ZYNQ_GPIO_MAX_BANK,
632 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
633 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
634 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
635 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
636 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
637 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
638 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
639 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
640};
641
642static const struct of_device_id zynq_gpio_of_match[] = {
643 { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def },
644 { .compatible = "xlnx,zynqmp-gpio-1.0",
645 .data = (void *)&zynqmp_gpio_def },
646 { /* end of table */ }
647};
648MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
649
650/**
651 * zynq_gpio_probe - Initialization method for a zynq_gpio device
652 * @pdev: platform device instance
653 *
654 * This function allocates memory resources for the gpio device and registers
655 * all the banks of the device. It will also set up interrupts for the gpio
656 * pins.
657 * Note: Interrupts are disabled for all the banks during initialization.
658 *
659 * Return: 0 on success, negative error otherwise.
660 */
661static int zynq_gpio_probe(struct platform_device *pdev)
662{
663 int ret, bank_num;
664 struct zynq_gpio *gpio;
665 struct gpio_chip *chip;
666 struct resource *res;
667 const struct of_device_id *match;
668
669 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
670 if (!gpio)
671 return -ENOMEM;
672
673 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
674 if (!match) {
675 dev_err(&pdev->dev, "of_match_node() failed\n");
676 return -EINVAL;
677 }
678 gpio->p_data = match->data;
679 platform_set_drvdata(pdev, gpio);
680
681 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
682 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
683 if (IS_ERR(gpio->base_addr))
684 return PTR_ERR(gpio->base_addr);
685
686 gpio->irq = platform_get_irq(pdev, 0);
687 if (gpio->irq < 0) {
688 dev_err(&pdev->dev, "invalid IRQ\n");
689 return gpio->irq;
690 }
691
692 /* configure the gpio chip */
693 chip = &gpio->chip;
694 chip->label = gpio->p_data->label;
695 chip->owner = THIS_MODULE;
696 chip->parent = &pdev->dev;
697 chip->get = zynq_gpio_get_value;
698 chip->set = zynq_gpio_set_value;
699 chip->request = zynq_gpio_request;
700 chip->free = zynq_gpio_free;
701 chip->direction_input = zynq_gpio_dir_in;
702 chip->direction_output = zynq_gpio_dir_out;
703 chip->base = -1;
704 chip->ngpio = gpio->p_data->ngpio;
705
706 /* Retrieve GPIO clock */
707 gpio->clk = devm_clk_get(&pdev->dev, NULL);
708 if (IS_ERR(gpio->clk)) {
709 dev_err(&pdev->dev, "input clock not found.\n");
710 return PTR_ERR(gpio->clk);
711 }
712
713 pm_runtime_enable(&pdev->dev);
714 ret = pm_runtime_get_sync(&pdev->dev);
715 if (ret < 0)
716 return ret;
717
718 /* report a bug if gpio chip registration fails */
719 ret = gpiochip_add_data(chip, gpio);
720 if (ret) {
721 dev_err(&pdev->dev, "Failed to add gpio chip\n");
722 goto err_pm_put;
723 }
724
725 /* disable interrupts for all banks */
726 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
727 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
728 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
729
730 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
731 handle_level_irq, IRQ_TYPE_NONE);
732 if (ret) {
733 dev_err(&pdev->dev, "Failed to add irq chip\n");
734 goto err_rm_gpiochip;
735 }
736
737 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
738 zynq_gpio_irqhandler);
739
740 pm_runtime_put(&pdev->dev);
741
742 return 0;
743
744err_rm_gpiochip:
745 gpiochip_remove(chip);
746err_pm_put:
747 pm_runtime_put(&pdev->dev);
748
749 return ret;
750}
751
752/**
753 * zynq_gpio_remove - Driver removal function
754 * @pdev: platform device instance
755 *
756 * Return: 0 always
757 */
758static int zynq_gpio_remove(struct platform_device *pdev)
759{
760 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
761
762 pm_runtime_get_sync(&pdev->dev);
763 gpiochip_remove(&gpio->chip);
764 clk_disable_unprepare(gpio->clk);
765 device_set_wakeup_capable(&pdev->dev, 0);
766 pm_runtime_disable(&pdev->dev);
767 return 0;
768}
769
770static struct platform_driver zynq_gpio_driver = {
771 .driver = {
772 .name = DRIVER_NAME,
773 .pm = &zynq_gpio_dev_pm_ops,
774 .of_match_table = zynq_gpio_of_match,
775 },
776 .probe = zynq_gpio_probe,
777 .remove = zynq_gpio_remove,
778};
779
780/**
781 * zynq_gpio_init - Initial driver registration call
782 *
783 * Return: value from platform_driver_register
784 */
785static int __init zynq_gpio_init(void)
786{
787 return platform_driver_register(&zynq_gpio_driver);
788}
789postcore_initcall(zynq_gpio_init);
790
791static void __exit zynq_gpio_exit(void)
792{
793 platform_driver_unregister(&zynq_gpio_driver);
794}
795module_exit(zynq_gpio_exit);
796
797MODULE_AUTHOR("Xilinx Inc.");
798MODULE_DESCRIPTION("Zynq GPIO driver");
799MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Xilinx Zynq GPIO device driver
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/of.h>
19
20#define DRIVER_NAME "zynq-gpio"
21
22/* Maximum banks */
23#define ZYNQ_GPIO_MAX_BANK 4
24#define ZYNQMP_GPIO_MAX_BANK 6
25#define VERSAL_GPIO_MAX_BANK 4
26#define PMC_GPIO_MAX_BANK 5
27#define VERSAL_UNUSED_BANKS 2
28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
62
63/* Register offsets for the GPIO device */
64/* LSW Mask & Data -WO */
65#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
66/* MSW Mask & Data -WO */
67#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
68/* Data Register-RW */
69#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
102#define GPIO_QUIRK_VERSAL BIT(2)
103
104struct gpio_regs {
105 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
106 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
107 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
108 u32 outen[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
113 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
114};
115
116/**
117 * struct zynq_gpio - gpio device private data structure
118 * @chip: instance of the gpio_chip
119 * @base_addr: base address of the GPIO device
120 * @clk: clock resource for this controller
121 * @irq: interrupt for the GPIO device
122 * @p_data: pointer to platform data
123 * @context: context registers
124 * @dirlock: lock used for direction in/out synchronization
125 */
126struct zynq_gpio {
127 struct gpio_chip chip;
128 void __iomem *base_addr;
129 struct clk *clk;
130 int irq;
131 const struct zynq_platform_data *p_data;
132 struct gpio_regs context;
133 spinlock_t dirlock; /* lock */
134};
135
136/**
137 * struct zynq_platform_data - zynq gpio platform data structure
138 * @label: string to store in gpio->label
139 * @quirks: Flags is used to identify the platform
140 * @ngpio: max number of gpio pins
141 * @max_bank: maximum number of gpio banks
142 * @bank_min: this array represents bank's min pin
143 * @bank_max: this array represents bank's max pin
144 */
145struct zynq_platform_data {
146 const char *label;
147 u32 quirks;
148 u16 ngpio;
149 int max_bank;
150 int bank_min[ZYNQMP_GPIO_MAX_BANK];
151 int bank_max[ZYNQMP_GPIO_MAX_BANK];
152};
153
154static struct irq_chip zynq_gpio_level_irqchip;
155static struct irq_chip zynq_gpio_edge_irqchip;
156
157/**
158 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
159 * @gpio: Pointer to driver data struct
160 *
161 * Return: 0 if zynqmp, 1 if zynq.
162 */
163static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
164{
165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
166}
167
168/**
169 * gpio_data_ro_bug - test if HW bug exists or not
170 * @gpio: Pointer to driver data struct
171 *
172 * Return: 0 if bug doesnot exist, 1 if bug exists.
173 */
174static int gpio_data_ro_bug(struct zynq_gpio *gpio)
175{
176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
177}
178
179/**
180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
181 * for a given pin in the GPIO device
182 * @pin_num: gpio pin number within the device
183 * @bank_num: an output parameter used to return the bank number of the gpio
184 * pin
185 * @bank_pin_num: an output parameter used to return pin number within a bank
186 * for the given gpio pin
187 * @gpio: gpio device data structure
188 *
189 * Returns the bank number and pin offset within the bank.
190 */
191static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
192 unsigned int *bank_num,
193 unsigned int *bank_pin_num,
194 struct zynq_gpio *gpio)
195{
196 int bank;
197
198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
199 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
200 (pin_num <= gpio->p_data->bank_max[bank])) {
201 *bank_num = bank;
202 *bank_pin_num = pin_num -
203 gpio->p_data->bank_min[bank];
204 return;
205 }
206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
207 bank = bank + VERSAL_UNUSED_BANKS;
208 }
209
210 /* default */
211 WARN(true, "invalid GPIO pin number: %u", pin_num);
212 *bank_num = 0;
213 *bank_pin_num = 0;
214}
215
216/**
217 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
218 * @chip: gpio_chip instance to be worked on
219 * @pin: gpio pin number within the device
220 *
221 * This function reads the state of the specified pin of the GPIO device.
222 *
223 * Return: 0 if the pin is low, 1 if pin is high.
224 */
225static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
226{
227 u32 data;
228 unsigned int bank_num, bank_pin_num;
229 struct zynq_gpio *gpio = gpiochip_get_data(chip);
230
231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
232
233 if (gpio_data_ro_bug(gpio)) {
234 if (zynq_gpio_is_zynq(gpio)) {
235 if (bank_num <= 1) {
236 data = readl_relaxed(gpio->base_addr +
237 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
238 } else {
239 data = readl_relaxed(gpio->base_addr +
240 ZYNQ_GPIO_DATA_OFFSET(bank_num));
241 }
242 } else {
243 if (bank_num <= 2) {
244 data = readl_relaxed(gpio->base_addr +
245 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
246 } else {
247 data = readl_relaxed(gpio->base_addr +
248 ZYNQ_GPIO_DATA_OFFSET(bank_num));
249 }
250 }
251 } else {
252 data = readl_relaxed(gpio->base_addr +
253 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
254 }
255 return (data >> bank_pin_num) & 1;
256}
257
258/**
259 * zynq_gpio_set_value - Modify the state of the pin with specified value
260 * @chip: gpio_chip instance to be worked on
261 * @pin: gpio pin number within the device
262 * @state: value used to modify the state of the specified pin
263 *
264 * This function calculates the register offset (i.e to lower 16 bits or
265 * upper 16 bits) based on the given pin number and sets the state of a
266 * gpio pin to the specified value. The state is either 0 or non-zero.
267 */
268static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
269 int state)
270{
271 unsigned int reg_offset, bank_num, bank_pin_num;
272 struct zynq_gpio *gpio = gpiochip_get_data(chip);
273
274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
275
276 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
277 /* only 16 data bits in bit maskable reg */
278 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
279 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
280 } else {
281 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
282 }
283
284 /*
285 * get the 32 bit value to be written to the mask/data register where
286 * the upper 16 bits is the mask and lower 16 bits is the data
287 */
288 state = !!state;
289 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
290 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
291
292 writel_relaxed(state, gpio->base_addr + reg_offset);
293}
294
295/**
296 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
297 * @chip: gpio_chip instance to be worked on
298 * @pin: gpio pin number within the device
299 *
300 * This function uses the read-modify-write sequence to set the direction of
301 * the gpio pin as input.
302 *
303 * Return: 0 always
304 */
305static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
306{
307 u32 reg;
308 unsigned int bank_num, bank_pin_num;
309 unsigned long flags;
310 struct zynq_gpio *gpio = gpiochip_get_data(chip);
311
312 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
313
314 /*
315 * On zynq bank 0 pins 7 and 8 are special and cannot be used
316 * as inputs.
317 */
318 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
319 (bank_pin_num == 7 || bank_pin_num == 8))
320 return -EINVAL;
321
322 /* clear the bit in direction mode reg to set the pin as input */
323 spin_lock_irqsave(&gpio->dirlock, flags);
324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
325 reg &= ~BIT(bank_pin_num);
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
327 spin_unlock_irqrestore(&gpio->dirlock, flags);
328
329 return 0;
330}
331
332/**
333 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
334 * @chip: gpio_chip instance to be worked on
335 * @pin: gpio pin number within the device
336 * @state: value to be written to specified pin
337 *
338 * This function sets the direction of specified GPIO pin as output, configures
339 * the Output Enable register for the pin and uses zynq_gpio_set to set
340 * the state of the pin to the value specified.
341 *
342 * Return: 0 always
343 */
344static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
345 int state)
346{
347 u32 reg;
348 unsigned int bank_num, bank_pin_num;
349 unsigned long flags;
350 struct zynq_gpio *gpio = gpiochip_get_data(chip);
351
352 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
353
354 /* set the GPIO pin as output */
355 spin_lock_irqsave(&gpio->dirlock, flags);
356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
357 reg |= BIT(bank_pin_num);
358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
359
360 /* configure the output enable reg for the pin */
361 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
362 reg |= BIT(bank_pin_num);
363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
364 spin_unlock_irqrestore(&gpio->dirlock, flags);
365
366 /* set the state of the pin */
367 zynq_gpio_set_value(chip, pin, state);
368 return 0;
369}
370
371/**
372 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
373 * @chip: gpio_chip instance to be worked on
374 * @pin: gpio pin number within the device
375 *
376 * This function returns the direction of the specified GPIO.
377 *
378 * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
379 */
380static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
381{
382 u32 reg;
383 unsigned int bank_num, bank_pin_num;
384 struct zynq_gpio *gpio = gpiochip_get_data(chip);
385
386 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
387
388 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
389
390 if (reg & BIT(bank_pin_num))
391 return GPIO_LINE_DIRECTION_OUT;
392
393 return GPIO_LINE_DIRECTION_IN;
394}
395
396/**
397 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
398 * @irq_data: per irq and chip data passed down to chip functions
399 *
400 * This function calculates gpio pin number from irq number and sets the
401 * bit in the Interrupt Disable register of the corresponding bank to disable
402 * interrupts for that pin.
403 */
404static void zynq_gpio_irq_mask(struct irq_data *irq_data)
405{
406 unsigned int device_pin_num, bank_num, bank_pin_num;
407 struct zynq_gpio *gpio =
408 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
409
410 device_pin_num = irq_data->hwirq;
411 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
412 writel_relaxed(BIT(bank_pin_num),
413 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
414}
415
416/**
417 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
418 * @irq_data: irq data containing irq number of gpio pin for the interrupt
419 * to enable
420 *
421 * This function calculates the gpio pin number from irq number and sets the
422 * bit in the Interrupt Enable register of the corresponding bank to enable
423 * interrupts for that pin.
424 */
425static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
426{
427 unsigned int device_pin_num, bank_num, bank_pin_num;
428 struct zynq_gpio *gpio =
429 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
430
431 device_pin_num = irq_data->hwirq;
432 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
433 writel_relaxed(BIT(bank_pin_num),
434 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
435}
436
437/**
438 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
439 * @irq_data: irq data containing irq number of gpio pin for the interrupt
440 * to ack
441 *
442 * This function calculates gpio pin number from irq number and sets the bit
443 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
444 */
445static void zynq_gpio_irq_ack(struct irq_data *irq_data)
446{
447 unsigned int device_pin_num, bank_num, bank_pin_num;
448 struct zynq_gpio *gpio =
449 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
450
451 device_pin_num = irq_data->hwirq;
452 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
453 writel_relaxed(BIT(bank_pin_num),
454 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
455}
456
457/**
458 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
459 * @irq_data: irq data containing irq number of gpio pin for the interrupt
460 * to enable
461 *
462 * Clears the INTSTS bit and unmasks the given interrupt.
463 */
464static void zynq_gpio_irq_enable(struct irq_data *irq_data)
465{
466 /*
467 * The Zynq GPIO controller does not disable interrupt detection when
468 * the interrupt is masked and only disables the propagation of the
469 * interrupt. This means when the controller detects an interrupt
470 * condition while the interrupt is logically disabled it will propagate
471 * that interrupt event once the interrupt is enabled. This will cause
472 * the interrupt consumer to see spurious interrupts to prevent this
473 * first make sure that the interrupt is not asserted and then enable
474 * it.
475 */
476 zynq_gpio_irq_ack(irq_data);
477 zynq_gpio_irq_unmask(irq_data);
478}
479
480/**
481 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
482 * @irq_data: irq data containing irq number of gpio pin
483 * @type: interrupt type that is to be set for the gpio pin
484 *
485 * This function gets the gpio pin number and its bank from the gpio pin number
486 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
487 *
488 * Return: 0, negative error otherwise.
489 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
490 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
491 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
492 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
493 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
494 */
495static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
496{
497 u32 int_type, int_pol, int_any;
498 unsigned int device_pin_num, bank_num, bank_pin_num;
499 struct zynq_gpio *gpio =
500 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
501
502 device_pin_num = irq_data->hwirq;
503 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
504
505 int_type = readl_relaxed(gpio->base_addr +
506 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
507 int_pol = readl_relaxed(gpio->base_addr +
508 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
509 int_any = readl_relaxed(gpio->base_addr +
510 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
511
512 /*
513 * based on the type requested, configure the INT_TYPE, INT_POLARITY
514 * and INT_ANY registers
515 */
516 switch (type) {
517 case IRQ_TYPE_EDGE_RISING:
518 int_type |= BIT(bank_pin_num);
519 int_pol |= BIT(bank_pin_num);
520 int_any &= ~BIT(bank_pin_num);
521 break;
522 case IRQ_TYPE_EDGE_FALLING:
523 int_type |= BIT(bank_pin_num);
524 int_pol &= ~BIT(bank_pin_num);
525 int_any &= ~BIT(bank_pin_num);
526 break;
527 case IRQ_TYPE_EDGE_BOTH:
528 int_type |= BIT(bank_pin_num);
529 int_any |= BIT(bank_pin_num);
530 break;
531 case IRQ_TYPE_LEVEL_HIGH:
532 int_type &= ~BIT(bank_pin_num);
533 int_pol |= BIT(bank_pin_num);
534 break;
535 case IRQ_TYPE_LEVEL_LOW:
536 int_type &= ~BIT(bank_pin_num);
537 int_pol &= ~BIT(bank_pin_num);
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 writel_relaxed(int_type,
544 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
545 writel_relaxed(int_pol,
546 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
547 writel_relaxed(int_any,
548 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
549
550 if (type & IRQ_TYPE_LEVEL_MASK)
551 irq_set_chip_handler_name_locked(irq_data,
552 &zynq_gpio_level_irqchip,
553 handle_fasteoi_irq, NULL);
554 else
555 irq_set_chip_handler_name_locked(irq_data,
556 &zynq_gpio_edge_irqchip,
557 handle_level_irq, NULL);
558
559 return 0;
560}
561
562static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
563{
564 struct zynq_gpio *gpio =
565 gpiochip_get_data(irq_data_get_irq_chip_data(data));
566
567 irq_set_irq_wake(gpio->irq, on);
568
569 return 0;
570}
571
572static int zynq_gpio_irq_reqres(struct irq_data *d)
573{
574 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
575 int ret;
576
577 ret = pm_runtime_resume_and_get(chip->parent);
578 if (ret < 0)
579 return ret;
580
581 return gpiochip_reqres_irq(chip, d->hwirq);
582}
583
584static void zynq_gpio_irq_relres(struct irq_data *d)
585{
586 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
587
588 gpiochip_relres_irq(chip, d->hwirq);
589 pm_runtime_put(chip->parent);
590}
591
592/* irq chip descriptor */
593static struct irq_chip zynq_gpio_level_irqchip = {
594 .name = DRIVER_NAME,
595 .irq_enable = zynq_gpio_irq_enable,
596 .irq_eoi = zynq_gpio_irq_ack,
597 .irq_mask = zynq_gpio_irq_mask,
598 .irq_unmask = zynq_gpio_irq_unmask,
599 .irq_set_type = zynq_gpio_set_irq_type,
600 .irq_set_wake = zynq_gpio_set_wake,
601 .irq_request_resources = zynq_gpio_irq_reqres,
602 .irq_release_resources = zynq_gpio_irq_relres,
603 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
604 IRQCHIP_MASK_ON_SUSPEND,
605};
606
607static struct irq_chip zynq_gpio_edge_irqchip = {
608 .name = DRIVER_NAME,
609 .irq_enable = zynq_gpio_irq_enable,
610 .irq_ack = zynq_gpio_irq_ack,
611 .irq_mask = zynq_gpio_irq_mask,
612 .irq_unmask = zynq_gpio_irq_unmask,
613 .irq_set_type = zynq_gpio_set_irq_type,
614 .irq_set_wake = zynq_gpio_set_wake,
615 .irq_request_resources = zynq_gpio_irq_reqres,
616 .irq_release_resources = zynq_gpio_irq_relres,
617 .flags = IRQCHIP_MASK_ON_SUSPEND,
618};
619
620static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
621 unsigned int bank_num,
622 unsigned long pending)
623{
624 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
625 struct irq_domain *irqdomain = gpio->chip.irq.domain;
626 int offset;
627
628 if (!pending)
629 return;
630
631 for_each_set_bit(offset, &pending, 32)
632 generic_handle_domain_irq(irqdomain, offset + bank_offset);
633}
634
635/**
636 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
637 * @desc: irq descriptor instance of the 'irq'
638 *
639 * This function reads the Interrupt Status Register of each bank to get the
640 * gpio pin number which has triggered an interrupt. It then acks the triggered
641 * interrupt and calls the pin specific handler set by the higher layer
642 * application for that pin.
643 * Note: A bug is reported if no handler is set for the gpio pin.
644 */
645static void zynq_gpio_irqhandler(struct irq_desc *desc)
646{
647 u32 int_sts, int_enb;
648 unsigned int bank_num;
649 struct zynq_gpio *gpio =
650 gpiochip_get_data(irq_desc_get_handler_data(desc));
651 struct irq_chip *irqchip = irq_desc_get_chip(desc);
652
653 chained_irq_enter(irqchip, desc);
654
655 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
656 int_sts = readl_relaxed(gpio->base_addr +
657 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
658 int_enb = readl_relaxed(gpio->base_addr +
659 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
660 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
661 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
662 bank_num = bank_num + VERSAL_UNUSED_BANKS;
663 }
664
665 chained_irq_exit(irqchip, desc);
666}
667
668static void zynq_gpio_save_context(struct zynq_gpio *gpio)
669{
670 unsigned int bank_num;
671
672 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
673 gpio->context.datalsw[bank_num] =
674 readl_relaxed(gpio->base_addr +
675 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
676 gpio->context.datamsw[bank_num] =
677 readl_relaxed(gpio->base_addr +
678 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
679 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
680 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
681 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
682 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
683 gpio->context.int_type[bank_num] =
684 readl_relaxed(gpio->base_addr +
685 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
686 gpio->context.int_polarity[bank_num] =
687 readl_relaxed(gpio->base_addr +
688 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
689 gpio->context.int_any[bank_num] =
690 readl_relaxed(gpio->base_addr +
691 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
692 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
693 bank_num = bank_num + VERSAL_UNUSED_BANKS;
694 }
695}
696
697static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
698{
699 unsigned int bank_num;
700
701 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
702 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
703 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
704 writel_relaxed(gpio->context.datalsw[bank_num],
705 gpio->base_addr +
706 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
707 writel_relaxed(gpio->context.datamsw[bank_num],
708 gpio->base_addr +
709 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
710 writel_relaxed(gpio->context.dirm[bank_num],
711 gpio->base_addr +
712 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
713 writel_relaxed(gpio->context.int_type[bank_num],
714 gpio->base_addr +
715 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
716 writel_relaxed(gpio->context.int_polarity[bank_num],
717 gpio->base_addr +
718 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
719 writel_relaxed(gpio->context.int_any[bank_num],
720 gpio->base_addr +
721 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
722 writel_relaxed(~(gpio->context.int_en[bank_num]),
723 gpio->base_addr +
724 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
725 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
726 bank_num = bank_num + VERSAL_UNUSED_BANKS;
727 }
728}
729
730static int __maybe_unused zynq_gpio_suspend(struct device *dev)
731{
732 struct zynq_gpio *gpio = dev_get_drvdata(dev);
733 struct irq_data *data = irq_get_irq_data(gpio->irq);
734
735 if (!data) {
736 dev_err(dev, "irq_get_irq_data() failed\n");
737 return -EINVAL;
738 }
739
740 if (!device_may_wakeup(dev))
741 disable_irq(gpio->irq);
742
743 if (!irqd_is_wakeup_set(data)) {
744 zynq_gpio_save_context(gpio);
745 return pm_runtime_force_suspend(dev);
746 }
747
748 return 0;
749}
750
751static int __maybe_unused zynq_gpio_resume(struct device *dev)
752{
753 struct zynq_gpio *gpio = dev_get_drvdata(dev);
754 struct irq_data *data = irq_get_irq_data(gpio->irq);
755 int ret;
756
757 if (!data) {
758 dev_err(dev, "irq_get_irq_data() failed\n");
759 return -EINVAL;
760 }
761
762 if (!device_may_wakeup(dev))
763 enable_irq(gpio->irq);
764
765 if (!irqd_is_wakeup_set(data)) {
766 ret = pm_runtime_force_resume(dev);
767 zynq_gpio_restore_context(gpio);
768 return ret;
769 }
770
771 return 0;
772}
773
774static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
775{
776 struct zynq_gpio *gpio = dev_get_drvdata(dev);
777
778 clk_disable_unprepare(gpio->clk);
779
780 return 0;
781}
782
783static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
784{
785 struct zynq_gpio *gpio = dev_get_drvdata(dev);
786
787 return clk_prepare_enable(gpio->clk);
788}
789
790static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
791{
792 int ret;
793
794 ret = pm_runtime_get_sync(chip->parent);
795
796 /*
797 * If the device is already active pm_runtime_get() will return 1 on
798 * success, but gpio_request still needs to return 0.
799 */
800 return ret < 0 ? ret : 0;
801}
802
803static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
804{
805 pm_runtime_put(chip->parent);
806}
807
808static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
809 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
810 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
811 zynq_gpio_runtime_resume, NULL)
812};
813
814static const struct zynq_platform_data versal_gpio_def = {
815 .label = "versal_gpio",
816 .quirks = GPIO_QUIRK_VERSAL,
817 .ngpio = 58,
818 .max_bank = VERSAL_GPIO_MAX_BANK,
819 .bank_min[0] = 0,
820 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
821 .bank_min[3] = 26,
822 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
823};
824
825static const struct zynq_platform_data pmc_gpio_def = {
826 .label = "pmc_gpio",
827 .ngpio = 116,
828 .max_bank = PMC_GPIO_MAX_BANK,
829 .bank_min[0] = 0,
830 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
831 .bank_min[1] = 26,
832 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
833 .bank_min[3] = 52,
834 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
835 .bank_min[4] = 84,
836 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
837};
838
839static const struct zynq_platform_data zynqmp_gpio_def = {
840 .label = "zynqmp_gpio",
841 .quirks = GPIO_QUIRK_DATA_RO_BUG,
842 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
843 .max_bank = ZYNQMP_GPIO_MAX_BANK,
844 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
845 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
846 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
847 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
848 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
849 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
850 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
851 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
852 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
853 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
854 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
855 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
856};
857
858static const struct zynq_platform_data zynq_gpio_def = {
859 .label = "zynq_gpio",
860 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
861 .ngpio = ZYNQ_GPIO_NR_GPIOS,
862 .max_bank = ZYNQ_GPIO_MAX_BANK,
863 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
864 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
865 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
866 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
867 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
868 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
869 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
870 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
871};
872
873static const struct of_device_id zynq_gpio_of_match[] = {
874 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
875 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
876 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
877 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
878 { /* end of table */ }
879};
880MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
881
882/**
883 * zynq_gpio_probe - Initialization method for a zynq_gpio device
884 * @pdev: platform device instance
885 *
886 * This function allocates memory resources for the gpio device and registers
887 * all the banks of the device. It will also set up interrupts for the gpio
888 * pins.
889 * Note: Interrupts are disabled for all the banks during initialization.
890 *
891 * Return: 0 on success, negative error otherwise.
892 */
893static int zynq_gpio_probe(struct platform_device *pdev)
894{
895 int ret, bank_num;
896 struct zynq_gpio *gpio;
897 struct gpio_chip *chip;
898 struct gpio_irq_chip *girq;
899 const struct of_device_id *match;
900
901 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
902 if (!gpio)
903 return -ENOMEM;
904
905 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
906 if (!match) {
907 dev_err(&pdev->dev, "of_match_node() failed\n");
908 return -EINVAL;
909 }
910 gpio->p_data = match->data;
911 platform_set_drvdata(pdev, gpio);
912
913 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
914 if (IS_ERR(gpio->base_addr))
915 return PTR_ERR(gpio->base_addr);
916
917 gpio->irq = platform_get_irq(pdev, 0);
918 if (gpio->irq < 0)
919 return gpio->irq;
920
921 /* configure the gpio chip */
922 chip = &gpio->chip;
923 chip->label = gpio->p_data->label;
924 chip->owner = THIS_MODULE;
925 chip->parent = &pdev->dev;
926 chip->get = zynq_gpio_get_value;
927 chip->set = zynq_gpio_set_value;
928 chip->request = zynq_gpio_request;
929 chip->free = zynq_gpio_free;
930 chip->direction_input = zynq_gpio_dir_in;
931 chip->direction_output = zynq_gpio_dir_out;
932 chip->get_direction = zynq_gpio_get_direction;
933 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
934 chip->ngpio = gpio->p_data->ngpio;
935
936 /* Retrieve GPIO clock */
937 gpio->clk = devm_clk_get(&pdev->dev, NULL);
938 if (IS_ERR(gpio->clk))
939 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n");
940
941 ret = clk_prepare_enable(gpio->clk);
942 if (ret) {
943 dev_err(&pdev->dev, "Unable to enable clock.\n");
944 return ret;
945 }
946
947 spin_lock_init(&gpio->dirlock);
948
949 pm_runtime_set_active(&pdev->dev);
950 pm_runtime_enable(&pdev->dev);
951 ret = pm_runtime_resume_and_get(&pdev->dev);
952 if (ret < 0)
953 goto err_pm_dis;
954
955 /* disable interrupts for all banks */
956 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
957 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
958 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
959 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
960 bank_num = bank_num + VERSAL_UNUSED_BANKS;
961 }
962
963 /* Set up the GPIO irqchip */
964 girq = &chip->irq;
965 girq->chip = &zynq_gpio_edge_irqchip;
966 girq->parent_handler = zynq_gpio_irqhandler;
967 girq->num_parents = 1;
968 girq->parents = devm_kcalloc(&pdev->dev, 1,
969 sizeof(*girq->parents),
970 GFP_KERNEL);
971 if (!girq->parents) {
972 ret = -ENOMEM;
973 goto err_pm_put;
974 }
975 girq->parents[0] = gpio->irq;
976 girq->default_type = IRQ_TYPE_NONE;
977 girq->handler = handle_level_irq;
978
979 /* report a bug if gpio chip registration fails */
980 ret = gpiochip_add_data(chip, gpio);
981 if (ret) {
982 dev_err(&pdev->dev, "Failed to add gpio chip\n");
983 goto err_pm_put;
984 }
985
986 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
987 device_init_wakeup(&pdev->dev, 1);
988 pm_runtime_put(&pdev->dev);
989
990 return 0;
991
992err_pm_put:
993 pm_runtime_put(&pdev->dev);
994err_pm_dis:
995 pm_runtime_disable(&pdev->dev);
996 clk_disable_unprepare(gpio->clk);
997
998 return ret;
999}
1000
1001/**
1002 * zynq_gpio_remove - Driver removal function
1003 * @pdev: platform device instance
1004 *
1005 * Return: 0 always
1006 */
1007static int zynq_gpio_remove(struct platform_device *pdev)
1008{
1009 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
1010 int ret;
1011
1012 ret = pm_runtime_get_sync(&pdev->dev);
1013 if (ret < 0)
1014 dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n");
1015 gpiochip_remove(&gpio->chip);
1016 clk_disable_unprepare(gpio->clk);
1017 device_set_wakeup_capable(&pdev->dev, 0);
1018 pm_runtime_disable(&pdev->dev);
1019 return 0;
1020}
1021
1022static struct platform_driver zynq_gpio_driver = {
1023 .driver = {
1024 .name = DRIVER_NAME,
1025 .pm = &zynq_gpio_dev_pm_ops,
1026 .of_match_table = zynq_gpio_of_match,
1027 },
1028 .probe = zynq_gpio_probe,
1029 .remove = zynq_gpio_remove,
1030};
1031
1032module_platform_driver(zynq_gpio_driver);
1033
1034MODULE_AUTHOR("Xilinx Inc.");
1035MODULE_DESCRIPTION("Zynq GPIO driver");
1036MODULE_LICENSE("GPL");