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1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/of.h>
22
23#define DRIVER_NAME "zynq-gpio"
24
25/* Maximum banks */
26#define ZYNQ_GPIO_MAX_BANK 4
27#define ZYNQMP_GPIO_MAX_BANK 6
28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
62
63
64/* Register offsets for the GPIO device */
65/* LSW Mask & Data -WO */
66#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
67/* MSW Mask & Data -WO */
68#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
69/* Data Register-RW */
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
99/**
100 * struct zynq_gpio - gpio device private data structure
101 * @chip: instance of the gpio_chip
102 * @base_addr: base address of the GPIO device
103 * @clk: clock resource for this controller
104 * @irq: interrupt for the GPIO device
105 * @p_data: pointer to platform data
106 */
107struct zynq_gpio {
108 struct gpio_chip chip;
109 void __iomem *base_addr;
110 struct clk *clk;
111 int irq;
112 const struct zynq_platform_data *p_data;
113};
114
115/**
116 * struct zynq_platform_data - zynq gpio platform data structure
117 * @label: string to store in gpio->label
118 * @ngpio: max number of gpio pins
119 * @max_bank: maximum number of gpio banks
120 * @bank_min: this array represents bank's min pin
121 * @bank_max: this array represents bank's max pin
122*/
123struct zynq_platform_data {
124 const char *label;
125 u16 ngpio;
126 int max_bank;
127 int bank_min[ZYNQMP_GPIO_MAX_BANK];
128 int bank_max[ZYNQMP_GPIO_MAX_BANK];
129};
130
131static struct irq_chip zynq_gpio_level_irqchip;
132static struct irq_chip zynq_gpio_edge_irqchip;
133
134/**
135 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
136 * for a given pin in the GPIO device
137 * @pin_num: gpio pin number within the device
138 * @bank_num: an output parameter used to return the bank number of the gpio
139 * pin
140 * @bank_pin_num: an output parameter used to return pin number within a bank
141 * for the given gpio pin
142 *
143 * Returns the bank number and pin offset within the bank.
144 */
145static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
146 unsigned int *bank_num,
147 unsigned int *bank_pin_num,
148 struct zynq_gpio *gpio)
149{
150 int bank;
151
152 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
153 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
154 (pin_num <= gpio->p_data->bank_max[bank])) {
155 *bank_num = bank;
156 *bank_pin_num = pin_num -
157 gpio->p_data->bank_min[bank];
158 return;
159 }
160 }
161
162 /* default */
163 WARN(true, "invalid GPIO pin number: %u", pin_num);
164 *bank_num = 0;
165 *bank_pin_num = 0;
166}
167
168/**
169 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
170 * @chip: gpio_chip instance to be worked on
171 * @pin: gpio pin number within the device
172 *
173 * This function reads the state of the specified pin of the GPIO device.
174 *
175 * Return: 0 if the pin is low, 1 if pin is high.
176 */
177static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
178{
179 u32 data;
180 unsigned int bank_num, bank_pin_num;
181 struct zynq_gpio *gpio = gpiochip_get_data(chip);
182
183 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
184
185 data = readl_relaxed(gpio->base_addr +
186 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
187
188 return (data >> bank_pin_num) & 1;
189}
190
191/**
192 * zynq_gpio_set_value - Modify the state of the pin with specified value
193 * @chip: gpio_chip instance to be worked on
194 * @pin: gpio pin number within the device
195 * @state: value used to modify the state of the specified pin
196 *
197 * This function calculates the register offset (i.e to lower 16 bits or
198 * upper 16 bits) based on the given pin number and sets the state of a
199 * gpio pin to the specified value. The state is either 0 or non-zero.
200 */
201static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
202 int state)
203{
204 unsigned int reg_offset, bank_num, bank_pin_num;
205 struct zynq_gpio *gpio = gpiochip_get_data(chip);
206
207 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
208
209 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
210 /* only 16 data bits in bit maskable reg */
211 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
212 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
213 } else {
214 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
215 }
216
217 /*
218 * get the 32 bit value to be written to the mask/data register where
219 * the upper 16 bits is the mask and lower 16 bits is the data
220 */
221 state = !!state;
222 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
223 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
224
225 writel_relaxed(state, gpio->base_addr + reg_offset);
226}
227
228/**
229 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
230 * @chip: gpio_chip instance to be worked on
231 * @pin: gpio pin number within the device
232 *
233 * This function uses the read-modify-write sequence to set the direction of
234 * the gpio pin as input.
235 *
236 * Return: 0 always
237 */
238static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
239{
240 u32 reg;
241 unsigned int bank_num, bank_pin_num;
242 struct zynq_gpio *gpio = gpiochip_get_data(chip);
243
244 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
245
246 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
247 if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
248 return -EINVAL;
249
250 /* clear the bit in direction mode reg to set the pin as input */
251 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
252 reg &= ~BIT(bank_pin_num);
253 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
254
255 return 0;
256}
257
258/**
259 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
260 * @chip: gpio_chip instance to be worked on
261 * @pin: gpio pin number within the device
262 * @state: value to be written to specified pin
263 *
264 * This function sets the direction of specified GPIO pin as output, configures
265 * the Output Enable register for the pin and uses zynq_gpio_set to set
266 * the state of the pin to the value specified.
267 *
268 * Return: 0 always
269 */
270static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
271 int state)
272{
273 u32 reg;
274 unsigned int bank_num, bank_pin_num;
275 struct zynq_gpio *gpio = gpiochip_get_data(chip);
276
277 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
278
279 /* set the GPIO pin as output */
280 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
281 reg |= BIT(bank_pin_num);
282 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
283
284 /* configure the output enable reg for the pin */
285 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
286 reg |= BIT(bank_pin_num);
287 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
288
289 /* set the state of the pin */
290 zynq_gpio_set_value(chip, pin, state);
291 return 0;
292}
293
294/**
295 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
296 * @irq_data: per irq and chip data passed down to chip functions
297 *
298 * This function calculates gpio pin number from irq number and sets the
299 * bit in the Interrupt Disable register of the corresponding bank to disable
300 * interrupts for that pin.
301 */
302static void zynq_gpio_irq_mask(struct irq_data *irq_data)
303{
304 unsigned int device_pin_num, bank_num, bank_pin_num;
305 struct zynq_gpio *gpio =
306 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
307
308 device_pin_num = irq_data->hwirq;
309 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
310 writel_relaxed(BIT(bank_pin_num),
311 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
312}
313
314/**
315 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
316 * @irq_data: irq data containing irq number of gpio pin for the interrupt
317 * to enable
318 *
319 * This function calculates the gpio pin number from irq number and sets the
320 * bit in the Interrupt Enable register of the corresponding bank to enable
321 * interrupts for that pin.
322 */
323static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
324{
325 unsigned int device_pin_num, bank_num, bank_pin_num;
326 struct zynq_gpio *gpio =
327 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
328
329 device_pin_num = irq_data->hwirq;
330 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
331 writel_relaxed(BIT(bank_pin_num),
332 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
333}
334
335/**
336 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
337 * @irq_data: irq data containing irq number of gpio pin for the interrupt
338 * to ack
339 *
340 * This function calculates gpio pin number from irq number and sets the bit
341 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
342 */
343static void zynq_gpio_irq_ack(struct irq_data *irq_data)
344{
345 unsigned int device_pin_num, bank_num, bank_pin_num;
346 struct zynq_gpio *gpio =
347 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
348
349 device_pin_num = irq_data->hwirq;
350 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
351 writel_relaxed(BIT(bank_pin_num),
352 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
353}
354
355/**
356 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
357 * @irq_data: irq data containing irq number of gpio pin for the interrupt
358 * to enable
359 *
360 * Clears the INTSTS bit and unmasks the given interrupt.
361 */
362static void zynq_gpio_irq_enable(struct irq_data *irq_data)
363{
364 /*
365 * The Zynq GPIO controller does not disable interrupt detection when
366 * the interrupt is masked and only disables the propagation of the
367 * interrupt. This means when the controller detects an interrupt
368 * condition while the interrupt is logically disabled it will propagate
369 * that interrupt event once the interrupt is enabled. This will cause
370 * the interrupt consumer to see spurious interrupts to prevent this
371 * first make sure that the interrupt is not asserted and then enable
372 * it.
373 */
374 zynq_gpio_irq_ack(irq_data);
375 zynq_gpio_irq_unmask(irq_data);
376}
377
378/**
379 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
380 * @irq_data: irq data containing irq number of gpio pin
381 * @type: interrupt type that is to be set for the gpio pin
382 *
383 * This function gets the gpio pin number and its bank from the gpio pin number
384 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
385 *
386 * Return: 0, negative error otherwise.
387 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
388 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
389 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
390 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
391 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
392 */
393static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
394{
395 u32 int_type, int_pol, int_any;
396 unsigned int device_pin_num, bank_num, bank_pin_num;
397 struct zynq_gpio *gpio =
398 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
399
400 device_pin_num = irq_data->hwirq;
401 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
402
403 int_type = readl_relaxed(gpio->base_addr +
404 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
405 int_pol = readl_relaxed(gpio->base_addr +
406 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
407 int_any = readl_relaxed(gpio->base_addr +
408 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
409
410 /*
411 * based on the type requested, configure the INT_TYPE, INT_POLARITY
412 * and INT_ANY registers
413 */
414 switch (type) {
415 case IRQ_TYPE_EDGE_RISING:
416 int_type |= BIT(bank_pin_num);
417 int_pol |= BIT(bank_pin_num);
418 int_any &= ~BIT(bank_pin_num);
419 break;
420 case IRQ_TYPE_EDGE_FALLING:
421 int_type |= BIT(bank_pin_num);
422 int_pol &= ~BIT(bank_pin_num);
423 int_any &= ~BIT(bank_pin_num);
424 break;
425 case IRQ_TYPE_EDGE_BOTH:
426 int_type |= BIT(bank_pin_num);
427 int_any |= BIT(bank_pin_num);
428 break;
429 case IRQ_TYPE_LEVEL_HIGH:
430 int_type &= ~BIT(bank_pin_num);
431 int_pol |= BIT(bank_pin_num);
432 break;
433 case IRQ_TYPE_LEVEL_LOW:
434 int_type &= ~BIT(bank_pin_num);
435 int_pol &= ~BIT(bank_pin_num);
436 break;
437 default:
438 return -EINVAL;
439 }
440
441 writel_relaxed(int_type,
442 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
443 writel_relaxed(int_pol,
444 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
445 writel_relaxed(int_any,
446 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
447
448 if (type & IRQ_TYPE_LEVEL_MASK) {
449 irq_set_chip_handler_name_locked(irq_data,
450 &zynq_gpio_level_irqchip, handle_fasteoi_irq, NULL);
451 } else {
452 irq_set_chip_handler_name_locked(irq_data,
453 &zynq_gpio_edge_irqchip, handle_level_irq, NULL);
454 }
455
456 return 0;
457}
458
459static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
460{
461 struct zynq_gpio *gpio =
462 gpiochip_get_data(irq_data_get_irq_chip_data(data));
463
464 irq_set_irq_wake(gpio->irq, on);
465
466 return 0;
467}
468
469/* irq chip descriptor */
470static struct irq_chip zynq_gpio_level_irqchip = {
471 .name = DRIVER_NAME,
472 .irq_enable = zynq_gpio_irq_enable,
473 .irq_eoi = zynq_gpio_irq_ack,
474 .irq_mask = zynq_gpio_irq_mask,
475 .irq_unmask = zynq_gpio_irq_unmask,
476 .irq_set_type = zynq_gpio_set_irq_type,
477 .irq_set_wake = zynq_gpio_set_wake,
478 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
479 IRQCHIP_MASK_ON_SUSPEND,
480};
481
482static struct irq_chip zynq_gpio_edge_irqchip = {
483 .name = DRIVER_NAME,
484 .irq_enable = zynq_gpio_irq_enable,
485 .irq_ack = zynq_gpio_irq_ack,
486 .irq_mask = zynq_gpio_irq_mask,
487 .irq_unmask = zynq_gpio_irq_unmask,
488 .irq_set_type = zynq_gpio_set_irq_type,
489 .irq_set_wake = zynq_gpio_set_wake,
490 .flags = IRQCHIP_MASK_ON_SUSPEND,
491};
492
493static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
494 unsigned int bank_num,
495 unsigned long pending)
496{
497 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
498 struct irq_domain *irqdomain = gpio->chip.irqdomain;
499 int offset;
500
501 if (!pending)
502 return;
503
504 for_each_set_bit(offset, &pending, 32) {
505 unsigned int gpio_irq;
506
507 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
508 generic_handle_irq(gpio_irq);
509 }
510}
511
512/**
513 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
514 * @irq: irq number of the gpio bank where interrupt has occurred
515 * @desc: irq descriptor instance of the 'irq'
516 *
517 * This function reads the Interrupt Status Register of each bank to get the
518 * gpio pin number which has triggered an interrupt. It then acks the triggered
519 * interrupt and calls the pin specific handler set by the higher layer
520 * application for that pin.
521 * Note: A bug is reported if no handler is set for the gpio pin.
522 */
523static void zynq_gpio_irqhandler(struct irq_desc *desc)
524{
525 u32 int_sts, int_enb;
526 unsigned int bank_num;
527 struct zynq_gpio *gpio =
528 gpiochip_get_data(irq_desc_get_handler_data(desc));
529 struct irq_chip *irqchip = irq_desc_get_chip(desc);
530
531 chained_irq_enter(irqchip, desc);
532
533 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
534 int_sts = readl_relaxed(gpio->base_addr +
535 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
536 int_enb = readl_relaxed(gpio->base_addr +
537 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
538 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
539 }
540
541 chained_irq_exit(irqchip, desc);
542}
543
544static int __maybe_unused zynq_gpio_suspend(struct device *dev)
545{
546 struct platform_device *pdev = to_platform_device(dev);
547 int irq = platform_get_irq(pdev, 0);
548 struct irq_data *data = irq_get_irq_data(irq);
549
550 if (!irqd_is_wakeup_set(data))
551 return pm_runtime_force_suspend(dev);
552
553 return 0;
554}
555
556static int __maybe_unused zynq_gpio_resume(struct device *dev)
557{
558 struct platform_device *pdev = to_platform_device(dev);
559 int irq = platform_get_irq(pdev, 0);
560 struct irq_data *data = irq_get_irq_data(irq);
561
562 if (!irqd_is_wakeup_set(data))
563 return pm_runtime_force_resume(dev);
564
565 return 0;
566}
567
568static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
569{
570 struct platform_device *pdev = to_platform_device(dev);
571 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
572
573 clk_disable_unprepare(gpio->clk);
574
575 return 0;
576}
577
578static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
579{
580 struct platform_device *pdev = to_platform_device(dev);
581 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
582
583 return clk_prepare_enable(gpio->clk);
584}
585
586static int zynq_gpio_request(struct gpio_chip *chip, unsigned offset)
587{
588 int ret;
589
590 ret = pm_runtime_get_sync(chip->parent);
591
592 /*
593 * If the device is already active pm_runtime_get() will return 1 on
594 * success, but gpio_request still needs to return 0.
595 */
596 return ret < 0 ? ret : 0;
597}
598
599static void zynq_gpio_free(struct gpio_chip *chip, unsigned offset)
600{
601 pm_runtime_put(chip->parent);
602}
603
604static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
605 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
606 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
607 zynq_gpio_runtime_resume, NULL)
608};
609
610static const struct zynq_platform_data zynqmp_gpio_def = {
611 .label = "zynqmp_gpio",
612 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
613 .max_bank = ZYNQMP_GPIO_MAX_BANK,
614 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
615 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
616 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
617 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
618 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
619 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
620 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
621 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
622 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
623 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
624 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
625 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
626};
627
628static const struct zynq_platform_data zynq_gpio_def = {
629 .label = "zynq_gpio",
630 .ngpio = ZYNQ_GPIO_NR_GPIOS,
631 .max_bank = ZYNQ_GPIO_MAX_BANK,
632 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
633 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
634 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
635 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
636 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
637 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
638 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
639 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
640};
641
642static const struct of_device_id zynq_gpio_of_match[] = {
643 { .compatible = "xlnx,zynq-gpio-1.0", .data = (void *)&zynq_gpio_def },
644 { .compatible = "xlnx,zynqmp-gpio-1.0",
645 .data = (void *)&zynqmp_gpio_def },
646 { /* end of table */ }
647};
648MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
649
650/**
651 * zynq_gpio_probe - Initialization method for a zynq_gpio device
652 * @pdev: platform device instance
653 *
654 * This function allocates memory resources for the gpio device and registers
655 * all the banks of the device. It will also set up interrupts for the gpio
656 * pins.
657 * Note: Interrupts are disabled for all the banks during initialization.
658 *
659 * Return: 0 on success, negative error otherwise.
660 */
661static int zynq_gpio_probe(struct platform_device *pdev)
662{
663 int ret, bank_num;
664 struct zynq_gpio *gpio;
665 struct gpio_chip *chip;
666 struct resource *res;
667 const struct of_device_id *match;
668
669 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
670 if (!gpio)
671 return -ENOMEM;
672
673 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
674 if (!match) {
675 dev_err(&pdev->dev, "of_match_node() failed\n");
676 return -EINVAL;
677 }
678 gpio->p_data = match->data;
679 platform_set_drvdata(pdev, gpio);
680
681 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
682 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
683 if (IS_ERR(gpio->base_addr))
684 return PTR_ERR(gpio->base_addr);
685
686 gpio->irq = platform_get_irq(pdev, 0);
687 if (gpio->irq < 0) {
688 dev_err(&pdev->dev, "invalid IRQ\n");
689 return gpio->irq;
690 }
691
692 /* configure the gpio chip */
693 chip = &gpio->chip;
694 chip->label = gpio->p_data->label;
695 chip->owner = THIS_MODULE;
696 chip->parent = &pdev->dev;
697 chip->get = zynq_gpio_get_value;
698 chip->set = zynq_gpio_set_value;
699 chip->request = zynq_gpio_request;
700 chip->free = zynq_gpio_free;
701 chip->direction_input = zynq_gpio_dir_in;
702 chip->direction_output = zynq_gpio_dir_out;
703 chip->base = -1;
704 chip->ngpio = gpio->p_data->ngpio;
705
706 /* Retrieve GPIO clock */
707 gpio->clk = devm_clk_get(&pdev->dev, NULL);
708 if (IS_ERR(gpio->clk)) {
709 dev_err(&pdev->dev, "input clock not found.\n");
710 return PTR_ERR(gpio->clk);
711 }
712
713 pm_runtime_enable(&pdev->dev);
714 ret = pm_runtime_get_sync(&pdev->dev);
715 if (ret < 0)
716 return ret;
717
718 /* report a bug if gpio chip registration fails */
719 ret = gpiochip_add_data(chip, gpio);
720 if (ret) {
721 dev_err(&pdev->dev, "Failed to add gpio chip\n");
722 goto err_pm_put;
723 }
724
725 /* disable interrupts for all banks */
726 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
727 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
728 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
729
730 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
731 handle_level_irq, IRQ_TYPE_NONE);
732 if (ret) {
733 dev_err(&pdev->dev, "Failed to add irq chip\n");
734 goto err_rm_gpiochip;
735 }
736
737 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
738 zynq_gpio_irqhandler);
739
740 pm_runtime_put(&pdev->dev);
741
742 return 0;
743
744err_rm_gpiochip:
745 gpiochip_remove(chip);
746err_pm_put:
747 pm_runtime_put(&pdev->dev);
748
749 return ret;
750}
751
752/**
753 * zynq_gpio_remove - Driver removal function
754 * @pdev: platform device instance
755 *
756 * Return: 0 always
757 */
758static int zynq_gpio_remove(struct platform_device *pdev)
759{
760 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
761
762 pm_runtime_get_sync(&pdev->dev);
763 gpiochip_remove(&gpio->chip);
764 clk_disable_unprepare(gpio->clk);
765 device_set_wakeup_capable(&pdev->dev, 0);
766 pm_runtime_disable(&pdev->dev);
767 return 0;
768}
769
770static struct platform_driver zynq_gpio_driver = {
771 .driver = {
772 .name = DRIVER_NAME,
773 .pm = &zynq_gpio_dev_pm_ops,
774 .of_match_table = zynq_gpio_of_match,
775 },
776 .probe = zynq_gpio_probe,
777 .remove = zynq_gpio_remove,
778};
779
780/**
781 * zynq_gpio_init - Initial driver registration call
782 *
783 * Return: value from platform_driver_register
784 */
785static int __init zynq_gpio_init(void)
786{
787 return platform_driver_register(&zynq_gpio_driver);
788}
789postcore_initcall(zynq_gpio_init);
790
791static void __exit zynq_gpio_exit(void)
792{
793 platform_driver_unregister(&zynq_gpio_driver);
794}
795module_exit(zynq_gpio_exit);
796
797MODULE_AUTHOR("Xilinx Inc.");
798MODULE_DESCRIPTION("Zynq GPIO driver");
799MODULE_LICENSE("GPL");
1/*
2 * Xilinx Zynq GPIO device driver
3 *
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
9 * version.
10 */
11
12#include <linux/bitops.h>
13#include <linux/clk.h>
14#include <linux/gpio/driver.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/of.h>
22
23#define DRIVER_NAME "zynq-gpio"
24
25/* Maximum banks */
26#define ZYNQ_GPIO_MAX_BANK 4
27#define ZYNQMP_GPIO_MAX_BANK 6
28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
62
63/* Register offsets for the GPIO device */
64/* LSW Mask & Data -WO */
65#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
66/* MSW Mask & Data -WO */
67#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
68/* Data Register-RW */
69#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
102
103struct gpio_regs {
104 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
105 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
106 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
107 u32 outen[ZYNQMP_GPIO_MAX_BANK];
108 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
113};
114
115/**
116 * struct zynq_gpio - gpio device private data structure
117 * @chip: instance of the gpio_chip
118 * @base_addr: base address of the GPIO device
119 * @clk: clock resource for this controller
120 * @irq: interrupt for the GPIO device
121 * @p_data: pointer to platform data
122 * @context: context registers
123 */
124struct zynq_gpio {
125 struct gpio_chip chip;
126 void __iomem *base_addr;
127 struct clk *clk;
128 int irq;
129 const struct zynq_platform_data *p_data;
130 struct gpio_regs context;
131};
132
133/**
134 * struct zynq_platform_data - zynq gpio platform data structure
135 * @label: string to store in gpio->label
136 * @quirks: Flags is used to identify the platform
137 * @ngpio: max number of gpio pins
138 * @max_bank: maximum number of gpio banks
139 * @bank_min: this array represents bank's min pin
140 * @bank_max: this array represents bank's max pin
141 */
142struct zynq_platform_data {
143 const char *label;
144 u32 quirks;
145 u16 ngpio;
146 int max_bank;
147 int bank_min[ZYNQMP_GPIO_MAX_BANK];
148 int bank_max[ZYNQMP_GPIO_MAX_BANK];
149};
150
151static struct irq_chip zynq_gpio_level_irqchip;
152static struct irq_chip zynq_gpio_edge_irqchip;
153
154/**
155 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
156 * @gpio: Pointer to driver data struct
157 *
158 * Return: 0 if zynqmp, 1 if zynq.
159 */
160static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
161{
162 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
163}
164
165/**
166 * gpio_data_ro_bug - test if HW bug exists or not
167 * @gpio: Pointer to driver data struct
168 *
169 * Return: 0 if bug doesnot exist, 1 if bug exists.
170 */
171static int gpio_data_ro_bug(struct zynq_gpio *gpio)
172{
173 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
174}
175
176/**
177 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
178 * for a given pin in the GPIO device
179 * @pin_num: gpio pin number within the device
180 * @bank_num: an output parameter used to return the bank number of the gpio
181 * pin
182 * @bank_pin_num: an output parameter used to return pin number within a bank
183 * for the given gpio pin
184 * @gpio: gpio device data structure
185 *
186 * Returns the bank number and pin offset within the bank.
187 */
188static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
189 unsigned int *bank_num,
190 unsigned int *bank_pin_num,
191 struct zynq_gpio *gpio)
192{
193 int bank;
194
195 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
196 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
197 (pin_num <= gpio->p_data->bank_max[bank])) {
198 *bank_num = bank;
199 *bank_pin_num = pin_num -
200 gpio->p_data->bank_min[bank];
201 return;
202 }
203 }
204
205 /* default */
206 WARN(true, "invalid GPIO pin number: %u", pin_num);
207 *bank_num = 0;
208 *bank_pin_num = 0;
209}
210
211/**
212 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
213 * @chip: gpio_chip instance to be worked on
214 * @pin: gpio pin number within the device
215 *
216 * This function reads the state of the specified pin of the GPIO device.
217 *
218 * Return: 0 if the pin is low, 1 if pin is high.
219 */
220static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
221{
222 u32 data;
223 unsigned int bank_num, bank_pin_num;
224 struct zynq_gpio *gpio = gpiochip_get_data(chip);
225
226 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
227
228 if (gpio_data_ro_bug(gpio)) {
229 if (zynq_gpio_is_zynq(gpio)) {
230 if (bank_num <= 1) {
231 data = readl_relaxed(gpio->base_addr +
232 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
233 } else {
234 data = readl_relaxed(gpio->base_addr +
235 ZYNQ_GPIO_DATA_OFFSET(bank_num));
236 }
237 } else {
238 if (bank_num <= 2) {
239 data = readl_relaxed(gpio->base_addr +
240 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
241 } else {
242 data = readl_relaxed(gpio->base_addr +
243 ZYNQ_GPIO_DATA_OFFSET(bank_num));
244 }
245 }
246 } else {
247 data = readl_relaxed(gpio->base_addr +
248 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
249 }
250 return (data >> bank_pin_num) & 1;
251}
252
253/**
254 * zynq_gpio_set_value - Modify the state of the pin with specified value
255 * @chip: gpio_chip instance to be worked on
256 * @pin: gpio pin number within the device
257 * @state: value used to modify the state of the specified pin
258 *
259 * This function calculates the register offset (i.e to lower 16 bits or
260 * upper 16 bits) based on the given pin number and sets the state of a
261 * gpio pin to the specified value. The state is either 0 or non-zero.
262 */
263static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
264 int state)
265{
266 unsigned int reg_offset, bank_num, bank_pin_num;
267 struct zynq_gpio *gpio = gpiochip_get_data(chip);
268
269 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
270
271 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
272 /* only 16 data bits in bit maskable reg */
273 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
274 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
275 } else {
276 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
277 }
278
279 /*
280 * get the 32 bit value to be written to the mask/data register where
281 * the upper 16 bits is the mask and lower 16 bits is the data
282 */
283 state = !!state;
284 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
285 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
286
287 writel_relaxed(state, gpio->base_addr + reg_offset);
288}
289
290/**
291 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
292 * @chip: gpio_chip instance to be worked on
293 * @pin: gpio pin number within the device
294 *
295 * This function uses the read-modify-write sequence to set the direction of
296 * the gpio pin as input.
297 *
298 * Return: 0 always
299 */
300static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
301{
302 u32 reg;
303 unsigned int bank_num, bank_pin_num;
304 struct zynq_gpio *gpio = gpiochip_get_data(chip);
305
306 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
307
308 /*
309 * On zynq bank 0 pins 7 and 8 are special and cannot be used
310 * as inputs.
311 */
312 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
313 (bank_pin_num == 7 || bank_pin_num == 8))
314 return -EINVAL;
315
316 /* clear the bit in direction mode reg to set the pin as input */
317 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
318 reg &= ~BIT(bank_pin_num);
319 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
320
321 return 0;
322}
323
324/**
325 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
326 * @chip: gpio_chip instance to be worked on
327 * @pin: gpio pin number within the device
328 * @state: value to be written to specified pin
329 *
330 * This function sets the direction of specified GPIO pin as output, configures
331 * the Output Enable register for the pin and uses zynq_gpio_set to set
332 * the state of the pin to the value specified.
333 *
334 * Return: 0 always
335 */
336static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
337 int state)
338{
339 u32 reg;
340 unsigned int bank_num, bank_pin_num;
341 struct zynq_gpio *gpio = gpiochip_get_data(chip);
342
343 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
344
345 /* set the GPIO pin as output */
346 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
347 reg |= BIT(bank_pin_num);
348 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
349
350 /* configure the output enable reg for the pin */
351 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
352 reg |= BIT(bank_pin_num);
353 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
354
355 /* set the state of the pin */
356 zynq_gpio_set_value(chip, pin, state);
357 return 0;
358}
359
360/**
361 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
362 * @irq_data: per irq and chip data passed down to chip functions
363 *
364 * This function calculates gpio pin number from irq number and sets the
365 * bit in the Interrupt Disable register of the corresponding bank to disable
366 * interrupts for that pin.
367 */
368static void zynq_gpio_irq_mask(struct irq_data *irq_data)
369{
370 unsigned int device_pin_num, bank_num, bank_pin_num;
371 struct zynq_gpio *gpio =
372 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
373
374 device_pin_num = irq_data->hwirq;
375 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
376 writel_relaxed(BIT(bank_pin_num),
377 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
378}
379
380/**
381 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
382 * @irq_data: irq data containing irq number of gpio pin for the interrupt
383 * to enable
384 *
385 * This function calculates the gpio pin number from irq number and sets the
386 * bit in the Interrupt Enable register of the corresponding bank to enable
387 * interrupts for that pin.
388 */
389static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
390{
391 unsigned int device_pin_num, bank_num, bank_pin_num;
392 struct zynq_gpio *gpio =
393 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
394
395 device_pin_num = irq_data->hwirq;
396 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
397 writel_relaxed(BIT(bank_pin_num),
398 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
399}
400
401/**
402 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
403 * @irq_data: irq data containing irq number of gpio pin for the interrupt
404 * to ack
405 *
406 * This function calculates gpio pin number from irq number and sets the bit
407 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
408 */
409static void zynq_gpio_irq_ack(struct irq_data *irq_data)
410{
411 unsigned int device_pin_num, bank_num, bank_pin_num;
412 struct zynq_gpio *gpio =
413 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
414
415 device_pin_num = irq_data->hwirq;
416 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
417 writel_relaxed(BIT(bank_pin_num),
418 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
419}
420
421/**
422 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
423 * @irq_data: irq data containing irq number of gpio pin for the interrupt
424 * to enable
425 *
426 * Clears the INTSTS bit and unmasks the given interrupt.
427 */
428static void zynq_gpio_irq_enable(struct irq_data *irq_data)
429{
430 /*
431 * The Zynq GPIO controller does not disable interrupt detection when
432 * the interrupt is masked and only disables the propagation of the
433 * interrupt. This means when the controller detects an interrupt
434 * condition while the interrupt is logically disabled it will propagate
435 * that interrupt event once the interrupt is enabled. This will cause
436 * the interrupt consumer to see spurious interrupts to prevent this
437 * first make sure that the interrupt is not asserted and then enable
438 * it.
439 */
440 zynq_gpio_irq_ack(irq_data);
441 zynq_gpio_irq_unmask(irq_data);
442}
443
444/**
445 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
446 * @irq_data: irq data containing irq number of gpio pin
447 * @type: interrupt type that is to be set for the gpio pin
448 *
449 * This function gets the gpio pin number and its bank from the gpio pin number
450 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
451 *
452 * Return: 0, negative error otherwise.
453 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
454 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
455 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
456 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
457 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
458 */
459static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
460{
461 u32 int_type, int_pol, int_any;
462 unsigned int device_pin_num, bank_num, bank_pin_num;
463 struct zynq_gpio *gpio =
464 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
465
466 device_pin_num = irq_data->hwirq;
467 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
468
469 int_type = readl_relaxed(gpio->base_addr +
470 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
471 int_pol = readl_relaxed(gpio->base_addr +
472 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
473 int_any = readl_relaxed(gpio->base_addr +
474 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
475
476 /*
477 * based on the type requested, configure the INT_TYPE, INT_POLARITY
478 * and INT_ANY registers
479 */
480 switch (type) {
481 case IRQ_TYPE_EDGE_RISING:
482 int_type |= BIT(bank_pin_num);
483 int_pol |= BIT(bank_pin_num);
484 int_any &= ~BIT(bank_pin_num);
485 break;
486 case IRQ_TYPE_EDGE_FALLING:
487 int_type |= BIT(bank_pin_num);
488 int_pol &= ~BIT(bank_pin_num);
489 int_any &= ~BIT(bank_pin_num);
490 break;
491 case IRQ_TYPE_EDGE_BOTH:
492 int_type |= BIT(bank_pin_num);
493 int_any |= BIT(bank_pin_num);
494 break;
495 case IRQ_TYPE_LEVEL_HIGH:
496 int_type &= ~BIT(bank_pin_num);
497 int_pol |= BIT(bank_pin_num);
498 break;
499 case IRQ_TYPE_LEVEL_LOW:
500 int_type &= ~BIT(bank_pin_num);
501 int_pol &= ~BIT(bank_pin_num);
502 break;
503 default:
504 return -EINVAL;
505 }
506
507 writel_relaxed(int_type,
508 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
509 writel_relaxed(int_pol,
510 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
511 writel_relaxed(int_any,
512 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
513
514 if (type & IRQ_TYPE_LEVEL_MASK)
515 irq_set_chip_handler_name_locked(irq_data,
516 &zynq_gpio_level_irqchip,
517 handle_fasteoi_irq, NULL);
518 else
519 irq_set_chip_handler_name_locked(irq_data,
520 &zynq_gpio_edge_irqchip,
521 handle_level_irq, NULL);
522
523 return 0;
524}
525
526static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
527{
528 struct zynq_gpio *gpio =
529 gpiochip_get_data(irq_data_get_irq_chip_data(data));
530
531 irq_set_irq_wake(gpio->irq, on);
532
533 return 0;
534}
535
536/* irq chip descriptor */
537static struct irq_chip zynq_gpio_level_irqchip = {
538 .name = DRIVER_NAME,
539 .irq_enable = zynq_gpio_irq_enable,
540 .irq_eoi = zynq_gpio_irq_ack,
541 .irq_mask = zynq_gpio_irq_mask,
542 .irq_unmask = zynq_gpio_irq_unmask,
543 .irq_set_type = zynq_gpio_set_irq_type,
544 .irq_set_wake = zynq_gpio_set_wake,
545 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
546 IRQCHIP_MASK_ON_SUSPEND,
547};
548
549static struct irq_chip zynq_gpio_edge_irqchip = {
550 .name = DRIVER_NAME,
551 .irq_enable = zynq_gpio_irq_enable,
552 .irq_ack = zynq_gpio_irq_ack,
553 .irq_mask = zynq_gpio_irq_mask,
554 .irq_unmask = zynq_gpio_irq_unmask,
555 .irq_set_type = zynq_gpio_set_irq_type,
556 .irq_set_wake = zynq_gpio_set_wake,
557 .flags = IRQCHIP_MASK_ON_SUSPEND,
558};
559
560static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
561 unsigned int bank_num,
562 unsigned long pending)
563{
564 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
565 struct irq_domain *irqdomain = gpio->chip.irq.domain;
566 int offset;
567
568 if (!pending)
569 return;
570
571 for_each_set_bit(offset, &pending, 32) {
572 unsigned int gpio_irq;
573
574 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
575 generic_handle_irq(gpio_irq);
576 }
577}
578
579/**
580 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
581 * @desc: irq descriptor instance of the 'irq'
582 *
583 * This function reads the Interrupt Status Register of each bank to get the
584 * gpio pin number which has triggered an interrupt. It then acks the triggered
585 * interrupt and calls the pin specific handler set by the higher layer
586 * application for that pin.
587 * Note: A bug is reported if no handler is set for the gpio pin.
588 */
589static void zynq_gpio_irqhandler(struct irq_desc *desc)
590{
591 u32 int_sts, int_enb;
592 unsigned int bank_num;
593 struct zynq_gpio *gpio =
594 gpiochip_get_data(irq_desc_get_handler_data(desc));
595 struct irq_chip *irqchip = irq_desc_get_chip(desc);
596
597 chained_irq_enter(irqchip, desc);
598
599 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
600 int_sts = readl_relaxed(gpio->base_addr +
601 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
602 int_enb = readl_relaxed(gpio->base_addr +
603 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
604 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
605 }
606
607 chained_irq_exit(irqchip, desc);
608}
609
610static void zynq_gpio_save_context(struct zynq_gpio *gpio)
611{
612 unsigned int bank_num;
613
614 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
615 gpio->context.datalsw[bank_num] =
616 readl_relaxed(gpio->base_addr +
617 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
618 gpio->context.datamsw[bank_num] =
619 readl_relaxed(gpio->base_addr +
620 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
621 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
622 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
623 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
624 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
625 gpio->context.int_type[bank_num] =
626 readl_relaxed(gpio->base_addr +
627 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
628 gpio->context.int_polarity[bank_num] =
629 readl_relaxed(gpio->base_addr +
630 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
631 gpio->context.int_any[bank_num] =
632 readl_relaxed(gpio->base_addr +
633 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
634 }
635}
636
637static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
638{
639 unsigned int bank_num;
640
641 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
642 writel_relaxed(gpio->context.datalsw[bank_num],
643 gpio->base_addr +
644 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
645 writel_relaxed(gpio->context.datamsw[bank_num],
646 gpio->base_addr +
647 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
648 writel_relaxed(gpio->context.dirm[bank_num],
649 gpio->base_addr +
650 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
651 writel_relaxed(gpio->context.int_en[bank_num],
652 gpio->base_addr +
653 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
654 writel_relaxed(gpio->context.int_type[bank_num],
655 gpio->base_addr +
656 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
657 writel_relaxed(gpio->context.int_polarity[bank_num],
658 gpio->base_addr +
659 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
660 writel_relaxed(gpio->context.int_any[bank_num],
661 gpio->base_addr +
662 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
663 }
664}
665
666static int __maybe_unused zynq_gpio_suspend(struct device *dev)
667{
668 struct platform_device *pdev = to_platform_device(dev);
669 int irq = platform_get_irq(pdev, 0);
670 struct irq_data *data = irq_get_irq_data(irq);
671 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
672
673 if (!irqd_is_wakeup_set(data)) {
674 zynq_gpio_save_context(gpio);
675 return pm_runtime_force_suspend(dev);
676 }
677
678 return 0;
679}
680
681static int __maybe_unused zynq_gpio_resume(struct device *dev)
682{
683 struct platform_device *pdev = to_platform_device(dev);
684 int irq = platform_get_irq(pdev, 0);
685 struct irq_data *data = irq_get_irq_data(irq);
686 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
687 int ret;
688
689 if (!irqd_is_wakeup_set(data)) {
690 ret = pm_runtime_force_resume(dev);
691 zynq_gpio_restore_context(gpio);
692 return ret;
693 }
694
695 return 0;
696}
697
698static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
699{
700 struct platform_device *pdev = to_platform_device(dev);
701 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
702
703 clk_disable_unprepare(gpio->clk);
704
705 return 0;
706}
707
708static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
709{
710 struct platform_device *pdev = to_platform_device(dev);
711 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
712
713 return clk_prepare_enable(gpio->clk);
714}
715
716static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
717{
718 int ret;
719
720 ret = pm_runtime_get_sync(chip->parent);
721
722 /*
723 * If the device is already active pm_runtime_get() will return 1 on
724 * success, but gpio_request still needs to return 0.
725 */
726 return ret < 0 ? ret : 0;
727}
728
729static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
730{
731 pm_runtime_put(chip->parent);
732}
733
734static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
735 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
736 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
737 zynq_gpio_runtime_resume, NULL)
738};
739
740static const struct zynq_platform_data zynqmp_gpio_def = {
741 .label = "zynqmp_gpio",
742 .quirks = GPIO_QUIRK_DATA_RO_BUG,
743 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
744 .max_bank = ZYNQMP_GPIO_MAX_BANK,
745 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
746 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
747 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
748 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
749 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
750 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
751 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
752 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
753 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
754 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
755 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
756 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
757};
758
759static const struct zynq_platform_data zynq_gpio_def = {
760 .label = "zynq_gpio",
761 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
762 .ngpio = ZYNQ_GPIO_NR_GPIOS,
763 .max_bank = ZYNQ_GPIO_MAX_BANK,
764 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
765 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
766 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
767 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
768 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
769 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
770 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
771 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
772};
773
774static const struct of_device_id zynq_gpio_of_match[] = {
775 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
776 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
777 { /* end of table */ }
778};
779MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
780
781/**
782 * zynq_gpio_probe - Initialization method for a zynq_gpio device
783 * @pdev: platform device instance
784 *
785 * This function allocates memory resources for the gpio device and registers
786 * all the banks of the device. It will also set up interrupts for the gpio
787 * pins.
788 * Note: Interrupts are disabled for all the banks during initialization.
789 *
790 * Return: 0 on success, negative error otherwise.
791 */
792static int zynq_gpio_probe(struct platform_device *pdev)
793{
794 int ret, bank_num;
795 struct zynq_gpio *gpio;
796 struct gpio_chip *chip;
797 struct resource *res;
798 const struct of_device_id *match;
799
800 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
801 if (!gpio)
802 return -ENOMEM;
803
804 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
805 if (!match) {
806 dev_err(&pdev->dev, "of_match_node() failed\n");
807 return -EINVAL;
808 }
809 gpio->p_data = match->data;
810 platform_set_drvdata(pdev, gpio);
811
812 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
813 gpio->base_addr = devm_ioremap_resource(&pdev->dev, res);
814 if (IS_ERR(gpio->base_addr))
815 return PTR_ERR(gpio->base_addr);
816
817 gpio->irq = platform_get_irq(pdev, 0);
818 if (gpio->irq < 0) {
819 dev_err(&pdev->dev, "invalid IRQ\n");
820 return gpio->irq;
821 }
822
823 /* configure the gpio chip */
824 chip = &gpio->chip;
825 chip->label = gpio->p_data->label;
826 chip->owner = THIS_MODULE;
827 chip->parent = &pdev->dev;
828 chip->get = zynq_gpio_get_value;
829 chip->set = zynq_gpio_set_value;
830 chip->request = zynq_gpio_request;
831 chip->free = zynq_gpio_free;
832 chip->direction_input = zynq_gpio_dir_in;
833 chip->direction_output = zynq_gpio_dir_out;
834 chip->base = -1;
835 chip->ngpio = gpio->p_data->ngpio;
836
837 /* Retrieve GPIO clock */
838 gpio->clk = devm_clk_get(&pdev->dev, NULL);
839 if (IS_ERR(gpio->clk)) {
840 dev_err(&pdev->dev, "input clock not found.\n");
841 return PTR_ERR(gpio->clk);
842 }
843 ret = clk_prepare_enable(gpio->clk);
844 if (ret) {
845 dev_err(&pdev->dev, "Unable to enable clock.\n");
846 return ret;
847 }
848
849 pm_runtime_set_active(&pdev->dev);
850 pm_runtime_enable(&pdev->dev);
851 ret = pm_runtime_get_sync(&pdev->dev);
852 if (ret < 0)
853 goto err_pm_dis;
854
855 /* report a bug if gpio chip registration fails */
856 ret = gpiochip_add_data(chip, gpio);
857 if (ret) {
858 dev_err(&pdev->dev, "Failed to add gpio chip\n");
859 goto err_pm_put;
860 }
861
862 /* disable interrupts for all banks */
863 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
864 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
865 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
866
867 ret = gpiochip_irqchip_add(chip, &zynq_gpio_edge_irqchip, 0,
868 handle_level_irq, IRQ_TYPE_NONE);
869 if (ret) {
870 dev_err(&pdev->dev, "Failed to add irq chip\n");
871 goto err_rm_gpiochip;
872 }
873
874 gpiochip_set_chained_irqchip(chip, &zynq_gpio_edge_irqchip, gpio->irq,
875 zynq_gpio_irqhandler);
876
877 pm_runtime_put(&pdev->dev);
878
879 return 0;
880
881err_rm_gpiochip:
882 gpiochip_remove(chip);
883err_pm_put:
884 pm_runtime_put(&pdev->dev);
885err_pm_dis:
886 pm_runtime_disable(&pdev->dev);
887 clk_disable_unprepare(gpio->clk);
888
889 return ret;
890}
891
892/**
893 * zynq_gpio_remove - Driver removal function
894 * @pdev: platform device instance
895 *
896 * Return: 0 always
897 */
898static int zynq_gpio_remove(struct platform_device *pdev)
899{
900 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
901
902 pm_runtime_get_sync(&pdev->dev);
903 gpiochip_remove(&gpio->chip);
904 clk_disable_unprepare(gpio->clk);
905 device_set_wakeup_capable(&pdev->dev, 0);
906 pm_runtime_disable(&pdev->dev);
907 return 0;
908}
909
910static struct platform_driver zynq_gpio_driver = {
911 .driver = {
912 .name = DRIVER_NAME,
913 .pm = &zynq_gpio_dev_pm_ops,
914 .of_match_table = zynq_gpio_of_match,
915 },
916 .probe = zynq_gpio_probe,
917 .remove = zynq_gpio_remove,
918};
919
920/**
921 * zynq_gpio_init - Initial driver registration call
922 *
923 * Return: value from platform_driver_register
924 */
925static int __init zynq_gpio_init(void)
926{
927 return platform_driver_register(&zynq_gpio_driver);
928}
929postcore_initcall(zynq_gpio_init);
930
931static void __exit zynq_gpio_exit(void)
932{
933 platform_driver_unregister(&zynq_gpio_driver);
934}
935module_exit(zynq_gpio_exit);
936
937MODULE_AUTHOR("Xilinx Inc.");
938MODULE_DESCRIPTION("Zynq GPIO driver");
939MODULE_LICENSE("GPL");