Loading...
1/*
2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/irqchip/mips-gic.h>
14#include <linux/sched.h>
15#include <linux/slab.h>
16#include <linux/smp.h>
17#include <linux/types.h>
18
19#include <asm/bcache.h>
20#include <asm/mips-cm.h>
21#include <asm/mips-cpc.h>
22#include <asm/mips_mt.h>
23#include <asm/mipsregs.h>
24#include <asm/pm-cps.h>
25#include <asm/r4kcache.h>
26#include <asm/smp-cps.h>
27#include <asm/time.h>
28#include <asm/uasm.h>
29
30static DECLARE_BITMAP(core_power, NR_CPUS);
31
32struct core_boot_config *mips_cps_core_bootcfg;
33
34static unsigned core_vpe_count(unsigned core)
35{
36 unsigned cfg;
37
38 if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
39 return 1;
40
41 mips_cm_lock_other(core, 0);
42 cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
43 mips_cm_unlock_other();
44 return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
45}
46
47static void __init cps_smp_setup(void)
48{
49 unsigned int ncores, nvpes, core_vpes;
50 int c, v;
51
52 /* Detect & record VPE topology */
53 ncores = mips_cm_numcores();
54 pr_info("VPE topology ");
55 for (c = nvpes = 0; c < ncores; c++) {
56 core_vpes = core_vpe_count(c);
57 pr_cont("%c%u", c ? ',' : '{', core_vpes);
58
59 /* Use the number of VPEs in core 0 for smp_num_siblings */
60 if (!c)
61 smp_num_siblings = core_vpes;
62
63 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
64 cpu_data[nvpes + v].core = c;
65#ifdef CONFIG_MIPS_MT_SMP
66 cpu_data[nvpes + v].vpe_id = v;
67#endif
68 }
69
70 nvpes += core_vpes;
71 }
72 pr_cont("} total %u\n", nvpes);
73
74 /* Indicate present CPUs (CPU being synonymous with VPE) */
75 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
76 set_cpu_possible(v, true);
77 set_cpu_present(v, true);
78 __cpu_number_map[v] = v;
79 __cpu_logical_map[v] = v;
80 }
81
82 /* Set a coherent default CCA (CWB) */
83 change_c0_config(CONF_CM_CMASK, 0x5);
84
85 /* Core 0 is powered up (we're running on it) */
86 bitmap_set(core_power, 0, 1);
87
88 /* Initialise core 0 */
89 mips_cps_core_init();
90
91 /* Make core 0 coherent with everything */
92 write_gcr_cl_coherence(0xff);
93
94#ifdef CONFIG_MIPS_MT_FPAFF
95 /* If we have an FPU, enroll ourselves in the FPU-full mask */
96 if (cpu_has_fpu)
97 cpumask_set_cpu(0, &mt_fpu_cpumask);
98#endif /* CONFIG_MIPS_MT_FPAFF */
99}
100
101static void __init cps_prepare_cpus(unsigned int max_cpus)
102{
103 unsigned ncores, core_vpes, c, cca;
104 bool cca_unsuitable;
105 u32 *entry_code;
106
107 mips_mt_set_cpuoptions();
108
109 /* Detect whether the CCA is unsuited to multi-core SMP */
110 cca = read_c0_config() & CONF_CM_CMASK;
111 switch (cca) {
112 case 0x4: /* CWBE */
113 case 0x5: /* CWB */
114 /* The CCA is coherent, multi-core is fine */
115 cca_unsuitable = false;
116 break;
117
118 default:
119 /* CCA is not coherent, multi-core is not usable */
120 cca_unsuitable = true;
121 }
122
123 /* Warn the user if the CCA prevents multi-core */
124 ncores = mips_cm_numcores();
125 if (cca_unsuitable && ncores > 1) {
126 pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
127 cca);
128
129 for_each_present_cpu(c) {
130 if (cpu_data[c].core)
131 set_cpu_present(c, false);
132 }
133 }
134
135 /*
136 * Patch the start of mips_cps_core_entry to provide:
137 *
138 * s0 = kseg0 CCA
139 */
140 entry_code = (u32 *)&mips_cps_core_entry;
141 uasm_i_addiu(&entry_code, 16, 0, cca);
142 blast_dcache_range((unsigned long)&mips_cps_core_entry,
143 (unsigned long)entry_code);
144 bc_wback_inv((unsigned long)&mips_cps_core_entry,
145 (void *)entry_code - (void *)&mips_cps_core_entry);
146 __sync();
147
148 /* Allocate core boot configuration structs */
149 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
150 GFP_KERNEL);
151 if (!mips_cps_core_bootcfg) {
152 pr_err("Failed to allocate boot config for %u cores\n", ncores);
153 goto err_out;
154 }
155
156 /* Allocate VPE boot configuration structs */
157 for (c = 0; c < ncores; c++) {
158 core_vpes = core_vpe_count(c);
159 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
160 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
161 GFP_KERNEL);
162 if (!mips_cps_core_bootcfg[c].vpe_config) {
163 pr_err("Failed to allocate %u VPE boot configs\n",
164 core_vpes);
165 goto err_out;
166 }
167 }
168
169 /* Mark this CPU as booted */
170 atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
171 1 << cpu_vpe_id(¤t_cpu_data));
172
173 return;
174err_out:
175 /* Clean up allocations */
176 if (mips_cps_core_bootcfg) {
177 for (c = 0; c < ncores; c++)
178 kfree(mips_cps_core_bootcfg[c].vpe_config);
179 kfree(mips_cps_core_bootcfg);
180 mips_cps_core_bootcfg = NULL;
181 }
182
183 /* Effectively disable SMP by declaring CPUs not present */
184 for_each_possible_cpu(c) {
185 if (c == 0)
186 continue;
187 set_cpu_present(c, false);
188 }
189}
190
191static void boot_core(unsigned core)
192{
193 u32 access, stat, seq_state;
194 unsigned timeout;
195
196 /* Select the appropriate core */
197 mips_cm_lock_other(core, 0);
198
199 /* Set its reset vector */
200 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
201
202 /* Ensure its coherency is disabled */
203 write_gcr_co_coherence(0);
204
205 /* Start it with the legacy memory map and exception base */
206 write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB);
207
208 /* Ensure the core can access the GCRs */
209 access = read_gcr_access();
210 access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
211 write_gcr_access(access);
212
213 if (mips_cpc_present()) {
214 /* Reset the core */
215 mips_cpc_lock_other(core);
216 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
217
218 timeout = 100;
219 while (true) {
220 stat = read_cpc_co_stat_conf();
221 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
222
223 /* U6 == coherent execution, ie. the core is up */
224 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
225 break;
226
227 /* Delay a little while before we start warning */
228 if (timeout) {
229 timeout--;
230 mdelay(10);
231 continue;
232 }
233
234 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
235 core, stat);
236 mdelay(1000);
237 }
238
239 mips_cpc_unlock_other();
240 } else {
241 /* Take the core out of reset */
242 write_gcr_co_reset_release(0);
243 }
244
245 mips_cm_unlock_other();
246
247 /* The core is now powered up */
248 bitmap_set(core_power, core, 1);
249}
250
251static void remote_vpe_boot(void *dummy)
252{
253 mips_cps_boot_vpes();
254}
255
256static void cps_boot_secondary(int cpu, struct task_struct *idle)
257{
258 unsigned core = cpu_data[cpu].core;
259 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
260 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
261 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
262 unsigned int remote;
263 int err;
264
265 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
266 vpe_cfg->sp = __KSTK_TOS(idle);
267 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
268
269 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
270
271 preempt_disable();
272
273 if (!test_bit(core, core_power)) {
274 /* Boot a VPE on a powered down core */
275 boot_core(core);
276 goto out;
277 }
278
279 if (core != current_cpu_data.core) {
280 /* Boot a VPE on another powered up core */
281 for (remote = 0; remote < NR_CPUS; remote++) {
282 if (cpu_data[remote].core != core)
283 continue;
284 if (cpu_online(remote))
285 break;
286 }
287 BUG_ON(remote >= NR_CPUS);
288
289 err = smp_call_function_single(remote, remote_vpe_boot,
290 NULL, 1);
291 if (err)
292 panic("Failed to call remote CPU\n");
293 goto out;
294 }
295
296 BUG_ON(!cpu_has_mipsmt);
297
298 /* Boot a VPE on this core */
299 mips_cps_boot_vpes();
300out:
301 preempt_enable();
302}
303
304static void cps_init_secondary(void)
305{
306 /* Disable MT - we only want to run 1 TC per VPE */
307 if (cpu_has_mipsmt)
308 dmt();
309
310 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
311 STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
312}
313
314static void cps_smp_finish(void)
315{
316 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
317
318#ifdef CONFIG_MIPS_MT_FPAFF
319 /* If we have an FPU, enroll ourselves in the FPU-full mask */
320 if (cpu_has_fpu)
321 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
322#endif /* CONFIG_MIPS_MT_FPAFF */
323
324 local_irq_enable();
325}
326
327#ifdef CONFIG_HOTPLUG_CPU
328
329static int cps_cpu_disable(void)
330{
331 unsigned cpu = smp_processor_id();
332 struct core_boot_config *core_cfg;
333
334 if (!cpu)
335 return -EBUSY;
336
337 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
338 return -EINVAL;
339
340 core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
341 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
342 smp_mb__after_atomic();
343 set_cpu_online(cpu, false);
344 cpumask_clear_cpu(cpu, &cpu_callin_map);
345
346 return 0;
347}
348
349static DECLARE_COMPLETION(cpu_death_chosen);
350static unsigned cpu_death_sibling;
351static enum {
352 CPU_DEATH_HALT,
353 CPU_DEATH_POWER,
354} cpu_death;
355
356void play_dead(void)
357{
358 unsigned cpu, core;
359
360 local_irq_disable();
361 idle_task_exit();
362 cpu = smp_processor_id();
363 cpu_death = CPU_DEATH_POWER;
364
365 if (cpu_has_mipsmt) {
366 core = cpu_data[cpu].core;
367
368 /* Look for another online VPE within the core */
369 for_each_online_cpu(cpu_death_sibling) {
370 if (cpu_data[cpu_death_sibling].core != core)
371 continue;
372
373 /*
374 * There is an online VPE within the core. Just halt
375 * this TC and leave the core alone.
376 */
377 cpu_death = CPU_DEATH_HALT;
378 break;
379 }
380 }
381
382 /* This CPU has chosen its way out */
383 complete(&cpu_death_chosen);
384
385 if (cpu_death == CPU_DEATH_HALT) {
386 /* Halt this TC */
387 write_c0_tchalt(TCHALT_H);
388 instruction_hazard();
389 } else {
390 /* Power down the core */
391 cps_pm_enter_state(CPS_PM_POWER_GATED);
392 }
393
394 /* This should never be reached */
395 panic("Failed to offline CPU %u", cpu);
396}
397
398static void wait_for_sibling_halt(void *ptr_cpu)
399{
400 unsigned cpu = (unsigned long)ptr_cpu;
401 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
402 unsigned halted;
403 unsigned long flags;
404
405 do {
406 local_irq_save(flags);
407 settc(vpe_id);
408 halted = read_tc_c0_tchalt();
409 local_irq_restore(flags);
410 } while (!(halted & TCHALT_H));
411}
412
413static void cps_cpu_die(unsigned int cpu)
414{
415 unsigned core = cpu_data[cpu].core;
416 unsigned stat;
417 int err;
418
419 /* Wait for the cpu to choose its way out */
420 if (!wait_for_completion_timeout(&cpu_death_chosen,
421 msecs_to_jiffies(5000))) {
422 pr_err("CPU%u: didn't offline\n", cpu);
423 return;
424 }
425
426 /*
427 * Now wait for the CPU to actually offline. Without doing this that
428 * offlining may race with one or more of:
429 *
430 * - Onlining the CPU again.
431 * - Powering down the core if another VPE within it is offlined.
432 * - A sibling VPE entering a non-coherent state.
433 *
434 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
435 * with which we could race, so do nothing.
436 */
437 if (cpu_death == CPU_DEATH_POWER) {
438 /*
439 * Wait for the core to enter a powered down or clock gated
440 * state, the latter happening when a JTAG probe is connected
441 * in which case the CPC will refuse to power down the core.
442 */
443 do {
444 mips_cpc_lock_other(core);
445 stat = read_cpc_co_stat_conf();
446 stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
447 mips_cpc_unlock_other();
448 } while (stat != CPC_Cx_STAT_CONF_SEQSTATE_D0 &&
449 stat != CPC_Cx_STAT_CONF_SEQSTATE_D2 &&
450 stat != CPC_Cx_STAT_CONF_SEQSTATE_U2);
451
452 /* Indicate the core is powered off */
453 bitmap_clear(core_power, core, 1);
454 } else if (cpu_has_mipsmt) {
455 /*
456 * Have a CPU with access to the offlined CPUs registers wait
457 * for its TC to halt.
458 */
459 err = smp_call_function_single(cpu_death_sibling,
460 wait_for_sibling_halt,
461 (void *)(unsigned long)cpu, 1);
462 if (err)
463 panic("Failed to call remote sibling CPU\n");
464 }
465}
466
467#endif /* CONFIG_HOTPLUG_CPU */
468
469static struct plat_smp_ops cps_smp_ops = {
470 .smp_setup = cps_smp_setup,
471 .prepare_cpus = cps_prepare_cpus,
472 .boot_secondary = cps_boot_secondary,
473 .init_secondary = cps_init_secondary,
474 .smp_finish = cps_smp_finish,
475 .send_ipi_single = mips_smp_send_ipi_single,
476 .send_ipi_mask = mips_smp_send_ipi_mask,
477#ifdef CONFIG_HOTPLUG_CPU
478 .cpu_disable = cps_cpu_disable,
479 .cpu_die = cps_cpu_die,
480#endif
481};
482
483bool mips_cps_smp_in_use(void)
484{
485 extern struct plat_smp_ops *mp_ops;
486 return mp_ops == &cps_smp_ops;
487}
488
489int register_cps_smp_ops(void)
490{
491 if (!mips_cm_present()) {
492 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
493 return -ENODEV;
494 }
495
496 /* check we have a GIC - we need one for IPIs */
497 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
498 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
499 return -ENODEV;
500 }
501
502 register_smp_ops(&cps_smp_ops);
503 return 0;
504}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7#include <linux/cpu.h>
8#include <linux/delay.h>
9#include <linux/io.h>
10#include <linux/sched/task_stack.h>
11#include <linux/sched/hotplug.h>
12#include <linux/slab.h>
13#include <linux/smp.h>
14#include <linux/types.h>
15#include <linux/irq.h>
16
17#include <asm/bcache.h>
18#include <asm/mips-cps.h>
19#include <asm/mips_mt.h>
20#include <asm/mipsregs.h>
21#include <asm/pm-cps.h>
22#include <asm/r4kcache.h>
23#include <asm/smp-cps.h>
24#include <asm/time.h>
25#include <asm/uasm.h>
26
27static bool threads_disabled;
28static DECLARE_BITMAP(core_power, NR_CPUS);
29
30struct core_boot_config *mips_cps_core_bootcfg;
31
32static int __init setup_nothreads(char *s)
33{
34 threads_disabled = true;
35 return 0;
36}
37early_param("nothreads", setup_nothreads);
38
39static unsigned core_vpe_count(unsigned int cluster, unsigned core)
40{
41 if (threads_disabled)
42 return 1;
43
44 return mips_cps_numvps(cluster, core);
45}
46
47static void __init cps_smp_setup(void)
48{
49 unsigned int nclusters, ncores, nvpes, core_vpes;
50 unsigned long core_entry;
51 int cl, c, v;
52
53 /* Detect & record VPE topology */
54 nvpes = 0;
55 nclusters = mips_cps_numclusters();
56 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
57 for (cl = 0; cl < nclusters; cl++) {
58 if (cl > 0)
59 pr_cont(",");
60 pr_cont("{");
61
62 ncores = mips_cps_numcores(cl);
63 for (c = 0; c < ncores; c++) {
64 core_vpes = core_vpe_count(cl, c);
65
66 if (c > 0)
67 pr_cont(",");
68 pr_cont("%u", core_vpes);
69
70 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
71 if (!cl && !c)
72 smp_num_siblings = core_vpes;
73
74 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
75 cpu_set_cluster(&cpu_data[nvpes + v], cl);
76 cpu_set_core(&cpu_data[nvpes + v], c);
77 cpu_set_vpe_id(&cpu_data[nvpes + v], v);
78 }
79
80 nvpes += core_vpes;
81 }
82
83 pr_cont("}");
84 }
85 pr_cont(" total %u\n", nvpes);
86
87 /* Indicate present CPUs (CPU being synonymous with VPE) */
88 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
89 set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
90 set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
91 __cpu_number_map[v] = v;
92 __cpu_logical_map[v] = v;
93 }
94
95 /* Set a coherent default CCA (CWB) */
96 change_c0_config(CONF_CM_CMASK, 0x5);
97
98 /* Core 0 is powered up (we're running on it) */
99 bitmap_set(core_power, 0, 1);
100
101 /* Initialise core 0 */
102 mips_cps_core_init();
103
104 /* Make core 0 coherent with everything */
105 write_gcr_cl_coherence(0xff);
106
107 if (mips_cm_revision() >= CM_REV_CM3) {
108 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
109 write_gcr_bev_base(core_entry);
110 }
111
112#ifdef CONFIG_MIPS_MT_FPAFF
113 /* If we have an FPU, enroll ourselves in the FPU-full mask */
114 if (cpu_has_fpu)
115 cpumask_set_cpu(0, &mt_fpu_cpumask);
116#endif /* CONFIG_MIPS_MT_FPAFF */
117}
118
119static void __init cps_prepare_cpus(unsigned int max_cpus)
120{
121 unsigned ncores, core_vpes, c, cca;
122 bool cca_unsuitable, cores_limited;
123 u32 *entry_code;
124
125 mips_mt_set_cpuoptions();
126
127 /* Detect whether the CCA is unsuited to multi-core SMP */
128 cca = read_c0_config() & CONF_CM_CMASK;
129 switch (cca) {
130 case 0x4: /* CWBE */
131 case 0x5: /* CWB */
132 /* The CCA is coherent, multi-core is fine */
133 cca_unsuitable = false;
134 break;
135
136 default:
137 /* CCA is not coherent, multi-core is not usable */
138 cca_unsuitable = true;
139 }
140
141 /* Warn the user if the CCA prevents multi-core */
142 cores_limited = false;
143 if (cca_unsuitable || cpu_has_dc_aliases) {
144 for_each_present_cpu(c) {
145 if (cpus_are_siblings(smp_processor_id(), c))
146 continue;
147
148 set_cpu_present(c, false);
149 cores_limited = true;
150 }
151 }
152 if (cores_limited)
153 pr_warn("Using only one core due to %s%s%s\n",
154 cca_unsuitable ? "unsuitable CCA" : "",
155 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
156 cpu_has_dc_aliases ? "dcache aliasing" : "");
157
158 /*
159 * Patch the start of mips_cps_core_entry to provide:
160 *
161 * s0 = kseg0 CCA
162 */
163 entry_code = (u32 *)&mips_cps_core_entry;
164 uasm_i_addiu(&entry_code, 16, 0, cca);
165 blast_dcache_range((unsigned long)&mips_cps_core_entry,
166 (unsigned long)entry_code);
167 bc_wback_inv((unsigned long)&mips_cps_core_entry,
168 (void *)entry_code - (void *)&mips_cps_core_entry);
169 __sync();
170
171 /* Allocate core boot configuration structs */
172 ncores = mips_cps_numcores(0);
173 mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
174 GFP_KERNEL);
175 if (!mips_cps_core_bootcfg) {
176 pr_err("Failed to allocate boot config for %u cores\n", ncores);
177 goto err_out;
178 }
179
180 /* Allocate VPE boot configuration structs */
181 for (c = 0; c < ncores; c++) {
182 core_vpes = core_vpe_count(0, c);
183 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
184 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
185 GFP_KERNEL);
186 if (!mips_cps_core_bootcfg[c].vpe_config) {
187 pr_err("Failed to allocate %u VPE boot configs\n",
188 core_vpes);
189 goto err_out;
190 }
191 }
192
193 /* Mark this CPU as booted */
194 atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask,
195 1 << cpu_vpe_id(¤t_cpu_data));
196
197 return;
198err_out:
199 /* Clean up allocations */
200 if (mips_cps_core_bootcfg) {
201 for (c = 0; c < ncores; c++)
202 kfree(mips_cps_core_bootcfg[c].vpe_config);
203 kfree(mips_cps_core_bootcfg);
204 mips_cps_core_bootcfg = NULL;
205 }
206
207 /* Effectively disable SMP by declaring CPUs not present */
208 for_each_possible_cpu(c) {
209 if (c == 0)
210 continue;
211 set_cpu_present(c, false);
212 }
213}
214
215static void boot_core(unsigned int core, unsigned int vpe_id)
216{
217 u32 stat, seq_state;
218 unsigned timeout;
219
220 /* Select the appropriate core */
221 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
222
223 /* Set its reset vector */
224 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
225
226 /* Ensure its coherency is disabled */
227 write_gcr_co_coherence(0);
228
229 /* Start it with the legacy memory map and exception base */
230 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
231
232 /* Ensure the core can access the GCRs */
233 set_gcr_access(1 << core);
234
235 if (mips_cpc_present()) {
236 /* Reset the core */
237 mips_cpc_lock_other(core);
238
239 if (mips_cm_revision() >= CM_REV_CM3) {
240 /* Run only the requested VP following the reset */
241 write_cpc_co_vp_stop(0xf);
242 write_cpc_co_vp_run(1 << vpe_id);
243
244 /*
245 * Ensure that the VP_RUN register is written before the
246 * core leaves reset.
247 */
248 wmb();
249 }
250
251 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
252
253 timeout = 100;
254 while (true) {
255 stat = read_cpc_co_stat_conf();
256 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
257 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
258
259 /* U6 == coherent execution, ie. the core is up */
260 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
261 break;
262
263 /* Delay a little while before we start warning */
264 if (timeout) {
265 timeout--;
266 mdelay(10);
267 continue;
268 }
269
270 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
271 core, stat);
272 mdelay(1000);
273 }
274
275 mips_cpc_unlock_other();
276 } else {
277 /* Take the core out of reset */
278 write_gcr_co_reset_release(0);
279 }
280
281 mips_cm_unlock_other();
282
283 /* The core is now powered up */
284 bitmap_set(core_power, core, 1);
285}
286
287static void remote_vpe_boot(void *dummy)
288{
289 unsigned core = cpu_core(¤t_cpu_data);
290 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
291
292 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
293}
294
295static int cps_boot_secondary(int cpu, struct task_struct *idle)
296{
297 unsigned core = cpu_core(&cpu_data[cpu]);
298 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
299 struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
300 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
301 unsigned long core_entry;
302 unsigned int remote;
303 int err;
304
305 /* We don't yet support booting CPUs in other clusters */
306 if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
307 return -ENOSYS;
308
309 vpe_cfg->pc = (unsigned long)&smp_bootstrap;
310 vpe_cfg->sp = __KSTK_TOS(idle);
311 vpe_cfg->gp = (unsigned long)task_thread_info(idle);
312
313 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
314
315 preempt_disable();
316
317 if (!test_bit(core, core_power)) {
318 /* Boot a VPE on a powered down core */
319 boot_core(core, vpe_id);
320 goto out;
321 }
322
323 if (cpu_has_vp) {
324 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
325 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
326 write_gcr_co_reset_base(core_entry);
327 mips_cm_unlock_other();
328 }
329
330 if (!cpus_are_siblings(cpu, smp_processor_id())) {
331 /* Boot a VPE on another powered up core */
332 for (remote = 0; remote < NR_CPUS; remote++) {
333 if (!cpus_are_siblings(cpu, remote))
334 continue;
335 if (cpu_online(remote))
336 break;
337 }
338 if (remote >= NR_CPUS) {
339 pr_crit("No online CPU in core %u to start CPU%d\n",
340 core, cpu);
341 goto out;
342 }
343
344 err = smp_call_function_single(remote, remote_vpe_boot,
345 NULL, 1);
346 if (err)
347 panic("Failed to call remote CPU\n");
348 goto out;
349 }
350
351 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
352
353 /* Boot a VPE on this core */
354 mips_cps_boot_vpes(core_cfg, vpe_id);
355out:
356 preempt_enable();
357 return 0;
358}
359
360static void cps_init_secondary(void)
361{
362 /* Disable MT - we only want to run 1 TC per VPE */
363 if (cpu_has_mipsmt)
364 dmt();
365
366 if (mips_cm_revision() >= CM_REV_CM3) {
367 unsigned int ident = read_gic_vl_ident();
368
369 /*
370 * Ensure that our calculation of the VP ID matches up with
371 * what the GIC reports, otherwise we'll have configured
372 * interrupts incorrectly.
373 */
374 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
375 }
376
377 if (cpu_has_veic)
378 clear_c0_status(ST0_IM);
379 else
380 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
381 STATUSF_IP4 | STATUSF_IP5 |
382 STATUSF_IP6 | STATUSF_IP7);
383}
384
385static void cps_smp_finish(void)
386{
387 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
388
389#ifdef CONFIG_MIPS_MT_FPAFF
390 /* If we have an FPU, enroll ourselves in the FPU-full mask */
391 if (cpu_has_fpu)
392 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
393#endif /* CONFIG_MIPS_MT_FPAFF */
394
395 local_irq_enable();
396}
397
398#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
399
400enum cpu_death {
401 CPU_DEATH_HALT,
402 CPU_DEATH_POWER,
403};
404
405static void cps_shutdown_this_cpu(enum cpu_death death)
406{
407 unsigned int cpu, core, vpe_id;
408
409 cpu = smp_processor_id();
410 core = cpu_core(&cpu_data[cpu]);
411
412 if (death == CPU_DEATH_HALT) {
413 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
414
415 pr_debug("Halting core %d VP%d\n", core, vpe_id);
416 if (cpu_has_mipsmt) {
417 /* Halt this TC */
418 write_c0_tchalt(TCHALT_H);
419 instruction_hazard();
420 } else if (cpu_has_vp) {
421 write_cpc_cl_vp_stop(1 << vpe_id);
422
423 /* Ensure that the VP_STOP register is written */
424 wmb();
425 }
426 } else {
427 pr_debug("Gating power to core %d\n", core);
428 /* Power down the core */
429 cps_pm_enter_state(CPS_PM_POWER_GATED);
430 }
431}
432
433#ifdef CONFIG_KEXEC
434
435static void cps_kexec_nonboot_cpu(void)
436{
437 if (cpu_has_mipsmt || cpu_has_vp)
438 cps_shutdown_this_cpu(CPU_DEATH_HALT);
439 else
440 cps_shutdown_this_cpu(CPU_DEATH_POWER);
441}
442
443#endif /* CONFIG_KEXEC */
444
445#endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
446
447#ifdef CONFIG_HOTPLUG_CPU
448
449static int cps_cpu_disable(void)
450{
451 unsigned cpu = smp_processor_id();
452 struct core_boot_config *core_cfg;
453
454 if (!cps_pm_support_state(CPS_PM_POWER_GATED))
455 return -EINVAL;
456
457 core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)];
458 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
459 smp_mb__after_atomic();
460 set_cpu_online(cpu, false);
461 calculate_cpu_foreign_map();
462 irq_migrate_all_off_this_cpu();
463
464 return 0;
465}
466
467static unsigned cpu_death_sibling;
468static enum cpu_death cpu_death;
469
470void play_dead(void)
471{
472 unsigned int cpu;
473
474 local_irq_disable();
475 idle_task_exit();
476 cpu = smp_processor_id();
477 cpu_death = CPU_DEATH_POWER;
478
479 pr_debug("CPU%d going offline\n", cpu);
480
481 if (cpu_has_mipsmt || cpu_has_vp) {
482 /* Look for another online VPE within the core */
483 for_each_online_cpu(cpu_death_sibling) {
484 if (!cpus_are_siblings(cpu, cpu_death_sibling))
485 continue;
486
487 /*
488 * There is an online VPE within the core. Just halt
489 * this TC and leave the core alone.
490 */
491 cpu_death = CPU_DEATH_HALT;
492 break;
493 }
494 }
495
496 /* This CPU has chosen its way out */
497 (void)cpu_report_death();
498
499 cps_shutdown_this_cpu(cpu_death);
500
501 /* This should never be reached */
502 panic("Failed to offline CPU %u", cpu);
503}
504
505static void wait_for_sibling_halt(void *ptr_cpu)
506{
507 unsigned cpu = (unsigned long)ptr_cpu;
508 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
509 unsigned halted;
510 unsigned long flags;
511
512 do {
513 local_irq_save(flags);
514 settc(vpe_id);
515 halted = read_tc_c0_tchalt();
516 local_irq_restore(flags);
517 } while (!(halted & TCHALT_H));
518}
519
520static void cps_cpu_die(unsigned int cpu)
521{
522 unsigned core = cpu_core(&cpu_data[cpu]);
523 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
524 ktime_t fail_time;
525 unsigned stat;
526 int err;
527
528 /* Wait for the cpu to choose its way out */
529 if (!cpu_wait_death(cpu, 5)) {
530 pr_err("CPU%u: didn't offline\n", cpu);
531 return;
532 }
533
534 /*
535 * Now wait for the CPU to actually offline. Without doing this that
536 * offlining may race with one or more of:
537 *
538 * - Onlining the CPU again.
539 * - Powering down the core if another VPE within it is offlined.
540 * - A sibling VPE entering a non-coherent state.
541 *
542 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
543 * with which we could race, so do nothing.
544 */
545 if (cpu_death == CPU_DEATH_POWER) {
546 /*
547 * Wait for the core to enter a powered down or clock gated
548 * state, the latter happening when a JTAG probe is connected
549 * in which case the CPC will refuse to power down the core.
550 */
551 fail_time = ktime_add_ms(ktime_get(), 2000);
552 do {
553 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
554 mips_cpc_lock_other(core);
555 stat = read_cpc_co_stat_conf();
556 stat &= CPC_Cx_STAT_CONF_SEQSTATE;
557 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
558 mips_cpc_unlock_other();
559 mips_cm_unlock_other();
560
561 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
562 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
563 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
564 break;
565
566 /*
567 * The core ought to have powered down, but didn't &
568 * now we don't really know what state it's in. It's
569 * likely that its _pwr_up pin has been wired to logic
570 * 1 & it powered back up as soon as we powered it
571 * down...
572 *
573 * The best we can do is warn the user & continue in
574 * the hope that the core is doing nothing harmful &
575 * might behave properly if we online it later.
576 */
577 if (WARN(ktime_after(ktime_get(), fail_time),
578 "CPU%u hasn't powered down, seq. state %u\n",
579 cpu, stat))
580 break;
581 } while (1);
582
583 /* Indicate the core is powered off */
584 bitmap_clear(core_power, core, 1);
585 } else if (cpu_has_mipsmt) {
586 /*
587 * Have a CPU with access to the offlined CPUs registers wait
588 * for its TC to halt.
589 */
590 err = smp_call_function_single(cpu_death_sibling,
591 wait_for_sibling_halt,
592 (void *)(unsigned long)cpu, 1);
593 if (err)
594 panic("Failed to call remote sibling CPU\n");
595 } else if (cpu_has_vp) {
596 do {
597 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
598 stat = read_cpc_co_vp_running();
599 mips_cm_unlock_other();
600 } while (stat & (1 << vpe_id));
601 }
602}
603
604#endif /* CONFIG_HOTPLUG_CPU */
605
606static const struct plat_smp_ops cps_smp_ops = {
607 .smp_setup = cps_smp_setup,
608 .prepare_cpus = cps_prepare_cpus,
609 .boot_secondary = cps_boot_secondary,
610 .init_secondary = cps_init_secondary,
611 .smp_finish = cps_smp_finish,
612 .send_ipi_single = mips_smp_send_ipi_single,
613 .send_ipi_mask = mips_smp_send_ipi_mask,
614#ifdef CONFIG_HOTPLUG_CPU
615 .cpu_disable = cps_cpu_disable,
616 .cpu_die = cps_cpu_die,
617#endif
618#ifdef CONFIG_KEXEC
619 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu,
620#endif
621};
622
623bool mips_cps_smp_in_use(void)
624{
625 extern const struct plat_smp_ops *mp_ops;
626 return mp_ops == &cps_smp_ops;
627}
628
629int register_cps_smp_ops(void)
630{
631 if (!mips_cm_present()) {
632 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
633 return -ENODEV;
634 }
635
636 /* check we have a GIC - we need one for IPIs */
637 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
638 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
639 return -ENODEV;
640 }
641
642 register_smp_ops(&cps_smp_ops);
643 return 0;
644}