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1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
17#include <linux/smp.h>
18#include <linux/stddef.h>
19#include <linux/export.h>
20
21#include <asm/bugs.h>
22#include <asm/cpu.h>
23#include <asm/cpu-features.h>
24#include <asm/cpu-type.h>
25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
27#include <asm/mipsmtregs.h>
28#include <asm/msa.h>
29#include <asm/watch.h>
30#include <asm/elf.h>
31#include <asm/pgtable-bits.h>
32#include <asm/spram.h>
33#include <asm/uaccess.h>
34
35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37
38/*
39 * Get the FPU Implementation/Revision.
40 */
41static inline unsigned long cpu_get_fpu_id(void)
42{
43 unsigned long tmp, fpu_id;
44
45 tmp = read_c0_status();
46 __enable_fpu(FPU_AS_IS);
47 fpu_id = read_32bit_cp1_register(CP1_REVISION);
48 write_c0_status(tmp);
49 return fpu_id;
50}
51
52/*
53 * Check if the CPU has an external FPU.
54 */
55static inline int __cpu_has_fpu(void)
56{
57 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
58}
59
60static inline unsigned long cpu_get_msa_id(void)
61{
62 unsigned long status, msa_id;
63
64 status = read_c0_status();
65 __enable_fpu(FPU_64BIT);
66 enable_msa();
67 msa_id = read_msa_ir();
68 disable_msa();
69 write_c0_status(status);
70 return msa_id;
71}
72
73/*
74 * Determine the FCSR mask for FPU hardware.
75 */
76static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
77{
78 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
79
80 fcsr = c->fpu_csr31;
81 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
82
83 sr = read_c0_status();
84 __enable_fpu(FPU_AS_IS);
85
86 fcsr0 = fcsr & mask;
87 write_32bit_cp1_register(CP1_STATUS, fcsr0);
88 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
89
90 fcsr1 = fcsr | ~mask;
91 write_32bit_cp1_register(CP1_STATUS, fcsr1);
92 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
93
94 write_32bit_cp1_register(CP1_STATUS, fcsr);
95
96 write_c0_status(sr);
97
98 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
99}
100
101/*
102 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
103 * supported by FPU hardware.
104 */
105static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
106{
107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
110 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
111
112 sr = read_c0_status();
113 __enable_fpu(FPU_AS_IS);
114
115 fir = read_32bit_cp1_register(CP1_REVISION);
116 if (fir & MIPS_FPIR_HAS2008) {
117 fcsr = read_32bit_cp1_register(CP1_STATUS);
118
119 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
120 write_32bit_cp1_register(CP1_STATUS, fcsr0);
121 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
122
123 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
124 write_32bit_cp1_register(CP1_STATUS, fcsr1);
125 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
126
127 write_32bit_cp1_register(CP1_STATUS, fcsr);
128
129 if (!(fcsr0 & FPU_CSR_NAN2008))
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 if (fcsr1 & FPU_CSR_NAN2008)
132 c->options |= MIPS_CPU_NAN_2008;
133
134 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
135 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
136 else
137 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
138
139 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
140 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
141 else
142 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
143 } else {
144 c->options |= MIPS_CPU_NAN_LEGACY;
145 }
146
147 write_c0_status(sr);
148 } else {
149 c->options |= MIPS_CPU_NAN_LEGACY;
150 }
151}
152
153/*
154 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
155 * ABS.fmt/NEG.fmt execution mode.
156 */
157static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
158
159/*
160 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
161 * to support by the FPU emulator according to the IEEE 754 conformance
162 * mode selected. Note that "relaxed" straps the emulator so that it
163 * allows 2008-NaN binaries even for legacy processors.
164 */
165static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
166{
167 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
168 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
169 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170
171 switch (ieee754) {
172 case STRICT:
173 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
174 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
175 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
176 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
177 } else {
178 c->options |= MIPS_CPU_NAN_LEGACY;
179 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
180 }
181 break;
182 case LEGACY:
183 c->options |= MIPS_CPU_NAN_LEGACY;
184 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
185 break;
186 case STD2008:
187 c->options |= MIPS_CPU_NAN_2008;
188 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 break;
191 case RELAXED:
192 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
193 break;
194 }
195}
196
197/*
198 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
199 * according to the "ieee754=" parameter.
200 */
201static void cpu_set_nan_2008(struct cpuinfo_mips *c)
202{
203 switch (ieee754) {
204 case STRICT:
205 mips_use_nan_legacy = !!cpu_has_nan_legacy;
206 mips_use_nan_2008 = !!cpu_has_nan_2008;
207 break;
208 case LEGACY:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !cpu_has_nan_legacy;
211 break;
212 case STD2008:
213 mips_use_nan_legacy = !cpu_has_nan_2008;
214 mips_use_nan_2008 = !!cpu_has_nan_2008;
215 break;
216 case RELAXED:
217 mips_use_nan_legacy = true;
218 mips_use_nan_2008 = true;
219 break;
220 }
221}
222
223/*
224 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
225 * settings:
226 *
227 * strict: accept binaries that request a NaN encoding supported by the FPU
228 * legacy: only accept legacy-NaN binaries
229 * 2008: only accept 2008-NaN binaries
230 * relaxed: accept any binaries regardless of whether supported by the FPU
231 */
232static int __init ieee754_setup(char *s)
233{
234 if (!s)
235 return -1;
236 else if (!strcmp(s, "strict"))
237 ieee754 = STRICT;
238 else if (!strcmp(s, "legacy"))
239 ieee754 = LEGACY;
240 else if (!strcmp(s, "2008"))
241 ieee754 = STD2008;
242 else if (!strcmp(s, "relaxed"))
243 ieee754 = RELAXED;
244 else
245 return -1;
246
247 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
248 cpu_set_nofpu_2008(&boot_cpu_data);
249 cpu_set_nan_2008(&boot_cpu_data);
250
251 return 0;
252}
253
254early_param("ieee754", ieee754_setup);
255
256/*
257 * Set the FIR feature flags for the FPU emulator.
258 */
259static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
260{
261 u32 value;
262
263 value = 0;
264 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
265 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
266 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
267 value |= MIPS_FPIR_D | MIPS_FPIR_S;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
269 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
270 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
271 if (c->options & MIPS_CPU_NAN_2008)
272 value |= MIPS_FPIR_HAS2008;
273 c->fpu_id = value;
274}
275
276/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
277static unsigned int mips_nofpu_msk31;
278
279/*
280 * Set options for FPU hardware.
281 */
282static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
283{
284 c->fpu_id = cpu_get_fpu_id();
285 mips_nofpu_msk31 = c->fpu_msk31;
286
287 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
288 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
289 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
290 if (c->fpu_id & MIPS_FPIR_3D)
291 c->ases |= MIPS_ASE_MIPS3D;
292 if (c->fpu_id & MIPS_FPIR_FREP)
293 c->options |= MIPS_CPU_FRE;
294 }
295
296 cpu_set_fpu_fcsr_mask(c);
297 cpu_set_fpu_2008(c);
298 cpu_set_nan_2008(c);
299}
300
301/*
302 * Set options for the FPU emulator.
303 */
304static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
305{
306 c->options &= ~MIPS_CPU_FPU;
307 c->fpu_msk31 = mips_nofpu_msk31;
308
309 cpu_set_nofpu_2008(c);
310 cpu_set_nan_2008(c);
311 cpu_set_nofpu_id(c);
312}
313
314static int mips_fpu_disabled;
315
316static int __init fpu_disable(char *s)
317{
318 cpu_set_nofpu_opts(&boot_cpu_data);
319 mips_fpu_disabled = 1;
320
321 return 1;
322}
323
324__setup("nofpu", fpu_disable);
325
326int mips_dsp_disabled;
327
328static int __init dsp_disable(char *s)
329{
330 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
331 mips_dsp_disabled = 1;
332
333 return 1;
334}
335
336__setup("nodsp", dsp_disable);
337
338static int mips_htw_disabled;
339
340static int __init htw_disable(char *s)
341{
342 mips_htw_disabled = 1;
343 cpu_data[0].options &= ~MIPS_CPU_HTW;
344 write_c0_pwctl(read_c0_pwctl() &
345 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
346
347 return 1;
348}
349
350__setup("nohtw", htw_disable);
351
352static int mips_ftlb_disabled;
353static int mips_has_ftlb_configured;
354
355static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
356
357static int __init ftlb_disable(char *s)
358{
359 unsigned int config4, mmuextdef;
360
361 /*
362 * If the core hasn't done any FTLB configuration, there is nothing
363 * for us to do here.
364 */
365 if (!mips_has_ftlb_configured)
366 return 1;
367
368 /* Disable it in the boot cpu */
369 if (set_ftlb_enable(&cpu_data[0], 0)) {
370 pr_warn("Can't turn FTLB off\n");
371 return 1;
372 }
373
374 back_to_back_c0_hazard();
375
376 config4 = read_c0_config4();
377
378 /* Check that FTLB has been disabled */
379 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
380 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
381 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
382 /* This should never happen */
383 pr_warn("FTLB could not be disabled!\n");
384 return 1;
385 }
386
387 mips_ftlb_disabled = 1;
388 mips_has_ftlb_configured = 0;
389
390 /*
391 * noftlb is mainly used for debug purposes so print
392 * an informative message instead of using pr_debug()
393 */
394 pr_info("FTLB has been disabled\n");
395
396 /*
397 * Some of these bits are duplicated in the decode_config4.
398 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
399 * once FTLB has been disabled so undo what decode_config4 did.
400 */
401 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
402 cpu_data[0].tlbsizeftlbsets;
403 cpu_data[0].tlbsizeftlbsets = 0;
404 cpu_data[0].tlbsizeftlbways = 0;
405
406 return 1;
407}
408
409__setup("noftlb", ftlb_disable);
410
411
412static inline void check_errata(void)
413{
414 struct cpuinfo_mips *c = ¤t_cpu_data;
415
416 switch (current_cpu_type()) {
417 case CPU_34K:
418 /*
419 * Erratum "RPS May Cause Incorrect Instruction Execution"
420 * This code only handles VPE0, any SMP/RTOS code
421 * making use of VPE1 will be responsable for that VPE.
422 */
423 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
424 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
425 break;
426 default:
427 break;
428 }
429}
430
431void __init check_bugs32(void)
432{
433 check_errata();
434}
435
436/*
437 * Probe whether cpu has config register by trying to play with
438 * alternate cache bit and see whether it matters.
439 * It's used by cpu_probe to distinguish between R3000A and R3081.
440 */
441static inline int cpu_has_confreg(void)
442{
443#ifdef CONFIG_CPU_R3000
444 extern unsigned long r3k_cache_size(unsigned long);
445 unsigned long size1, size2;
446 unsigned long cfg = read_c0_conf();
447
448 size1 = r3k_cache_size(ST0_ISC);
449 write_c0_conf(cfg ^ R30XX_CONF_AC);
450 size2 = r3k_cache_size(ST0_ISC);
451 write_c0_conf(cfg);
452 return size1 != size2;
453#else
454 return 0;
455#endif
456}
457
458static inline void set_elf_platform(int cpu, const char *plat)
459{
460 if (cpu == 0)
461 __elf_platform = plat;
462}
463
464static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
465{
466#ifdef __NEED_VMBITS_PROBE
467 write_c0_entryhi(0x3fffffffffffe000ULL);
468 back_to_back_c0_hazard();
469 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
470#endif
471}
472
473static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
474{
475 switch (isa) {
476 case MIPS_CPU_ISA_M64R2:
477 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
478 case MIPS_CPU_ISA_M64R1:
479 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
480 case MIPS_CPU_ISA_V:
481 c->isa_level |= MIPS_CPU_ISA_V;
482 case MIPS_CPU_ISA_IV:
483 c->isa_level |= MIPS_CPU_ISA_IV;
484 case MIPS_CPU_ISA_III:
485 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
486 break;
487
488 /* R6 incompatible with everything else */
489 case MIPS_CPU_ISA_M64R6:
490 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
491 case MIPS_CPU_ISA_M32R6:
492 c->isa_level |= MIPS_CPU_ISA_M32R6;
493 /* Break here so we don't add incompatible ISAs */
494 break;
495 case MIPS_CPU_ISA_M32R2:
496 c->isa_level |= MIPS_CPU_ISA_M32R2;
497 case MIPS_CPU_ISA_M32R1:
498 c->isa_level |= MIPS_CPU_ISA_M32R1;
499 case MIPS_CPU_ISA_II:
500 c->isa_level |= MIPS_CPU_ISA_II;
501 break;
502 }
503}
504
505static char unknown_isa[] = KERN_ERR \
506 "Unsupported ISA type, c0.config0: %d.";
507
508static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
509{
510
511 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
512
513 /*
514 * 0 = All TLBWR instructions go to FTLB
515 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
516 * FTLB and 1 goes to the VTLB.
517 * 2 = 7:1: As above with 7:1 ratio.
518 * 3 = 3:1: As above with 3:1 ratio.
519 *
520 * Use the linear midpoint as the probability threshold.
521 */
522 if (probability >= 12)
523 return 1;
524 else if (probability >= 6)
525 return 2;
526 else
527 /*
528 * So FTLB is less than 4 times bigger than VTLB.
529 * A 3:1 ratio can still be useful though.
530 */
531 return 3;
532}
533
534static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
535{
536 unsigned int config;
537
538 /* It's implementation dependent how the FTLB can be enabled */
539 switch (c->cputype) {
540 case CPU_PROAPTIV:
541 case CPU_P5600:
542 /* proAptiv & related cores use Config6 to enable the FTLB */
543 config = read_c0_config6();
544 /* Clear the old probability value */
545 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
546 if (enable)
547 /* Enable FTLB */
548 write_c0_config6(config |
549 (calculate_ftlb_probability(c)
550 << MIPS_CONF6_FTLBP_SHIFT)
551 | MIPS_CONF6_FTLBEN);
552 else
553 /* Disable FTLB */
554 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
555 break;
556 case CPU_I6400:
557 /* I6400 & related cores use Config7 to configure FTLB */
558 config = read_c0_config7();
559 /* Clear the old probability value */
560 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
561 write_c0_config7(config | (calculate_ftlb_probability(c)
562 << MIPS_CONF7_FTLBP_SHIFT));
563 break;
564 default:
565 return 1;
566 }
567
568 return 0;
569}
570
571static inline unsigned int decode_config0(struct cpuinfo_mips *c)
572{
573 unsigned int config0;
574 int isa, mt;
575
576 config0 = read_c0_config();
577
578 /*
579 * Look for Standard TLB or Dual VTLB and FTLB
580 */
581 mt = config0 & MIPS_CONF_MT;
582 if (mt == MIPS_CONF_MT_TLB)
583 c->options |= MIPS_CPU_TLB;
584 else if (mt == MIPS_CONF_MT_FTLB)
585 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
586
587 isa = (config0 & MIPS_CONF_AT) >> 13;
588 switch (isa) {
589 case 0:
590 switch ((config0 & MIPS_CONF_AR) >> 10) {
591 case 0:
592 set_isa(c, MIPS_CPU_ISA_M32R1);
593 break;
594 case 1:
595 set_isa(c, MIPS_CPU_ISA_M32R2);
596 break;
597 case 2:
598 set_isa(c, MIPS_CPU_ISA_M32R6);
599 break;
600 default:
601 goto unknown;
602 }
603 break;
604 case 2:
605 switch ((config0 & MIPS_CONF_AR) >> 10) {
606 case 0:
607 set_isa(c, MIPS_CPU_ISA_M64R1);
608 break;
609 case 1:
610 set_isa(c, MIPS_CPU_ISA_M64R2);
611 break;
612 case 2:
613 set_isa(c, MIPS_CPU_ISA_M64R6);
614 break;
615 default:
616 goto unknown;
617 }
618 break;
619 default:
620 goto unknown;
621 }
622
623 return config0 & MIPS_CONF_M;
624
625unknown:
626 panic(unknown_isa, config0);
627}
628
629static inline unsigned int decode_config1(struct cpuinfo_mips *c)
630{
631 unsigned int config1;
632
633 config1 = read_c0_config1();
634
635 if (config1 & MIPS_CONF1_MD)
636 c->ases |= MIPS_ASE_MDMX;
637 if (config1 & MIPS_CONF1_WR)
638 c->options |= MIPS_CPU_WATCH;
639 if (config1 & MIPS_CONF1_CA)
640 c->ases |= MIPS_ASE_MIPS16;
641 if (config1 & MIPS_CONF1_EP)
642 c->options |= MIPS_CPU_EJTAG;
643 if (config1 & MIPS_CONF1_FP) {
644 c->options |= MIPS_CPU_FPU;
645 c->options |= MIPS_CPU_32FPR;
646 }
647 if (cpu_has_tlb) {
648 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
649 c->tlbsizevtlb = c->tlbsize;
650 c->tlbsizeftlbsets = 0;
651 }
652
653 return config1 & MIPS_CONF_M;
654}
655
656static inline unsigned int decode_config2(struct cpuinfo_mips *c)
657{
658 unsigned int config2;
659
660 config2 = read_c0_config2();
661
662 if (config2 & MIPS_CONF2_SL)
663 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
664
665 return config2 & MIPS_CONF_M;
666}
667
668static inline unsigned int decode_config3(struct cpuinfo_mips *c)
669{
670 unsigned int config3;
671
672 config3 = read_c0_config3();
673
674 if (config3 & MIPS_CONF3_SM) {
675 c->ases |= MIPS_ASE_SMARTMIPS;
676 c->options |= MIPS_CPU_RIXI;
677 }
678 if (config3 & MIPS_CONF3_RXI)
679 c->options |= MIPS_CPU_RIXI;
680 if (config3 & MIPS_CONF3_DSP)
681 c->ases |= MIPS_ASE_DSP;
682 if (config3 & MIPS_CONF3_DSP2P)
683 c->ases |= MIPS_ASE_DSP2P;
684 if (config3 & MIPS_CONF3_VINT)
685 c->options |= MIPS_CPU_VINT;
686 if (config3 & MIPS_CONF3_VEIC)
687 c->options |= MIPS_CPU_VEIC;
688 if (config3 & MIPS_CONF3_MT)
689 c->ases |= MIPS_ASE_MIPSMT;
690 if (config3 & MIPS_CONF3_ULRI)
691 c->options |= MIPS_CPU_ULRI;
692 if (config3 & MIPS_CONF3_ISA)
693 c->options |= MIPS_CPU_MICROMIPS;
694 if (config3 & MIPS_CONF3_VZ)
695 c->ases |= MIPS_ASE_VZ;
696 if (config3 & MIPS_CONF3_SC)
697 c->options |= MIPS_CPU_SEGMENTS;
698 if (config3 & MIPS_CONF3_MSA)
699 c->ases |= MIPS_ASE_MSA;
700 if (config3 & MIPS_CONF3_PW) {
701 c->htw_seq = 0;
702 c->options |= MIPS_CPU_HTW;
703 }
704 if (config3 & MIPS_CONF3_CDMM)
705 c->options |= MIPS_CPU_CDMM;
706 if (config3 & MIPS_CONF3_SP)
707 c->options |= MIPS_CPU_SP;
708
709 return config3 & MIPS_CONF_M;
710}
711
712static inline unsigned int decode_config4(struct cpuinfo_mips *c)
713{
714 unsigned int config4;
715 unsigned int newcf4;
716 unsigned int mmuextdef;
717 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
718
719 config4 = read_c0_config4();
720
721 if (cpu_has_tlb) {
722 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
723 c->options |= MIPS_CPU_TLBINV;
724
725 /*
726 * R6 has dropped the MMUExtDef field from config4.
727 * On R6 the fields always describe the FTLB, and only if it is
728 * present according to Config.MT.
729 */
730 if (!cpu_has_mips_r6)
731 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
732 else if (cpu_has_ftlb)
733 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
734 else
735 mmuextdef = 0;
736
737 switch (mmuextdef) {
738 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
739 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
740 c->tlbsizevtlb = c->tlbsize;
741 break;
742 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
743 c->tlbsizevtlb +=
744 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
745 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
746 c->tlbsize = c->tlbsizevtlb;
747 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
748 /* fall through */
749 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
750 if (mips_ftlb_disabled)
751 break;
752 newcf4 = (config4 & ~ftlb_page) |
753 (page_size_ftlb(mmuextdef) <<
754 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
755 write_c0_config4(newcf4);
756 back_to_back_c0_hazard();
757 config4 = read_c0_config4();
758 if (config4 != newcf4) {
759 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
760 PAGE_SIZE, config4);
761 /* Switch FTLB off */
762 set_ftlb_enable(c, 0);
763 break;
764 }
765 c->tlbsizeftlbsets = 1 <<
766 ((config4 & MIPS_CONF4_FTLBSETS) >>
767 MIPS_CONF4_FTLBSETS_SHIFT);
768 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
769 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
770 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
771 mips_has_ftlb_configured = 1;
772 break;
773 }
774 }
775
776 c->kscratch_mask = (config4 >> 16) & 0xff;
777
778 return config4 & MIPS_CONF_M;
779}
780
781static inline unsigned int decode_config5(struct cpuinfo_mips *c)
782{
783 unsigned int config5;
784
785 config5 = read_c0_config5();
786 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
787 write_c0_config5(config5);
788
789 if (config5 & MIPS_CONF5_EVA)
790 c->options |= MIPS_CPU_EVA;
791 if (config5 & MIPS_CONF5_MRP)
792 c->options |= MIPS_CPU_MAAR;
793 if (config5 & MIPS_CONF5_LLB)
794 c->options |= MIPS_CPU_RW_LLB;
795#ifdef CONFIG_XPA
796 if (config5 & MIPS_CONF5_MVH)
797 c->options |= MIPS_CPU_XPA;
798#endif
799
800 return config5 & MIPS_CONF_M;
801}
802
803static void decode_configs(struct cpuinfo_mips *c)
804{
805 int ok;
806
807 /* MIPS32 or MIPS64 compliant CPU. */
808 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
809 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
810
811 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
812
813 /* Enable FTLB if present and not disabled */
814 set_ftlb_enable(c, !mips_ftlb_disabled);
815
816 ok = decode_config0(c); /* Read Config registers. */
817 BUG_ON(!ok); /* Arch spec violation! */
818 if (ok)
819 ok = decode_config1(c);
820 if (ok)
821 ok = decode_config2(c);
822 if (ok)
823 ok = decode_config3(c);
824 if (ok)
825 ok = decode_config4(c);
826 if (ok)
827 ok = decode_config5(c);
828
829 mips_probe_watch_registers(c);
830
831 if (cpu_has_rixi) {
832 /* Enable the RIXI exceptions */
833 set_c0_pagegrain(PG_IEC);
834 back_to_back_c0_hazard();
835 /* Verify the IEC bit is set */
836 if (read_c0_pagegrain() & PG_IEC)
837 c->options |= MIPS_CPU_RIXIEX;
838 }
839
840#ifndef CONFIG_MIPS_CPS
841 if (cpu_has_mips_r2_r6) {
842 c->core = get_ebase_cpunum();
843 if (cpu_has_mipsmt)
844 c->core >>= fls(core_nvpes()) - 1;
845 }
846#endif
847}
848
849#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
850 | MIPS_CPU_COUNTER)
851
852static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
853{
854 switch (c->processor_id & PRID_IMP_MASK) {
855 case PRID_IMP_R2000:
856 c->cputype = CPU_R2000;
857 __cpu_name[cpu] = "R2000";
858 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
859 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
860 MIPS_CPU_NOFPUEX;
861 if (__cpu_has_fpu())
862 c->options |= MIPS_CPU_FPU;
863 c->tlbsize = 64;
864 break;
865 case PRID_IMP_R3000:
866 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
867 if (cpu_has_confreg()) {
868 c->cputype = CPU_R3081E;
869 __cpu_name[cpu] = "R3081";
870 } else {
871 c->cputype = CPU_R3000A;
872 __cpu_name[cpu] = "R3000A";
873 }
874 } else {
875 c->cputype = CPU_R3000;
876 __cpu_name[cpu] = "R3000";
877 }
878 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
879 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
880 MIPS_CPU_NOFPUEX;
881 if (__cpu_has_fpu())
882 c->options |= MIPS_CPU_FPU;
883 c->tlbsize = 64;
884 break;
885 case PRID_IMP_R4000:
886 if (read_c0_config() & CONF_SC) {
887 if ((c->processor_id & PRID_REV_MASK) >=
888 PRID_REV_R4400) {
889 c->cputype = CPU_R4400PC;
890 __cpu_name[cpu] = "R4400PC";
891 } else {
892 c->cputype = CPU_R4000PC;
893 __cpu_name[cpu] = "R4000PC";
894 }
895 } else {
896 int cca = read_c0_config() & CONF_CM_CMASK;
897 int mc;
898
899 /*
900 * SC and MC versions can't be reliably told apart,
901 * but only the latter support coherent caching
902 * modes so assume the firmware has set the KSEG0
903 * coherency attribute reasonably (if uncached, we
904 * assume SC).
905 */
906 switch (cca) {
907 case CONF_CM_CACHABLE_CE:
908 case CONF_CM_CACHABLE_COW:
909 case CONF_CM_CACHABLE_CUW:
910 mc = 1;
911 break;
912 default:
913 mc = 0;
914 break;
915 }
916 if ((c->processor_id & PRID_REV_MASK) >=
917 PRID_REV_R4400) {
918 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
919 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
920 } else {
921 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
922 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
923 }
924 }
925
926 set_isa(c, MIPS_CPU_ISA_III);
927 c->fpu_msk31 |= FPU_CSR_CONDX;
928 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
929 MIPS_CPU_WATCH | MIPS_CPU_VCE |
930 MIPS_CPU_LLSC;
931 c->tlbsize = 48;
932 break;
933 case PRID_IMP_VR41XX:
934 set_isa(c, MIPS_CPU_ISA_III);
935 c->fpu_msk31 |= FPU_CSR_CONDX;
936 c->options = R4K_OPTS;
937 c->tlbsize = 32;
938 switch (c->processor_id & 0xf0) {
939 case PRID_REV_VR4111:
940 c->cputype = CPU_VR4111;
941 __cpu_name[cpu] = "NEC VR4111";
942 break;
943 case PRID_REV_VR4121:
944 c->cputype = CPU_VR4121;
945 __cpu_name[cpu] = "NEC VR4121";
946 break;
947 case PRID_REV_VR4122:
948 if ((c->processor_id & 0xf) < 0x3) {
949 c->cputype = CPU_VR4122;
950 __cpu_name[cpu] = "NEC VR4122";
951 } else {
952 c->cputype = CPU_VR4181A;
953 __cpu_name[cpu] = "NEC VR4181A";
954 }
955 break;
956 case PRID_REV_VR4130:
957 if ((c->processor_id & 0xf) < 0x4) {
958 c->cputype = CPU_VR4131;
959 __cpu_name[cpu] = "NEC VR4131";
960 } else {
961 c->cputype = CPU_VR4133;
962 c->options |= MIPS_CPU_LLSC;
963 __cpu_name[cpu] = "NEC VR4133";
964 }
965 break;
966 default:
967 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
968 c->cputype = CPU_VR41XX;
969 __cpu_name[cpu] = "NEC Vr41xx";
970 break;
971 }
972 break;
973 case PRID_IMP_R4300:
974 c->cputype = CPU_R4300;
975 __cpu_name[cpu] = "R4300";
976 set_isa(c, MIPS_CPU_ISA_III);
977 c->fpu_msk31 |= FPU_CSR_CONDX;
978 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
979 MIPS_CPU_LLSC;
980 c->tlbsize = 32;
981 break;
982 case PRID_IMP_R4600:
983 c->cputype = CPU_R4600;
984 __cpu_name[cpu] = "R4600";
985 set_isa(c, MIPS_CPU_ISA_III);
986 c->fpu_msk31 |= FPU_CSR_CONDX;
987 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
988 MIPS_CPU_LLSC;
989 c->tlbsize = 48;
990 break;
991 #if 0
992 case PRID_IMP_R4650:
993 /*
994 * This processor doesn't have an MMU, so it's not
995 * "real easy" to run Linux on it. It is left purely
996 * for documentation. Commented out because it shares
997 * it's c0_prid id number with the TX3900.
998 */
999 c->cputype = CPU_R4650;
1000 __cpu_name[cpu] = "R4650";
1001 set_isa(c, MIPS_CPU_ISA_III);
1002 c->fpu_msk31 |= FPU_CSR_CONDX;
1003 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1004 c->tlbsize = 48;
1005 break;
1006 #endif
1007 case PRID_IMP_TX39:
1008 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1009 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1010
1011 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1012 c->cputype = CPU_TX3927;
1013 __cpu_name[cpu] = "TX3927";
1014 c->tlbsize = 64;
1015 } else {
1016 switch (c->processor_id & PRID_REV_MASK) {
1017 case PRID_REV_TX3912:
1018 c->cputype = CPU_TX3912;
1019 __cpu_name[cpu] = "TX3912";
1020 c->tlbsize = 32;
1021 break;
1022 case PRID_REV_TX3922:
1023 c->cputype = CPU_TX3922;
1024 __cpu_name[cpu] = "TX3922";
1025 c->tlbsize = 64;
1026 break;
1027 }
1028 }
1029 break;
1030 case PRID_IMP_R4700:
1031 c->cputype = CPU_R4700;
1032 __cpu_name[cpu] = "R4700";
1033 set_isa(c, MIPS_CPU_ISA_III);
1034 c->fpu_msk31 |= FPU_CSR_CONDX;
1035 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1036 MIPS_CPU_LLSC;
1037 c->tlbsize = 48;
1038 break;
1039 case PRID_IMP_TX49:
1040 c->cputype = CPU_TX49XX;
1041 __cpu_name[cpu] = "R49XX";
1042 set_isa(c, MIPS_CPU_ISA_III);
1043 c->fpu_msk31 |= FPU_CSR_CONDX;
1044 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1045 if (!(c->processor_id & 0x08))
1046 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1047 c->tlbsize = 48;
1048 break;
1049 case PRID_IMP_R5000:
1050 c->cputype = CPU_R5000;
1051 __cpu_name[cpu] = "R5000";
1052 set_isa(c, MIPS_CPU_ISA_IV);
1053 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1054 MIPS_CPU_LLSC;
1055 c->tlbsize = 48;
1056 break;
1057 case PRID_IMP_R5432:
1058 c->cputype = CPU_R5432;
1059 __cpu_name[cpu] = "R5432";
1060 set_isa(c, MIPS_CPU_ISA_IV);
1061 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1062 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1063 c->tlbsize = 48;
1064 break;
1065 case PRID_IMP_R5500:
1066 c->cputype = CPU_R5500;
1067 __cpu_name[cpu] = "R5500";
1068 set_isa(c, MIPS_CPU_ISA_IV);
1069 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1070 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1071 c->tlbsize = 48;
1072 break;
1073 case PRID_IMP_NEVADA:
1074 c->cputype = CPU_NEVADA;
1075 __cpu_name[cpu] = "Nevada";
1076 set_isa(c, MIPS_CPU_ISA_IV);
1077 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1078 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1079 c->tlbsize = 48;
1080 break;
1081 case PRID_IMP_R6000:
1082 c->cputype = CPU_R6000;
1083 __cpu_name[cpu] = "R6000";
1084 set_isa(c, MIPS_CPU_ISA_II);
1085 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1086 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1087 MIPS_CPU_LLSC;
1088 c->tlbsize = 32;
1089 break;
1090 case PRID_IMP_R6000A:
1091 c->cputype = CPU_R6000A;
1092 __cpu_name[cpu] = "R6000A";
1093 set_isa(c, MIPS_CPU_ISA_II);
1094 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1095 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1096 MIPS_CPU_LLSC;
1097 c->tlbsize = 32;
1098 break;
1099 case PRID_IMP_RM7000:
1100 c->cputype = CPU_RM7000;
1101 __cpu_name[cpu] = "RM7000";
1102 set_isa(c, MIPS_CPU_ISA_IV);
1103 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1104 MIPS_CPU_LLSC;
1105 /*
1106 * Undocumented RM7000: Bit 29 in the info register of
1107 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1108 * entries.
1109 *
1110 * 29 1 => 64 entry JTLB
1111 * 0 => 48 entry JTLB
1112 */
1113 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1114 break;
1115 case PRID_IMP_R8000:
1116 c->cputype = CPU_R8000;
1117 __cpu_name[cpu] = "RM8000";
1118 set_isa(c, MIPS_CPU_ISA_IV);
1119 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1120 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1121 MIPS_CPU_LLSC;
1122 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1123 break;
1124 case PRID_IMP_R10000:
1125 c->cputype = CPU_R10000;
1126 __cpu_name[cpu] = "R10000";
1127 set_isa(c, MIPS_CPU_ISA_IV);
1128 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1129 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1130 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1131 MIPS_CPU_LLSC;
1132 c->tlbsize = 64;
1133 break;
1134 case PRID_IMP_R12000:
1135 c->cputype = CPU_R12000;
1136 __cpu_name[cpu] = "R12000";
1137 set_isa(c, MIPS_CPU_ISA_IV);
1138 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1139 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1140 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1141 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1142 c->tlbsize = 64;
1143 break;
1144 case PRID_IMP_R14000:
1145 if (((c->processor_id >> 4) & 0x0f) > 2) {
1146 c->cputype = CPU_R16000;
1147 __cpu_name[cpu] = "R16000";
1148 } else {
1149 c->cputype = CPU_R14000;
1150 __cpu_name[cpu] = "R14000";
1151 }
1152 set_isa(c, MIPS_CPU_ISA_IV);
1153 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1154 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1155 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1156 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1157 c->tlbsize = 64;
1158 break;
1159 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1160 switch (c->processor_id & PRID_REV_MASK) {
1161 case PRID_REV_LOONGSON2E:
1162 c->cputype = CPU_LOONGSON2;
1163 __cpu_name[cpu] = "ICT Loongson-2";
1164 set_elf_platform(cpu, "loongson2e");
1165 set_isa(c, MIPS_CPU_ISA_III);
1166 c->fpu_msk31 |= FPU_CSR_CONDX;
1167 break;
1168 case PRID_REV_LOONGSON2F:
1169 c->cputype = CPU_LOONGSON2;
1170 __cpu_name[cpu] = "ICT Loongson-2";
1171 set_elf_platform(cpu, "loongson2f");
1172 set_isa(c, MIPS_CPU_ISA_III);
1173 c->fpu_msk31 |= FPU_CSR_CONDX;
1174 break;
1175 case PRID_REV_LOONGSON3A:
1176 c->cputype = CPU_LOONGSON3;
1177 __cpu_name[cpu] = "ICT Loongson-3";
1178 set_elf_platform(cpu, "loongson3a");
1179 set_isa(c, MIPS_CPU_ISA_M64R1);
1180 break;
1181 case PRID_REV_LOONGSON3B_R1:
1182 case PRID_REV_LOONGSON3B_R2:
1183 c->cputype = CPU_LOONGSON3;
1184 __cpu_name[cpu] = "ICT Loongson-3";
1185 set_elf_platform(cpu, "loongson3b");
1186 set_isa(c, MIPS_CPU_ISA_M64R1);
1187 break;
1188 }
1189
1190 c->options = R4K_OPTS |
1191 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1192 MIPS_CPU_32FPR;
1193 c->tlbsize = 64;
1194 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1195 break;
1196 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1197 decode_configs(c);
1198
1199 c->cputype = CPU_LOONGSON1;
1200
1201 switch (c->processor_id & PRID_REV_MASK) {
1202 case PRID_REV_LOONGSON1B:
1203 __cpu_name[cpu] = "Loongson 1B";
1204 break;
1205 }
1206
1207 break;
1208 }
1209}
1210
1211static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1212{
1213 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1214 switch (c->processor_id & PRID_IMP_MASK) {
1215 case PRID_IMP_QEMU_GENERIC:
1216 c->writecombine = _CACHE_UNCACHED;
1217 c->cputype = CPU_QEMU_GENERIC;
1218 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1219 break;
1220 case PRID_IMP_4KC:
1221 c->cputype = CPU_4KC;
1222 c->writecombine = _CACHE_UNCACHED;
1223 __cpu_name[cpu] = "MIPS 4Kc";
1224 break;
1225 case PRID_IMP_4KEC:
1226 case PRID_IMP_4KECR2:
1227 c->cputype = CPU_4KEC;
1228 c->writecombine = _CACHE_UNCACHED;
1229 __cpu_name[cpu] = "MIPS 4KEc";
1230 break;
1231 case PRID_IMP_4KSC:
1232 case PRID_IMP_4KSD:
1233 c->cputype = CPU_4KSC;
1234 c->writecombine = _CACHE_UNCACHED;
1235 __cpu_name[cpu] = "MIPS 4KSc";
1236 break;
1237 case PRID_IMP_5KC:
1238 c->cputype = CPU_5KC;
1239 c->writecombine = _CACHE_UNCACHED;
1240 __cpu_name[cpu] = "MIPS 5Kc";
1241 break;
1242 case PRID_IMP_5KE:
1243 c->cputype = CPU_5KE;
1244 c->writecombine = _CACHE_UNCACHED;
1245 __cpu_name[cpu] = "MIPS 5KE";
1246 break;
1247 case PRID_IMP_20KC:
1248 c->cputype = CPU_20KC;
1249 c->writecombine = _CACHE_UNCACHED;
1250 __cpu_name[cpu] = "MIPS 20Kc";
1251 break;
1252 case PRID_IMP_24K:
1253 c->cputype = CPU_24K;
1254 c->writecombine = _CACHE_UNCACHED;
1255 __cpu_name[cpu] = "MIPS 24Kc";
1256 break;
1257 case PRID_IMP_24KE:
1258 c->cputype = CPU_24K;
1259 c->writecombine = _CACHE_UNCACHED;
1260 __cpu_name[cpu] = "MIPS 24KEc";
1261 break;
1262 case PRID_IMP_25KF:
1263 c->cputype = CPU_25KF;
1264 c->writecombine = _CACHE_UNCACHED;
1265 __cpu_name[cpu] = "MIPS 25Kc";
1266 break;
1267 case PRID_IMP_34K:
1268 c->cputype = CPU_34K;
1269 c->writecombine = _CACHE_UNCACHED;
1270 __cpu_name[cpu] = "MIPS 34Kc";
1271 break;
1272 case PRID_IMP_74K:
1273 c->cputype = CPU_74K;
1274 c->writecombine = _CACHE_UNCACHED;
1275 __cpu_name[cpu] = "MIPS 74Kc";
1276 break;
1277 case PRID_IMP_M14KC:
1278 c->cputype = CPU_M14KC;
1279 c->writecombine = _CACHE_UNCACHED;
1280 __cpu_name[cpu] = "MIPS M14Kc";
1281 break;
1282 case PRID_IMP_M14KEC:
1283 c->cputype = CPU_M14KEC;
1284 c->writecombine = _CACHE_UNCACHED;
1285 __cpu_name[cpu] = "MIPS M14KEc";
1286 break;
1287 case PRID_IMP_1004K:
1288 c->cputype = CPU_1004K;
1289 c->writecombine = _CACHE_UNCACHED;
1290 __cpu_name[cpu] = "MIPS 1004Kc";
1291 break;
1292 case PRID_IMP_1074K:
1293 c->cputype = CPU_1074K;
1294 c->writecombine = _CACHE_UNCACHED;
1295 __cpu_name[cpu] = "MIPS 1074Kc";
1296 break;
1297 case PRID_IMP_INTERAPTIV_UP:
1298 c->cputype = CPU_INTERAPTIV;
1299 __cpu_name[cpu] = "MIPS interAptiv";
1300 break;
1301 case PRID_IMP_INTERAPTIV_MP:
1302 c->cputype = CPU_INTERAPTIV;
1303 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1304 break;
1305 case PRID_IMP_PROAPTIV_UP:
1306 c->cputype = CPU_PROAPTIV;
1307 __cpu_name[cpu] = "MIPS proAptiv";
1308 break;
1309 case PRID_IMP_PROAPTIV_MP:
1310 c->cputype = CPU_PROAPTIV;
1311 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1312 break;
1313 case PRID_IMP_P5600:
1314 c->cputype = CPU_P5600;
1315 __cpu_name[cpu] = "MIPS P5600";
1316 break;
1317 case PRID_IMP_I6400:
1318 c->cputype = CPU_I6400;
1319 __cpu_name[cpu] = "MIPS I6400";
1320 break;
1321 case PRID_IMP_M5150:
1322 c->cputype = CPU_M5150;
1323 __cpu_name[cpu] = "MIPS M5150";
1324 break;
1325 }
1326
1327 decode_configs(c);
1328
1329 spram_config();
1330}
1331
1332static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1333{
1334 decode_configs(c);
1335 switch (c->processor_id & PRID_IMP_MASK) {
1336 case PRID_IMP_AU1_REV1:
1337 case PRID_IMP_AU1_REV2:
1338 c->cputype = CPU_ALCHEMY;
1339 switch ((c->processor_id >> 24) & 0xff) {
1340 case 0:
1341 __cpu_name[cpu] = "Au1000";
1342 break;
1343 case 1:
1344 __cpu_name[cpu] = "Au1500";
1345 break;
1346 case 2:
1347 __cpu_name[cpu] = "Au1100";
1348 break;
1349 case 3:
1350 __cpu_name[cpu] = "Au1550";
1351 break;
1352 case 4:
1353 __cpu_name[cpu] = "Au1200";
1354 if ((c->processor_id & PRID_REV_MASK) == 2)
1355 __cpu_name[cpu] = "Au1250";
1356 break;
1357 case 5:
1358 __cpu_name[cpu] = "Au1210";
1359 break;
1360 default:
1361 __cpu_name[cpu] = "Au1xxx";
1362 break;
1363 }
1364 break;
1365 }
1366}
1367
1368static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1369{
1370 decode_configs(c);
1371
1372 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1373 switch (c->processor_id & PRID_IMP_MASK) {
1374 case PRID_IMP_SB1:
1375 c->cputype = CPU_SB1;
1376 __cpu_name[cpu] = "SiByte SB1";
1377 /* FPU in pass1 is known to have issues. */
1378 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1379 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1380 break;
1381 case PRID_IMP_SB1A:
1382 c->cputype = CPU_SB1A;
1383 __cpu_name[cpu] = "SiByte SB1A";
1384 break;
1385 }
1386}
1387
1388static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1389{
1390 decode_configs(c);
1391 switch (c->processor_id & PRID_IMP_MASK) {
1392 case PRID_IMP_SR71000:
1393 c->cputype = CPU_SR71000;
1394 __cpu_name[cpu] = "Sandcraft SR71000";
1395 c->scache.ways = 8;
1396 c->tlbsize = 64;
1397 break;
1398 }
1399}
1400
1401static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1402{
1403 decode_configs(c);
1404 switch (c->processor_id & PRID_IMP_MASK) {
1405 case PRID_IMP_PR4450:
1406 c->cputype = CPU_PR4450;
1407 __cpu_name[cpu] = "Philips PR4450";
1408 set_isa(c, MIPS_CPU_ISA_M32R1);
1409 break;
1410 }
1411}
1412
1413static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1414{
1415 decode_configs(c);
1416 switch (c->processor_id & PRID_IMP_MASK) {
1417 case PRID_IMP_BMIPS32_REV4:
1418 case PRID_IMP_BMIPS32_REV8:
1419 c->cputype = CPU_BMIPS32;
1420 __cpu_name[cpu] = "Broadcom BMIPS32";
1421 set_elf_platform(cpu, "bmips32");
1422 break;
1423 case PRID_IMP_BMIPS3300:
1424 case PRID_IMP_BMIPS3300_ALT:
1425 case PRID_IMP_BMIPS3300_BUG:
1426 c->cputype = CPU_BMIPS3300;
1427 __cpu_name[cpu] = "Broadcom BMIPS3300";
1428 set_elf_platform(cpu, "bmips3300");
1429 break;
1430 case PRID_IMP_BMIPS43XX: {
1431 int rev = c->processor_id & PRID_REV_MASK;
1432
1433 if (rev >= PRID_REV_BMIPS4380_LO &&
1434 rev <= PRID_REV_BMIPS4380_HI) {
1435 c->cputype = CPU_BMIPS4380;
1436 __cpu_name[cpu] = "Broadcom BMIPS4380";
1437 set_elf_platform(cpu, "bmips4380");
1438 } else {
1439 c->cputype = CPU_BMIPS4350;
1440 __cpu_name[cpu] = "Broadcom BMIPS4350";
1441 set_elf_platform(cpu, "bmips4350");
1442 }
1443 break;
1444 }
1445 case PRID_IMP_BMIPS5000:
1446 case PRID_IMP_BMIPS5200:
1447 c->cputype = CPU_BMIPS5000;
1448 __cpu_name[cpu] = "Broadcom BMIPS5000";
1449 set_elf_platform(cpu, "bmips5000");
1450 c->options |= MIPS_CPU_ULRI;
1451 break;
1452 }
1453}
1454
1455static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1456{
1457 decode_configs(c);
1458 switch (c->processor_id & PRID_IMP_MASK) {
1459 case PRID_IMP_CAVIUM_CN38XX:
1460 case PRID_IMP_CAVIUM_CN31XX:
1461 case PRID_IMP_CAVIUM_CN30XX:
1462 c->cputype = CPU_CAVIUM_OCTEON;
1463 __cpu_name[cpu] = "Cavium Octeon";
1464 goto platform;
1465 case PRID_IMP_CAVIUM_CN58XX:
1466 case PRID_IMP_CAVIUM_CN56XX:
1467 case PRID_IMP_CAVIUM_CN50XX:
1468 case PRID_IMP_CAVIUM_CN52XX:
1469 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1470 __cpu_name[cpu] = "Cavium Octeon+";
1471platform:
1472 set_elf_platform(cpu, "octeon");
1473 break;
1474 case PRID_IMP_CAVIUM_CN61XX:
1475 case PRID_IMP_CAVIUM_CN63XX:
1476 case PRID_IMP_CAVIUM_CN66XX:
1477 case PRID_IMP_CAVIUM_CN68XX:
1478 case PRID_IMP_CAVIUM_CNF71XX:
1479 c->cputype = CPU_CAVIUM_OCTEON2;
1480 __cpu_name[cpu] = "Cavium Octeon II";
1481 set_elf_platform(cpu, "octeon2");
1482 break;
1483 case PRID_IMP_CAVIUM_CN70XX:
1484 case PRID_IMP_CAVIUM_CN78XX:
1485 c->cputype = CPU_CAVIUM_OCTEON3;
1486 __cpu_name[cpu] = "Cavium Octeon III";
1487 set_elf_platform(cpu, "octeon3");
1488 break;
1489 default:
1490 printk(KERN_INFO "Unknown Octeon chip!\n");
1491 c->cputype = CPU_UNKNOWN;
1492 break;
1493 }
1494}
1495
1496static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1497{
1498 decode_configs(c);
1499 /* JZRISC does not implement the CP0 counter. */
1500 c->options &= ~MIPS_CPU_COUNTER;
1501 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1502 switch (c->processor_id & PRID_IMP_MASK) {
1503 case PRID_IMP_JZRISC:
1504 c->cputype = CPU_JZRISC;
1505 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1506 __cpu_name[cpu] = "Ingenic JZRISC";
1507 break;
1508 default:
1509 panic("Unknown Ingenic Processor ID!");
1510 break;
1511 }
1512}
1513
1514static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1515{
1516 decode_configs(c);
1517
1518 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1519 c->cputype = CPU_ALCHEMY;
1520 __cpu_name[cpu] = "Au1300";
1521 /* following stuff is not for Alchemy */
1522 return;
1523 }
1524
1525 c->options = (MIPS_CPU_TLB |
1526 MIPS_CPU_4KEX |
1527 MIPS_CPU_COUNTER |
1528 MIPS_CPU_DIVEC |
1529 MIPS_CPU_WATCH |
1530 MIPS_CPU_EJTAG |
1531 MIPS_CPU_LLSC);
1532
1533 switch (c->processor_id & PRID_IMP_MASK) {
1534 case PRID_IMP_NETLOGIC_XLP2XX:
1535 case PRID_IMP_NETLOGIC_XLP9XX:
1536 case PRID_IMP_NETLOGIC_XLP5XX:
1537 c->cputype = CPU_XLP;
1538 __cpu_name[cpu] = "Broadcom XLPII";
1539 break;
1540
1541 case PRID_IMP_NETLOGIC_XLP8XX:
1542 case PRID_IMP_NETLOGIC_XLP3XX:
1543 c->cputype = CPU_XLP;
1544 __cpu_name[cpu] = "Netlogic XLP";
1545 break;
1546
1547 case PRID_IMP_NETLOGIC_XLR732:
1548 case PRID_IMP_NETLOGIC_XLR716:
1549 case PRID_IMP_NETLOGIC_XLR532:
1550 case PRID_IMP_NETLOGIC_XLR308:
1551 case PRID_IMP_NETLOGIC_XLR532C:
1552 case PRID_IMP_NETLOGIC_XLR516C:
1553 case PRID_IMP_NETLOGIC_XLR508C:
1554 case PRID_IMP_NETLOGIC_XLR308C:
1555 c->cputype = CPU_XLR;
1556 __cpu_name[cpu] = "Netlogic XLR";
1557 break;
1558
1559 case PRID_IMP_NETLOGIC_XLS608:
1560 case PRID_IMP_NETLOGIC_XLS408:
1561 case PRID_IMP_NETLOGIC_XLS404:
1562 case PRID_IMP_NETLOGIC_XLS208:
1563 case PRID_IMP_NETLOGIC_XLS204:
1564 case PRID_IMP_NETLOGIC_XLS108:
1565 case PRID_IMP_NETLOGIC_XLS104:
1566 case PRID_IMP_NETLOGIC_XLS616B:
1567 case PRID_IMP_NETLOGIC_XLS608B:
1568 case PRID_IMP_NETLOGIC_XLS416B:
1569 case PRID_IMP_NETLOGIC_XLS412B:
1570 case PRID_IMP_NETLOGIC_XLS408B:
1571 case PRID_IMP_NETLOGIC_XLS404B:
1572 c->cputype = CPU_XLR;
1573 __cpu_name[cpu] = "Netlogic XLS";
1574 break;
1575
1576 default:
1577 pr_info("Unknown Netlogic chip id [%02x]!\n",
1578 c->processor_id);
1579 c->cputype = CPU_XLR;
1580 break;
1581 }
1582
1583 if (c->cputype == CPU_XLP) {
1584 set_isa(c, MIPS_CPU_ISA_M64R2);
1585 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1586 /* This will be updated again after all threads are woken up */
1587 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1588 } else {
1589 set_isa(c, MIPS_CPU_ISA_M64R1);
1590 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1591 }
1592 c->kscratch_mask = 0xf;
1593}
1594
1595#ifdef CONFIG_64BIT
1596/* For use by uaccess.h */
1597u64 __ua_limit;
1598EXPORT_SYMBOL(__ua_limit);
1599#endif
1600
1601const char *__cpu_name[NR_CPUS];
1602const char *__elf_platform;
1603
1604void cpu_probe(void)
1605{
1606 struct cpuinfo_mips *c = ¤t_cpu_data;
1607 unsigned int cpu = smp_processor_id();
1608
1609 c->processor_id = PRID_IMP_UNKNOWN;
1610 c->fpu_id = FPIR_IMP_NONE;
1611 c->cputype = CPU_UNKNOWN;
1612 c->writecombine = _CACHE_UNCACHED;
1613
1614 c->fpu_csr31 = FPU_CSR_RN;
1615 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1616
1617 c->processor_id = read_c0_prid();
1618 switch (c->processor_id & PRID_COMP_MASK) {
1619 case PRID_COMP_LEGACY:
1620 cpu_probe_legacy(c, cpu);
1621 break;
1622 case PRID_COMP_MIPS:
1623 cpu_probe_mips(c, cpu);
1624 break;
1625 case PRID_COMP_ALCHEMY:
1626 cpu_probe_alchemy(c, cpu);
1627 break;
1628 case PRID_COMP_SIBYTE:
1629 cpu_probe_sibyte(c, cpu);
1630 break;
1631 case PRID_COMP_BROADCOM:
1632 cpu_probe_broadcom(c, cpu);
1633 break;
1634 case PRID_COMP_SANDCRAFT:
1635 cpu_probe_sandcraft(c, cpu);
1636 break;
1637 case PRID_COMP_NXP:
1638 cpu_probe_nxp(c, cpu);
1639 break;
1640 case PRID_COMP_CAVIUM:
1641 cpu_probe_cavium(c, cpu);
1642 break;
1643 case PRID_COMP_INGENIC_D0:
1644 case PRID_COMP_INGENIC_D1:
1645 case PRID_COMP_INGENIC_E1:
1646 cpu_probe_ingenic(c, cpu);
1647 break;
1648 case PRID_COMP_NETLOGIC:
1649 cpu_probe_netlogic(c, cpu);
1650 break;
1651 }
1652
1653 BUG_ON(!__cpu_name[cpu]);
1654 BUG_ON(c->cputype == CPU_UNKNOWN);
1655
1656 /*
1657 * Platform code can force the cpu type to optimize code
1658 * generation. In that case be sure the cpu type is correctly
1659 * manually setup otherwise it could trigger some nasty bugs.
1660 */
1661 BUG_ON(current_cpu_type() != c->cputype);
1662
1663 if (mips_fpu_disabled)
1664 c->options &= ~MIPS_CPU_FPU;
1665
1666 if (mips_dsp_disabled)
1667 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1668
1669 if (mips_htw_disabled) {
1670 c->options &= ~MIPS_CPU_HTW;
1671 write_c0_pwctl(read_c0_pwctl() &
1672 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1673 }
1674
1675 if (c->options & MIPS_CPU_FPU)
1676 cpu_set_fpu_opts(c);
1677 else
1678 cpu_set_nofpu_opts(c);
1679
1680 if (cpu_has_bp_ghist)
1681 write_c0_r10k_diag(read_c0_r10k_diag() |
1682 R10K_DIAG_E_GHIST);
1683
1684 if (cpu_has_mips_r2_r6) {
1685 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1686 /* R2 has Performance Counter Interrupt indicator */
1687 c->options |= MIPS_CPU_PCI;
1688 }
1689 else
1690 c->srsets = 1;
1691
1692 if (cpu_has_mips_r6)
1693 elf_hwcap |= HWCAP_MIPS_R6;
1694
1695 if (cpu_has_msa) {
1696 c->msa_id = cpu_get_msa_id();
1697 WARN(c->msa_id & MSA_IR_WRPF,
1698 "Vector register partitioning unimplemented!");
1699 elf_hwcap |= HWCAP_MIPS_MSA;
1700 }
1701
1702 cpu_probe_vmbits(c);
1703
1704#ifdef CONFIG_64BIT
1705 if (cpu == 0)
1706 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1707#endif
1708}
1709
1710void cpu_report(void)
1711{
1712 struct cpuinfo_mips *c = ¤t_cpu_data;
1713
1714 pr_info("CPU%d revision is: %08x (%s)\n",
1715 smp_processor_id(), c->processor_id, cpu_name_string());
1716 if (c->options & MIPS_CPU_FPU)
1717 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1718 if (cpu_has_msa)
1719 pr_info("MSA revision is: %08x\n", c->msa_id);
1720}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/ptrace.h>
13#include <linux/smp.h>
14#include <linux/stddef.h>
15#include <linux/export.h>
16
17#include <asm/bugs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/cpu-type.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/mipsmtregs.h>
24#include <asm/msa.h>
25#include <asm/watch.h>
26#include <asm/elf.h>
27#include <asm/pgtable-bits.h>
28#include <asm/spram.h>
29#include <asm/traps.h>
30#include <linux/uaccess.h>
31
32#include "fpu-probe.h"
33
34#include <asm/mach-loongson64/cpucfg-emul.h>
35
36/* Hardware capabilities */
37unsigned int elf_hwcap __read_mostly;
38EXPORT_SYMBOL_GPL(elf_hwcap);
39
40static inline unsigned long cpu_get_msa_id(void)
41{
42 unsigned long status, msa_id;
43
44 status = read_c0_status();
45 __enable_fpu(FPU_64BIT);
46 enable_msa();
47 msa_id = read_msa_ir();
48 disable_msa();
49 write_c0_status(status);
50 return msa_id;
51}
52
53static int mips_dsp_disabled;
54
55static int __init dsp_disable(char *s)
56{
57 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
58 mips_dsp_disabled = 1;
59
60 return 1;
61}
62
63__setup("nodsp", dsp_disable);
64
65static int mips_htw_disabled;
66
67static int __init htw_disable(char *s)
68{
69 mips_htw_disabled = 1;
70 cpu_data[0].options &= ~MIPS_CPU_HTW;
71 write_c0_pwctl(read_c0_pwctl() &
72 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
73
74 return 1;
75}
76
77__setup("nohtw", htw_disable);
78
79static int mips_ftlb_disabled;
80static int mips_has_ftlb_configured;
81
82enum ftlb_flags {
83 FTLB_EN = 1 << 0,
84 FTLB_SET_PROB = 1 << 1,
85};
86
87static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
88
89static int __init ftlb_disable(char *s)
90{
91 unsigned int config4, mmuextdef;
92
93 /*
94 * If the core hasn't done any FTLB configuration, there is nothing
95 * for us to do here.
96 */
97 if (!mips_has_ftlb_configured)
98 return 1;
99
100 /* Disable it in the boot cpu */
101 if (set_ftlb_enable(&cpu_data[0], 0)) {
102 pr_warn("Can't turn FTLB off\n");
103 return 1;
104 }
105
106 config4 = read_c0_config4();
107
108 /* Check that FTLB has been disabled */
109 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
110 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
111 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
112 /* This should never happen */
113 pr_warn("FTLB could not be disabled!\n");
114 return 1;
115 }
116
117 mips_ftlb_disabled = 1;
118 mips_has_ftlb_configured = 0;
119
120 /*
121 * noftlb is mainly used for debug purposes so print
122 * an informative message instead of using pr_debug()
123 */
124 pr_info("FTLB has been disabled\n");
125
126 /*
127 * Some of these bits are duplicated in the decode_config4.
128 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
129 * once FTLB has been disabled so undo what decode_config4 did.
130 */
131 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
132 cpu_data[0].tlbsizeftlbsets;
133 cpu_data[0].tlbsizeftlbsets = 0;
134 cpu_data[0].tlbsizeftlbways = 0;
135
136 return 1;
137}
138
139__setup("noftlb", ftlb_disable);
140
141/*
142 * Check if the CPU has per tc perf counters
143 */
144static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
145{
146 if (read_c0_config7() & MTI_CONF7_PTC)
147 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
148}
149
150static inline void check_errata(void)
151{
152 struct cpuinfo_mips *c = ¤t_cpu_data;
153
154 switch (current_cpu_type()) {
155 case CPU_34K:
156 /*
157 * Erratum "RPS May Cause Incorrect Instruction Execution"
158 * This code only handles VPE0, any SMP/RTOS code
159 * making use of VPE1 will be responsible for that VPE.
160 */
161 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
162 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
163 break;
164 default:
165 break;
166 }
167}
168
169void __init check_bugs32(void)
170{
171 check_errata();
172}
173
174/*
175 * Probe whether cpu has config register by trying to play with
176 * alternate cache bit and see whether it matters.
177 * It's used by cpu_probe to distinguish between R3000A and R3081.
178 */
179static inline int cpu_has_confreg(void)
180{
181#ifdef CONFIG_CPU_R3000
182 extern unsigned long r3k_cache_size(unsigned long);
183 unsigned long size1, size2;
184 unsigned long cfg = read_c0_conf();
185
186 size1 = r3k_cache_size(ST0_ISC);
187 write_c0_conf(cfg ^ R30XX_CONF_AC);
188 size2 = r3k_cache_size(ST0_ISC);
189 write_c0_conf(cfg);
190 return size1 != size2;
191#else
192 return 0;
193#endif
194}
195
196static inline void set_elf_platform(int cpu, const char *plat)
197{
198 if (cpu == 0)
199 __elf_platform = plat;
200}
201
202static inline void set_elf_base_platform(const char *plat)
203{
204 if (__elf_base_platform == NULL) {
205 __elf_base_platform = plat;
206 }
207}
208
209static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
210{
211#ifdef __NEED_VMBITS_PROBE
212 write_c0_entryhi(0x3fffffffffffe000ULL);
213 back_to_back_c0_hazard();
214 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
215#endif
216}
217
218static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
219{
220 switch (isa) {
221 case MIPS_CPU_ISA_M64R5:
222 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
223 set_elf_base_platform("mips64r5");
224 fallthrough;
225 case MIPS_CPU_ISA_M64R2:
226 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
227 set_elf_base_platform("mips64r2");
228 fallthrough;
229 case MIPS_CPU_ISA_M64R1:
230 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
231 set_elf_base_platform("mips64");
232 fallthrough;
233 case MIPS_CPU_ISA_V:
234 c->isa_level |= MIPS_CPU_ISA_V;
235 set_elf_base_platform("mips5");
236 fallthrough;
237 case MIPS_CPU_ISA_IV:
238 c->isa_level |= MIPS_CPU_ISA_IV;
239 set_elf_base_platform("mips4");
240 fallthrough;
241 case MIPS_CPU_ISA_III:
242 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
243 set_elf_base_platform("mips3");
244 break;
245
246 /* R6 incompatible with everything else */
247 case MIPS_CPU_ISA_M64R6:
248 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
249 set_elf_base_platform("mips64r6");
250 fallthrough;
251 case MIPS_CPU_ISA_M32R6:
252 c->isa_level |= MIPS_CPU_ISA_M32R6;
253 set_elf_base_platform("mips32r6");
254 /* Break here so we don't add incompatible ISAs */
255 break;
256 case MIPS_CPU_ISA_M32R5:
257 c->isa_level |= MIPS_CPU_ISA_M32R5;
258 set_elf_base_platform("mips32r5");
259 fallthrough;
260 case MIPS_CPU_ISA_M32R2:
261 c->isa_level |= MIPS_CPU_ISA_M32R2;
262 set_elf_base_platform("mips32r2");
263 fallthrough;
264 case MIPS_CPU_ISA_M32R1:
265 c->isa_level |= MIPS_CPU_ISA_M32R1;
266 set_elf_base_platform("mips32");
267 fallthrough;
268 case MIPS_CPU_ISA_II:
269 c->isa_level |= MIPS_CPU_ISA_II;
270 set_elf_base_platform("mips2");
271 break;
272 }
273}
274
275static char unknown_isa[] = KERN_ERR \
276 "Unsupported ISA type, c0.config0: %d.";
277
278static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
279{
280
281 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
282
283 /*
284 * 0 = All TLBWR instructions go to FTLB
285 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
286 * FTLB and 1 goes to the VTLB.
287 * 2 = 7:1: As above with 7:1 ratio.
288 * 3 = 3:1: As above with 3:1 ratio.
289 *
290 * Use the linear midpoint as the probability threshold.
291 */
292 if (probability >= 12)
293 return 1;
294 else if (probability >= 6)
295 return 2;
296 else
297 /*
298 * So FTLB is less than 4 times bigger than VTLB.
299 * A 3:1 ratio can still be useful though.
300 */
301 return 3;
302}
303
304static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
305{
306 unsigned int config;
307
308 /* It's implementation dependent how the FTLB can be enabled */
309 switch (c->cputype) {
310 case CPU_PROAPTIV:
311 case CPU_P5600:
312 case CPU_P6600:
313 /* proAptiv & related cores use Config6 to enable the FTLB */
314 config = read_c0_config6();
315
316 if (flags & FTLB_EN)
317 config |= MTI_CONF6_FTLBEN;
318 else
319 config &= ~MTI_CONF6_FTLBEN;
320
321 if (flags & FTLB_SET_PROB) {
322 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
323 config |= calculate_ftlb_probability(c)
324 << MTI_CONF6_FTLBP_SHIFT;
325 }
326
327 write_c0_config6(config);
328 back_to_back_c0_hazard();
329 break;
330 case CPU_I6400:
331 case CPU_I6500:
332 /* There's no way to disable the FTLB */
333 if (!(flags & FTLB_EN))
334 return 1;
335 return 0;
336 case CPU_LOONGSON64:
337 /* Flush ITLB, DTLB, VTLB and FTLB */
338 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
339 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
340 /* Loongson-3 cores use Config6 to enable the FTLB */
341 config = read_c0_config6();
342 if (flags & FTLB_EN)
343 /* Enable FTLB */
344 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
345 else
346 /* Disable FTLB */
347 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
348 break;
349 default:
350 return 1;
351 }
352
353 return 0;
354}
355
356static int mm_config(struct cpuinfo_mips *c)
357{
358 unsigned int config0, update, mm;
359
360 config0 = read_c0_config();
361 mm = config0 & MIPS_CONF_MM;
362
363 /*
364 * It's implementation dependent what type of write-merge is supported
365 * and whether it can be enabled/disabled. If it is settable lets make
366 * the merging allowed by default. Some platforms might have
367 * write-through caching unsupported. In this case just ignore the
368 * CP0.Config.MM bit field value.
369 */
370 switch (c->cputype) {
371 case CPU_24K:
372 case CPU_34K:
373 case CPU_74K:
374 case CPU_P5600:
375 case CPU_P6600:
376 c->options |= MIPS_CPU_MM_FULL;
377 update = MIPS_CONF_MM_FULL;
378 break;
379 case CPU_1004K:
380 case CPU_1074K:
381 case CPU_INTERAPTIV:
382 case CPU_PROAPTIV:
383 mm = 0;
384 fallthrough;
385 default:
386 update = 0;
387 break;
388 }
389
390 if (update) {
391 config0 = (config0 & ~MIPS_CONF_MM) | update;
392 write_c0_config(config0);
393 } else if (mm == MIPS_CONF_MM_SYSAD) {
394 c->options |= MIPS_CPU_MM_SYSAD;
395 } else if (mm == MIPS_CONF_MM_FULL) {
396 c->options |= MIPS_CPU_MM_FULL;
397 }
398
399 return 0;
400}
401
402static inline unsigned int decode_config0(struct cpuinfo_mips *c)
403{
404 unsigned int config0;
405 int isa, mt;
406
407 config0 = read_c0_config();
408
409 /*
410 * Look for Standard TLB or Dual VTLB and FTLB
411 */
412 mt = config0 & MIPS_CONF_MT;
413 if (mt == MIPS_CONF_MT_TLB)
414 c->options |= MIPS_CPU_TLB;
415 else if (mt == MIPS_CONF_MT_FTLB)
416 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
417
418 isa = (config0 & MIPS_CONF_AT) >> 13;
419 switch (isa) {
420 case 0:
421 switch ((config0 & MIPS_CONF_AR) >> 10) {
422 case 0:
423 set_isa(c, MIPS_CPU_ISA_M32R1);
424 break;
425 case 1:
426 set_isa(c, MIPS_CPU_ISA_M32R2);
427 break;
428 case 2:
429 set_isa(c, MIPS_CPU_ISA_M32R6);
430 break;
431 default:
432 goto unknown;
433 }
434 break;
435 case 2:
436 switch ((config0 & MIPS_CONF_AR) >> 10) {
437 case 0:
438 set_isa(c, MIPS_CPU_ISA_M64R1);
439 break;
440 case 1:
441 set_isa(c, MIPS_CPU_ISA_M64R2);
442 break;
443 case 2:
444 set_isa(c, MIPS_CPU_ISA_M64R6);
445 break;
446 default:
447 goto unknown;
448 }
449 break;
450 default:
451 goto unknown;
452 }
453
454 return config0 & MIPS_CONF_M;
455
456unknown:
457 panic(unknown_isa, config0);
458}
459
460static inline unsigned int decode_config1(struct cpuinfo_mips *c)
461{
462 unsigned int config1;
463
464 config1 = read_c0_config1();
465
466 if (config1 & MIPS_CONF1_MD)
467 c->ases |= MIPS_ASE_MDMX;
468 if (config1 & MIPS_CONF1_PC)
469 c->options |= MIPS_CPU_PERF;
470 if (config1 & MIPS_CONF1_WR)
471 c->options |= MIPS_CPU_WATCH;
472 if (config1 & MIPS_CONF1_CA)
473 c->ases |= MIPS_ASE_MIPS16;
474 if (config1 & MIPS_CONF1_EP)
475 c->options |= MIPS_CPU_EJTAG;
476 if (config1 & MIPS_CONF1_FP) {
477 c->options |= MIPS_CPU_FPU;
478 c->options |= MIPS_CPU_32FPR;
479 }
480 if (cpu_has_tlb) {
481 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
482 c->tlbsizevtlb = c->tlbsize;
483 c->tlbsizeftlbsets = 0;
484 }
485
486 return config1 & MIPS_CONF_M;
487}
488
489static inline unsigned int decode_config2(struct cpuinfo_mips *c)
490{
491 unsigned int config2;
492
493 config2 = read_c0_config2();
494
495 if (config2 & MIPS_CONF2_SL)
496 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
497
498 return config2 & MIPS_CONF_M;
499}
500
501static inline unsigned int decode_config3(struct cpuinfo_mips *c)
502{
503 unsigned int config3;
504
505 config3 = read_c0_config3();
506
507 if (config3 & MIPS_CONF3_SM) {
508 c->ases |= MIPS_ASE_SMARTMIPS;
509 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
510 }
511 if (config3 & MIPS_CONF3_RXI)
512 c->options |= MIPS_CPU_RIXI;
513 if (config3 & MIPS_CONF3_CTXTC)
514 c->options |= MIPS_CPU_CTXTC;
515 if (config3 & MIPS_CONF3_DSP)
516 c->ases |= MIPS_ASE_DSP;
517 if (config3 & MIPS_CONF3_DSP2P) {
518 c->ases |= MIPS_ASE_DSP2P;
519 if (cpu_has_mips_r6)
520 c->ases |= MIPS_ASE_DSP3;
521 }
522 if (config3 & MIPS_CONF3_VINT)
523 c->options |= MIPS_CPU_VINT;
524 if (config3 & MIPS_CONF3_VEIC)
525 c->options |= MIPS_CPU_VEIC;
526 if (config3 & MIPS_CONF3_LPA)
527 c->options |= MIPS_CPU_LPA;
528 if (config3 & MIPS_CONF3_MT)
529 c->ases |= MIPS_ASE_MIPSMT;
530 if (config3 & MIPS_CONF3_ULRI)
531 c->options |= MIPS_CPU_ULRI;
532 if (config3 & MIPS_CONF3_ISA)
533 c->options |= MIPS_CPU_MICROMIPS;
534 if (config3 & MIPS_CONF3_VZ)
535 c->ases |= MIPS_ASE_VZ;
536 if (config3 & MIPS_CONF3_SC)
537 c->options |= MIPS_CPU_SEGMENTS;
538 if (config3 & MIPS_CONF3_BI)
539 c->options |= MIPS_CPU_BADINSTR;
540 if (config3 & MIPS_CONF3_BP)
541 c->options |= MIPS_CPU_BADINSTRP;
542 if (config3 & MIPS_CONF3_MSA)
543 c->ases |= MIPS_ASE_MSA;
544 if (config3 & MIPS_CONF3_PW) {
545 c->htw_seq = 0;
546 c->options |= MIPS_CPU_HTW;
547 }
548 if (config3 & MIPS_CONF3_CDMM)
549 c->options |= MIPS_CPU_CDMM;
550 if (config3 & MIPS_CONF3_SP)
551 c->options |= MIPS_CPU_SP;
552
553 return config3 & MIPS_CONF_M;
554}
555
556static inline unsigned int decode_config4(struct cpuinfo_mips *c)
557{
558 unsigned int config4;
559 unsigned int newcf4;
560 unsigned int mmuextdef;
561 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
562 unsigned long asid_mask;
563
564 config4 = read_c0_config4();
565
566 if (cpu_has_tlb) {
567 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
568 c->options |= MIPS_CPU_TLBINV;
569
570 /*
571 * R6 has dropped the MMUExtDef field from config4.
572 * On R6 the fields always describe the FTLB, and only if it is
573 * present according to Config.MT.
574 */
575 if (!cpu_has_mips_r6)
576 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
577 else if (cpu_has_ftlb)
578 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
579 else
580 mmuextdef = 0;
581
582 switch (mmuextdef) {
583 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
584 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
585 c->tlbsizevtlb = c->tlbsize;
586 break;
587 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
588 c->tlbsizevtlb +=
589 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
590 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
591 c->tlbsize = c->tlbsizevtlb;
592 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
593 fallthrough;
594 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
595 if (mips_ftlb_disabled)
596 break;
597 newcf4 = (config4 & ~ftlb_page) |
598 (page_size_ftlb(mmuextdef) <<
599 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
600 write_c0_config4(newcf4);
601 back_to_back_c0_hazard();
602 config4 = read_c0_config4();
603 if (config4 != newcf4) {
604 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
605 PAGE_SIZE, config4);
606 /* Switch FTLB off */
607 set_ftlb_enable(c, 0);
608 mips_ftlb_disabled = 1;
609 break;
610 }
611 c->tlbsizeftlbsets = 1 <<
612 ((config4 & MIPS_CONF4_FTLBSETS) >>
613 MIPS_CONF4_FTLBSETS_SHIFT);
614 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
615 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
616 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
617 mips_has_ftlb_configured = 1;
618 break;
619 }
620 }
621
622 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
623 >> MIPS_CONF4_KSCREXIST_SHIFT;
624
625 asid_mask = MIPS_ENTRYHI_ASID;
626 if (config4 & MIPS_CONF4_AE)
627 asid_mask |= MIPS_ENTRYHI_ASIDX;
628 set_cpu_asid_mask(c, asid_mask);
629
630 /*
631 * Warn if the computed ASID mask doesn't match the mask the kernel
632 * is built for. This may indicate either a serious problem or an
633 * easy optimisation opportunity, but either way should be addressed.
634 */
635 WARN_ON(asid_mask != cpu_asid_mask(c));
636
637 return config4 & MIPS_CONF_M;
638}
639
640static inline unsigned int decode_config5(struct cpuinfo_mips *c)
641{
642 unsigned int config5, max_mmid_width;
643 unsigned long asid_mask;
644
645 config5 = read_c0_config5();
646 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
647
648 if (cpu_has_mips_r6) {
649 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
650 config5 |= MIPS_CONF5_MI;
651 else
652 config5 &= ~MIPS_CONF5_MI;
653 }
654
655 write_c0_config5(config5);
656
657 if (config5 & MIPS_CONF5_EVA)
658 c->options |= MIPS_CPU_EVA;
659 if (config5 & MIPS_CONF5_MRP)
660 c->options |= MIPS_CPU_MAAR;
661 if (config5 & MIPS_CONF5_LLB)
662 c->options |= MIPS_CPU_RW_LLB;
663 if (config5 & MIPS_CONF5_MVH)
664 c->options |= MIPS_CPU_MVH;
665 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
666 c->options |= MIPS_CPU_VP;
667 if (config5 & MIPS_CONF5_CA2)
668 c->ases |= MIPS_ASE_MIPS16E2;
669
670 if (config5 & MIPS_CONF5_CRCP)
671 elf_hwcap |= HWCAP_MIPS_CRC32;
672
673 if (cpu_has_mips_r6) {
674 /* Ensure the write to config5 above takes effect */
675 back_to_back_c0_hazard();
676
677 /* Check whether we successfully enabled MMID support */
678 config5 = read_c0_config5();
679 if (config5 & MIPS_CONF5_MI)
680 c->options |= MIPS_CPU_MMID;
681
682 /*
683 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
684 * for the CPU we're running on, or if CPUs in an SMP system
685 * have inconsistent MMID support.
686 */
687 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
688
689 if (cpu_has_mmid) {
690 write_c0_memorymapid(~0ul);
691 back_to_back_c0_hazard();
692 asid_mask = read_c0_memorymapid();
693
694 /*
695 * We maintain a bitmap to track MMID allocation, and
696 * need a sensible upper bound on the size of that
697 * bitmap. The initial CPU with MMID support (I6500)
698 * supports 16 bit MMIDs, which gives us an 8KiB
699 * bitmap. The architecture recommends that hardware
700 * support 32 bit MMIDs, which would give us a 512MiB
701 * bitmap - that's too big in most cases.
702 *
703 * Cap MMID width at 16 bits for now & we can revisit
704 * this if & when hardware supports anything wider.
705 */
706 max_mmid_width = 16;
707 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
708 pr_info("Capping MMID width at %d bits",
709 max_mmid_width);
710 asid_mask = GENMASK(max_mmid_width - 1, 0);
711 }
712
713 set_cpu_asid_mask(c, asid_mask);
714 }
715 }
716
717 return config5 & MIPS_CONF_M;
718}
719
720static void decode_configs(struct cpuinfo_mips *c)
721{
722 int ok;
723
724 /* MIPS32 or MIPS64 compliant CPU. */
725 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
726 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
727
728 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
729
730 /* Enable FTLB if present and not disabled */
731 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
732
733 ok = decode_config0(c); /* Read Config registers. */
734 BUG_ON(!ok); /* Arch spec violation! */
735 if (ok)
736 ok = decode_config1(c);
737 if (ok)
738 ok = decode_config2(c);
739 if (ok)
740 ok = decode_config3(c);
741 if (ok)
742 ok = decode_config4(c);
743 if (ok)
744 ok = decode_config5(c);
745
746 /* Probe the EBase.WG bit */
747 if (cpu_has_mips_r2_r6) {
748 u64 ebase;
749 unsigned int status;
750
751 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
752 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
753 : (s32)read_c0_ebase();
754 if (ebase & MIPS_EBASE_WG) {
755 /* WG bit already set, we can avoid the clumsy probe */
756 c->options |= MIPS_CPU_EBASE_WG;
757 } else {
758 /* Its UNDEFINED to change EBase while BEV=0 */
759 status = read_c0_status();
760 write_c0_status(status | ST0_BEV);
761 irq_enable_hazard();
762 /*
763 * On pre-r6 cores, this may well clobber the upper bits
764 * of EBase. This is hard to avoid without potentially
765 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
766 */
767 if (cpu_has_mips64r6)
768 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
769 else
770 write_c0_ebase(ebase | MIPS_EBASE_WG);
771 back_to_back_c0_hazard();
772 /* Restore BEV */
773 write_c0_status(status);
774 if (read_c0_ebase() & MIPS_EBASE_WG) {
775 c->options |= MIPS_CPU_EBASE_WG;
776 write_c0_ebase(ebase);
777 }
778 }
779 }
780
781 /* configure the FTLB write probability */
782 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
783
784 mips_probe_watch_registers(c);
785
786#ifndef CONFIG_MIPS_CPS
787 if (cpu_has_mips_r2_r6) {
788 unsigned int core;
789
790 core = get_ebase_cpunum();
791 if (cpu_has_mipsmt)
792 core >>= fls(core_nvpes()) - 1;
793 cpu_set_core(c, core);
794 }
795#endif
796}
797
798/*
799 * Probe for certain guest capabilities by writing config bits and reading back.
800 * Finally write back the original value.
801 */
802#define probe_gc0_config(name, maxconf, bits) \
803do { \
804 unsigned int tmp; \
805 tmp = read_gc0_##name(); \
806 write_gc0_##name(tmp | (bits)); \
807 back_to_back_c0_hazard(); \
808 maxconf = read_gc0_##name(); \
809 write_gc0_##name(tmp); \
810} while (0)
811
812/*
813 * Probe for dynamic guest capabilities by changing certain config bits and
814 * reading back to see if they change. Finally write back the original value.
815 */
816#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
817do { \
818 maxconf = read_gc0_##name(); \
819 write_gc0_##name(maxconf ^ (bits)); \
820 back_to_back_c0_hazard(); \
821 dynconf = maxconf ^ read_gc0_##name(); \
822 write_gc0_##name(maxconf); \
823 maxconf |= dynconf; \
824} while (0)
825
826static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
827{
828 unsigned int config0;
829
830 probe_gc0_config(config, config0, MIPS_CONF_M);
831
832 if (config0 & MIPS_CONF_M)
833 c->guest.conf |= BIT(1);
834 return config0 & MIPS_CONF_M;
835}
836
837static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
838{
839 unsigned int config1, config1_dyn;
840
841 probe_gc0_config_dyn(config1, config1, config1_dyn,
842 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
843 MIPS_CONF1_FP);
844
845 if (config1 & MIPS_CONF1_FP)
846 c->guest.options |= MIPS_CPU_FPU;
847 if (config1_dyn & MIPS_CONF1_FP)
848 c->guest.options_dyn |= MIPS_CPU_FPU;
849
850 if (config1 & MIPS_CONF1_WR)
851 c->guest.options |= MIPS_CPU_WATCH;
852 if (config1_dyn & MIPS_CONF1_WR)
853 c->guest.options_dyn |= MIPS_CPU_WATCH;
854
855 if (config1 & MIPS_CONF1_PC)
856 c->guest.options |= MIPS_CPU_PERF;
857 if (config1_dyn & MIPS_CONF1_PC)
858 c->guest.options_dyn |= MIPS_CPU_PERF;
859
860 if (config1 & MIPS_CONF_M)
861 c->guest.conf |= BIT(2);
862 return config1 & MIPS_CONF_M;
863}
864
865static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
866{
867 unsigned int config2;
868
869 probe_gc0_config(config2, config2, MIPS_CONF_M);
870
871 if (config2 & MIPS_CONF_M)
872 c->guest.conf |= BIT(3);
873 return config2 & MIPS_CONF_M;
874}
875
876static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
877{
878 unsigned int config3, config3_dyn;
879
880 probe_gc0_config_dyn(config3, config3, config3_dyn,
881 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
882 MIPS_CONF3_CTXTC);
883
884 if (config3 & MIPS_CONF3_CTXTC)
885 c->guest.options |= MIPS_CPU_CTXTC;
886 if (config3_dyn & MIPS_CONF3_CTXTC)
887 c->guest.options_dyn |= MIPS_CPU_CTXTC;
888
889 if (config3 & MIPS_CONF3_PW)
890 c->guest.options |= MIPS_CPU_HTW;
891
892 if (config3 & MIPS_CONF3_ULRI)
893 c->guest.options |= MIPS_CPU_ULRI;
894
895 if (config3 & MIPS_CONF3_SC)
896 c->guest.options |= MIPS_CPU_SEGMENTS;
897
898 if (config3 & MIPS_CONF3_BI)
899 c->guest.options |= MIPS_CPU_BADINSTR;
900 if (config3 & MIPS_CONF3_BP)
901 c->guest.options |= MIPS_CPU_BADINSTRP;
902
903 if (config3 & MIPS_CONF3_MSA)
904 c->guest.ases |= MIPS_ASE_MSA;
905 if (config3_dyn & MIPS_CONF3_MSA)
906 c->guest.ases_dyn |= MIPS_ASE_MSA;
907
908 if (config3 & MIPS_CONF_M)
909 c->guest.conf |= BIT(4);
910 return config3 & MIPS_CONF_M;
911}
912
913static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
914{
915 unsigned int config4;
916
917 probe_gc0_config(config4, config4,
918 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
919
920 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
921 >> MIPS_CONF4_KSCREXIST_SHIFT;
922
923 if (config4 & MIPS_CONF_M)
924 c->guest.conf |= BIT(5);
925 return config4 & MIPS_CONF_M;
926}
927
928static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
929{
930 unsigned int config5, config5_dyn;
931
932 probe_gc0_config_dyn(config5, config5, config5_dyn,
933 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
934
935 if (config5 & MIPS_CONF5_MRP)
936 c->guest.options |= MIPS_CPU_MAAR;
937 if (config5_dyn & MIPS_CONF5_MRP)
938 c->guest.options_dyn |= MIPS_CPU_MAAR;
939
940 if (config5 & MIPS_CONF5_LLB)
941 c->guest.options |= MIPS_CPU_RW_LLB;
942
943 if (config5 & MIPS_CONF5_MVH)
944 c->guest.options |= MIPS_CPU_MVH;
945
946 if (config5 & MIPS_CONF_M)
947 c->guest.conf |= BIT(6);
948 return config5 & MIPS_CONF_M;
949}
950
951static inline void decode_guest_configs(struct cpuinfo_mips *c)
952{
953 unsigned int ok;
954
955 ok = decode_guest_config0(c);
956 if (ok)
957 ok = decode_guest_config1(c);
958 if (ok)
959 ok = decode_guest_config2(c);
960 if (ok)
961 ok = decode_guest_config3(c);
962 if (ok)
963 ok = decode_guest_config4(c);
964 if (ok)
965 decode_guest_config5(c);
966}
967
968static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
969{
970 unsigned int guestctl0, temp;
971
972 guestctl0 = read_c0_guestctl0();
973
974 if (guestctl0 & MIPS_GCTL0_G0E)
975 c->options |= MIPS_CPU_GUESTCTL0EXT;
976 if (guestctl0 & MIPS_GCTL0_G1)
977 c->options |= MIPS_CPU_GUESTCTL1;
978 if (guestctl0 & MIPS_GCTL0_G2)
979 c->options |= MIPS_CPU_GUESTCTL2;
980 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
981 c->options |= MIPS_CPU_GUESTID;
982
983 /*
984 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
985 * first, otherwise all data accesses will be fully virtualised
986 * as if they were performed by guest mode.
987 */
988 write_c0_guestctl1(0);
989 tlbw_use_hazard();
990
991 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
992 back_to_back_c0_hazard();
993 temp = read_c0_guestctl0();
994
995 if (temp & MIPS_GCTL0_DRG) {
996 write_c0_guestctl0(guestctl0);
997 c->options |= MIPS_CPU_DRG;
998 }
999 }
1000}
1001
1002static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1003{
1004 if (cpu_has_guestid) {
1005 /* determine the number of bits of GuestID available */
1006 write_c0_guestctl1(MIPS_GCTL1_ID);
1007 back_to_back_c0_hazard();
1008 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1009 >> MIPS_GCTL1_ID_SHIFT;
1010 write_c0_guestctl1(0);
1011 }
1012}
1013
1014static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1015{
1016 /* determine the number of bits of GTOffset available */
1017 write_c0_gtoffset(0xffffffff);
1018 back_to_back_c0_hazard();
1019 c->gtoffset_mask = read_c0_gtoffset();
1020 write_c0_gtoffset(0);
1021}
1022
1023static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1024{
1025 cpu_probe_guestctl0(c);
1026 if (cpu_has_guestctl1)
1027 cpu_probe_guestctl1(c);
1028
1029 cpu_probe_gtoffset(c);
1030
1031 decode_guest_configs(c);
1032}
1033
1034#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1035 | MIPS_CPU_COUNTER)
1036
1037static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1038{
1039 switch (c->processor_id & PRID_IMP_MASK) {
1040 case PRID_IMP_R2000:
1041 c->cputype = CPU_R2000;
1042 __cpu_name[cpu] = "R2000";
1043 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1044 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1045 MIPS_CPU_NOFPUEX;
1046 if (__cpu_has_fpu())
1047 c->options |= MIPS_CPU_FPU;
1048 c->tlbsize = 64;
1049 break;
1050 case PRID_IMP_R3000:
1051 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1052 if (cpu_has_confreg()) {
1053 c->cputype = CPU_R3081E;
1054 __cpu_name[cpu] = "R3081";
1055 } else {
1056 c->cputype = CPU_R3000A;
1057 __cpu_name[cpu] = "R3000A";
1058 }
1059 } else {
1060 c->cputype = CPU_R3000;
1061 __cpu_name[cpu] = "R3000";
1062 }
1063 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1064 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1065 MIPS_CPU_NOFPUEX;
1066 if (__cpu_has_fpu())
1067 c->options |= MIPS_CPU_FPU;
1068 c->tlbsize = 64;
1069 break;
1070 case PRID_IMP_R4000:
1071 if (read_c0_config() & CONF_SC) {
1072 if ((c->processor_id & PRID_REV_MASK) >=
1073 PRID_REV_R4400) {
1074 c->cputype = CPU_R4400PC;
1075 __cpu_name[cpu] = "R4400PC";
1076 } else {
1077 c->cputype = CPU_R4000PC;
1078 __cpu_name[cpu] = "R4000PC";
1079 }
1080 } else {
1081 int cca = read_c0_config() & CONF_CM_CMASK;
1082 int mc;
1083
1084 /*
1085 * SC and MC versions can't be reliably told apart,
1086 * but only the latter support coherent caching
1087 * modes so assume the firmware has set the KSEG0
1088 * coherency attribute reasonably (if uncached, we
1089 * assume SC).
1090 */
1091 switch (cca) {
1092 case CONF_CM_CACHABLE_CE:
1093 case CONF_CM_CACHABLE_COW:
1094 case CONF_CM_CACHABLE_CUW:
1095 mc = 1;
1096 break;
1097 default:
1098 mc = 0;
1099 break;
1100 }
1101 if ((c->processor_id & PRID_REV_MASK) >=
1102 PRID_REV_R4400) {
1103 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1104 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1105 } else {
1106 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1107 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1108 }
1109 }
1110
1111 set_isa(c, MIPS_CPU_ISA_III);
1112 c->fpu_msk31 |= FPU_CSR_CONDX;
1113 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1114 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1115 MIPS_CPU_LLSC;
1116 c->tlbsize = 48;
1117 break;
1118 case PRID_IMP_R4300:
1119 c->cputype = CPU_R4300;
1120 __cpu_name[cpu] = "R4300";
1121 set_isa(c, MIPS_CPU_ISA_III);
1122 c->fpu_msk31 |= FPU_CSR_CONDX;
1123 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1124 MIPS_CPU_LLSC;
1125 c->tlbsize = 32;
1126 break;
1127 case PRID_IMP_R4600:
1128 c->cputype = CPU_R4600;
1129 __cpu_name[cpu] = "R4600";
1130 set_isa(c, MIPS_CPU_ISA_III);
1131 c->fpu_msk31 |= FPU_CSR_CONDX;
1132 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1133 MIPS_CPU_LLSC;
1134 c->tlbsize = 48;
1135 break;
1136 #if 0
1137 case PRID_IMP_R4650:
1138 /*
1139 * This processor doesn't have an MMU, so it's not
1140 * "real easy" to run Linux on it. It is left purely
1141 * for documentation. Commented out because it shares
1142 * it's c0_prid id number with the TX3900.
1143 */
1144 c->cputype = CPU_R4650;
1145 __cpu_name[cpu] = "R4650";
1146 set_isa(c, MIPS_CPU_ISA_III);
1147 c->fpu_msk31 |= FPU_CSR_CONDX;
1148 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1149 c->tlbsize = 48;
1150 break;
1151 #endif
1152 case PRID_IMP_R4700:
1153 c->cputype = CPU_R4700;
1154 __cpu_name[cpu] = "R4700";
1155 set_isa(c, MIPS_CPU_ISA_III);
1156 c->fpu_msk31 |= FPU_CSR_CONDX;
1157 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1158 MIPS_CPU_LLSC;
1159 c->tlbsize = 48;
1160 break;
1161 case PRID_IMP_TX49:
1162 c->cputype = CPU_TX49XX;
1163 __cpu_name[cpu] = "R49XX";
1164 set_isa(c, MIPS_CPU_ISA_III);
1165 c->fpu_msk31 |= FPU_CSR_CONDX;
1166 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1167 if (!(c->processor_id & 0x08))
1168 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1169 c->tlbsize = 48;
1170 break;
1171 case PRID_IMP_R5000:
1172 c->cputype = CPU_R5000;
1173 __cpu_name[cpu] = "R5000";
1174 set_isa(c, MIPS_CPU_ISA_IV);
1175 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1176 MIPS_CPU_LLSC;
1177 c->tlbsize = 48;
1178 break;
1179 case PRID_IMP_R5500:
1180 c->cputype = CPU_R5500;
1181 __cpu_name[cpu] = "R5500";
1182 set_isa(c, MIPS_CPU_ISA_IV);
1183 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1184 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1185 c->tlbsize = 48;
1186 break;
1187 case PRID_IMP_NEVADA:
1188 c->cputype = CPU_NEVADA;
1189 __cpu_name[cpu] = "Nevada";
1190 set_isa(c, MIPS_CPU_ISA_IV);
1191 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1192 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1193 c->tlbsize = 48;
1194 break;
1195 case PRID_IMP_RM7000:
1196 c->cputype = CPU_RM7000;
1197 __cpu_name[cpu] = "RM7000";
1198 set_isa(c, MIPS_CPU_ISA_IV);
1199 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1200 MIPS_CPU_LLSC;
1201 /*
1202 * Undocumented RM7000: Bit 29 in the info register of
1203 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1204 * entries.
1205 *
1206 * 29 1 => 64 entry JTLB
1207 * 0 => 48 entry JTLB
1208 */
1209 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1210 break;
1211 case PRID_IMP_R10000:
1212 c->cputype = CPU_R10000;
1213 __cpu_name[cpu] = "R10000";
1214 set_isa(c, MIPS_CPU_ISA_IV);
1215 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1216 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1217 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1218 MIPS_CPU_LLSC;
1219 c->tlbsize = 64;
1220 break;
1221 case PRID_IMP_R12000:
1222 c->cputype = CPU_R12000;
1223 __cpu_name[cpu] = "R12000";
1224 set_isa(c, MIPS_CPU_ISA_IV);
1225 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1226 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1227 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1228 MIPS_CPU_LLSC;
1229 c->tlbsize = 64;
1230 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1231 break;
1232 case PRID_IMP_R14000:
1233 if (((c->processor_id >> 4) & 0x0f) > 2) {
1234 c->cputype = CPU_R16000;
1235 __cpu_name[cpu] = "R16000";
1236 } else {
1237 c->cputype = CPU_R14000;
1238 __cpu_name[cpu] = "R14000";
1239 }
1240 set_isa(c, MIPS_CPU_ISA_IV);
1241 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1242 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1243 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1244 MIPS_CPU_LLSC;
1245 c->tlbsize = 64;
1246 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1247 break;
1248 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1249 switch (c->processor_id & PRID_REV_MASK) {
1250 case PRID_REV_LOONGSON2E:
1251 c->cputype = CPU_LOONGSON2EF;
1252 __cpu_name[cpu] = "ICT Loongson-2";
1253 set_elf_platform(cpu, "loongson2e");
1254 set_isa(c, MIPS_CPU_ISA_III);
1255 c->fpu_msk31 |= FPU_CSR_CONDX;
1256 break;
1257 case PRID_REV_LOONGSON2F:
1258 c->cputype = CPU_LOONGSON2EF;
1259 __cpu_name[cpu] = "ICT Loongson-2";
1260 set_elf_platform(cpu, "loongson2f");
1261 set_isa(c, MIPS_CPU_ISA_III);
1262 c->fpu_msk31 |= FPU_CSR_CONDX;
1263 break;
1264 case PRID_REV_LOONGSON3A_R1:
1265 c->cputype = CPU_LOONGSON64;
1266 __cpu_name[cpu] = "ICT Loongson-3";
1267 set_elf_platform(cpu, "loongson3a");
1268 set_isa(c, MIPS_CPU_ISA_M64R1);
1269 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1270 MIPS_ASE_LOONGSON_EXT);
1271 break;
1272 case PRID_REV_LOONGSON3B_R1:
1273 case PRID_REV_LOONGSON3B_R2:
1274 c->cputype = CPU_LOONGSON64;
1275 __cpu_name[cpu] = "ICT Loongson-3";
1276 set_elf_platform(cpu, "loongson3b");
1277 set_isa(c, MIPS_CPU_ISA_M64R1);
1278 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1279 MIPS_ASE_LOONGSON_EXT);
1280 break;
1281 }
1282
1283 c->options = R4K_OPTS |
1284 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1285 MIPS_CPU_32FPR;
1286 c->tlbsize = 64;
1287 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1288 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1289 break;
1290 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1291 decode_configs(c);
1292
1293 c->cputype = CPU_LOONGSON32;
1294
1295 switch (c->processor_id & PRID_REV_MASK) {
1296 case PRID_REV_LOONGSON1B:
1297 __cpu_name[cpu] = "Loongson 1B";
1298 break;
1299 }
1300
1301 break;
1302 }
1303}
1304
1305static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1306{
1307 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1308 switch (c->processor_id & PRID_IMP_MASK) {
1309 case PRID_IMP_QEMU_GENERIC:
1310 c->writecombine = _CACHE_UNCACHED;
1311 c->cputype = CPU_QEMU_GENERIC;
1312 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1313 break;
1314 case PRID_IMP_4KC:
1315 c->cputype = CPU_4KC;
1316 c->writecombine = _CACHE_UNCACHED;
1317 __cpu_name[cpu] = "MIPS 4Kc";
1318 break;
1319 case PRID_IMP_4KEC:
1320 case PRID_IMP_4KECR2:
1321 c->cputype = CPU_4KEC;
1322 c->writecombine = _CACHE_UNCACHED;
1323 __cpu_name[cpu] = "MIPS 4KEc";
1324 break;
1325 case PRID_IMP_4KSC:
1326 case PRID_IMP_4KSD:
1327 c->cputype = CPU_4KSC;
1328 c->writecombine = _CACHE_UNCACHED;
1329 __cpu_name[cpu] = "MIPS 4KSc";
1330 break;
1331 case PRID_IMP_5KC:
1332 c->cputype = CPU_5KC;
1333 c->writecombine = _CACHE_UNCACHED;
1334 __cpu_name[cpu] = "MIPS 5Kc";
1335 break;
1336 case PRID_IMP_5KE:
1337 c->cputype = CPU_5KE;
1338 c->writecombine = _CACHE_UNCACHED;
1339 __cpu_name[cpu] = "MIPS 5KE";
1340 break;
1341 case PRID_IMP_20KC:
1342 c->cputype = CPU_20KC;
1343 c->writecombine = _CACHE_UNCACHED;
1344 __cpu_name[cpu] = "MIPS 20Kc";
1345 break;
1346 case PRID_IMP_24K:
1347 c->cputype = CPU_24K;
1348 c->writecombine = _CACHE_UNCACHED;
1349 __cpu_name[cpu] = "MIPS 24Kc";
1350 break;
1351 case PRID_IMP_24KE:
1352 c->cputype = CPU_24K;
1353 c->writecombine = _CACHE_UNCACHED;
1354 __cpu_name[cpu] = "MIPS 24KEc";
1355 break;
1356 case PRID_IMP_25KF:
1357 c->cputype = CPU_25KF;
1358 c->writecombine = _CACHE_UNCACHED;
1359 __cpu_name[cpu] = "MIPS 25Kc";
1360 break;
1361 case PRID_IMP_34K:
1362 c->cputype = CPU_34K;
1363 c->writecombine = _CACHE_UNCACHED;
1364 __cpu_name[cpu] = "MIPS 34Kc";
1365 cpu_set_mt_per_tc_perf(c);
1366 break;
1367 case PRID_IMP_74K:
1368 c->cputype = CPU_74K;
1369 c->writecombine = _CACHE_UNCACHED;
1370 __cpu_name[cpu] = "MIPS 74Kc";
1371 break;
1372 case PRID_IMP_M14KC:
1373 c->cputype = CPU_M14KC;
1374 c->writecombine = _CACHE_UNCACHED;
1375 __cpu_name[cpu] = "MIPS M14Kc";
1376 break;
1377 case PRID_IMP_M14KEC:
1378 c->cputype = CPU_M14KEC;
1379 c->writecombine = _CACHE_UNCACHED;
1380 __cpu_name[cpu] = "MIPS M14KEc";
1381 break;
1382 case PRID_IMP_1004K:
1383 c->cputype = CPU_1004K;
1384 c->writecombine = _CACHE_UNCACHED;
1385 __cpu_name[cpu] = "MIPS 1004Kc";
1386 cpu_set_mt_per_tc_perf(c);
1387 break;
1388 case PRID_IMP_1074K:
1389 c->cputype = CPU_1074K;
1390 c->writecombine = _CACHE_UNCACHED;
1391 __cpu_name[cpu] = "MIPS 1074Kc";
1392 break;
1393 case PRID_IMP_INTERAPTIV_UP:
1394 c->cputype = CPU_INTERAPTIV;
1395 __cpu_name[cpu] = "MIPS interAptiv";
1396 cpu_set_mt_per_tc_perf(c);
1397 break;
1398 case PRID_IMP_INTERAPTIV_MP:
1399 c->cputype = CPU_INTERAPTIV;
1400 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1401 cpu_set_mt_per_tc_perf(c);
1402 break;
1403 case PRID_IMP_PROAPTIV_UP:
1404 c->cputype = CPU_PROAPTIV;
1405 __cpu_name[cpu] = "MIPS proAptiv";
1406 break;
1407 case PRID_IMP_PROAPTIV_MP:
1408 c->cputype = CPU_PROAPTIV;
1409 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1410 break;
1411 case PRID_IMP_P5600:
1412 c->cputype = CPU_P5600;
1413 __cpu_name[cpu] = "MIPS P5600";
1414 break;
1415 case PRID_IMP_P6600:
1416 c->cputype = CPU_P6600;
1417 __cpu_name[cpu] = "MIPS P6600";
1418 break;
1419 case PRID_IMP_I6400:
1420 c->cputype = CPU_I6400;
1421 __cpu_name[cpu] = "MIPS I6400";
1422 break;
1423 case PRID_IMP_I6500:
1424 c->cputype = CPU_I6500;
1425 __cpu_name[cpu] = "MIPS I6500";
1426 break;
1427 case PRID_IMP_M5150:
1428 c->cputype = CPU_M5150;
1429 __cpu_name[cpu] = "MIPS M5150";
1430 break;
1431 case PRID_IMP_M6250:
1432 c->cputype = CPU_M6250;
1433 __cpu_name[cpu] = "MIPS M6250";
1434 break;
1435 }
1436
1437 decode_configs(c);
1438
1439 spram_config();
1440
1441 mm_config(c);
1442
1443 switch (__get_cpu_type(c->cputype)) {
1444 case CPU_M5150:
1445 case CPU_P5600:
1446 set_isa(c, MIPS_CPU_ISA_M32R5);
1447 break;
1448 case CPU_I6500:
1449 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1450 fallthrough;
1451 case CPU_I6400:
1452 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1453 fallthrough;
1454 default:
1455 break;
1456 }
1457
1458 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
1459 * cache/FTLB parity exceptions.
1460 */
1461 switch (__get_cpu_type(c->cputype)) {
1462 case CPU_PROAPTIV:
1463 case CPU_P5600:
1464 case CPU_P6600:
1465 case CPU_I6400:
1466 case CPU_I6500:
1467 c->options |= MIPS_CPU_FTLBPAREX;
1468 break;
1469 }
1470}
1471
1472static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1473{
1474 decode_configs(c);
1475 switch (c->processor_id & PRID_IMP_MASK) {
1476 case PRID_IMP_AU1_REV1:
1477 case PRID_IMP_AU1_REV2:
1478 c->cputype = CPU_ALCHEMY;
1479 switch ((c->processor_id >> 24) & 0xff) {
1480 case 0:
1481 __cpu_name[cpu] = "Au1000";
1482 break;
1483 case 1:
1484 __cpu_name[cpu] = "Au1500";
1485 break;
1486 case 2:
1487 __cpu_name[cpu] = "Au1100";
1488 break;
1489 case 3:
1490 __cpu_name[cpu] = "Au1550";
1491 break;
1492 case 4:
1493 __cpu_name[cpu] = "Au1200";
1494 if ((c->processor_id & PRID_REV_MASK) == 2)
1495 __cpu_name[cpu] = "Au1250";
1496 break;
1497 case 5:
1498 __cpu_name[cpu] = "Au1210";
1499 break;
1500 default:
1501 __cpu_name[cpu] = "Au1xxx";
1502 break;
1503 }
1504 break;
1505 }
1506}
1507
1508static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1509{
1510 decode_configs(c);
1511
1512 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1513 switch (c->processor_id & PRID_IMP_MASK) {
1514 case PRID_IMP_SB1:
1515 c->cputype = CPU_SB1;
1516 __cpu_name[cpu] = "SiByte SB1";
1517 /* FPU in pass1 is known to have issues. */
1518 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1519 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1520 break;
1521 case PRID_IMP_SB1A:
1522 c->cputype = CPU_SB1A;
1523 __cpu_name[cpu] = "SiByte SB1A";
1524 break;
1525 }
1526}
1527
1528static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1529{
1530 decode_configs(c);
1531 switch (c->processor_id & PRID_IMP_MASK) {
1532 case PRID_IMP_SR71000:
1533 c->cputype = CPU_SR71000;
1534 __cpu_name[cpu] = "Sandcraft SR71000";
1535 c->scache.ways = 8;
1536 c->tlbsize = 64;
1537 break;
1538 }
1539}
1540
1541static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1542{
1543 decode_configs(c);
1544 switch (c->processor_id & PRID_IMP_MASK) {
1545 case PRID_IMP_PR4450:
1546 c->cputype = CPU_PR4450;
1547 __cpu_name[cpu] = "Philips PR4450";
1548 set_isa(c, MIPS_CPU_ISA_M32R1);
1549 break;
1550 }
1551}
1552
1553static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1554{
1555 decode_configs(c);
1556 switch (c->processor_id & PRID_IMP_MASK) {
1557 case PRID_IMP_BMIPS32_REV4:
1558 case PRID_IMP_BMIPS32_REV8:
1559 c->cputype = CPU_BMIPS32;
1560 __cpu_name[cpu] = "Broadcom BMIPS32";
1561 set_elf_platform(cpu, "bmips32");
1562 break;
1563 case PRID_IMP_BMIPS3300:
1564 case PRID_IMP_BMIPS3300_ALT:
1565 case PRID_IMP_BMIPS3300_BUG:
1566 c->cputype = CPU_BMIPS3300;
1567 __cpu_name[cpu] = "Broadcom BMIPS3300";
1568 set_elf_platform(cpu, "bmips3300");
1569 reserve_exception_space(0x400, VECTORSPACING * 64);
1570 break;
1571 case PRID_IMP_BMIPS43XX: {
1572 int rev = c->processor_id & PRID_REV_MASK;
1573
1574 if (rev >= PRID_REV_BMIPS4380_LO &&
1575 rev <= PRID_REV_BMIPS4380_HI) {
1576 c->cputype = CPU_BMIPS4380;
1577 __cpu_name[cpu] = "Broadcom BMIPS4380";
1578 set_elf_platform(cpu, "bmips4380");
1579 c->options |= MIPS_CPU_RIXI;
1580 reserve_exception_space(0x400, VECTORSPACING * 64);
1581 } else {
1582 c->cputype = CPU_BMIPS4350;
1583 __cpu_name[cpu] = "Broadcom BMIPS4350";
1584 set_elf_platform(cpu, "bmips4350");
1585 }
1586 break;
1587 }
1588 case PRID_IMP_BMIPS5000:
1589 case PRID_IMP_BMIPS5200:
1590 c->cputype = CPU_BMIPS5000;
1591 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1592 __cpu_name[cpu] = "Broadcom BMIPS5200";
1593 else
1594 __cpu_name[cpu] = "Broadcom BMIPS5000";
1595 set_elf_platform(cpu, "bmips5000");
1596 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1597 reserve_exception_space(0x1000, VECTORSPACING * 64);
1598 break;
1599 }
1600}
1601
1602static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1603{
1604 decode_configs(c);
1605 switch (c->processor_id & PRID_IMP_MASK) {
1606 case PRID_IMP_CAVIUM_CN38XX:
1607 case PRID_IMP_CAVIUM_CN31XX:
1608 case PRID_IMP_CAVIUM_CN30XX:
1609 c->cputype = CPU_CAVIUM_OCTEON;
1610 __cpu_name[cpu] = "Cavium Octeon";
1611 goto platform;
1612 case PRID_IMP_CAVIUM_CN58XX:
1613 case PRID_IMP_CAVIUM_CN56XX:
1614 case PRID_IMP_CAVIUM_CN50XX:
1615 case PRID_IMP_CAVIUM_CN52XX:
1616 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1617 __cpu_name[cpu] = "Cavium Octeon+";
1618platform:
1619 set_elf_platform(cpu, "octeon");
1620 break;
1621 case PRID_IMP_CAVIUM_CN61XX:
1622 case PRID_IMP_CAVIUM_CN63XX:
1623 case PRID_IMP_CAVIUM_CN66XX:
1624 case PRID_IMP_CAVIUM_CN68XX:
1625 case PRID_IMP_CAVIUM_CNF71XX:
1626 c->cputype = CPU_CAVIUM_OCTEON2;
1627 __cpu_name[cpu] = "Cavium Octeon II";
1628 set_elf_platform(cpu, "octeon2");
1629 break;
1630 case PRID_IMP_CAVIUM_CN70XX:
1631 case PRID_IMP_CAVIUM_CN73XX:
1632 case PRID_IMP_CAVIUM_CNF75XX:
1633 case PRID_IMP_CAVIUM_CN78XX:
1634 c->cputype = CPU_CAVIUM_OCTEON3;
1635 __cpu_name[cpu] = "Cavium Octeon III";
1636 set_elf_platform(cpu, "octeon3");
1637 break;
1638 default:
1639 printk(KERN_INFO "Unknown Octeon chip!\n");
1640 c->cputype = CPU_UNKNOWN;
1641 break;
1642 }
1643}
1644
1645#ifdef CONFIG_CPU_LOONGSON64
1646#include <loongson_regs.h>
1647
1648static inline void decode_cpucfg(struct cpuinfo_mips *c)
1649{
1650 u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
1651 u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
1652 u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
1653
1654 if (cfg1 & LOONGSON_CFG1_MMI)
1655 c->ases |= MIPS_ASE_LOONGSON_MMI;
1656
1657 if (cfg2 & LOONGSON_CFG2_LEXT1)
1658 c->ases |= MIPS_ASE_LOONGSON_EXT;
1659
1660 if (cfg2 & LOONGSON_CFG2_LEXT2)
1661 c->ases |= MIPS_ASE_LOONGSON_EXT2;
1662
1663 if (cfg2 & LOONGSON_CFG2_LSPW) {
1664 c->options |= MIPS_CPU_LDPTE;
1665 c->guest.options |= MIPS_CPU_LDPTE;
1666 }
1667
1668 if (cfg3 & LOONGSON_CFG3_LCAMP)
1669 c->ases |= MIPS_ASE_LOONGSON_CAM;
1670}
1671
1672static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1673{
1674 /* All Loongson processors covered here define ExcCode 16 as GSExc. */
1675 c->options |= MIPS_CPU_GSEXCEX;
1676
1677 switch (c->processor_id & PRID_IMP_MASK) {
1678 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
1679 switch (c->processor_id & PRID_REV_MASK) {
1680 case PRID_REV_LOONGSON2K_R1_0:
1681 case PRID_REV_LOONGSON2K_R1_1:
1682 case PRID_REV_LOONGSON2K_R1_2:
1683 case PRID_REV_LOONGSON2K_R1_3:
1684 c->cputype = CPU_LOONGSON64;
1685 __cpu_name[cpu] = "Loongson-2K";
1686 set_elf_platform(cpu, "gs264e");
1687 set_isa(c, MIPS_CPU_ISA_M64R2);
1688 break;
1689 }
1690 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
1691 MIPS_ASE_LOONGSON_EXT2);
1692 break;
1693 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */
1694 switch (c->processor_id & PRID_REV_MASK) {
1695 case PRID_REV_LOONGSON3A_R2_0:
1696 case PRID_REV_LOONGSON3A_R2_1:
1697 c->cputype = CPU_LOONGSON64;
1698 __cpu_name[cpu] = "ICT Loongson-3";
1699 set_elf_platform(cpu, "loongson3a");
1700 set_isa(c, MIPS_CPU_ISA_M64R2);
1701 break;
1702 case PRID_REV_LOONGSON3A_R3_0:
1703 case PRID_REV_LOONGSON3A_R3_1:
1704 c->cputype = CPU_LOONGSON64;
1705 __cpu_name[cpu] = "ICT Loongson-3";
1706 set_elf_platform(cpu, "loongson3a");
1707 set_isa(c, MIPS_CPU_ISA_M64R2);
1708 break;
1709 }
1710 /*
1711 * Loongson-3 Classic did not implement MIPS standard TLBINV
1712 * but implemented TLBINVF and EHINV. As currently we're only
1713 * using these two features, enable MIPS_CPU_TLBINV as well.
1714 *
1715 * Also some early Loongson-3A2000 had wrong TLB type in Config
1716 * register, we correct it here.
1717 */
1718 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1719 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1720 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1721 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
1722 break;
1723 case PRID_IMP_LOONGSON_64G:
1724 c->cputype = CPU_LOONGSON64;
1725 __cpu_name[cpu] = "ICT Loongson-3";
1726 set_elf_platform(cpu, "loongson3a");
1727 set_isa(c, MIPS_CPU_ISA_M64R2);
1728 decode_cpucfg(c);
1729 break;
1730 default:
1731 panic("Unknown Loongson Processor ID!");
1732 break;
1733 }
1734
1735 decode_configs(c);
1736}
1737#else
1738static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
1739#endif
1740
1741static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1742{
1743 decode_configs(c);
1744
1745 /*
1746 * XBurst misses a config2 register, so config3 decode was skipped in
1747 * decode_configs().
1748 */
1749 decode_config3(c);
1750
1751 /* XBurst does not implement the CP0 counter. */
1752 c->options &= ~MIPS_CPU_COUNTER;
1753 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
1754
1755 /* XBurst has virtually tagged icache */
1756 c->icache.flags |= MIPS_CACHE_VTAG;
1757
1758 switch (c->processor_id & PRID_IMP_MASK) {
1759
1760 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
1761 case PRID_IMP_XBURST_REV1:
1762
1763 /*
1764 * The XBurst core by default attempts to avoid branch target
1765 * buffer lookups by detecting & special casing loops. This
1766 * feature will cause BogoMIPS and lpj calculate in error.
1767 * Set cp0 config7 bit 4 to disable this feature.
1768 */
1769 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
1770
1771 switch (c->processor_id & PRID_COMP_MASK) {
1772
1773 /*
1774 * The config0 register in the XBurst CPUs with a processor ID of
1775 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
1776 * but they don't actually support this ISA.
1777 */
1778 case PRID_COMP_INGENIC_D0:
1779 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
1780
1781 /* FPU is not properly detected on JZ4760(B). */
1782 if (c->processor_id == 0x2ed0024f)
1783 c->options |= MIPS_CPU_FPU;
1784
1785 fallthrough;
1786
1787 /*
1788 * The config0 register in the XBurst CPUs with a processor ID of
1789 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
1790 * huge page tlb mode, this mode is not compatible with the MIPS
1791 * standard, it will cause tlbmiss and into an infinite loop
1792 * (line 21 in the tlb-funcs.S) when starting the init process.
1793 * After chip reset, the default is HPTLB mode, Write 0xa9000000
1794 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
1795 * getting stuck.
1796 */
1797 case PRID_COMP_INGENIC_D1:
1798 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
1799 break;
1800
1801 default:
1802 break;
1803 }
1804 fallthrough;
1805
1806 /* XBurst®1 with MXU2.0 SIMD ISA */
1807 case PRID_IMP_XBURST_REV2:
1808 /* Ingenic uses the WA bit to achieve write-combine memory writes */
1809 c->writecombine = _CACHE_CACHABLE_WA;
1810 c->cputype = CPU_XBURST;
1811 __cpu_name[cpu] = "Ingenic XBurst";
1812 break;
1813
1814 /* XBurst®2 with MXU2.1 SIMD ISA */
1815 case PRID_IMP_XBURST2:
1816 c->cputype = CPU_XBURST;
1817 __cpu_name[cpu] = "Ingenic XBurst II";
1818 break;
1819
1820 default:
1821 panic("Unknown Ingenic Processor ID!");
1822 break;
1823 }
1824}
1825
1826#ifdef CONFIG_64BIT
1827/* For use by uaccess.h */
1828u64 __ua_limit;
1829EXPORT_SYMBOL(__ua_limit);
1830#endif
1831
1832const char *__cpu_name[NR_CPUS];
1833const char *__elf_platform;
1834const char *__elf_base_platform;
1835
1836void cpu_probe(void)
1837{
1838 struct cpuinfo_mips *c = ¤t_cpu_data;
1839 unsigned int cpu = smp_processor_id();
1840
1841 /*
1842 * Set a default elf platform, cpu probe may later
1843 * overwrite it with a more precise value
1844 */
1845 set_elf_platform(cpu, "mips");
1846
1847 c->processor_id = PRID_IMP_UNKNOWN;
1848 c->fpu_id = FPIR_IMP_NONE;
1849 c->cputype = CPU_UNKNOWN;
1850 c->writecombine = _CACHE_UNCACHED;
1851
1852 c->fpu_csr31 = FPU_CSR_RN;
1853 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1854
1855 c->processor_id = read_c0_prid();
1856 switch (c->processor_id & PRID_COMP_MASK) {
1857 case PRID_COMP_LEGACY:
1858 cpu_probe_legacy(c, cpu);
1859 break;
1860 case PRID_COMP_MIPS:
1861 cpu_probe_mips(c, cpu);
1862 break;
1863 case PRID_COMP_ALCHEMY:
1864 cpu_probe_alchemy(c, cpu);
1865 break;
1866 case PRID_COMP_SIBYTE:
1867 cpu_probe_sibyte(c, cpu);
1868 break;
1869 case PRID_COMP_BROADCOM:
1870 cpu_probe_broadcom(c, cpu);
1871 break;
1872 case PRID_COMP_SANDCRAFT:
1873 cpu_probe_sandcraft(c, cpu);
1874 break;
1875 case PRID_COMP_NXP:
1876 cpu_probe_nxp(c, cpu);
1877 break;
1878 case PRID_COMP_CAVIUM:
1879 cpu_probe_cavium(c, cpu);
1880 break;
1881 case PRID_COMP_LOONGSON:
1882 cpu_probe_loongson(c, cpu);
1883 break;
1884 case PRID_COMP_INGENIC_13:
1885 case PRID_COMP_INGENIC_D0:
1886 case PRID_COMP_INGENIC_D1:
1887 case PRID_COMP_INGENIC_E1:
1888 cpu_probe_ingenic(c, cpu);
1889 break;
1890 }
1891
1892 BUG_ON(!__cpu_name[cpu]);
1893 BUG_ON(c->cputype == CPU_UNKNOWN);
1894
1895 /*
1896 * Platform code can force the cpu type to optimize code
1897 * generation. In that case be sure the cpu type is correctly
1898 * manually setup otherwise it could trigger some nasty bugs.
1899 */
1900 BUG_ON(current_cpu_type() != c->cputype);
1901
1902 if (cpu_has_rixi) {
1903 /* Enable the RIXI exceptions */
1904 set_c0_pagegrain(PG_IEC);
1905 back_to_back_c0_hazard();
1906 /* Verify the IEC bit is set */
1907 if (read_c0_pagegrain() & PG_IEC)
1908 c->options |= MIPS_CPU_RIXIEX;
1909 }
1910
1911 if (mips_fpu_disabled)
1912 c->options &= ~MIPS_CPU_FPU;
1913
1914 if (mips_dsp_disabled)
1915 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1916
1917 if (mips_htw_disabled) {
1918 c->options &= ~MIPS_CPU_HTW;
1919 write_c0_pwctl(read_c0_pwctl() &
1920 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1921 }
1922
1923 if (c->options & MIPS_CPU_FPU)
1924 cpu_set_fpu_opts(c);
1925 else
1926 cpu_set_nofpu_opts(c);
1927
1928 if (cpu_has_mips_r2_r6) {
1929 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1930 /* R2 has Performance Counter Interrupt indicator */
1931 c->options |= MIPS_CPU_PCI;
1932 }
1933 else
1934 c->srsets = 1;
1935
1936 if (cpu_has_mips_r6)
1937 elf_hwcap |= HWCAP_MIPS_R6;
1938
1939 if (cpu_has_msa) {
1940 c->msa_id = cpu_get_msa_id();
1941 WARN(c->msa_id & MSA_IR_WRPF,
1942 "Vector register partitioning unimplemented!");
1943 elf_hwcap |= HWCAP_MIPS_MSA;
1944 }
1945
1946 if (cpu_has_mips16)
1947 elf_hwcap |= HWCAP_MIPS_MIPS16;
1948
1949 if (cpu_has_mdmx)
1950 elf_hwcap |= HWCAP_MIPS_MDMX;
1951
1952 if (cpu_has_mips3d)
1953 elf_hwcap |= HWCAP_MIPS_MIPS3D;
1954
1955 if (cpu_has_smartmips)
1956 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
1957
1958 if (cpu_has_dsp)
1959 elf_hwcap |= HWCAP_MIPS_DSP;
1960
1961 if (cpu_has_dsp2)
1962 elf_hwcap |= HWCAP_MIPS_DSP2;
1963
1964 if (cpu_has_dsp3)
1965 elf_hwcap |= HWCAP_MIPS_DSP3;
1966
1967 if (cpu_has_mips16e2)
1968 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
1969
1970 if (cpu_has_loongson_mmi)
1971 elf_hwcap |= HWCAP_LOONGSON_MMI;
1972
1973 if (cpu_has_loongson_ext)
1974 elf_hwcap |= HWCAP_LOONGSON_EXT;
1975
1976 if (cpu_has_loongson_ext2)
1977 elf_hwcap |= HWCAP_LOONGSON_EXT2;
1978
1979 if (cpu_has_vz)
1980 cpu_probe_vz(c);
1981
1982 cpu_probe_vmbits(c);
1983
1984 /* Synthesize CPUCFG data if running on Loongson processors;
1985 * no-op otherwise.
1986 *
1987 * This looks at previously probed features, so keep this at bottom.
1988 */
1989 loongson3_cpucfg_synthesize_data(c);
1990
1991#ifdef CONFIG_64BIT
1992 if (cpu == 0)
1993 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1994#endif
1995
1996 reserve_exception_space(0, 0x1000);
1997}
1998
1999void cpu_report(void)
2000{
2001 struct cpuinfo_mips *c = ¤t_cpu_data;
2002
2003 pr_info("CPU%d revision is: %08x (%s)\n",
2004 smp_processor_id(), c->processor_id, cpu_name_string());
2005 if (c->options & MIPS_CPU_FPU)
2006 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2007 if (cpu_has_msa)
2008 pr_info("MSA revision is: %08x\n", c->msa_id);
2009}
2010
2011void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2012{
2013 /* Ensure the core number fits in the field */
2014 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2015 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2016
2017 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2018 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2019}
2020
2021void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2022{
2023 /* Ensure the core number fits in the field */
2024 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2025
2026 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2027 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2028}
2029
2030void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2031{
2032 /* Ensure the VP(E) ID fits in the field */
2033 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2034
2035 /* Ensure we're not using VP(E)s without support */
2036 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2037 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2038
2039 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2040 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2041}