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1/**************************************************************************
2 *
3 * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27#include <linux/module.h>
28#include <linux/console.h>
29
30#include <drm/drmP.h>
31#include "vmwgfx_drv.h"
32#include "vmwgfx_binding.h"
33#include <drm/ttm/ttm_placement.h>
34#include <drm/ttm/ttm_bo_driver.h>
35#include <drm/ttm/ttm_object.h>
36#include <drm/ttm/ttm_module.h>
37#include <linux/dma_remapping.h>
38
39#define VMWGFX_DRIVER_NAME "vmwgfx"
40#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
41#define VMWGFX_CHIP_SVGAII 0
42#define VMW_FB_RESERVATION 0
43
44#define VMW_MIN_INITIAL_WIDTH 800
45#define VMW_MIN_INITIAL_HEIGHT 600
46
47
48/**
49 * Fully encoded drm commands. Might move to vmw_drm.h
50 */
51
52#define DRM_IOCTL_VMW_GET_PARAM \
53 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
54 struct drm_vmw_getparam_arg)
55#define DRM_IOCTL_VMW_ALLOC_DMABUF \
56 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
57 union drm_vmw_alloc_dmabuf_arg)
58#define DRM_IOCTL_VMW_UNREF_DMABUF \
59 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
60 struct drm_vmw_unref_dmabuf_arg)
61#define DRM_IOCTL_VMW_CURSOR_BYPASS \
62 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
63 struct drm_vmw_cursor_bypass_arg)
64
65#define DRM_IOCTL_VMW_CONTROL_STREAM \
66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
67 struct drm_vmw_control_stream_arg)
68#define DRM_IOCTL_VMW_CLAIM_STREAM \
69 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
70 struct drm_vmw_stream_arg)
71#define DRM_IOCTL_VMW_UNREF_STREAM \
72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
73 struct drm_vmw_stream_arg)
74
75#define DRM_IOCTL_VMW_CREATE_CONTEXT \
76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
77 struct drm_vmw_context_arg)
78#define DRM_IOCTL_VMW_UNREF_CONTEXT \
79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
80 struct drm_vmw_context_arg)
81#define DRM_IOCTL_VMW_CREATE_SURFACE \
82 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
83 union drm_vmw_surface_create_arg)
84#define DRM_IOCTL_VMW_UNREF_SURFACE \
85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
86 struct drm_vmw_surface_arg)
87#define DRM_IOCTL_VMW_REF_SURFACE \
88 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
89 union drm_vmw_surface_reference_arg)
90#define DRM_IOCTL_VMW_EXECBUF \
91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
92 struct drm_vmw_execbuf_arg)
93#define DRM_IOCTL_VMW_GET_3D_CAP \
94 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
95 struct drm_vmw_get_3d_cap_arg)
96#define DRM_IOCTL_VMW_FENCE_WAIT \
97 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
98 struct drm_vmw_fence_wait_arg)
99#define DRM_IOCTL_VMW_FENCE_SIGNALED \
100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
101 struct drm_vmw_fence_signaled_arg)
102#define DRM_IOCTL_VMW_FENCE_UNREF \
103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
104 struct drm_vmw_fence_arg)
105#define DRM_IOCTL_VMW_FENCE_EVENT \
106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
107 struct drm_vmw_fence_event_arg)
108#define DRM_IOCTL_VMW_PRESENT \
109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
110 struct drm_vmw_present_arg)
111#define DRM_IOCTL_VMW_PRESENT_READBACK \
112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
113 struct drm_vmw_present_readback_arg)
114#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
116 struct drm_vmw_update_layout_arg)
117#define DRM_IOCTL_VMW_CREATE_SHADER \
118 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
119 struct drm_vmw_shader_create_arg)
120#define DRM_IOCTL_VMW_UNREF_SHADER \
121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
122 struct drm_vmw_shader_arg)
123#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
124 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
125 union drm_vmw_gb_surface_create_arg)
126#define DRM_IOCTL_VMW_GB_SURFACE_REF \
127 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
128 union drm_vmw_gb_surface_reference_arg)
129#define DRM_IOCTL_VMW_SYNCCPU \
130 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
131 struct drm_vmw_synccpu_arg)
132#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
134 struct drm_vmw_context_arg)
135
136/**
137 * The core DRM version of this macro doesn't account for
138 * DRM_COMMAND_BASE.
139 */
140
141#define VMW_IOCTL_DEF(ioctl, func, flags) \
142 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
143
144/**
145 * Ioctl definitions.
146 */
147
148static const struct drm_ioctl_desc vmw_ioctls[] = {
149 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
150 DRM_AUTH | DRM_RENDER_ALLOW),
151 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
152 DRM_AUTH | DRM_RENDER_ALLOW),
153 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
154 DRM_RENDER_ALLOW),
155 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
156 vmw_kms_cursor_bypass_ioctl,
157 DRM_MASTER | DRM_CONTROL_ALLOW),
158
159 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
160 DRM_MASTER | DRM_CONTROL_ALLOW),
161 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
162 DRM_MASTER | DRM_CONTROL_ALLOW),
163 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
164 DRM_MASTER | DRM_CONTROL_ALLOW),
165
166 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
167 DRM_AUTH | DRM_RENDER_ALLOW),
168 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
169 DRM_RENDER_ALLOW),
170 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
171 DRM_AUTH | DRM_RENDER_ALLOW),
172 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
173 DRM_RENDER_ALLOW),
174 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
175 DRM_AUTH | DRM_RENDER_ALLOW),
176 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
177 DRM_RENDER_ALLOW),
178 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
179 DRM_RENDER_ALLOW),
180 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
181 vmw_fence_obj_signaled_ioctl,
182 DRM_RENDER_ALLOW),
183 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
184 DRM_RENDER_ALLOW),
185 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
186 DRM_AUTH | DRM_RENDER_ALLOW),
187 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
188 DRM_AUTH | DRM_RENDER_ALLOW),
189
190 /* these allow direct access to the framebuffers mark as master only */
191 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
192 DRM_MASTER | DRM_AUTH),
193 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
194 vmw_present_readback_ioctl,
195 DRM_MASTER | DRM_AUTH),
196 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
197 vmw_kms_update_layout_ioctl,
198 DRM_MASTER | DRM_CONTROL_ALLOW),
199 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
200 vmw_shader_define_ioctl,
201 DRM_AUTH | DRM_RENDER_ALLOW),
202 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
203 vmw_shader_destroy_ioctl,
204 DRM_RENDER_ALLOW),
205 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
206 vmw_gb_surface_define_ioctl,
207 DRM_AUTH | DRM_RENDER_ALLOW),
208 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
209 vmw_gb_surface_reference_ioctl,
210 DRM_AUTH | DRM_RENDER_ALLOW),
211 VMW_IOCTL_DEF(VMW_SYNCCPU,
212 vmw_user_dmabuf_synccpu_ioctl,
213 DRM_RENDER_ALLOW),
214 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
215 vmw_extended_context_define_ioctl,
216 DRM_AUTH | DRM_RENDER_ALLOW),
217};
218
219static struct pci_device_id vmw_pci_id_list[] = {
220 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
221 {0, 0, 0}
222};
223MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
224
225static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
226static int vmw_force_iommu;
227static int vmw_restrict_iommu;
228static int vmw_force_coherent;
229static int vmw_restrict_dma_mask;
230
231static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
232static void vmw_master_init(struct vmw_master *);
233static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
234 void *ptr);
235
236MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
237module_param_named(enable_fbdev, enable_fbdev, int, 0600);
238MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
239module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
240MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
241module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
242MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
243module_param_named(force_coherent, vmw_force_coherent, int, 0600);
244MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
245module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
246
247
248static void vmw_print_capabilities(uint32_t capabilities)
249{
250 DRM_INFO("Capabilities:\n");
251 if (capabilities & SVGA_CAP_RECT_COPY)
252 DRM_INFO(" Rect copy.\n");
253 if (capabilities & SVGA_CAP_CURSOR)
254 DRM_INFO(" Cursor.\n");
255 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
256 DRM_INFO(" Cursor bypass.\n");
257 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
258 DRM_INFO(" Cursor bypass 2.\n");
259 if (capabilities & SVGA_CAP_8BIT_EMULATION)
260 DRM_INFO(" 8bit emulation.\n");
261 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
262 DRM_INFO(" Alpha cursor.\n");
263 if (capabilities & SVGA_CAP_3D)
264 DRM_INFO(" 3D.\n");
265 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
266 DRM_INFO(" Extended Fifo.\n");
267 if (capabilities & SVGA_CAP_MULTIMON)
268 DRM_INFO(" Multimon.\n");
269 if (capabilities & SVGA_CAP_PITCHLOCK)
270 DRM_INFO(" Pitchlock.\n");
271 if (capabilities & SVGA_CAP_IRQMASK)
272 DRM_INFO(" Irq mask.\n");
273 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
274 DRM_INFO(" Display Topology.\n");
275 if (capabilities & SVGA_CAP_GMR)
276 DRM_INFO(" GMR.\n");
277 if (capabilities & SVGA_CAP_TRACES)
278 DRM_INFO(" Traces.\n");
279 if (capabilities & SVGA_CAP_GMR2)
280 DRM_INFO(" GMR2.\n");
281 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
282 DRM_INFO(" Screen Object 2.\n");
283 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
284 DRM_INFO(" Command Buffers.\n");
285 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
286 DRM_INFO(" Command Buffers 2.\n");
287 if (capabilities & SVGA_CAP_GBOBJECTS)
288 DRM_INFO(" Guest Backed Resources.\n");
289 if (capabilities & SVGA_CAP_DX)
290 DRM_INFO(" DX Features.\n");
291}
292
293/**
294 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
295 *
296 * @dev_priv: A device private structure.
297 *
298 * This function creates a small buffer object that holds the query
299 * result for dummy queries emitted as query barriers.
300 * The function will then map the first page and initialize a pending
301 * occlusion query result structure, Finally it will unmap the buffer.
302 * No interruptible waits are done within this function.
303 *
304 * Returns an error if bo creation or initialization fails.
305 */
306static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
307{
308 int ret;
309 struct vmw_dma_buffer *vbo;
310 struct ttm_bo_kmap_obj map;
311 volatile SVGA3dQueryResult *result;
312 bool dummy;
313
314 /*
315 * Create the vbo as pinned, so that a tryreserve will
316 * immediately succeed. This is because we're the only
317 * user of the bo currently.
318 */
319 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
320 if (!vbo)
321 return -ENOMEM;
322
323 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
324 &vmw_sys_ne_placement, false,
325 &vmw_dmabuf_bo_free);
326 if (unlikely(ret != 0))
327 return ret;
328
329 ret = ttm_bo_reserve(&vbo->base, false, true, false, NULL);
330 BUG_ON(ret != 0);
331 vmw_bo_pin_reserved(vbo, true);
332
333 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
334 if (likely(ret == 0)) {
335 result = ttm_kmap_obj_virtual(&map, &dummy);
336 result->totalSize = sizeof(*result);
337 result->state = SVGA3D_QUERYSTATE_PENDING;
338 result->result32 = 0xff;
339 ttm_bo_kunmap(&map);
340 }
341 vmw_bo_pin_reserved(vbo, false);
342 ttm_bo_unreserve(&vbo->base);
343
344 if (unlikely(ret != 0)) {
345 DRM_ERROR("Dummy query buffer map failed.\n");
346 vmw_dmabuf_unreference(&vbo);
347 } else
348 dev_priv->dummy_query_bo = vbo;
349
350 return ret;
351}
352
353/**
354 * vmw_request_device_late - Perform late device setup
355 *
356 * @dev_priv: Pointer to device private.
357 *
358 * This function performs setup of otables and enables large command
359 * buffer submission. These tasks are split out to a separate function
360 * because it reverts vmw_release_device_early and is intended to be used
361 * by an error path in the hibernation code.
362 */
363static int vmw_request_device_late(struct vmw_private *dev_priv)
364{
365 int ret;
366
367 if (dev_priv->has_mob) {
368 ret = vmw_otables_setup(dev_priv);
369 if (unlikely(ret != 0)) {
370 DRM_ERROR("Unable to initialize "
371 "guest Memory OBjects.\n");
372 return ret;
373 }
374 }
375
376 if (dev_priv->cman) {
377 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
378 256*4096, 2*4096);
379 if (ret) {
380 struct vmw_cmdbuf_man *man = dev_priv->cman;
381
382 dev_priv->cman = NULL;
383 vmw_cmdbuf_man_destroy(man);
384 }
385 }
386
387 return 0;
388}
389
390static int vmw_request_device(struct vmw_private *dev_priv)
391{
392 int ret;
393
394 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
395 if (unlikely(ret != 0)) {
396 DRM_ERROR("Unable to initialize FIFO.\n");
397 return ret;
398 }
399 vmw_fence_fifo_up(dev_priv->fman);
400 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
401 if (IS_ERR(dev_priv->cman)) {
402 dev_priv->cman = NULL;
403 dev_priv->has_dx = false;
404 }
405
406 ret = vmw_request_device_late(dev_priv);
407 if (ret)
408 goto out_no_mob;
409
410 ret = vmw_dummy_query_bo_create(dev_priv);
411 if (unlikely(ret != 0))
412 goto out_no_query_bo;
413
414 return 0;
415
416out_no_query_bo:
417 if (dev_priv->cman)
418 vmw_cmdbuf_remove_pool(dev_priv->cman);
419 if (dev_priv->has_mob) {
420 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
421 vmw_otables_takedown(dev_priv);
422 }
423 if (dev_priv->cman)
424 vmw_cmdbuf_man_destroy(dev_priv->cman);
425out_no_mob:
426 vmw_fence_fifo_down(dev_priv->fman);
427 vmw_fifo_release(dev_priv, &dev_priv->fifo);
428 return ret;
429}
430
431/**
432 * vmw_release_device_early - Early part of fifo takedown.
433 *
434 * @dev_priv: Pointer to device private struct.
435 *
436 * This is the first part of command submission takedown, to be called before
437 * buffer management is taken down.
438 */
439static void vmw_release_device_early(struct vmw_private *dev_priv)
440{
441 /*
442 * Previous destructions should've released
443 * the pinned bo.
444 */
445
446 BUG_ON(dev_priv->pinned_bo != NULL);
447
448 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
449 if (dev_priv->cman)
450 vmw_cmdbuf_remove_pool(dev_priv->cman);
451
452 if (dev_priv->has_mob) {
453 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
454 vmw_otables_takedown(dev_priv);
455 }
456}
457
458/**
459 * vmw_release_device_late - Late part of fifo takedown.
460 *
461 * @dev_priv: Pointer to device private struct.
462 *
463 * This is the last part of the command submission takedown, to be called when
464 * command submission is no longer needed. It may wait on pending fences.
465 */
466static void vmw_release_device_late(struct vmw_private *dev_priv)
467{
468 vmw_fence_fifo_down(dev_priv->fman);
469 if (dev_priv->cman)
470 vmw_cmdbuf_man_destroy(dev_priv->cman);
471
472 vmw_fifo_release(dev_priv, &dev_priv->fifo);
473}
474
475/**
476 * Sets the initial_[width|height] fields on the given vmw_private.
477 *
478 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
479 * clamping the value to fb_max_[width|height] fields and the
480 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
481 * If the values appear to be invalid, set them to
482 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
483 */
484static void vmw_get_initial_size(struct vmw_private *dev_priv)
485{
486 uint32_t width;
487 uint32_t height;
488
489 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
490 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
491
492 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
493 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
494
495 if (width > dev_priv->fb_max_width ||
496 height > dev_priv->fb_max_height) {
497
498 /*
499 * This is a host error and shouldn't occur.
500 */
501
502 width = VMW_MIN_INITIAL_WIDTH;
503 height = VMW_MIN_INITIAL_HEIGHT;
504 }
505
506 dev_priv->initial_width = width;
507 dev_priv->initial_height = height;
508}
509
510/**
511 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
512 * system.
513 *
514 * @dev_priv: Pointer to a struct vmw_private
515 *
516 * This functions tries to determine the IOMMU setup and what actions
517 * need to be taken by the driver to make system pages visible to the
518 * device.
519 * If this function decides that DMA is not possible, it returns -EINVAL.
520 * The driver may then try to disable features of the device that require
521 * DMA.
522 */
523static int vmw_dma_select_mode(struct vmw_private *dev_priv)
524{
525 static const char *names[vmw_dma_map_max] = {
526 [vmw_dma_phys] = "Using physical TTM page addresses.",
527 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
528 [vmw_dma_map_populate] = "Keeping DMA mappings.",
529 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
530#ifdef CONFIG_X86
531 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
532
533#ifdef CONFIG_INTEL_IOMMU
534 if (intel_iommu_enabled) {
535 dev_priv->map_mode = vmw_dma_map_populate;
536 goto out_fixup;
537 }
538#endif
539
540 if (!(vmw_force_iommu || vmw_force_coherent)) {
541 dev_priv->map_mode = vmw_dma_phys;
542 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
543 return 0;
544 }
545
546 dev_priv->map_mode = vmw_dma_map_populate;
547
548 if (dma_ops->sync_single_for_cpu)
549 dev_priv->map_mode = vmw_dma_alloc_coherent;
550#ifdef CONFIG_SWIOTLB
551 if (swiotlb_nr_tbl() == 0)
552 dev_priv->map_mode = vmw_dma_map_populate;
553#endif
554
555#ifdef CONFIG_INTEL_IOMMU
556out_fixup:
557#endif
558 if (dev_priv->map_mode == vmw_dma_map_populate &&
559 vmw_restrict_iommu)
560 dev_priv->map_mode = vmw_dma_map_bind;
561
562 if (vmw_force_coherent)
563 dev_priv->map_mode = vmw_dma_alloc_coherent;
564
565#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
566 /*
567 * No coherent page pool
568 */
569 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
570 return -EINVAL;
571#endif
572
573#else /* CONFIG_X86 */
574 dev_priv->map_mode = vmw_dma_map_populate;
575#endif /* CONFIG_X86 */
576
577 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
578
579 return 0;
580}
581
582/**
583 * vmw_dma_masks - set required page- and dma masks
584 *
585 * @dev: Pointer to struct drm-device
586 *
587 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
588 * restriction also for 64-bit systems.
589 */
590#ifdef CONFIG_INTEL_IOMMU
591static int vmw_dma_masks(struct vmw_private *dev_priv)
592{
593 struct drm_device *dev = dev_priv->dev;
594
595 if (intel_iommu_enabled &&
596 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
597 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
598 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
599 }
600 return 0;
601}
602#else
603static int vmw_dma_masks(struct vmw_private *dev_priv)
604{
605 return 0;
606}
607#endif
608
609static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
610{
611 struct vmw_private *dev_priv;
612 int ret;
613 uint32_t svga_id;
614 enum vmw_res_type i;
615 bool refuse_dma = false;
616
617 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
618 if (unlikely(dev_priv == NULL)) {
619 DRM_ERROR("Failed allocating a device private struct.\n");
620 return -ENOMEM;
621 }
622
623 pci_set_master(dev->pdev);
624
625 dev_priv->dev = dev;
626 dev_priv->vmw_chipset = chipset;
627 dev_priv->last_read_seqno = (uint32_t) -100;
628 mutex_init(&dev_priv->cmdbuf_mutex);
629 mutex_init(&dev_priv->release_mutex);
630 mutex_init(&dev_priv->binding_mutex);
631 rwlock_init(&dev_priv->resource_lock);
632 ttm_lock_init(&dev_priv->reservation_sem);
633 spin_lock_init(&dev_priv->hw_lock);
634 spin_lock_init(&dev_priv->waiter_lock);
635 spin_lock_init(&dev_priv->cap_lock);
636 spin_lock_init(&dev_priv->svga_lock);
637
638 for (i = vmw_res_context; i < vmw_res_max; ++i) {
639 idr_init(&dev_priv->res_idr[i]);
640 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
641 }
642
643 mutex_init(&dev_priv->init_mutex);
644 init_waitqueue_head(&dev_priv->fence_queue);
645 init_waitqueue_head(&dev_priv->fifo_queue);
646 dev_priv->fence_queue_waiters = 0;
647 dev_priv->fifo_queue_waiters = 0;
648
649 dev_priv->used_memory_size = 0;
650
651 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
652 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
653 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
654
655 dev_priv->enable_fb = enable_fbdev;
656
657 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
658 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
659 if (svga_id != SVGA_ID_2) {
660 ret = -ENOSYS;
661 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
662 goto out_err0;
663 }
664
665 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
666 ret = vmw_dma_select_mode(dev_priv);
667 if (unlikely(ret != 0)) {
668 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
669 refuse_dma = true;
670 }
671
672 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
673 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
674 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
675 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
676
677 vmw_get_initial_size(dev_priv);
678
679 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
680 dev_priv->max_gmr_ids =
681 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
682 dev_priv->max_gmr_pages =
683 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
684 dev_priv->memory_size =
685 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
686 dev_priv->memory_size -= dev_priv->vram_size;
687 } else {
688 /*
689 * An arbitrary limit of 512MiB on surface
690 * memory. But all HWV8 hardware supports GMR2.
691 */
692 dev_priv->memory_size = 512*1024*1024;
693 }
694 dev_priv->max_mob_pages = 0;
695 dev_priv->max_mob_size = 0;
696 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
697 uint64_t mem_size =
698 vmw_read(dev_priv,
699 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
700
701 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
702 dev_priv->prim_bb_mem =
703 vmw_read(dev_priv,
704 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
705 dev_priv->max_mob_size =
706 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
707 dev_priv->stdu_max_width =
708 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
709 dev_priv->stdu_max_height =
710 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
711
712 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
713 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
714 dev_priv->texture_max_width = vmw_read(dev_priv,
715 SVGA_REG_DEV_CAP);
716 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
717 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
718 dev_priv->texture_max_height = vmw_read(dev_priv,
719 SVGA_REG_DEV_CAP);
720 } else {
721 dev_priv->texture_max_width = 8192;
722 dev_priv->texture_max_height = 8192;
723 dev_priv->prim_bb_mem = dev_priv->vram_size;
724 }
725
726 vmw_print_capabilities(dev_priv->capabilities);
727
728 ret = vmw_dma_masks(dev_priv);
729 if (unlikely(ret != 0))
730 goto out_err0;
731
732 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
733 DRM_INFO("Max GMR ids is %u\n",
734 (unsigned)dev_priv->max_gmr_ids);
735 DRM_INFO("Max number of GMR pages is %u\n",
736 (unsigned)dev_priv->max_gmr_pages);
737 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
738 (unsigned)dev_priv->memory_size / 1024);
739 }
740 DRM_INFO("Maximum display memory size is %u kiB\n",
741 dev_priv->prim_bb_mem / 1024);
742 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
743 dev_priv->vram_start, dev_priv->vram_size / 1024);
744 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
745 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
746
747 ret = vmw_ttm_global_init(dev_priv);
748 if (unlikely(ret != 0))
749 goto out_err0;
750
751
752 vmw_master_init(&dev_priv->fbdev_master);
753 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
754 dev_priv->active_master = &dev_priv->fbdev_master;
755
756 dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
757 dev_priv->mmio_size, MEMREMAP_WB);
758
759 if (unlikely(dev_priv->mmio_virt == NULL)) {
760 ret = -ENOMEM;
761 DRM_ERROR("Failed mapping MMIO.\n");
762 goto out_err3;
763 }
764
765 /* Need mmio memory to check for fifo pitchlock cap. */
766 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
767 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
768 !vmw_fifo_have_pitchlock(dev_priv)) {
769 ret = -ENOSYS;
770 DRM_ERROR("Hardware has no pitchlock\n");
771 goto out_err4;
772 }
773
774 dev_priv->tdev = ttm_object_device_init
775 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
776
777 if (unlikely(dev_priv->tdev == NULL)) {
778 DRM_ERROR("Unable to initialize TTM object management.\n");
779 ret = -ENOMEM;
780 goto out_err4;
781 }
782
783 dev->dev_private = dev_priv;
784
785 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
786 dev_priv->stealth = (ret != 0);
787 if (dev_priv->stealth) {
788 /**
789 * Request at least the mmio PCI resource.
790 */
791
792 DRM_INFO("It appears like vesafb is loaded. "
793 "Ignore above error if any.\n");
794 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
795 if (unlikely(ret != 0)) {
796 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
797 goto out_no_device;
798 }
799 }
800
801 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
802 ret = drm_irq_install(dev, dev->pdev->irq);
803 if (ret != 0) {
804 DRM_ERROR("Failed installing irq: %d\n", ret);
805 goto out_no_irq;
806 }
807 }
808
809 dev_priv->fman = vmw_fence_manager_init(dev_priv);
810 if (unlikely(dev_priv->fman == NULL)) {
811 ret = -ENOMEM;
812 goto out_no_fman;
813 }
814
815 ret = ttm_bo_device_init(&dev_priv->bdev,
816 dev_priv->bo_global_ref.ref.object,
817 &vmw_bo_driver,
818 dev->anon_inode->i_mapping,
819 VMWGFX_FILE_PAGE_OFFSET,
820 false);
821 if (unlikely(ret != 0)) {
822 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
823 goto out_no_bdev;
824 }
825
826 /*
827 * Enable VRAM, but initially don't use it until SVGA is enabled and
828 * unhidden.
829 */
830 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
831 (dev_priv->vram_size >> PAGE_SHIFT));
832 if (unlikely(ret != 0)) {
833 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
834 goto out_no_vram;
835 }
836 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
837
838 dev_priv->has_gmr = true;
839 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
840 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
841 VMW_PL_GMR) != 0) {
842 DRM_INFO("No GMR memory available. "
843 "Graphics memory resources are very limited.\n");
844 dev_priv->has_gmr = false;
845 }
846
847 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
848 dev_priv->has_mob = true;
849 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
850 VMW_PL_MOB) != 0) {
851 DRM_INFO("No MOB memory available. "
852 "3D will be disabled.\n");
853 dev_priv->has_mob = false;
854 }
855 }
856
857 if (dev_priv->has_mob) {
858 spin_lock(&dev_priv->cap_lock);
859 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
860 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
861 spin_unlock(&dev_priv->cap_lock);
862 }
863
864
865 ret = vmw_kms_init(dev_priv);
866 if (unlikely(ret != 0))
867 goto out_no_kms;
868 vmw_overlay_init(dev_priv);
869
870 ret = vmw_request_device(dev_priv);
871 if (ret)
872 goto out_no_fifo;
873
874 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
875
876 if (dev_priv->enable_fb) {
877 vmw_fifo_resource_inc(dev_priv);
878 vmw_svga_enable(dev_priv);
879 vmw_fb_init(dev_priv);
880 }
881
882 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
883 register_pm_notifier(&dev_priv->pm_nb);
884
885 return 0;
886
887out_no_fifo:
888 vmw_overlay_close(dev_priv);
889 vmw_kms_close(dev_priv);
890out_no_kms:
891 if (dev_priv->has_mob)
892 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
893 if (dev_priv->has_gmr)
894 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
895 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
896out_no_vram:
897 (void)ttm_bo_device_release(&dev_priv->bdev);
898out_no_bdev:
899 vmw_fence_manager_takedown(dev_priv->fman);
900out_no_fman:
901 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
902 drm_irq_uninstall(dev_priv->dev);
903out_no_irq:
904 if (dev_priv->stealth)
905 pci_release_region(dev->pdev, 2);
906 else
907 pci_release_regions(dev->pdev);
908out_no_device:
909 ttm_object_device_release(&dev_priv->tdev);
910out_err4:
911 memunmap(dev_priv->mmio_virt);
912out_err3:
913 vmw_ttm_global_release(dev_priv);
914out_err0:
915 for (i = vmw_res_context; i < vmw_res_max; ++i)
916 idr_destroy(&dev_priv->res_idr[i]);
917
918 if (dev_priv->ctx.staged_bindings)
919 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
920 kfree(dev_priv);
921 return ret;
922}
923
924static int vmw_driver_unload(struct drm_device *dev)
925{
926 struct vmw_private *dev_priv = vmw_priv(dev);
927 enum vmw_res_type i;
928
929 unregister_pm_notifier(&dev_priv->pm_nb);
930
931 if (dev_priv->ctx.res_ht_initialized)
932 drm_ht_remove(&dev_priv->ctx.res_ht);
933 vfree(dev_priv->ctx.cmd_bounce);
934 if (dev_priv->enable_fb) {
935 vmw_fb_off(dev_priv);
936 vmw_fb_close(dev_priv);
937 vmw_fifo_resource_dec(dev_priv);
938 vmw_svga_disable(dev_priv);
939 }
940
941 vmw_kms_close(dev_priv);
942 vmw_overlay_close(dev_priv);
943
944 if (dev_priv->has_gmr)
945 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
946 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
947
948 vmw_release_device_early(dev_priv);
949 if (dev_priv->has_mob)
950 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
951 (void) ttm_bo_device_release(&dev_priv->bdev);
952 vmw_release_device_late(dev_priv);
953 vmw_fence_manager_takedown(dev_priv->fman);
954 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
955 drm_irq_uninstall(dev_priv->dev);
956 if (dev_priv->stealth)
957 pci_release_region(dev->pdev, 2);
958 else
959 pci_release_regions(dev->pdev);
960
961 ttm_object_device_release(&dev_priv->tdev);
962 memunmap(dev_priv->mmio_virt);
963 if (dev_priv->ctx.staged_bindings)
964 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
965 vmw_ttm_global_release(dev_priv);
966
967 for (i = vmw_res_context; i < vmw_res_max; ++i)
968 idr_destroy(&dev_priv->res_idr[i]);
969
970 kfree(dev_priv);
971
972 return 0;
973}
974
975static void vmw_postclose(struct drm_device *dev,
976 struct drm_file *file_priv)
977{
978 struct vmw_fpriv *vmw_fp;
979
980 vmw_fp = vmw_fpriv(file_priv);
981
982 if (vmw_fp->locked_master) {
983 struct vmw_master *vmaster =
984 vmw_master(vmw_fp->locked_master);
985
986 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
987 ttm_vt_unlock(&vmaster->lock);
988 drm_master_put(&vmw_fp->locked_master);
989 }
990
991 ttm_object_file_release(&vmw_fp->tfile);
992 kfree(vmw_fp);
993}
994
995static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
996{
997 struct vmw_private *dev_priv = vmw_priv(dev);
998 struct vmw_fpriv *vmw_fp;
999 int ret = -ENOMEM;
1000
1001 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1002 if (unlikely(vmw_fp == NULL))
1003 return ret;
1004
1005 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1006 if (unlikely(vmw_fp->tfile == NULL))
1007 goto out_no_tfile;
1008
1009 file_priv->driver_priv = vmw_fp;
1010
1011 return 0;
1012
1013out_no_tfile:
1014 kfree(vmw_fp);
1015 return ret;
1016}
1017
1018static struct vmw_master *vmw_master_check(struct drm_device *dev,
1019 struct drm_file *file_priv,
1020 unsigned int flags)
1021{
1022 int ret;
1023 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1024 struct vmw_master *vmaster;
1025
1026 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
1027 !(flags & DRM_AUTH))
1028 return NULL;
1029
1030 ret = mutex_lock_interruptible(&dev->master_mutex);
1031 if (unlikely(ret != 0))
1032 return ERR_PTR(-ERESTARTSYS);
1033
1034 if (file_priv->is_master) {
1035 mutex_unlock(&dev->master_mutex);
1036 return NULL;
1037 }
1038
1039 /*
1040 * Check if we were previously master, but now dropped. In that
1041 * case, allow at least render node functionality.
1042 */
1043 if (vmw_fp->locked_master) {
1044 mutex_unlock(&dev->master_mutex);
1045
1046 if (flags & DRM_RENDER_ALLOW)
1047 return NULL;
1048
1049 DRM_ERROR("Dropped master trying to access ioctl that "
1050 "requires authentication.\n");
1051 return ERR_PTR(-EACCES);
1052 }
1053 mutex_unlock(&dev->master_mutex);
1054
1055 /*
1056 * Take the TTM lock. Possibly sleep waiting for the authenticating
1057 * master to become master again, or for a SIGTERM if the
1058 * authenticating master exits.
1059 */
1060 vmaster = vmw_master(file_priv->master);
1061 ret = ttm_read_lock(&vmaster->lock, true);
1062 if (unlikely(ret != 0))
1063 vmaster = ERR_PTR(ret);
1064
1065 return vmaster;
1066}
1067
1068static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1069 unsigned long arg,
1070 long (*ioctl_func)(struct file *, unsigned int,
1071 unsigned long))
1072{
1073 struct drm_file *file_priv = filp->private_data;
1074 struct drm_device *dev = file_priv->minor->dev;
1075 unsigned int nr = DRM_IOCTL_NR(cmd);
1076 struct vmw_master *vmaster;
1077 unsigned int flags;
1078 long ret;
1079
1080 /*
1081 * Do extra checking on driver private ioctls.
1082 */
1083
1084 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1085 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1086 const struct drm_ioctl_desc *ioctl =
1087 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1088
1089 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1090 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1091 if (unlikely(ret != 0))
1092 return ret;
1093
1094 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1095 goto out_io_encoding;
1096
1097 return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1098 _IOC_SIZE(cmd));
1099 }
1100
1101 if (unlikely(ioctl->cmd != cmd))
1102 goto out_io_encoding;
1103
1104 flags = ioctl->flags;
1105 } else if (!drm_ioctl_flags(nr, &flags))
1106 return -EINVAL;
1107
1108 vmaster = vmw_master_check(dev, file_priv, flags);
1109 if (IS_ERR(vmaster)) {
1110 ret = PTR_ERR(vmaster);
1111
1112 if (ret != -ERESTARTSYS)
1113 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1114 nr, ret);
1115 return ret;
1116 }
1117
1118 ret = ioctl_func(filp, cmd, arg);
1119 if (vmaster)
1120 ttm_read_unlock(&vmaster->lock);
1121
1122 return ret;
1123
1124out_io_encoding:
1125 DRM_ERROR("Invalid command format, ioctl %d\n",
1126 nr - DRM_COMMAND_BASE);
1127
1128 return -EINVAL;
1129}
1130
1131static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1132 unsigned long arg)
1133{
1134 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1135}
1136
1137#ifdef CONFIG_COMPAT
1138static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1139 unsigned long arg)
1140{
1141 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1142}
1143#endif
1144
1145static void vmw_lastclose(struct drm_device *dev)
1146{
1147}
1148
1149static void vmw_master_init(struct vmw_master *vmaster)
1150{
1151 ttm_lock_init(&vmaster->lock);
1152}
1153
1154static int vmw_master_create(struct drm_device *dev,
1155 struct drm_master *master)
1156{
1157 struct vmw_master *vmaster;
1158
1159 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1160 if (unlikely(vmaster == NULL))
1161 return -ENOMEM;
1162
1163 vmw_master_init(vmaster);
1164 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1165 master->driver_priv = vmaster;
1166
1167 return 0;
1168}
1169
1170static void vmw_master_destroy(struct drm_device *dev,
1171 struct drm_master *master)
1172{
1173 struct vmw_master *vmaster = vmw_master(master);
1174
1175 master->driver_priv = NULL;
1176 kfree(vmaster);
1177}
1178
1179static int vmw_master_set(struct drm_device *dev,
1180 struct drm_file *file_priv,
1181 bool from_open)
1182{
1183 struct vmw_private *dev_priv = vmw_priv(dev);
1184 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1185 struct vmw_master *active = dev_priv->active_master;
1186 struct vmw_master *vmaster = vmw_master(file_priv->master);
1187 int ret = 0;
1188
1189 if (active) {
1190 BUG_ON(active != &dev_priv->fbdev_master);
1191 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1192 if (unlikely(ret != 0))
1193 return ret;
1194
1195 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1196 dev_priv->active_master = NULL;
1197 }
1198
1199 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1200 if (!from_open) {
1201 ttm_vt_unlock(&vmaster->lock);
1202 BUG_ON(vmw_fp->locked_master != file_priv->master);
1203 drm_master_put(&vmw_fp->locked_master);
1204 }
1205
1206 dev_priv->active_master = vmaster;
1207 drm_sysfs_hotplug_event(dev);
1208
1209 return 0;
1210}
1211
1212static void vmw_master_drop(struct drm_device *dev,
1213 struct drm_file *file_priv,
1214 bool from_release)
1215{
1216 struct vmw_private *dev_priv = vmw_priv(dev);
1217 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1218 struct vmw_master *vmaster = vmw_master(file_priv->master);
1219 int ret;
1220
1221 /**
1222 * Make sure the master doesn't disappear while we have
1223 * it locked.
1224 */
1225
1226 vmw_fp->locked_master = drm_master_get(file_priv->master);
1227 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1228 vmw_kms_legacy_hotspot_clear(dev_priv);
1229 if (unlikely((ret != 0))) {
1230 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1231 drm_master_put(&vmw_fp->locked_master);
1232 }
1233
1234 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1235
1236 if (!dev_priv->enable_fb)
1237 vmw_svga_disable(dev_priv);
1238
1239 dev_priv->active_master = &dev_priv->fbdev_master;
1240 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1241 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1242
1243 if (dev_priv->enable_fb)
1244 vmw_fb_on(dev_priv);
1245}
1246
1247/**
1248 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1249 *
1250 * @dev_priv: Pointer to device private struct.
1251 * Needs the reservation sem to be held in non-exclusive mode.
1252 */
1253static void __vmw_svga_enable(struct vmw_private *dev_priv)
1254{
1255 spin_lock(&dev_priv->svga_lock);
1256 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1257 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1258 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1259 }
1260 spin_unlock(&dev_priv->svga_lock);
1261}
1262
1263/**
1264 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1265 *
1266 * @dev_priv: Pointer to device private struct.
1267 */
1268void vmw_svga_enable(struct vmw_private *dev_priv)
1269{
1270 ttm_read_lock(&dev_priv->reservation_sem, false);
1271 __vmw_svga_enable(dev_priv);
1272 ttm_read_unlock(&dev_priv->reservation_sem);
1273}
1274
1275/**
1276 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1277 *
1278 * @dev_priv: Pointer to device private struct.
1279 * Needs the reservation sem to be held in exclusive mode.
1280 * Will not empty VRAM. VRAM must be emptied by caller.
1281 */
1282static void __vmw_svga_disable(struct vmw_private *dev_priv)
1283{
1284 spin_lock(&dev_priv->svga_lock);
1285 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1286 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1287 vmw_write(dev_priv, SVGA_REG_ENABLE,
1288 SVGA_REG_ENABLE_HIDE |
1289 SVGA_REG_ENABLE_ENABLE);
1290 }
1291 spin_unlock(&dev_priv->svga_lock);
1292}
1293
1294/**
1295 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1296 * running.
1297 *
1298 * @dev_priv: Pointer to device private struct.
1299 * Will empty VRAM.
1300 */
1301void vmw_svga_disable(struct vmw_private *dev_priv)
1302{
1303 ttm_write_lock(&dev_priv->reservation_sem, false);
1304 spin_lock(&dev_priv->svga_lock);
1305 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1306 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1307 spin_unlock(&dev_priv->svga_lock);
1308 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1309 DRM_ERROR("Failed evicting VRAM buffers.\n");
1310 vmw_write(dev_priv, SVGA_REG_ENABLE,
1311 SVGA_REG_ENABLE_HIDE |
1312 SVGA_REG_ENABLE_ENABLE);
1313 } else
1314 spin_unlock(&dev_priv->svga_lock);
1315 ttm_write_unlock(&dev_priv->reservation_sem);
1316}
1317
1318static void vmw_remove(struct pci_dev *pdev)
1319{
1320 struct drm_device *dev = pci_get_drvdata(pdev);
1321
1322 pci_disable_device(pdev);
1323 drm_put_dev(dev);
1324}
1325
1326static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1327 void *ptr)
1328{
1329 struct vmw_private *dev_priv =
1330 container_of(nb, struct vmw_private, pm_nb);
1331
1332 switch (val) {
1333 case PM_HIBERNATION_PREPARE:
1334 if (dev_priv->enable_fb)
1335 vmw_fb_off(dev_priv);
1336 ttm_suspend_lock(&dev_priv->reservation_sem);
1337
1338 /*
1339 * This empties VRAM and unbinds all GMR bindings.
1340 * Buffer contents is moved to swappable memory.
1341 */
1342 vmw_execbuf_release_pinned_bo(dev_priv);
1343 vmw_resource_evict_all(dev_priv);
1344 vmw_release_device_early(dev_priv);
1345 ttm_bo_swapout_all(&dev_priv->bdev);
1346 vmw_fence_fifo_down(dev_priv->fman);
1347 break;
1348 case PM_POST_HIBERNATION:
1349 case PM_POST_RESTORE:
1350 vmw_fence_fifo_up(dev_priv->fman);
1351 ttm_suspend_unlock(&dev_priv->reservation_sem);
1352 if (dev_priv->enable_fb)
1353 vmw_fb_on(dev_priv);
1354 break;
1355 case PM_RESTORE_PREPARE:
1356 break;
1357 default:
1358 break;
1359 }
1360 return 0;
1361}
1362
1363static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1364{
1365 struct drm_device *dev = pci_get_drvdata(pdev);
1366 struct vmw_private *dev_priv = vmw_priv(dev);
1367
1368 if (dev_priv->refuse_hibernation)
1369 return -EBUSY;
1370
1371 pci_save_state(pdev);
1372 pci_disable_device(pdev);
1373 pci_set_power_state(pdev, PCI_D3hot);
1374 return 0;
1375}
1376
1377static int vmw_pci_resume(struct pci_dev *pdev)
1378{
1379 pci_set_power_state(pdev, PCI_D0);
1380 pci_restore_state(pdev);
1381 return pci_enable_device(pdev);
1382}
1383
1384static int vmw_pm_suspend(struct device *kdev)
1385{
1386 struct pci_dev *pdev = to_pci_dev(kdev);
1387 struct pm_message dummy;
1388
1389 dummy.event = 0;
1390
1391 return vmw_pci_suspend(pdev, dummy);
1392}
1393
1394static int vmw_pm_resume(struct device *kdev)
1395{
1396 struct pci_dev *pdev = to_pci_dev(kdev);
1397
1398 return vmw_pci_resume(pdev);
1399}
1400
1401static int vmw_pm_freeze(struct device *kdev)
1402{
1403 struct pci_dev *pdev = to_pci_dev(kdev);
1404 struct drm_device *dev = pci_get_drvdata(pdev);
1405 struct vmw_private *dev_priv = vmw_priv(dev);
1406
1407 dev_priv->suspended = true;
1408 if (dev_priv->enable_fb)
1409 vmw_fifo_resource_dec(dev_priv);
1410
1411 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1412 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1413 if (dev_priv->enable_fb)
1414 vmw_fifo_resource_inc(dev_priv);
1415 WARN_ON(vmw_request_device_late(dev_priv));
1416 dev_priv->suspended = false;
1417 return -EBUSY;
1418 }
1419
1420 if (dev_priv->enable_fb)
1421 __vmw_svga_disable(dev_priv);
1422
1423 vmw_release_device_late(dev_priv);
1424
1425 return 0;
1426}
1427
1428static int vmw_pm_restore(struct device *kdev)
1429{
1430 struct pci_dev *pdev = to_pci_dev(kdev);
1431 struct drm_device *dev = pci_get_drvdata(pdev);
1432 struct vmw_private *dev_priv = vmw_priv(dev);
1433 int ret;
1434
1435 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1436 (void) vmw_read(dev_priv, SVGA_REG_ID);
1437
1438 if (dev_priv->enable_fb)
1439 vmw_fifo_resource_inc(dev_priv);
1440
1441 ret = vmw_request_device(dev_priv);
1442 if (ret)
1443 return ret;
1444
1445 if (dev_priv->enable_fb)
1446 __vmw_svga_enable(dev_priv);
1447
1448 dev_priv->suspended = false;
1449
1450 return 0;
1451}
1452
1453static const struct dev_pm_ops vmw_pm_ops = {
1454 .freeze = vmw_pm_freeze,
1455 .thaw = vmw_pm_restore,
1456 .restore = vmw_pm_restore,
1457 .suspend = vmw_pm_suspend,
1458 .resume = vmw_pm_resume,
1459};
1460
1461static const struct file_operations vmwgfx_driver_fops = {
1462 .owner = THIS_MODULE,
1463 .open = drm_open,
1464 .release = drm_release,
1465 .unlocked_ioctl = vmw_unlocked_ioctl,
1466 .mmap = vmw_mmap,
1467 .poll = vmw_fops_poll,
1468 .read = vmw_fops_read,
1469#if defined(CONFIG_COMPAT)
1470 .compat_ioctl = vmw_compat_ioctl,
1471#endif
1472 .llseek = noop_llseek,
1473};
1474
1475static struct drm_driver driver = {
1476 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1477 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1478 .load = vmw_driver_load,
1479 .unload = vmw_driver_unload,
1480 .lastclose = vmw_lastclose,
1481 .irq_preinstall = vmw_irq_preinstall,
1482 .irq_postinstall = vmw_irq_postinstall,
1483 .irq_uninstall = vmw_irq_uninstall,
1484 .irq_handler = vmw_irq_handler,
1485 .get_vblank_counter = vmw_get_vblank_counter,
1486 .enable_vblank = vmw_enable_vblank,
1487 .disable_vblank = vmw_disable_vblank,
1488 .ioctls = vmw_ioctls,
1489 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1490 .master_create = vmw_master_create,
1491 .master_destroy = vmw_master_destroy,
1492 .master_set = vmw_master_set,
1493 .master_drop = vmw_master_drop,
1494 .open = vmw_driver_open,
1495 .postclose = vmw_postclose,
1496 .set_busid = drm_pci_set_busid,
1497
1498 .dumb_create = vmw_dumb_create,
1499 .dumb_map_offset = vmw_dumb_map_offset,
1500 .dumb_destroy = vmw_dumb_destroy,
1501
1502 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1503 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1504
1505 .fops = &vmwgfx_driver_fops,
1506 .name = VMWGFX_DRIVER_NAME,
1507 .desc = VMWGFX_DRIVER_DESC,
1508 .date = VMWGFX_DRIVER_DATE,
1509 .major = VMWGFX_DRIVER_MAJOR,
1510 .minor = VMWGFX_DRIVER_MINOR,
1511 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1512};
1513
1514static struct pci_driver vmw_pci_driver = {
1515 .name = VMWGFX_DRIVER_NAME,
1516 .id_table = vmw_pci_id_list,
1517 .probe = vmw_probe,
1518 .remove = vmw_remove,
1519 .driver = {
1520 .pm = &vmw_pm_ops
1521 }
1522};
1523
1524static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1525{
1526 return drm_get_pci_dev(pdev, ent, &driver);
1527}
1528
1529static int __init vmwgfx_init(void)
1530{
1531 int ret;
1532
1533#ifdef CONFIG_VGA_CONSOLE
1534 if (vgacon_text_force())
1535 return -EINVAL;
1536#endif
1537
1538 ret = drm_pci_init(&driver, &vmw_pci_driver);
1539 if (ret)
1540 DRM_ERROR("Failed initializing DRM.\n");
1541 return ret;
1542}
1543
1544static void __exit vmwgfx_exit(void)
1545{
1546 drm_pci_exit(&driver, &vmw_pci_driver);
1547}
1548
1549module_init(vmwgfx_init);
1550module_exit(vmwgfx_exit);
1551
1552MODULE_AUTHOR("VMware Inc. and others");
1553MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1554MODULE_LICENSE("GPL and additional rights");
1555MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1556 __stringify(VMWGFX_DRIVER_MINOR) "."
1557 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1558 "0");
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/**************************************************************************
3 *
4 * Copyright 2009-2022 VMware, Inc., Palo Alto, CA., USA
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29#include "vmwgfx_drv.h"
30
31#include "vmwgfx_devcaps.h"
32#include "vmwgfx_mksstat.h"
33#include "vmwgfx_binding.h"
34#include "ttm_object.h"
35
36#include <drm/drm_aperture.h>
37#include <drm/drm_drv.h>
38#include <drm/drm_fbdev_generic.h>
39#include <drm/drm_gem_ttm_helper.h>
40#include <drm/drm_ioctl.h>
41#include <drm/drm_module.h>
42#include <drm/drm_sysfs.h>
43#include <drm/ttm/ttm_bo_driver.h>
44#include <drm/ttm/ttm_range_manager.h>
45#include <drm/ttm/ttm_placement.h>
46#include <generated/utsrelease.h>
47
48#include <linux/cc_platform.h>
49#include <linux/dma-mapping.h>
50#include <linux/module.h>
51#include <linux/pci.h>
52#include <linux/version.h>
53
54#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
55
56/*
57 * Fully encoded drm commands. Might move to vmw_drm.h
58 */
59
60#define DRM_IOCTL_VMW_GET_PARAM \
61 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
62 struct drm_vmw_getparam_arg)
63#define DRM_IOCTL_VMW_ALLOC_DMABUF \
64 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
65 union drm_vmw_alloc_dmabuf_arg)
66#define DRM_IOCTL_VMW_UNREF_DMABUF \
67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
68 struct drm_vmw_unref_dmabuf_arg)
69#define DRM_IOCTL_VMW_CURSOR_BYPASS \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
71 struct drm_vmw_cursor_bypass_arg)
72
73#define DRM_IOCTL_VMW_CONTROL_STREAM \
74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
75 struct drm_vmw_control_stream_arg)
76#define DRM_IOCTL_VMW_CLAIM_STREAM \
77 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
78 struct drm_vmw_stream_arg)
79#define DRM_IOCTL_VMW_UNREF_STREAM \
80 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
81 struct drm_vmw_stream_arg)
82
83#define DRM_IOCTL_VMW_CREATE_CONTEXT \
84 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
85 struct drm_vmw_context_arg)
86#define DRM_IOCTL_VMW_UNREF_CONTEXT \
87 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
88 struct drm_vmw_context_arg)
89#define DRM_IOCTL_VMW_CREATE_SURFACE \
90 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
91 union drm_vmw_surface_create_arg)
92#define DRM_IOCTL_VMW_UNREF_SURFACE \
93 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
94 struct drm_vmw_surface_arg)
95#define DRM_IOCTL_VMW_REF_SURFACE \
96 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
97 union drm_vmw_surface_reference_arg)
98#define DRM_IOCTL_VMW_EXECBUF \
99 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
100 struct drm_vmw_execbuf_arg)
101#define DRM_IOCTL_VMW_GET_3D_CAP \
102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
103 struct drm_vmw_get_3d_cap_arg)
104#define DRM_IOCTL_VMW_FENCE_WAIT \
105 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
106 struct drm_vmw_fence_wait_arg)
107#define DRM_IOCTL_VMW_FENCE_SIGNALED \
108 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
109 struct drm_vmw_fence_signaled_arg)
110#define DRM_IOCTL_VMW_FENCE_UNREF \
111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
112 struct drm_vmw_fence_arg)
113#define DRM_IOCTL_VMW_FENCE_EVENT \
114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
115 struct drm_vmw_fence_event_arg)
116#define DRM_IOCTL_VMW_PRESENT \
117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
118 struct drm_vmw_present_arg)
119#define DRM_IOCTL_VMW_PRESENT_READBACK \
120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
121 struct drm_vmw_present_readback_arg)
122#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
123 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
124 struct drm_vmw_update_layout_arg)
125#define DRM_IOCTL_VMW_CREATE_SHADER \
126 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
127 struct drm_vmw_shader_create_arg)
128#define DRM_IOCTL_VMW_UNREF_SHADER \
129 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
130 struct drm_vmw_shader_arg)
131#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
133 union drm_vmw_gb_surface_create_arg)
134#define DRM_IOCTL_VMW_GB_SURFACE_REF \
135 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
136 union drm_vmw_gb_surface_reference_arg)
137#define DRM_IOCTL_VMW_SYNCCPU \
138 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
139 struct drm_vmw_synccpu_arg)
140#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
141 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
142 struct drm_vmw_context_arg)
143#define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
145 union drm_vmw_gb_surface_create_ext_arg)
146#define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
147 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
148 union drm_vmw_gb_surface_reference_ext_arg)
149#define DRM_IOCTL_VMW_MSG \
150 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
151 struct drm_vmw_msg_arg)
152#define DRM_IOCTL_VMW_MKSSTAT_RESET \
153 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET)
154#define DRM_IOCTL_VMW_MKSSTAT_ADD \
155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \
156 struct drm_vmw_mksstat_add_arg)
157#define DRM_IOCTL_VMW_MKSSTAT_REMOVE \
158 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \
159 struct drm_vmw_mksstat_remove_arg)
160
161/*
162 * Ioctl definitions.
163 */
164
165static const struct drm_ioctl_desc vmw_ioctls[] = {
166 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl,
167 DRM_RENDER_ALLOW),
168 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl,
169 DRM_RENDER_ALLOW),
170 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
171 DRM_RENDER_ALLOW),
172 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS,
173 vmw_kms_cursor_bypass_ioctl,
174 DRM_MASTER),
175
176 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
177 DRM_MASTER),
178 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
179 DRM_MASTER),
180 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
181 DRM_MASTER),
182
183 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
184 DRM_RENDER_ALLOW),
185 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
186 DRM_RENDER_ALLOW),
187 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
188 DRM_RENDER_ALLOW),
189 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
190 DRM_RENDER_ALLOW),
191 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
192 DRM_RENDER_ALLOW),
193 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl,
194 DRM_RENDER_ALLOW),
195 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
196 DRM_RENDER_ALLOW),
197 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED,
198 vmw_fence_obj_signaled_ioctl,
199 DRM_RENDER_ALLOW),
200 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
201 DRM_RENDER_ALLOW),
202 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
203 DRM_RENDER_ALLOW),
204 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
205 DRM_RENDER_ALLOW),
206
207 /* these allow direct access to the framebuffers mark as master only */
208 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl,
209 DRM_MASTER | DRM_AUTH),
210 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK,
211 vmw_present_readback_ioctl,
212 DRM_MASTER | DRM_AUTH),
213 /*
214 * The permissions of the below ioctl are overridden in
215 * vmw_generic_ioctl(). We require either
216 * DRM_MASTER or capable(CAP_SYS_ADMIN).
217 */
218 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT,
219 vmw_kms_update_layout_ioctl,
220 DRM_RENDER_ALLOW),
221 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER,
222 vmw_shader_define_ioctl,
223 DRM_RENDER_ALLOW),
224 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER,
225 vmw_shader_destroy_ioctl,
226 DRM_RENDER_ALLOW),
227 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE,
228 vmw_gb_surface_define_ioctl,
229 DRM_RENDER_ALLOW),
230 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF,
231 vmw_gb_surface_reference_ioctl,
232 DRM_RENDER_ALLOW),
233 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU,
234 vmw_user_bo_synccpu_ioctl,
235 DRM_RENDER_ALLOW),
236 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT,
237 vmw_extended_context_define_ioctl,
238 DRM_RENDER_ALLOW),
239 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT,
240 vmw_gb_surface_define_ext_ioctl,
241 DRM_RENDER_ALLOW),
242 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT,
243 vmw_gb_surface_reference_ext_ioctl,
244 DRM_RENDER_ALLOW),
245 DRM_IOCTL_DEF_DRV(VMW_MSG,
246 vmw_msg_ioctl,
247 DRM_RENDER_ALLOW),
248 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET,
249 vmw_mksstat_reset_ioctl,
250 DRM_RENDER_ALLOW),
251 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD,
252 vmw_mksstat_add_ioctl,
253 DRM_RENDER_ALLOW),
254 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE,
255 vmw_mksstat_remove_ioctl,
256 DRM_RENDER_ALLOW),
257};
258
259static const struct pci_device_id vmw_pci_id_list[] = {
260 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) },
261 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) },
262 { }
263};
264MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
265
266static int vmw_restrict_iommu;
267static int vmw_force_coherent;
268static int vmw_restrict_dma_mask;
269static int vmw_assume_16bpp;
270
271static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
272static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
273 void *ptr);
274
275MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
276module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
277MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
278module_param_named(force_coherent, vmw_force_coherent, int, 0600);
279MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
280module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
281MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
282module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
283
284
285struct bitmap_name {
286 uint32 value;
287 const char *name;
288};
289
290static const struct bitmap_name cap1_names[] = {
291 { SVGA_CAP_RECT_COPY, "rect copy" },
292 { SVGA_CAP_CURSOR, "cursor" },
293 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" },
294 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" },
295 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" },
296 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" },
297 { SVGA_CAP_3D, "3D" },
298 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" },
299 { SVGA_CAP_MULTIMON, "multimon" },
300 { SVGA_CAP_PITCHLOCK, "pitchlock" },
301 { SVGA_CAP_IRQMASK, "irq mask" },
302 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" },
303 { SVGA_CAP_GMR, "gmr" },
304 { SVGA_CAP_TRACES, "traces" },
305 { SVGA_CAP_GMR2, "gmr2" },
306 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" },
307 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" },
308 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" },
309 { SVGA_CAP_GBOBJECTS, "gbobject" },
310 { SVGA_CAP_DX, "dx" },
311 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" },
312 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" },
313 { SVGA_CAP_CAP2_REGISTER, "cap2 register" },
314};
315
316
317static const struct bitmap_name cap2_names[] = {
318 { SVGA_CAP2_GROW_OTABLE, "grow otable" },
319 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" },
320 { SVGA_CAP2_DX2, "dx2" },
321 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" },
322 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" },
323 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" },
324 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" },
325 { SVGA_CAP2_CURSOR_MOB, "cursor mob" },
326 { SVGA_CAP2_MSHINT, "mshint" },
327 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" },
328 { SVGA_CAP2_DX3, "dx3" },
329 { SVGA_CAP2_FRAME_TYPE, "frame type" },
330 { SVGA_CAP2_COTABLE_COPY, "cotable copy" },
331 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" },
332 { SVGA_CAP2_EXTRA_REGS, "extra regs" },
333 { SVGA_CAP2_LO_STAGING, "lo staging" },
334};
335
336static void vmw_print_bitmap(struct drm_device *drm,
337 const char *prefix, uint32_t bitmap,
338 const struct bitmap_name *bnames,
339 uint32_t num_names)
340{
341 char buf[512];
342 uint32_t i;
343 uint32_t offset = 0;
344 for (i = 0; i < num_names; ++i) {
345 if ((bitmap & bnames[i].value) != 0) {
346 offset += snprintf(buf + offset,
347 ARRAY_SIZE(buf) - offset,
348 "%s, ", bnames[i].name);
349 bitmap &= ~bnames[i].value;
350 }
351 }
352
353 drm_info(drm, "%s: %s\n", prefix, buf);
354 if (bitmap != 0)
355 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap);
356}
357
358
359static void vmw_print_sm_type(struct vmw_private *dev_priv)
360{
361 static const char *names[] = {
362 [VMW_SM_LEGACY] = "Legacy",
363 [VMW_SM_4] = "SM4",
364 [VMW_SM_4_1] = "SM4_1",
365 [VMW_SM_5] = "SM_5",
366 [VMW_SM_5_1X] = "SM_5_1X",
367 [VMW_SM_MAX] = "Invalid"
368 };
369 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1));
370 drm_info(&dev_priv->drm, "Available shader model: %s.\n",
371 names[dev_priv->sm_type]);
372}
373
374/**
375 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
376 *
377 * @dev_priv: A device private structure.
378 *
379 * This function creates a small buffer object that holds the query
380 * result for dummy queries emitted as query barriers.
381 * The function will then map the first page and initialize a pending
382 * occlusion query result structure, Finally it will unmap the buffer.
383 * No interruptible waits are done within this function.
384 *
385 * Returns an error if bo creation or initialization fails.
386 */
387static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
388{
389 int ret;
390 struct vmw_buffer_object *vbo;
391 struct ttm_bo_kmap_obj map;
392 volatile SVGA3dQueryResult *result;
393 bool dummy;
394
395 /*
396 * Create the vbo as pinned, so that a tryreserve will
397 * immediately succeed. This is because we're the only
398 * user of the bo currently.
399 */
400 ret = vmw_bo_create(dev_priv, PAGE_SIZE,
401 &vmw_sys_placement, false, true,
402 &vmw_bo_bo_free, &vbo);
403 if (unlikely(ret != 0))
404 return ret;
405
406 ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
407 BUG_ON(ret != 0);
408 vmw_bo_pin_reserved(vbo, true);
409
410 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
411 if (likely(ret == 0)) {
412 result = ttm_kmap_obj_virtual(&map, &dummy);
413 result->totalSize = sizeof(*result);
414 result->state = SVGA3D_QUERYSTATE_PENDING;
415 result->result32 = 0xff;
416 ttm_bo_kunmap(&map);
417 }
418 vmw_bo_pin_reserved(vbo, false);
419 ttm_bo_unreserve(&vbo->base);
420
421 if (unlikely(ret != 0)) {
422 DRM_ERROR("Dummy query buffer map failed.\n");
423 vmw_bo_unreference(&vbo);
424 } else
425 dev_priv->dummy_query_bo = vbo;
426
427 return ret;
428}
429
430static int vmw_device_init(struct vmw_private *dev_priv)
431{
432 bool uses_fb_traces = false;
433
434 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
435 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
436 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
437
438 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
439 SVGA_REG_ENABLE_HIDE);
440
441 uses_fb_traces = !vmw_cmd_supported(dev_priv) &&
442 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0;
443
444 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces);
445 dev_priv->fifo = vmw_fifo_create(dev_priv);
446 if (IS_ERR(dev_priv->fifo)) {
447 int err = PTR_ERR(dev_priv->fifo);
448 dev_priv->fifo = NULL;
449 return err;
450 } else if (!dev_priv->fifo) {
451 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
452 }
453
454 dev_priv->last_read_seqno = vmw_fence_read(dev_priv);
455 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
456 return 0;
457}
458
459static void vmw_device_fini(struct vmw_private *vmw)
460{
461 /*
462 * Legacy sync
463 */
464 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
465 while (vmw_read(vmw, SVGA_REG_BUSY) != 0)
466 ;
467
468 vmw->last_read_seqno = vmw_fence_read(vmw);
469
470 vmw_write(vmw, SVGA_REG_CONFIG_DONE,
471 vmw->config_done_state);
472 vmw_write(vmw, SVGA_REG_ENABLE,
473 vmw->enable_state);
474 vmw_write(vmw, SVGA_REG_TRACES,
475 vmw->traces_state);
476
477 vmw_fifo_destroy(vmw);
478}
479
480/**
481 * vmw_request_device_late - Perform late device setup
482 *
483 * @dev_priv: Pointer to device private.
484 *
485 * This function performs setup of otables and enables large command
486 * buffer submission. These tasks are split out to a separate function
487 * because it reverts vmw_release_device_early and is intended to be used
488 * by an error path in the hibernation code.
489 */
490static int vmw_request_device_late(struct vmw_private *dev_priv)
491{
492 int ret;
493
494 if (dev_priv->has_mob) {
495 ret = vmw_otables_setup(dev_priv);
496 if (unlikely(ret != 0)) {
497 DRM_ERROR("Unable to initialize "
498 "guest Memory OBjects.\n");
499 return ret;
500 }
501 }
502
503 if (dev_priv->cman) {
504 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
505 if (ret) {
506 struct vmw_cmdbuf_man *man = dev_priv->cman;
507
508 dev_priv->cman = NULL;
509 vmw_cmdbuf_man_destroy(man);
510 }
511 }
512
513 return 0;
514}
515
516static int vmw_request_device(struct vmw_private *dev_priv)
517{
518 int ret;
519
520 ret = vmw_device_init(dev_priv);
521 if (unlikely(ret != 0)) {
522 DRM_ERROR("Unable to initialize the device.\n");
523 return ret;
524 }
525 vmw_fence_fifo_up(dev_priv->fman);
526 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
527 if (IS_ERR(dev_priv->cman)) {
528 dev_priv->cman = NULL;
529 dev_priv->sm_type = VMW_SM_LEGACY;
530 }
531
532 ret = vmw_request_device_late(dev_priv);
533 if (ret)
534 goto out_no_mob;
535
536 ret = vmw_dummy_query_bo_create(dev_priv);
537 if (unlikely(ret != 0))
538 goto out_no_query_bo;
539
540 return 0;
541
542out_no_query_bo:
543 if (dev_priv->cman)
544 vmw_cmdbuf_remove_pool(dev_priv->cman);
545 if (dev_priv->has_mob) {
546 struct ttm_resource_manager *man;
547
548 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
549 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
550 vmw_otables_takedown(dev_priv);
551 }
552 if (dev_priv->cman)
553 vmw_cmdbuf_man_destroy(dev_priv->cman);
554out_no_mob:
555 vmw_fence_fifo_down(dev_priv->fman);
556 vmw_device_fini(dev_priv);
557 return ret;
558}
559
560/**
561 * vmw_release_device_early - Early part of fifo takedown.
562 *
563 * @dev_priv: Pointer to device private struct.
564 *
565 * This is the first part of command submission takedown, to be called before
566 * buffer management is taken down.
567 */
568static void vmw_release_device_early(struct vmw_private *dev_priv)
569{
570 /*
571 * Previous destructions should've released
572 * the pinned bo.
573 */
574
575 BUG_ON(dev_priv->pinned_bo != NULL);
576
577 vmw_bo_unreference(&dev_priv->dummy_query_bo);
578 if (dev_priv->cman)
579 vmw_cmdbuf_remove_pool(dev_priv->cman);
580
581 if (dev_priv->has_mob) {
582 struct ttm_resource_manager *man;
583
584 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
585 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
586 vmw_otables_takedown(dev_priv);
587 }
588}
589
590/**
591 * vmw_release_device_late - Late part of fifo takedown.
592 *
593 * @dev_priv: Pointer to device private struct.
594 *
595 * This is the last part of the command submission takedown, to be called when
596 * command submission is no longer needed. It may wait on pending fences.
597 */
598static void vmw_release_device_late(struct vmw_private *dev_priv)
599{
600 vmw_fence_fifo_down(dev_priv->fman);
601 if (dev_priv->cman)
602 vmw_cmdbuf_man_destroy(dev_priv->cman);
603
604 vmw_device_fini(dev_priv);
605}
606
607/*
608 * Sets the initial_[width|height] fields on the given vmw_private.
609 *
610 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
611 * clamping the value to fb_max_[width|height] fields and the
612 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
613 * If the values appear to be invalid, set them to
614 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
615 */
616static void vmw_get_initial_size(struct vmw_private *dev_priv)
617{
618 uint32_t width;
619 uint32_t height;
620
621 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
622 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
623
624 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH);
625 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT);
626
627 if (width > dev_priv->fb_max_width ||
628 height > dev_priv->fb_max_height) {
629
630 /*
631 * This is a host error and shouldn't occur.
632 */
633
634 width = VMWGFX_MIN_INITIAL_WIDTH;
635 height = VMWGFX_MIN_INITIAL_HEIGHT;
636 }
637
638 dev_priv->initial_width = width;
639 dev_priv->initial_height = height;
640}
641
642/**
643 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
644 * system.
645 *
646 * @dev_priv: Pointer to a struct vmw_private
647 *
648 * This functions tries to determine what actions need to be taken by the
649 * driver to make system pages visible to the device.
650 * If this function decides that DMA is not possible, it returns -EINVAL.
651 * The driver may then try to disable features of the device that require
652 * DMA.
653 */
654static int vmw_dma_select_mode(struct vmw_private *dev_priv)
655{
656 static const char *names[vmw_dma_map_max] = {
657 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
658 [vmw_dma_map_populate] = "Caching DMA mappings.",
659 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
660
661 /* TTM currently doesn't fully support SEV encryption. */
662 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT))
663 return -EINVAL;
664
665 if (vmw_force_coherent)
666 dev_priv->map_mode = vmw_dma_alloc_coherent;
667 else if (vmw_restrict_iommu)
668 dev_priv->map_mode = vmw_dma_map_bind;
669 else
670 dev_priv->map_mode = vmw_dma_map_populate;
671
672 drm_info(&dev_priv->drm,
673 "DMA map mode: %s\n", names[dev_priv->map_mode]);
674 return 0;
675}
676
677/**
678 * vmw_dma_masks - set required page- and dma masks
679 *
680 * @dev_priv: Pointer to struct drm-device
681 *
682 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
683 * restriction also for 64-bit systems.
684 */
685static int vmw_dma_masks(struct vmw_private *dev_priv)
686{
687 struct drm_device *dev = &dev_priv->drm;
688 int ret = 0;
689
690 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
691 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) {
692 drm_info(&dev_priv->drm,
693 "Restricting DMA addresses to 44 bits.\n");
694 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
695 }
696
697 return ret;
698}
699
700static int vmw_vram_manager_init(struct vmw_private *dev_priv)
701{
702 int ret;
703 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
704 dev_priv->vram_size >> PAGE_SHIFT);
705 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
706 return ret;
707}
708
709static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
710{
711 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
712}
713
714static int vmw_setup_pci_resources(struct vmw_private *dev,
715 u32 pci_id)
716{
717 resource_size_t rmmio_start;
718 resource_size_t rmmio_size;
719 resource_size_t fifo_start;
720 resource_size_t fifo_size;
721 int ret;
722 struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
723
724 pci_set_master(pdev);
725
726 ret = pci_request_regions(pdev, "vmwgfx probe");
727 if (ret)
728 return ret;
729
730 dev->pci_id = pci_id;
731 if (pci_id == VMWGFX_PCI_ID_SVGA3) {
732 rmmio_start = pci_resource_start(pdev, 0);
733 rmmio_size = pci_resource_len(pdev, 0);
734 dev->vram_start = pci_resource_start(pdev, 2);
735 dev->vram_size = pci_resource_len(pdev, 2);
736
737 drm_info(&dev->drm,
738 "Register MMIO at 0x%pa size is %llu kiB\n",
739 &rmmio_start, (uint64_t)rmmio_size / 1024);
740 dev->rmmio = devm_ioremap(dev->drm.dev,
741 rmmio_start,
742 rmmio_size);
743 if (!dev->rmmio) {
744 drm_err(&dev->drm,
745 "Failed mapping registers mmio memory.\n");
746 pci_release_regions(pdev);
747 return -ENOMEM;
748 }
749 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) {
750 dev->io_start = pci_resource_start(pdev, 0);
751 dev->vram_start = pci_resource_start(pdev, 1);
752 dev->vram_size = pci_resource_len(pdev, 1);
753 fifo_start = pci_resource_start(pdev, 2);
754 fifo_size = pci_resource_len(pdev, 2);
755
756 drm_info(&dev->drm,
757 "FIFO at %pa size is %llu kiB\n",
758 &fifo_start, (uint64_t)fifo_size / 1024);
759 dev->fifo_mem = devm_memremap(dev->drm.dev,
760 fifo_start,
761 fifo_size,
762 MEMREMAP_WB);
763
764 if (IS_ERR(dev->fifo_mem)) {
765 drm_err(&dev->drm,
766 "Failed mapping FIFO memory.\n");
767 pci_release_regions(pdev);
768 return PTR_ERR(dev->fifo_mem);
769 }
770 } else {
771 pci_release_regions(pdev);
772 return -EINVAL;
773 }
774
775 /*
776 * This is approximate size of the vram, the exact size will only
777 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
778 * size will be equal to or bigger than the size reported by
779 * SVGA_REG_VRAM_SIZE.
780 */
781 drm_info(&dev->drm,
782 "VRAM at %pa size is %llu kiB\n",
783 &dev->vram_start, (uint64_t)dev->vram_size / 1024);
784
785 return 0;
786}
787
788static int vmw_detect_version(struct vmw_private *dev)
789{
790 uint32_t svga_id;
791
792 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ?
793 SVGA_ID_3 : SVGA_ID_2);
794 svga_id = vmw_read(dev, SVGA_REG_ID);
795 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) {
796 drm_err(&dev->drm,
797 "Unsupported SVGA ID 0x%x on chipset 0x%x\n",
798 svga_id, dev->pci_id);
799 return -ENOSYS;
800 }
801 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3));
802 drm_info(&dev->drm,
803 "Running on SVGA version %d.\n", (svga_id & 0xff));
804 return 0;
805}
806
807static void vmw_write_driver_id(struct vmw_private *dev)
808{
809 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) {
810 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
811 SVGA_REG_GUEST_DRIVER_ID_LINUX);
812
813 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1,
814 LINUX_VERSION_MAJOR << 24 |
815 LINUX_VERSION_PATCHLEVEL << 16 |
816 LINUX_VERSION_SUBLEVEL);
817 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2,
818 VMWGFX_DRIVER_MAJOR << 24 |
819 VMWGFX_DRIVER_MINOR << 16 |
820 VMWGFX_DRIVER_PATCHLEVEL);
821 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0);
822
823 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID,
824 SVGA_REG_GUEST_DRIVER_ID_SUBMIT);
825 }
826}
827
828static void vmw_sw_context_init(struct vmw_private *dev_priv)
829{
830 struct vmw_sw_context *sw_context = &dev_priv->ctx;
831
832 hash_init(sw_context->res_ht);
833}
834
835static void vmw_sw_context_fini(struct vmw_private *dev_priv)
836{
837 struct vmw_sw_context *sw_context = &dev_priv->ctx;
838
839 vfree(sw_context->cmd_bounce);
840 if (sw_context->staged_bindings)
841 vmw_binding_state_free(sw_context->staged_bindings);
842}
843
844static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
845{
846 int ret;
847 enum vmw_res_type i;
848 bool refuse_dma = false;
849 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
850
851 dev_priv->drm.dev_private = dev_priv;
852
853 vmw_sw_context_init(dev_priv);
854
855 mutex_init(&dev_priv->cmdbuf_mutex);
856 mutex_init(&dev_priv->binding_mutex);
857 spin_lock_init(&dev_priv->resource_lock);
858 spin_lock_init(&dev_priv->hw_lock);
859 spin_lock_init(&dev_priv->waiter_lock);
860 spin_lock_init(&dev_priv->cursor_lock);
861
862 ret = vmw_setup_pci_resources(dev_priv, pci_id);
863 if (ret)
864 return ret;
865 ret = vmw_detect_version(dev_priv);
866 if (ret)
867 goto out_no_pci_or_version;
868
869
870 for (i = vmw_res_context; i < vmw_res_max; ++i) {
871 idr_init_base(&dev_priv->res_idr[i], 1);
872 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
873 }
874
875 init_waitqueue_head(&dev_priv->fence_queue);
876 init_waitqueue_head(&dev_priv->fifo_queue);
877 dev_priv->fence_queue_waiters = 0;
878 dev_priv->fifo_queue_waiters = 0;
879
880 dev_priv->used_memory_size = 0;
881
882 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
883
884 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
885 vmw_print_bitmap(&dev_priv->drm, "Capabilities",
886 dev_priv->capabilities,
887 cap1_names, ARRAY_SIZE(cap1_names));
888 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
889 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
890 vmw_print_bitmap(&dev_priv->drm, "Capabilities2",
891 dev_priv->capabilities2,
892 cap2_names, ARRAY_SIZE(cap2_names));
893 }
894
895 ret = vmw_dma_select_mode(dev_priv);
896 if (unlikely(ret != 0)) {
897 drm_info(&dev_priv->drm,
898 "Restricting capabilities since DMA not available.\n");
899 refuse_dma = true;
900 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
901 drm_info(&dev_priv->drm,
902 "Disabling 3D acceleration.\n");
903 }
904
905 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
906 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
907 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
908 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
909
910 vmw_get_initial_size(dev_priv);
911
912 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
913 dev_priv->max_gmr_ids =
914 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
915 dev_priv->max_gmr_pages =
916 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
917 dev_priv->memory_size =
918 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
919 dev_priv->memory_size -= dev_priv->vram_size;
920 } else {
921 /*
922 * An arbitrary limit of 512MiB on surface
923 * memory. But all HWV8 hardware supports GMR2.
924 */
925 dev_priv->memory_size = 512*1024*1024;
926 }
927 dev_priv->max_mob_pages = 0;
928 dev_priv->max_mob_size = 0;
929 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
930 uint64_t mem_size;
931
932 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
933 mem_size = vmw_read(dev_priv,
934 SVGA_REG_GBOBJECT_MEM_SIZE_KB);
935 else
936 mem_size =
937 vmw_read(dev_priv,
938 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
939
940 /*
941 * Workaround for low memory 2D VMs to compensate for the
942 * allocation taken by fbdev
943 */
944 if (!(dev_priv->capabilities & SVGA_CAP_3D))
945 mem_size *= 3;
946
947 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
948 dev_priv->max_primary_mem =
949 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
950 dev_priv->max_mob_size =
951 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
952 dev_priv->stdu_max_width =
953 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
954 dev_priv->stdu_max_height =
955 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
956
957 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
958 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
959 dev_priv->texture_max_width = vmw_read(dev_priv,
960 SVGA_REG_DEV_CAP);
961 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
962 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
963 dev_priv->texture_max_height = vmw_read(dev_priv,
964 SVGA_REG_DEV_CAP);
965 } else {
966 dev_priv->texture_max_width = 8192;
967 dev_priv->texture_max_height = 8192;
968 dev_priv->max_primary_mem = dev_priv->vram_size;
969 }
970 drm_info(&dev_priv->drm,
971 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n",
972 (u64)dev_priv->vram_size / 1024,
973 (u64)dev_priv->fifo_mem_size / 1024,
974 dev_priv->memory_size / 1024);
975
976 drm_info(&dev_priv->drm,
977 "MOB limits: max mob size = %u kB, max mob pages = %u\n",
978 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);
979
980 ret = vmw_dma_masks(dev_priv);
981 if (unlikely(ret != 0))
982 goto out_err0;
983
984 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
985
986 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
987 drm_info(&dev_priv->drm,
988 "Max GMR ids is %u\n",
989 (unsigned)dev_priv->max_gmr_ids);
990 drm_info(&dev_priv->drm,
991 "Max number of GMR pages is %u\n",
992 (unsigned)dev_priv->max_gmr_pages);
993 }
994 drm_info(&dev_priv->drm,
995 "Maximum display memory size is %llu kiB\n",
996 (uint64_t)dev_priv->max_primary_mem / 1024);
997
998 /* Need mmio memory to check for fifo pitchlock cap. */
999 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
1000 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
1001 !vmw_fifo_have_pitchlock(dev_priv)) {
1002 ret = -ENOSYS;
1003 DRM_ERROR("Hardware has no pitchlock\n");
1004 goto out_err0;
1005 }
1006
1007 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops);
1008
1009 if (unlikely(dev_priv->tdev == NULL)) {
1010 drm_err(&dev_priv->drm,
1011 "Unable to initialize TTM object management.\n");
1012 ret = -ENOMEM;
1013 goto out_err0;
1014 }
1015
1016 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
1017 ret = vmw_irq_install(dev_priv);
1018 if (ret != 0) {
1019 drm_err(&dev_priv->drm,
1020 "Failed installing irq: %d\n", ret);
1021 goto out_no_irq;
1022 }
1023 }
1024
1025 dev_priv->fman = vmw_fence_manager_init(dev_priv);
1026 if (unlikely(dev_priv->fman == NULL)) {
1027 ret = -ENOMEM;
1028 goto out_no_fman;
1029 }
1030
1031 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,
1032 dev_priv->drm.dev,
1033 dev_priv->drm.anon_inode->i_mapping,
1034 dev_priv->drm.vma_offset_manager,
1035 dev_priv->map_mode == vmw_dma_alloc_coherent,
1036 false);
1037 if (unlikely(ret != 0)) {
1038 drm_err(&dev_priv->drm,
1039 "Failed initializing TTM buffer object driver.\n");
1040 goto out_no_bdev;
1041 }
1042
1043 /*
1044 * Enable VRAM, but initially don't use it until SVGA is enabled and
1045 * unhidden.
1046 */
1047
1048 ret = vmw_vram_manager_init(dev_priv);
1049 if (unlikely(ret != 0)) {
1050 drm_err(&dev_priv->drm,
1051 "Failed initializing memory manager for VRAM.\n");
1052 goto out_no_vram;
1053 }
1054
1055 ret = vmw_devcaps_create(dev_priv);
1056 if (unlikely(ret != 0)) {
1057 drm_err(&dev_priv->drm,
1058 "Failed initializing device caps.\n");
1059 goto out_no_vram;
1060 }
1061
1062 /*
1063 * "Guest Memory Regions" is an aperture like feature with
1064 * one slot per bo. There is an upper limit of the number of
1065 * slots as well as the bo size.
1066 */
1067 dev_priv->has_gmr = true;
1068 /* TODO: This is most likely not correct */
1069 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
1070 refuse_dma ||
1071 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
1072 drm_info(&dev_priv->drm,
1073 "No GMR memory available. "
1074 "Graphics memory resources are very limited.\n");
1075 dev_priv->has_gmr = false;
1076 }
1077
1078 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
1079 dev_priv->has_mob = true;
1080
1081 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
1082 drm_info(&dev_priv->drm,
1083 "No MOB memory available. "
1084 "3D will be disabled.\n");
1085 dev_priv->has_mob = false;
1086 }
1087 if (vmw_sys_man_init(dev_priv) != 0) {
1088 drm_info(&dev_priv->drm,
1089 "No MOB page table memory available. "
1090 "3D will be disabled.\n");
1091 dev_priv->has_mob = false;
1092 }
1093 }
1094
1095 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
1096 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT))
1097 dev_priv->sm_type = VMW_SM_4;
1098 }
1099
1100 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
1101 if (has_sm4_context(dev_priv) &&
1102 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
1103 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41))
1104 dev_priv->sm_type = VMW_SM_4_1;
1105 if (has_sm4_1_context(dev_priv) &&
1106 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
1107 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) {
1108 dev_priv->sm_type = VMW_SM_5;
1109 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43))
1110 dev_priv->sm_type = VMW_SM_5_1X;
1111 }
1112 }
1113 }
1114
1115 ret = vmw_kms_init(dev_priv);
1116 if (unlikely(ret != 0))
1117 goto out_no_kms;
1118 vmw_overlay_init(dev_priv);
1119
1120 ret = vmw_request_device(dev_priv);
1121 if (ret)
1122 goto out_no_fifo;
1123
1124 vmw_print_sm_type(dev_priv);
1125 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)",
1126 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
1127 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE);
1128 vmw_write_driver_id(dev_priv);
1129
1130 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
1131 register_pm_notifier(&dev_priv->pm_nb);
1132
1133 return 0;
1134
1135out_no_fifo:
1136 vmw_overlay_close(dev_priv);
1137 vmw_kms_close(dev_priv);
1138out_no_kms:
1139 if (dev_priv->has_mob) {
1140 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1141 vmw_sys_man_fini(dev_priv);
1142 }
1143 if (dev_priv->has_gmr)
1144 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1145 vmw_devcaps_destroy(dev_priv);
1146 vmw_vram_manager_fini(dev_priv);
1147out_no_vram:
1148 ttm_device_fini(&dev_priv->bdev);
1149out_no_bdev:
1150 vmw_fence_manager_takedown(dev_priv->fman);
1151out_no_fman:
1152 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1153 vmw_irq_uninstall(&dev_priv->drm);
1154out_no_irq:
1155 ttm_object_device_release(&dev_priv->tdev);
1156out_err0:
1157 for (i = vmw_res_context; i < vmw_res_max; ++i)
1158 idr_destroy(&dev_priv->res_idr[i]);
1159
1160 if (dev_priv->ctx.staged_bindings)
1161 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1162out_no_pci_or_version:
1163 pci_release_regions(pdev);
1164 return ret;
1165}
1166
1167static void vmw_driver_unload(struct drm_device *dev)
1168{
1169 struct vmw_private *dev_priv = vmw_priv(dev);
1170 struct pci_dev *pdev = to_pci_dev(dev->dev);
1171 enum vmw_res_type i;
1172
1173 unregister_pm_notifier(&dev_priv->pm_nb);
1174
1175 vmw_sw_context_fini(dev_priv);
1176 vmw_fifo_resource_dec(dev_priv);
1177
1178 vmw_svga_disable(dev_priv);
1179
1180 vmw_kms_close(dev_priv);
1181 vmw_overlay_close(dev_priv);
1182
1183 if (dev_priv->has_gmr)
1184 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1185
1186 vmw_release_device_early(dev_priv);
1187 if (dev_priv->has_mob) {
1188 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1189 vmw_sys_man_fini(dev_priv);
1190 }
1191 vmw_devcaps_destroy(dev_priv);
1192 vmw_vram_manager_fini(dev_priv);
1193 ttm_device_fini(&dev_priv->bdev);
1194 vmw_release_device_late(dev_priv);
1195 vmw_fence_manager_takedown(dev_priv->fman);
1196 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1197 vmw_irq_uninstall(&dev_priv->drm);
1198
1199 ttm_object_device_release(&dev_priv->tdev);
1200
1201 for (i = vmw_res_context; i < vmw_res_max; ++i)
1202 idr_destroy(&dev_priv->res_idr[i]);
1203
1204 vmw_mksstat_remove_all(dev_priv);
1205
1206 pci_release_regions(pdev);
1207}
1208
1209static void vmw_postclose(struct drm_device *dev,
1210 struct drm_file *file_priv)
1211{
1212 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1213
1214 ttm_object_file_release(&vmw_fp->tfile);
1215 kfree(vmw_fp);
1216}
1217
1218static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1219{
1220 struct vmw_private *dev_priv = vmw_priv(dev);
1221 struct vmw_fpriv *vmw_fp;
1222 int ret = -ENOMEM;
1223
1224 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1225 if (unlikely(!vmw_fp))
1226 return ret;
1227
1228 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev);
1229 if (unlikely(vmw_fp->tfile == NULL))
1230 goto out_no_tfile;
1231
1232 file_priv->driver_priv = vmw_fp;
1233
1234 return 0;
1235
1236out_no_tfile:
1237 kfree(vmw_fp);
1238 return ret;
1239}
1240
1241static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1242 unsigned long arg,
1243 long (*ioctl_func)(struct file *, unsigned int,
1244 unsigned long))
1245{
1246 struct drm_file *file_priv = filp->private_data;
1247 struct drm_device *dev = file_priv->minor->dev;
1248 unsigned int nr = DRM_IOCTL_NR(cmd);
1249 unsigned int flags;
1250
1251 /*
1252 * Do extra checking on driver private ioctls.
1253 */
1254
1255 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1256 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1257 const struct drm_ioctl_desc *ioctl =
1258 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1259
1260 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1261 return ioctl_func(filp, cmd, arg);
1262 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1263 if (!drm_is_current_master(file_priv) &&
1264 !capable(CAP_SYS_ADMIN))
1265 return -EACCES;
1266 }
1267
1268 if (unlikely(ioctl->cmd != cmd))
1269 goto out_io_encoding;
1270
1271 flags = ioctl->flags;
1272 } else if (!drm_ioctl_flags(nr, &flags))
1273 return -EINVAL;
1274
1275 return ioctl_func(filp, cmd, arg);
1276
1277out_io_encoding:
1278 DRM_ERROR("Invalid command format, ioctl %d\n",
1279 nr - DRM_COMMAND_BASE);
1280
1281 return -EINVAL;
1282}
1283
1284static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1285 unsigned long arg)
1286{
1287 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1288}
1289
1290#ifdef CONFIG_COMPAT
1291static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1292 unsigned long arg)
1293{
1294 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1295}
1296#endif
1297
1298static void vmw_master_set(struct drm_device *dev,
1299 struct drm_file *file_priv,
1300 bool from_open)
1301{
1302 /*
1303 * Inform a new master that the layout may have changed while
1304 * it was gone.
1305 */
1306 if (!from_open)
1307 drm_sysfs_hotplug_event(dev);
1308}
1309
1310static void vmw_master_drop(struct drm_device *dev,
1311 struct drm_file *file_priv)
1312{
1313 struct vmw_private *dev_priv = vmw_priv(dev);
1314
1315 vmw_kms_legacy_hotspot_clear(dev_priv);
1316}
1317
1318/**
1319 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1320 *
1321 * @dev_priv: Pointer to device private struct.
1322 * Needs the reservation sem to be held in non-exclusive mode.
1323 */
1324static void __vmw_svga_enable(struct vmw_private *dev_priv)
1325{
1326 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1327
1328 if (!ttm_resource_manager_used(man)) {
1329 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE);
1330 ttm_resource_manager_set_used(man, true);
1331 }
1332}
1333
1334/**
1335 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1336 *
1337 * @dev_priv: Pointer to device private struct.
1338 */
1339void vmw_svga_enable(struct vmw_private *dev_priv)
1340{
1341 __vmw_svga_enable(dev_priv);
1342}
1343
1344/**
1345 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1346 *
1347 * @dev_priv: Pointer to device private struct.
1348 * Needs the reservation sem to be held in exclusive mode.
1349 * Will not empty VRAM. VRAM must be emptied by caller.
1350 */
1351static void __vmw_svga_disable(struct vmw_private *dev_priv)
1352{
1353 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1354
1355 if (ttm_resource_manager_used(man)) {
1356 ttm_resource_manager_set_used(man, false);
1357 vmw_write(dev_priv, SVGA_REG_ENABLE,
1358 SVGA_REG_ENABLE_HIDE |
1359 SVGA_REG_ENABLE_ENABLE);
1360 }
1361}
1362
1363/**
1364 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1365 * running.
1366 *
1367 * @dev_priv: Pointer to device private struct.
1368 * Will empty VRAM.
1369 */
1370void vmw_svga_disable(struct vmw_private *dev_priv)
1371{
1372 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1373 /*
1374 * Disabling SVGA will turn off device modesetting capabilities, so
1375 * notify KMS about that so that it doesn't cache atomic state that
1376 * isn't valid anymore, for example crtcs turned on.
1377 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1378 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1379 * end up with lock order reversal. Thus, a master may actually perform
1380 * a new modeset just after we call vmw_kms_lost_device() and race with
1381 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1382 * to be inconsistent with the device, causing modesetting problems.
1383 *
1384 */
1385 vmw_kms_lost_device(&dev_priv->drm);
1386 if (ttm_resource_manager_used(man)) {
1387 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1388 DRM_ERROR("Failed evicting VRAM buffers.\n");
1389 ttm_resource_manager_set_used(man, false);
1390 vmw_write(dev_priv, SVGA_REG_ENABLE,
1391 SVGA_REG_ENABLE_HIDE |
1392 SVGA_REG_ENABLE_ENABLE);
1393 }
1394}
1395
1396static void vmw_remove(struct pci_dev *pdev)
1397{
1398 struct drm_device *dev = pci_get_drvdata(pdev);
1399
1400 drm_dev_unregister(dev);
1401 vmw_driver_unload(dev);
1402}
1403
1404static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw)
1405{
1406 struct drm_minor *minor = vmw->drm.primary;
1407 struct dentry *root = minor->debugfs_root;
1408
1409 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM),
1410 root, "system_ttm");
1411 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM),
1412 root, "vram_ttm");
1413 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR),
1414 root, "gmr_ttm");
1415 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB),
1416 root, "mob_ttm");
1417 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM),
1418 root, "system_mob_ttm");
1419}
1420
1421static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1422 void *ptr)
1423{
1424 struct vmw_private *dev_priv =
1425 container_of(nb, struct vmw_private, pm_nb);
1426
1427 switch (val) {
1428 case PM_HIBERNATION_PREPARE:
1429 /*
1430 * Take the reservation sem in write mode, which will make sure
1431 * there are no other processes holding a buffer object
1432 * reservation, meaning we should be able to evict all buffer
1433 * objects if needed.
1434 * Once user-space processes have been frozen, we can release
1435 * the lock again.
1436 */
1437 dev_priv->suspend_locked = true;
1438 break;
1439 case PM_POST_HIBERNATION:
1440 case PM_POST_RESTORE:
1441 if (READ_ONCE(dev_priv->suspend_locked)) {
1442 dev_priv->suspend_locked = false;
1443 }
1444 break;
1445 default:
1446 break;
1447 }
1448 return 0;
1449}
1450
1451static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1452{
1453 struct drm_device *dev = pci_get_drvdata(pdev);
1454 struct vmw_private *dev_priv = vmw_priv(dev);
1455
1456 if (dev_priv->refuse_hibernation)
1457 return -EBUSY;
1458
1459 pci_save_state(pdev);
1460 pci_disable_device(pdev);
1461 pci_set_power_state(pdev, PCI_D3hot);
1462 return 0;
1463}
1464
1465static int vmw_pci_resume(struct pci_dev *pdev)
1466{
1467 pci_set_power_state(pdev, PCI_D0);
1468 pci_restore_state(pdev);
1469 return pci_enable_device(pdev);
1470}
1471
1472static int vmw_pm_suspend(struct device *kdev)
1473{
1474 struct pci_dev *pdev = to_pci_dev(kdev);
1475 struct pm_message dummy;
1476
1477 dummy.event = 0;
1478
1479 return vmw_pci_suspend(pdev, dummy);
1480}
1481
1482static int vmw_pm_resume(struct device *kdev)
1483{
1484 struct pci_dev *pdev = to_pci_dev(kdev);
1485
1486 return vmw_pci_resume(pdev);
1487}
1488
1489static int vmw_pm_freeze(struct device *kdev)
1490{
1491 struct pci_dev *pdev = to_pci_dev(kdev);
1492 struct drm_device *dev = pci_get_drvdata(pdev);
1493 struct vmw_private *dev_priv = vmw_priv(dev);
1494 struct ttm_operation_ctx ctx = {
1495 .interruptible = false,
1496 .no_wait_gpu = false
1497 };
1498 int ret;
1499
1500 /*
1501 * No user-space processes should be running now.
1502 */
1503 ret = vmw_kms_suspend(&dev_priv->drm);
1504 if (ret) {
1505 DRM_ERROR("Failed to freeze modesetting.\n");
1506 return ret;
1507 }
1508
1509 vmw_execbuf_release_pinned_bo(dev_priv);
1510 vmw_resource_evict_all(dev_priv);
1511 vmw_release_device_early(dev_priv);
1512 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);
1513 vmw_fifo_resource_dec(dev_priv);
1514 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1515 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1516 vmw_fifo_resource_inc(dev_priv);
1517 WARN_ON(vmw_request_device_late(dev_priv));
1518 dev_priv->suspend_locked = false;
1519 if (dev_priv->suspend_state)
1520 vmw_kms_resume(dev);
1521 return -EBUSY;
1522 }
1523
1524 vmw_fence_fifo_down(dev_priv->fman);
1525 __vmw_svga_disable(dev_priv);
1526
1527 vmw_release_device_late(dev_priv);
1528 return 0;
1529}
1530
1531static int vmw_pm_restore(struct device *kdev)
1532{
1533 struct pci_dev *pdev = to_pci_dev(kdev);
1534 struct drm_device *dev = pci_get_drvdata(pdev);
1535 struct vmw_private *dev_priv = vmw_priv(dev);
1536 int ret;
1537
1538 vmw_detect_version(dev_priv);
1539
1540 vmw_fifo_resource_inc(dev_priv);
1541
1542 ret = vmw_request_device(dev_priv);
1543 if (ret)
1544 return ret;
1545
1546 __vmw_svga_enable(dev_priv);
1547
1548 vmw_fence_fifo_up(dev_priv->fman);
1549 dev_priv->suspend_locked = false;
1550 if (dev_priv->suspend_state)
1551 vmw_kms_resume(&dev_priv->drm);
1552
1553 return 0;
1554}
1555
1556static const struct dev_pm_ops vmw_pm_ops = {
1557 .freeze = vmw_pm_freeze,
1558 .thaw = vmw_pm_restore,
1559 .restore = vmw_pm_restore,
1560 .suspend = vmw_pm_suspend,
1561 .resume = vmw_pm_resume,
1562};
1563
1564static const struct file_operations vmwgfx_driver_fops = {
1565 .owner = THIS_MODULE,
1566 .open = drm_open,
1567 .release = drm_release,
1568 .unlocked_ioctl = vmw_unlocked_ioctl,
1569 .mmap = vmw_mmap,
1570 .poll = drm_poll,
1571 .read = drm_read,
1572#if defined(CONFIG_COMPAT)
1573 .compat_ioctl = vmw_compat_ioctl,
1574#endif
1575 .llseek = noop_llseek,
1576};
1577
1578static const struct drm_driver driver = {
1579 .driver_features =
1580 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM,
1581 .ioctls = vmw_ioctls,
1582 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1583 .master_set = vmw_master_set,
1584 .master_drop = vmw_master_drop,
1585 .open = vmw_driver_open,
1586 .postclose = vmw_postclose,
1587
1588 .dumb_create = vmw_dumb_create,
1589 .dumb_map_offset = drm_gem_ttm_dumb_map_offset,
1590
1591 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1592 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1593
1594 .fops = &vmwgfx_driver_fops,
1595 .name = VMWGFX_DRIVER_NAME,
1596 .desc = VMWGFX_DRIVER_DESC,
1597 .date = VMWGFX_DRIVER_DATE,
1598 .major = VMWGFX_DRIVER_MAJOR,
1599 .minor = VMWGFX_DRIVER_MINOR,
1600 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1601};
1602
1603static struct pci_driver vmw_pci_driver = {
1604 .name = VMWGFX_DRIVER_NAME,
1605 .id_table = vmw_pci_id_list,
1606 .probe = vmw_probe,
1607 .remove = vmw_remove,
1608 .driver = {
1609 .pm = &vmw_pm_ops
1610 }
1611};
1612
1613static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1614{
1615 struct vmw_private *vmw;
1616 int ret;
1617
1618 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver);
1619 if (ret)
1620 goto out_error;
1621
1622 ret = pcim_enable_device(pdev);
1623 if (ret)
1624 goto out_error;
1625
1626 vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
1627 struct vmw_private, drm);
1628 if (IS_ERR(vmw)) {
1629 ret = PTR_ERR(vmw);
1630 goto out_error;
1631 }
1632
1633 pci_set_drvdata(pdev, &vmw->drm);
1634
1635 ret = vmw_driver_load(vmw, ent->device);
1636 if (ret)
1637 goto out_error;
1638
1639 ret = drm_dev_register(&vmw->drm, 0);
1640 if (ret)
1641 goto out_unload;
1642
1643 vmw_fifo_resource_inc(vmw);
1644 vmw_svga_enable(vmw);
1645 drm_fbdev_generic_setup(&vmw->drm, 0);
1646
1647 vmw_debugfs_gem_init(vmw);
1648 vmw_debugfs_resource_managers_init(vmw);
1649
1650 return 0;
1651out_unload:
1652 vmw_driver_unload(&vmw->drm);
1653out_error:
1654 return ret;
1655}
1656
1657drm_module_pci_driver(vmw_pci_driver);
1658
1659MODULE_AUTHOR("VMware Inc. and others");
1660MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1661MODULE_LICENSE("GPL and additional rights");
1662MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1663 __stringify(VMWGFX_DRIVER_MINOR) "."
1664 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1665 "0");