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1/**************************************************************************
2 *
3 * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27#include <linux/module.h>
28#include <linux/console.h>
29
30#include <drm/drmP.h>
31#include "vmwgfx_drv.h"
32#include "vmwgfx_binding.h"
33#include <drm/ttm/ttm_placement.h>
34#include <drm/ttm/ttm_bo_driver.h>
35#include <drm/ttm/ttm_object.h>
36#include <drm/ttm/ttm_module.h>
37#include <linux/dma_remapping.h>
38
39#define VMWGFX_DRIVER_NAME "vmwgfx"
40#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
41#define VMWGFX_CHIP_SVGAII 0
42#define VMW_FB_RESERVATION 0
43
44#define VMW_MIN_INITIAL_WIDTH 800
45#define VMW_MIN_INITIAL_HEIGHT 600
46
47
48/**
49 * Fully encoded drm commands. Might move to vmw_drm.h
50 */
51
52#define DRM_IOCTL_VMW_GET_PARAM \
53 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
54 struct drm_vmw_getparam_arg)
55#define DRM_IOCTL_VMW_ALLOC_DMABUF \
56 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
57 union drm_vmw_alloc_dmabuf_arg)
58#define DRM_IOCTL_VMW_UNREF_DMABUF \
59 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
60 struct drm_vmw_unref_dmabuf_arg)
61#define DRM_IOCTL_VMW_CURSOR_BYPASS \
62 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
63 struct drm_vmw_cursor_bypass_arg)
64
65#define DRM_IOCTL_VMW_CONTROL_STREAM \
66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
67 struct drm_vmw_control_stream_arg)
68#define DRM_IOCTL_VMW_CLAIM_STREAM \
69 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
70 struct drm_vmw_stream_arg)
71#define DRM_IOCTL_VMW_UNREF_STREAM \
72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
73 struct drm_vmw_stream_arg)
74
75#define DRM_IOCTL_VMW_CREATE_CONTEXT \
76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
77 struct drm_vmw_context_arg)
78#define DRM_IOCTL_VMW_UNREF_CONTEXT \
79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
80 struct drm_vmw_context_arg)
81#define DRM_IOCTL_VMW_CREATE_SURFACE \
82 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
83 union drm_vmw_surface_create_arg)
84#define DRM_IOCTL_VMW_UNREF_SURFACE \
85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
86 struct drm_vmw_surface_arg)
87#define DRM_IOCTL_VMW_REF_SURFACE \
88 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
89 union drm_vmw_surface_reference_arg)
90#define DRM_IOCTL_VMW_EXECBUF \
91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
92 struct drm_vmw_execbuf_arg)
93#define DRM_IOCTL_VMW_GET_3D_CAP \
94 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
95 struct drm_vmw_get_3d_cap_arg)
96#define DRM_IOCTL_VMW_FENCE_WAIT \
97 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
98 struct drm_vmw_fence_wait_arg)
99#define DRM_IOCTL_VMW_FENCE_SIGNALED \
100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
101 struct drm_vmw_fence_signaled_arg)
102#define DRM_IOCTL_VMW_FENCE_UNREF \
103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
104 struct drm_vmw_fence_arg)
105#define DRM_IOCTL_VMW_FENCE_EVENT \
106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
107 struct drm_vmw_fence_event_arg)
108#define DRM_IOCTL_VMW_PRESENT \
109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
110 struct drm_vmw_present_arg)
111#define DRM_IOCTL_VMW_PRESENT_READBACK \
112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
113 struct drm_vmw_present_readback_arg)
114#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
116 struct drm_vmw_update_layout_arg)
117#define DRM_IOCTL_VMW_CREATE_SHADER \
118 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
119 struct drm_vmw_shader_create_arg)
120#define DRM_IOCTL_VMW_UNREF_SHADER \
121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
122 struct drm_vmw_shader_arg)
123#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
124 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
125 union drm_vmw_gb_surface_create_arg)
126#define DRM_IOCTL_VMW_GB_SURFACE_REF \
127 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
128 union drm_vmw_gb_surface_reference_arg)
129#define DRM_IOCTL_VMW_SYNCCPU \
130 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
131 struct drm_vmw_synccpu_arg)
132#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
134 struct drm_vmw_context_arg)
135
136/**
137 * The core DRM version of this macro doesn't account for
138 * DRM_COMMAND_BASE.
139 */
140
141#define VMW_IOCTL_DEF(ioctl, func, flags) \
142 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
143
144/**
145 * Ioctl definitions.
146 */
147
148static const struct drm_ioctl_desc vmw_ioctls[] = {
149 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
150 DRM_AUTH | DRM_RENDER_ALLOW),
151 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
152 DRM_AUTH | DRM_RENDER_ALLOW),
153 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
154 DRM_RENDER_ALLOW),
155 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
156 vmw_kms_cursor_bypass_ioctl,
157 DRM_MASTER | DRM_CONTROL_ALLOW),
158
159 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
160 DRM_MASTER | DRM_CONTROL_ALLOW),
161 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
162 DRM_MASTER | DRM_CONTROL_ALLOW),
163 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
164 DRM_MASTER | DRM_CONTROL_ALLOW),
165
166 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
167 DRM_AUTH | DRM_RENDER_ALLOW),
168 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
169 DRM_RENDER_ALLOW),
170 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
171 DRM_AUTH | DRM_RENDER_ALLOW),
172 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
173 DRM_RENDER_ALLOW),
174 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
175 DRM_AUTH | DRM_RENDER_ALLOW),
176 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
177 DRM_RENDER_ALLOW),
178 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
179 DRM_RENDER_ALLOW),
180 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
181 vmw_fence_obj_signaled_ioctl,
182 DRM_RENDER_ALLOW),
183 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
184 DRM_RENDER_ALLOW),
185 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
186 DRM_AUTH | DRM_RENDER_ALLOW),
187 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
188 DRM_AUTH | DRM_RENDER_ALLOW),
189
190 /* these allow direct access to the framebuffers mark as master only */
191 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
192 DRM_MASTER | DRM_AUTH),
193 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
194 vmw_present_readback_ioctl,
195 DRM_MASTER | DRM_AUTH),
196 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
197 vmw_kms_update_layout_ioctl,
198 DRM_MASTER | DRM_CONTROL_ALLOW),
199 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
200 vmw_shader_define_ioctl,
201 DRM_AUTH | DRM_RENDER_ALLOW),
202 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
203 vmw_shader_destroy_ioctl,
204 DRM_RENDER_ALLOW),
205 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
206 vmw_gb_surface_define_ioctl,
207 DRM_AUTH | DRM_RENDER_ALLOW),
208 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
209 vmw_gb_surface_reference_ioctl,
210 DRM_AUTH | DRM_RENDER_ALLOW),
211 VMW_IOCTL_DEF(VMW_SYNCCPU,
212 vmw_user_dmabuf_synccpu_ioctl,
213 DRM_RENDER_ALLOW),
214 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
215 vmw_extended_context_define_ioctl,
216 DRM_AUTH | DRM_RENDER_ALLOW),
217};
218
219static struct pci_device_id vmw_pci_id_list[] = {
220 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
221 {0, 0, 0}
222};
223MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
224
225static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
226static int vmw_force_iommu;
227static int vmw_restrict_iommu;
228static int vmw_force_coherent;
229static int vmw_restrict_dma_mask;
230
231static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
232static void vmw_master_init(struct vmw_master *);
233static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
234 void *ptr);
235
236MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
237module_param_named(enable_fbdev, enable_fbdev, int, 0600);
238MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
239module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
240MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
241module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
242MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
243module_param_named(force_coherent, vmw_force_coherent, int, 0600);
244MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
245module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
246
247
248static void vmw_print_capabilities(uint32_t capabilities)
249{
250 DRM_INFO("Capabilities:\n");
251 if (capabilities & SVGA_CAP_RECT_COPY)
252 DRM_INFO(" Rect copy.\n");
253 if (capabilities & SVGA_CAP_CURSOR)
254 DRM_INFO(" Cursor.\n");
255 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
256 DRM_INFO(" Cursor bypass.\n");
257 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
258 DRM_INFO(" Cursor bypass 2.\n");
259 if (capabilities & SVGA_CAP_8BIT_EMULATION)
260 DRM_INFO(" 8bit emulation.\n");
261 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
262 DRM_INFO(" Alpha cursor.\n");
263 if (capabilities & SVGA_CAP_3D)
264 DRM_INFO(" 3D.\n");
265 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
266 DRM_INFO(" Extended Fifo.\n");
267 if (capabilities & SVGA_CAP_MULTIMON)
268 DRM_INFO(" Multimon.\n");
269 if (capabilities & SVGA_CAP_PITCHLOCK)
270 DRM_INFO(" Pitchlock.\n");
271 if (capabilities & SVGA_CAP_IRQMASK)
272 DRM_INFO(" Irq mask.\n");
273 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
274 DRM_INFO(" Display Topology.\n");
275 if (capabilities & SVGA_CAP_GMR)
276 DRM_INFO(" GMR.\n");
277 if (capabilities & SVGA_CAP_TRACES)
278 DRM_INFO(" Traces.\n");
279 if (capabilities & SVGA_CAP_GMR2)
280 DRM_INFO(" GMR2.\n");
281 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
282 DRM_INFO(" Screen Object 2.\n");
283 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
284 DRM_INFO(" Command Buffers.\n");
285 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
286 DRM_INFO(" Command Buffers 2.\n");
287 if (capabilities & SVGA_CAP_GBOBJECTS)
288 DRM_INFO(" Guest Backed Resources.\n");
289 if (capabilities & SVGA_CAP_DX)
290 DRM_INFO(" DX Features.\n");
291}
292
293/**
294 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
295 *
296 * @dev_priv: A device private structure.
297 *
298 * This function creates a small buffer object that holds the query
299 * result for dummy queries emitted as query barriers.
300 * The function will then map the first page and initialize a pending
301 * occlusion query result structure, Finally it will unmap the buffer.
302 * No interruptible waits are done within this function.
303 *
304 * Returns an error if bo creation or initialization fails.
305 */
306static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
307{
308 int ret;
309 struct vmw_dma_buffer *vbo;
310 struct ttm_bo_kmap_obj map;
311 volatile SVGA3dQueryResult *result;
312 bool dummy;
313
314 /*
315 * Create the vbo as pinned, so that a tryreserve will
316 * immediately succeed. This is because we're the only
317 * user of the bo currently.
318 */
319 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
320 if (!vbo)
321 return -ENOMEM;
322
323 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
324 &vmw_sys_ne_placement, false,
325 &vmw_dmabuf_bo_free);
326 if (unlikely(ret != 0))
327 return ret;
328
329 ret = ttm_bo_reserve(&vbo->base, false, true, false, NULL);
330 BUG_ON(ret != 0);
331 vmw_bo_pin_reserved(vbo, true);
332
333 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
334 if (likely(ret == 0)) {
335 result = ttm_kmap_obj_virtual(&map, &dummy);
336 result->totalSize = sizeof(*result);
337 result->state = SVGA3D_QUERYSTATE_PENDING;
338 result->result32 = 0xff;
339 ttm_bo_kunmap(&map);
340 }
341 vmw_bo_pin_reserved(vbo, false);
342 ttm_bo_unreserve(&vbo->base);
343
344 if (unlikely(ret != 0)) {
345 DRM_ERROR("Dummy query buffer map failed.\n");
346 vmw_dmabuf_unreference(&vbo);
347 } else
348 dev_priv->dummy_query_bo = vbo;
349
350 return ret;
351}
352
353/**
354 * vmw_request_device_late - Perform late device setup
355 *
356 * @dev_priv: Pointer to device private.
357 *
358 * This function performs setup of otables and enables large command
359 * buffer submission. These tasks are split out to a separate function
360 * because it reverts vmw_release_device_early and is intended to be used
361 * by an error path in the hibernation code.
362 */
363static int vmw_request_device_late(struct vmw_private *dev_priv)
364{
365 int ret;
366
367 if (dev_priv->has_mob) {
368 ret = vmw_otables_setup(dev_priv);
369 if (unlikely(ret != 0)) {
370 DRM_ERROR("Unable to initialize "
371 "guest Memory OBjects.\n");
372 return ret;
373 }
374 }
375
376 if (dev_priv->cman) {
377 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
378 256*4096, 2*4096);
379 if (ret) {
380 struct vmw_cmdbuf_man *man = dev_priv->cman;
381
382 dev_priv->cman = NULL;
383 vmw_cmdbuf_man_destroy(man);
384 }
385 }
386
387 return 0;
388}
389
390static int vmw_request_device(struct vmw_private *dev_priv)
391{
392 int ret;
393
394 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
395 if (unlikely(ret != 0)) {
396 DRM_ERROR("Unable to initialize FIFO.\n");
397 return ret;
398 }
399 vmw_fence_fifo_up(dev_priv->fman);
400 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
401 if (IS_ERR(dev_priv->cman)) {
402 dev_priv->cman = NULL;
403 dev_priv->has_dx = false;
404 }
405
406 ret = vmw_request_device_late(dev_priv);
407 if (ret)
408 goto out_no_mob;
409
410 ret = vmw_dummy_query_bo_create(dev_priv);
411 if (unlikely(ret != 0))
412 goto out_no_query_bo;
413
414 return 0;
415
416out_no_query_bo:
417 if (dev_priv->cman)
418 vmw_cmdbuf_remove_pool(dev_priv->cman);
419 if (dev_priv->has_mob) {
420 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
421 vmw_otables_takedown(dev_priv);
422 }
423 if (dev_priv->cman)
424 vmw_cmdbuf_man_destroy(dev_priv->cman);
425out_no_mob:
426 vmw_fence_fifo_down(dev_priv->fman);
427 vmw_fifo_release(dev_priv, &dev_priv->fifo);
428 return ret;
429}
430
431/**
432 * vmw_release_device_early - Early part of fifo takedown.
433 *
434 * @dev_priv: Pointer to device private struct.
435 *
436 * This is the first part of command submission takedown, to be called before
437 * buffer management is taken down.
438 */
439static void vmw_release_device_early(struct vmw_private *dev_priv)
440{
441 /*
442 * Previous destructions should've released
443 * the pinned bo.
444 */
445
446 BUG_ON(dev_priv->pinned_bo != NULL);
447
448 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
449 if (dev_priv->cman)
450 vmw_cmdbuf_remove_pool(dev_priv->cman);
451
452 if (dev_priv->has_mob) {
453 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
454 vmw_otables_takedown(dev_priv);
455 }
456}
457
458/**
459 * vmw_release_device_late - Late part of fifo takedown.
460 *
461 * @dev_priv: Pointer to device private struct.
462 *
463 * This is the last part of the command submission takedown, to be called when
464 * command submission is no longer needed. It may wait on pending fences.
465 */
466static void vmw_release_device_late(struct vmw_private *dev_priv)
467{
468 vmw_fence_fifo_down(dev_priv->fman);
469 if (dev_priv->cman)
470 vmw_cmdbuf_man_destroy(dev_priv->cman);
471
472 vmw_fifo_release(dev_priv, &dev_priv->fifo);
473}
474
475/**
476 * Sets the initial_[width|height] fields on the given vmw_private.
477 *
478 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
479 * clamping the value to fb_max_[width|height] fields and the
480 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
481 * If the values appear to be invalid, set them to
482 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
483 */
484static void vmw_get_initial_size(struct vmw_private *dev_priv)
485{
486 uint32_t width;
487 uint32_t height;
488
489 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
490 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
491
492 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
493 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
494
495 if (width > dev_priv->fb_max_width ||
496 height > dev_priv->fb_max_height) {
497
498 /*
499 * This is a host error and shouldn't occur.
500 */
501
502 width = VMW_MIN_INITIAL_WIDTH;
503 height = VMW_MIN_INITIAL_HEIGHT;
504 }
505
506 dev_priv->initial_width = width;
507 dev_priv->initial_height = height;
508}
509
510/**
511 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
512 * system.
513 *
514 * @dev_priv: Pointer to a struct vmw_private
515 *
516 * This functions tries to determine the IOMMU setup and what actions
517 * need to be taken by the driver to make system pages visible to the
518 * device.
519 * If this function decides that DMA is not possible, it returns -EINVAL.
520 * The driver may then try to disable features of the device that require
521 * DMA.
522 */
523static int vmw_dma_select_mode(struct vmw_private *dev_priv)
524{
525 static const char *names[vmw_dma_map_max] = {
526 [vmw_dma_phys] = "Using physical TTM page addresses.",
527 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
528 [vmw_dma_map_populate] = "Keeping DMA mappings.",
529 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
530#ifdef CONFIG_X86
531 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
532
533#ifdef CONFIG_INTEL_IOMMU
534 if (intel_iommu_enabled) {
535 dev_priv->map_mode = vmw_dma_map_populate;
536 goto out_fixup;
537 }
538#endif
539
540 if (!(vmw_force_iommu || vmw_force_coherent)) {
541 dev_priv->map_mode = vmw_dma_phys;
542 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
543 return 0;
544 }
545
546 dev_priv->map_mode = vmw_dma_map_populate;
547
548 if (dma_ops->sync_single_for_cpu)
549 dev_priv->map_mode = vmw_dma_alloc_coherent;
550#ifdef CONFIG_SWIOTLB
551 if (swiotlb_nr_tbl() == 0)
552 dev_priv->map_mode = vmw_dma_map_populate;
553#endif
554
555#ifdef CONFIG_INTEL_IOMMU
556out_fixup:
557#endif
558 if (dev_priv->map_mode == vmw_dma_map_populate &&
559 vmw_restrict_iommu)
560 dev_priv->map_mode = vmw_dma_map_bind;
561
562 if (vmw_force_coherent)
563 dev_priv->map_mode = vmw_dma_alloc_coherent;
564
565#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
566 /*
567 * No coherent page pool
568 */
569 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
570 return -EINVAL;
571#endif
572
573#else /* CONFIG_X86 */
574 dev_priv->map_mode = vmw_dma_map_populate;
575#endif /* CONFIG_X86 */
576
577 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
578
579 return 0;
580}
581
582/**
583 * vmw_dma_masks - set required page- and dma masks
584 *
585 * @dev: Pointer to struct drm-device
586 *
587 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
588 * restriction also for 64-bit systems.
589 */
590#ifdef CONFIG_INTEL_IOMMU
591static int vmw_dma_masks(struct vmw_private *dev_priv)
592{
593 struct drm_device *dev = dev_priv->dev;
594
595 if (intel_iommu_enabled &&
596 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
597 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
598 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
599 }
600 return 0;
601}
602#else
603static int vmw_dma_masks(struct vmw_private *dev_priv)
604{
605 return 0;
606}
607#endif
608
609static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
610{
611 struct vmw_private *dev_priv;
612 int ret;
613 uint32_t svga_id;
614 enum vmw_res_type i;
615 bool refuse_dma = false;
616
617 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
618 if (unlikely(dev_priv == NULL)) {
619 DRM_ERROR("Failed allocating a device private struct.\n");
620 return -ENOMEM;
621 }
622
623 pci_set_master(dev->pdev);
624
625 dev_priv->dev = dev;
626 dev_priv->vmw_chipset = chipset;
627 dev_priv->last_read_seqno = (uint32_t) -100;
628 mutex_init(&dev_priv->cmdbuf_mutex);
629 mutex_init(&dev_priv->release_mutex);
630 mutex_init(&dev_priv->binding_mutex);
631 rwlock_init(&dev_priv->resource_lock);
632 ttm_lock_init(&dev_priv->reservation_sem);
633 spin_lock_init(&dev_priv->hw_lock);
634 spin_lock_init(&dev_priv->waiter_lock);
635 spin_lock_init(&dev_priv->cap_lock);
636 spin_lock_init(&dev_priv->svga_lock);
637
638 for (i = vmw_res_context; i < vmw_res_max; ++i) {
639 idr_init(&dev_priv->res_idr[i]);
640 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
641 }
642
643 mutex_init(&dev_priv->init_mutex);
644 init_waitqueue_head(&dev_priv->fence_queue);
645 init_waitqueue_head(&dev_priv->fifo_queue);
646 dev_priv->fence_queue_waiters = 0;
647 dev_priv->fifo_queue_waiters = 0;
648
649 dev_priv->used_memory_size = 0;
650
651 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
652 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
653 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
654
655 dev_priv->enable_fb = enable_fbdev;
656
657 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
658 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
659 if (svga_id != SVGA_ID_2) {
660 ret = -ENOSYS;
661 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
662 goto out_err0;
663 }
664
665 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
666 ret = vmw_dma_select_mode(dev_priv);
667 if (unlikely(ret != 0)) {
668 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
669 refuse_dma = true;
670 }
671
672 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
673 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
674 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
675 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
676
677 vmw_get_initial_size(dev_priv);
678
679 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
680 dev_priv->max_gmr_ids =
681 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
682 dev_priv->max_gmr_pages =
683 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
684 dev_priv->memory_size =
685 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
686 dev_priv->memory_size -= dev_priv->vram_size;
687 } else {
688 /*
689 * An arbitrary limit of 512MiB on surface
690 * memory. But all HWV8 hardware supports GMR2.
691 */
692 dev_priv->memory_size = 512*1024*1024;
693 }
694 dev_priv->max_mob_pages = 0;
695 dev_priv->max_mob_size = 0;
696 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
697 uint64_t mem_size =
698 vmw_read(dev_priv,
699 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
700
701 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
702 dev_priv->prim_bb_mem =
703 vmw_read(dev_priv,
704 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
705 dev_priv->max_mob_size =
706 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
707 dev_priv->stdu_max_width =
708 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
709 dev_priv->stdu_max_height =
710 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
711
712 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
713 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
714 dev_priv->texture_max_width = vmw_read(dev_priv,
715 SVGA_REG_DEV_CAP);
716 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
717 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
718 dev_priv->texture_max_height = vmw_read(dev_priv,
719 SVGA_REG_DEV_CAP);
720 } else {
721 dev_priv->texture_max_width = 8192;
722 dev_priv->texture_max_height = 8192;
723 dev_priv->prim_bb_mem = dev_priv->vram_size;
724 }
725
726 vmw_print_capabilities(dev_priv->capabilities);
727
728 ret = vmw_dma_masks(dev_priv);
729 if (unlikely(ret != 0))
730 goto out_err0;
731
732 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
733 DRM_INFO("Max GMR ids is %u\n",
734 (unsigned)dev_priv->max_gmr_ids);
735 DRM_INFO("Max number of GMR pages is %u\n",
736 (unsigned)dev_priv->max_gmr_pages);
737 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
738 (unsigned)dev_priv->memory_size / 1024);
739 }
740 DRM_INFO("Maximum display memory size is %u kiB\n",
741 dev_priv->prim_bb_mem / 1024);
742 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
743 dev_priv->vram_start, dev_priv->vram_size / 1024);
744 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
745 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
746
747 ret = vmw_ttm_global_init(dev_priv);
748 if (unlikely(ret != 0))
749 goto out_err0;
750
751
752 vmw_master_init(&dev_priv->fbdev_master);
753 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
754 dev_priv->active_master = &dev_priv->fbdev_master;
755
756 dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
757 dev_priv->mmio_size, MEMREMAP_WB);
758
759 if (unlikely(dev_priv->mmio_virt == NULL)) {
760 ret = -ENOMEM;
761 DRM_ERROR("Failed mapping MMIO.\n");
762 goto out_err3;
763 }
764
765 /* Need mmio memory to check for fifo pitchlock cap. */
766 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
767 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
768 !vmw_fifo_have_pitchlock(dev_priv)) {
769 ret = -ENOSYS;
770 DRM_ERROR("Hardware has no pitchlock\n");
771 goto out_err4;
772 }
773
774 dev_priv->tdev = ttm_object_device_init
775 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
776
777 if (unlikely(dev_priv->tdev == NULL)) {
778 DRM_ERROR("Unable to initialize TTM object management.\n");
779 ret = -ENOMEM;
780 goto out_err4;
781 }
782
783 dev->dev_private = dev_priv;
784
785 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
786 dev_priv->stealth = (ret != 0);
787 if (dev_priv->stealth) {
788 /**
789 * Request at least the mmio PCI resource.
790 */
791
792 DRM_INFO("It appears like vesafb is loaded. "
793 "Ignore above error if any.\n");
794 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
795 if (unlikely(ret != 0)) {
796 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
797 goto out_no_device;
798 }
799 }
800
801 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
802 ret = drm_irq_install(dev, dev->pdev->irq);
803 if (ret != 0) {
804 DRM_ERROR("Failed installing irq: %d\n", ret);
805 goto out_no_irq;
806 }
807 }
808
809 dev_priv->fman = vmw_fence_manager_init(dev_priv);
810 if (unlikely(dev_priv->fman == NULL)) {
811 ret = -ENOMEM;
812 goto out_no_fman;
813 }
814
815 ret = ttm_bo_device_init(&dev_priv->bdev,
816 dev_priv->bo_global_ref.ref.object,
817 &vmw_bo_driver,
818 dev->anon_inode->i_mapping,
819 VMWGFX_FILE_PAGE_OFFSET,
820 false);
821 if (unlikely(ret != 0)) {
822 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
823 goto out_no_bdev;
824 }
825
826 /*
827 * Enable VRAM, but initially don't use it until SVGA is enabled and
828 * unhidden.
829 */
830 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
831 (dev_priv->vram_size >> PAGE_SHIFT));
832 if (unlikely(ret != 0)) {
833 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
834 goto out_no_vram;
835 }
836 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
837
838 dev_priv->has_gmr = true;
839 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
840 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
841 VMW_PL_GMR) != 0) {
842 DRM_INFO("No GMR memory available. "
843 "Graphics memory resources are very limited.\n");
844 dev_priv->has_gmr = false;
845 }
846
847 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
848 dev_priv->has_mob = true;
849 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
850 VMW_PL_MOB) != 0) {
851 DRM_INFO("No MOB memory available. "
852 "3D will be disabled.\n");
853 dev_priv->has_mob = false;
854 }
855 }
856
857 if (dev_priv->has_mob) {
858 spin_lock(&dev_priv->cap_lock);
859 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
860 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
861 spin_unlock(&dev_priv->cap_lock);
862 }
863
864
865 ret = vmw_kms_init(dev_priv);
866 if (unlikely(ret != 0))
867 goto out_no_kms;
868 vmw_overlay_init(dev_priv);
869
870 ret = vmw_request_device(dev_priv);
871 if (ret)
872 goto out_no_fifo;
873
874 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
875
876 if (dev_priv->enable_fb) {
877 vmw_fifo_resource_inc(dev_priv);
878 vmw_svga_enable(dev_priv);
879 vmw_fb_init(dev_priv);
880 }
881
882 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
883 register_pm_notifier(&dev_priv->pm_nb);
884
885 return 0;
886
887out_no_fifo:
888 vmw_overlay_close(dev_priv);
889 vmw_kms_close(dev_priv);
890out_no_kms:
891 if (dev_priv->has_mob)
892 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
893 if (dev_priv->has_gmr)
894 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
895 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
896out_no_vram:
897 (void)ttm_bo_device_release(&dev_priv->bdev);
898out_no_bdev:
899 vmw_fence_manager_takedown(dev_priv->fman);
900out_no_fman:
901 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
902 drm_irq_uninstall(dev_priv->dev);
903out_no_irq:
904 if (dev_priv->stealth)
905 pci_release_region(dev->pdev, 2);
906 else
907 pci_release_regions(dev->pdev);
908out_no_device:
909 ttm_object_device_release(&dev_priv->tdev);
910out_err4:
911 memunmap(dev_priv->mmio_virt);
912out_err3:
913 vmw_ttm_global_release(dev_priv);
914out_err0:
915 for (i = vmw_res_context; i < vmw_res_max; ++i)
916 idr_destroy(&dev_priv->res_idr[i]);
917
918 if (dev_priv->ctx.staged_bindings)
919 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
920 kfree(dev_priv);
921 return ret;
922}
923
924static int vmw_driver_unload(struct drm_device *dev)
925{
926 struct vmw_private *dev_priv = vmw_priv(dev);
927 enum vmw_res_type i;
928
929 unregister_pm_notifier(&dev_priv->pm_nb);
930
931 if (dev_priv->ctx.res_ht_initialized)
932 drm_ht_remove(&dev_priv->ctx.res_ht);
933 vfree(dev_priv->ctx.cmd_bounce);
934 if (dev_priv->enable_fb) {
935 vmw_fb_off(dev_priv);
936 vmw_fb_close(dev_priv);
937 vmw_fifo_resource_dec(dev_priv);
938 vmw_svga_disable(dev_priv);
939 }
940
941 vmw_kms_close(dev_priv);
942 vmw_overlay_close(dev_priv);
943
944 if (dev_priv->has_gmr)
945 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
946 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
947
948 vmw_release_device_early(dev_priv);
949 if (dev_priv->has_mob)
950 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
951 (void) ttm_bo_device_release(&dev_priv->bdev);
952 vmw_release_device_late(dev_priv);
953 vmw_fence_manager_takedown(dev_priv->fman);
954 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
955 drm_irq_uninstall(dev_priv->dev);
956 if (dev_priv->stealth)
957 pci_release_region(dev->pdev, 2);
958 else
959 pci_release_regions(dev->pdev);
960
961 ttm_object_device_release(&dev_priv->tdev);
962 memunmap(dev_priv->mmio_virt);
963 if (dev_priv->ctx.staged_bindings)
964 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
965 vmw_ttm_global_release(dev_priv);
966
967 for (i = vmw_res_context; i < vmw_res_max; ++i)
968 idr_destroy(&dev_priv->res_idr[i]);
969
970 kfree(dev_priv);
971
972 return 0;
973}
974
975static void vmw_postclose(struct drm_device *dev,
976 struct drm_file *file_priv)
977{
978 struct vmw_fpriv *vmw_fp;
979
980 vmw_fp = vmw_fpriv(file_priv);
981
982 if (vmw_fp->locked_master) {
983 struct vmw_master *vmaster =
984 vmw_master(vmw_fp->locked_master);
985
986 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
987 ttm_vt_unlock(&vmaster->lock);
988 drm_master_put(&vmw_fp->locked_master);
989 }
990
991 ttm_object_file_release(&vmw_fp->tfile);
992 kfree(vmw_fp);
993}
994
995static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
996{
997 struct vmw_private *dev_priv = vmw_priv(dev);
998 struct vmw_fpriv *vmw_fp;
999 int ret = -ENOMEM;
1000
1001 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1002 if (unlikely(vmw_fp == NULL))
1003 return ret;
1004
1005 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1006 if (unlikely(vmw_fp->tfile == NULL))
1007 goto out_no_tfile;
1008
1009 file_priv->driver_priv = vmw_fp;
1010
1011 return 0;
1012
1013out_no_tfile:
1014 kfree(vmw_fp);
1015 return ret;
1016}
1017
1018static struct vmw_master *vmw_master_check(struct drm_device *dev,
1019 struct drm_file *file_priv,
1020 unsigned int flags)
1021{
1022 int ret;
1023 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1024 struct vmw_master *vmaster;
1025
1026 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
1027 !(flags & DRM_AUTH))
1028 return NULL;
1029
1030 ret = mutex_lock_interruptible(&dev->master_mutex);
1031 if (unlikely(ret != 0))
1032 return ERR_PTR(-ERESTARTSYS);
1033
1034 if (file_priv->is_master) {
1035 mutex_unlock(&dev->master_mutex);
1036 return NULL;
1037 }
1038
1039 /*
1040 * Check if we were previously master, but now dropped. In that
1041 * case, allow at least render node functionality.
1042 */
1043 if (vmw_fp->locked_master) {
1044 mutex_unlock(&dev->master_mutex);
1045
1046 if (flags & DRM_RENDER_ALLOW)
1047 return NULL;
1048
1049 DRM_ERROR("Dropped master trying to access ioctl that "
1050 "requires authentication.\n");
1051 return ERR_PTR(-EACCES);
1052 }
1053 mutex_unlock(&dev->master_mutex);
1054
1055 /*
1056 * Take the TTM lock. Possibly sleep waiting for the authenticating
1057 * master to become master again, or for a SIGTERM if the
1058 * authenticating master exits.
1059 */
1060 vmaster = vmw_master(file_priv->master);
1061 ret = ttm_read_lock(&vmaster->lock, true);
1062 if (unlikely(ret != 0))
1063 vmaster = ERR_PTR(ret);
1064
1065 return vmaster;
1066}
1067
1068static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1069 unsigned long arg,
1070 long (*ioctl_func)(struct file *, unsigned int,
1071 unsigned long))
1072{
1073 struct drm_file *file_priv = filp->private_data;
1074 struct drm_device *dev = file_priv->minor->dev;
1075 unsigned int nr = DRM_IOCTL_NR(cmd);
1076 struct vmw_master *vmaster;
1077 unsigned int flags;
1078 long ret;
1079
1080 /*
1081 * Do extra checking on driver private ioctls.
1082 */
1083
1084 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1085 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1086 const struct drm_ioctl_desc *ioctl =
1087 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1088
1089 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1090 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1091 if (unlikely(ret != 0))
1092 return ret;
1093
1094 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1095 goto out_io_encoding;
1096
1097 return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1098 _IOC_SIZE(cmd));
1099 }
1100
1101 if (unlikely(ioctl->cmd != cmd))
1102 goto out_io_encoding;
1103
1104 flags = ioctl->flags;
1105 } else if (!drm_ioctl_flags(nr, &flags))
1106 return -EINVAL;
1107
1108 vmaster = vmw_master_check(dev, file_priv, flags);
1109 if (IS_ERR(vmaster)) {
1110 ret = PTR_ERR(vmaster);
1111
1112 if (ret != -ERESTARTSYS)
1113 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1114 nr, ret);
1115 return ret;
1116 }
1117
1118 ret = ioctl_func(filp, cmd, arg);
1119 if (vmaster)
1120 ttm_read_unlock(&vmaster->lock);
1121
1122 return ret;
1123
1124out_io_encoding:
1125 DRM_ERROR("Invalid command format, ioctl %d\n",
1126 nr - DRM_COMMAND_BASE);
1127
1128 return -EINVAL;
1129}
1130
1131static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1132 unsigned long arg)
1133{
1134 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1135}
1136
1137#ifdef CONFIG_COMPAT
1138static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1139 unsigned long arg)
1140{
1141 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1142}
1143#endif
1144
1145static void vmw_lastclose(struct drm_device *dev)
1146{
1147}
1148
1149static void vmw_master_init(struct vmw_master *vmaster)
1150{
1151 ttm_lock_init(&vmaster->lock);
1152}
1153
1154static int vmw_master_create(struct drm_device *dev,
1155 struct drm_master *master)
1156{
1157 struct vmw_master *vmaster;
1158
1159 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1160 if (unlikely(vmaster == NULL))
1161 return -ENOMEM;
1162
1163 vmw_master_init(vmaster);
1164 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1165 master->driver_priv = vmaster;
1166
1167 return 0;
1168}
1169
1170static void vmw_master_destroy(struct drm_device *dev,
1171 struct drm_master *master)
1172{
1173 struct vmw_master *vmaster = vmw_master(master);
1174
1175 master->driver_priv = NULL;
1176 kfree(vmaster);
1177}
1178
1179static int vmw_master_set(struct drm_device *dev,
1180 struct drm_file *file_priv,
1181 bool from_open)
1182{
1183 struct vmw_private *dev_priv = vmw_priv(dev);
1184 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1185 struct vmw_master *active = dev_priv->active_master;
1186 struct vmw_master *vmaster = vmw_master(file_priv->master);
1187 int ret = 0;
1188
1189 if (active) {
1190 BUG_ON(active != &dev_priv->fbdev_master);
1191 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1192 if (unlikely(ret != 0))
1193 return ret;
1194
1195 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1196 dev_priv->active_master = NULL;
1197 }
1198
1199 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1200 if (!from_open) {
1201 ttm_vt_unlock(&vmaster->lock);
1202 BUG_ON(vmw_fp->locked_master != file_priv->master);
1203 drm_master_put(&vmw_fp->locked_master);
1204 }
1205
1206 dev_priv->active_master = vmaster;
1207 drm_sysfs_hotplug_event(dev);
1208
1209 return 0;
1210}
1211
1212static void vmw_master_drop(struct drm_device *dev,
1213 struct drm_file *file_priv,
1214 bool from_release)
1215{
1216 struct vmw_private *dev_priv = vmw_priv(dev);
1217 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1218 struct vmw_master *vmaster = vmw_master(file_priv->master);
1219 int ret;
1220
1221 /**
1222 * Make sure the master doesn't disappear while we have
1223 * it locked.
1224 */
1225
1226 vmw_fp->locked_master = drm_master_get(file_priv->master);
1227 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1228 vmw_kms_legacy_hotspot_clear(dev_priv);
1229 if (unlikely((ret != 0))) {
1230 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1231 drm_master_put(&vmw_fp->locked_master);
1232 }
1233
1234 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1235
1236 if (!dev_priv->enable_fb)
1237 vmw_svga_disable(dev_priv);
1238
1239 dev_priv->active_master = &dev_priv->fbdev_master;
1240 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1241 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1242
1243 if (dev_priv->enable_fb)
1244 vmw_fb_on(dev_priv);
1245}
1246
1247/**
1248 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1249 *
1250 * @dev_priv: Pointer to device private struct.
1251 * Needs the reservation sem to be held in non-exclusive mode.
1252 */
1253static void __vmw_svga_enable(struct vmw_private *dev_priv)
1254{
1255 spin_lock(&dev_priv->svga_lock);
1256 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1257 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1258 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1259 }
1260 spin_unlock(&dev_priv->svga_lock);
1261}
1262
1263/**
1264 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1265 *
1266 * @dev_priv: Pointer to device private struct.
1267 */
1268void vmw_svga_enable(struct vmw_private *dev_priv)
1269{
1270 ttm_read_lock(&dev_priv->reservation_sem, false);
1271 __vmw_svga_enable(dev_priv);
1272 ttm_read_unlock(&dev_priv->reservation_sem);
1273}
1274
1275/**
1276 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1277 *
1278 * @dev_priv: Pointer to device private struct.
1279 * Needs the reservation sem to be held in exclusive mode.
1280 * Will not empty VRAM. VRAM must be emptied by caller.
1281 */
1282static void __vmw_svga_disable(struct vmw_private *dev_priv)
1283{
1284 spin_lock(&dev_priv->svga_lock);
1285 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1286 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1287 vmw_write(dev_priv, SVGA_REG_ENABLE,
1288 SVGA_REG_ENABLE_HIDE |
1289 SVGA_REG_ENABLE_ENABLE);
1290 }
1291 spin_unlock(&dev_priv->svga_lock);
1292}
1293
1294/**
1295 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1296 * running.
1297 *
1298 * @dev_priv: Pointer to device private struct.
1299 * Will empty VRAM.
1300 */
1301void vmw_svga_disable(struct vmw_private *dev_priv)
1302{
1303 ttm_write_lock(&dev_priv->reservation_sem, false);
1304 spin_lock(&dev_priv->svga_lock);
1305 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1306 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1307 spin_unlock(&dev_priv->svga_lock);
1308 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1309 DRM_ERROR("Failed evicting VRAM buffers.\n");
1310 vmw_write(dev_priv, SVGA_REG_ENABLE,
1311 SVGA_REG_ENABLE_HIDE |
1312 SVGA_REG_ENABLE_ENABLE);
1313 } else
1314 spin_unlock(&dev_priv->svga_lock);
1315 ttm_write_unlock(&dev_priv->reservation_sem);
1316}
1317
1318static void vmw_remove(struct pci_dev *pdev)
1319{
1320 struct drm_device *dev = pci_get_drvdata(pdev);
1321
1322 pci_disable_device(pdev);
1323 drm_put_dev(dev);
1324}
1325
1326static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1327 void *ptr)
1328{
1329 struct vmw_private *dev_priv =
1330 container_of(nb, struct vmw_private, pm_nb);
1331
1332 switch (val) {
1333 case PM_HIBERNATION_PREPARE:
1334 if (dev_priv->enable_fb)
1335 vmw_fb_off(dev_priv);
1336 ttm_suspend_lock(&dev_priv->reservation_sem);
1337
1338 /*
1339 * This empties VRAM and unbinds all GMR bindings.
1340 * Buffer contents is moved to swappable memory.
1341 */
1342 vmw_execbuf_release_pinned_bo(dev_priv);
1343 vmw_resource_evict_all(dev_priv);
1344 vmw_release_device_early(dev_priv);
1345 ttm_bo_swapout_all(&dev_priv->bdev);
1346 vmw_fence_fifo_down(dev_priv->fman);
1347 break;
1348 case PM_POST_HIBERNATION:
1349 case PM_POST_RESTORE:
1350 vmw_fence_fifo_up(dev_priv->fman);
1351 ttm_suspend_unlock(&dev_priv->reservation_sem);
1352 if (dev_priv->enable_fb)
1353 vmw_fb_on(dev_priv);
1354 break;
1355 case PM_RESTORE_PREPARE:
1356 break;
1357 default:
1358 break;
1359 }
1360 return 0;
1361}
1362
1363static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1364{
1365 struct drm_device *dev = pci_get_drvdata(pdev);
1366 struct vmw_private *dev_priv = vmw_priv(dev);
1367
1368 if (dev_priv->refuse_hibernation)
1369 return -EBUSY;
1370
1371 pci_save_state(pdev);
1372 pci_disable_device(pdev);
1373 pci_set_power_state(pdev, PCI_D3hot);
1374 return 0;
1375}
1376
1377static int vmw_pci_resume(struct pci_dev *pdev)
1378{
1379 pci_set_power_state(pdev, PCI_D0);
1380 pci_restore_state(pdev);
1381 return pci_enable_device(pdev);
1382}
1383
1384static int vmw_pm_suspend(struct device *kdev)
1385{
1386 struct pci_dev *pdev = to_pci_dev(kdev);
1387 struct pm_message dummy;
1388
1389 dummy.event = 0;
1390
1391 return vmw_pci_suspend(pdev, dummy);
1392}
1393
1394static int vmw_pm_resume(struct device *kdev)
1395{
1396 struct pci_dev *pdev = to_pci_dev(kdev);
1397
1398 return vmw_pci_resume(pdev);
1399}
1400
1401static int vmw_pm_freeze(struct device *kdev)
1402{
1403 struct pci_dev *pdev = to_pci_dev(kdev);
1404 struct drm_device *dev = pci_get_drvdata(pdev);
1405 struct vmw_private *dev_priv = vmw_priv(dev);
1406
1407 dev_priv->suspended = true;
1408 if (dev_priv->enable_fb)
1409 vmw_fifo_resource_dec(dev_priv);
1410
1411 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1412 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1413 if (dev_priv->enable_fb)
1414 vmw_fifo_resource_inc(dev_priv);
1415 WARN_ON(vmw_request_device_late(dev_priv));
1416 dev_priv->suspended = false;
1417 return -EBUSY;
1418 }
1419
1420 if (dev_priv->enable_fb)
1421 __vmw_svga_disable(dev_priv);
1422
1423 vmw_release_device_late(dev_priv);
1424
1425 return 0;
1426}
1427
1428static int vmw_pm_restore(struct device *kdev)
1429{
1430 struct pci_dev *pdev = to_pci_dev(kdev);
1431 struct drm_device *dev = pci_get_drvdata(pdev);
1432 struct vmw_private *dev_priv = vmw_priv(dev);
1433 int ret;
1434
1435 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1436 (void) vmw_read(dev_priv, SVGA_REG_ID);
1437
1438 if (dev_priv->enable_fb)
1439 vmw_fifo_resource_inc(dev_priv);
1440
1441 ret = vmw_request_device(dev_priv);
1442 if (ret)
1443 return ret;
1444
1445 if (dev_priv->enable_fb)
1446 __vmw_svga_enable(dev_priv);
1447
1448 dev_priv->suspended = false;
1449
1450 return 0;
1451}
1452
1453static const struct dev_pm_ops vmw_pm_ops = {
1454 .freeze = vmw_pm_freeze,
1455 .thaw = vmw_pm_restore,
1456 .restore = vmw_pm_restore,
1457 .suspend = vmw_pm_suspend,
1458 .resume = vmw_pm_resume,
1459};
1460
1461static const struct file_operations vmwgfx_driver_fops = {
1462 .owner = THIS_MODULE,
1463 .open = drm_open,
1464 .release = drm_release,
1465 .unlocked_ioctl = vmw_unlocked_ioctl,
1466 .mmap = vmw_mmap,
1467 .poll = vmw_fops_poll,
1468 .read = vmw_fops_read,
1469#if defined(CONFIG_COMPAT)
1470 .compat_ioctl = vmw_compat_ioctl,
1471#endif
1472 .llseek = noop_llseek,
1473};
1474
1475static struct drm_driver driver = {
1476 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1477 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
1478 .load = vmw_driver_load,
1479 .unload = vmw_driver_unload,
1480 .lastclose = vmw_lastclose,
1481 .irq_preinstall = vmw_irq_preinstall,
1482 .irq_postinstall = vmw_irq_postinstall,
1483 .irq_uninstall = vmw_irq_uninstall,
1484 .irq_handler = vmw_irq_handler,
1485 .get_vblank_counter = vmw_get_vblank_counter,
1486 .enable_vblank = vmw_enable_vblank,
1487 .disable_vblank = vmw_disable_vblank,
1488 .ioctls = vmw_ioctls,
1489 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1490 .master_create = vmw_master_create,
1491 .master_destroy = vmw_master_destroy,
1492 .master_set = vmw_master_set,
1493 .master_drop = vmw_master_drop,
1494 .open = vmw_driver_open,
1495 .postclose = vmw_postclose,
1496 .set_busid = drm_pci_set_busid,
1497
1498 .dumb_create = vmw_dumb_create,
1499 .dumb_map_offset = vmw_dumb_map_offset,
1500 .dumb_destroy = vmw_dumb_destroy,
1501
1502 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1503 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1504
1505 .fops = &vmwgfx_driver_fops,
1506 .name = VMWGFX_DRIVER_NAME,
1507 .desc = VMWGFX_DRIVER_DESC,
1508 .date = VMWGFX_DRIVER_DATE,
1509 .major = VMWGFX_DRIVER_MAJOR,
1510 .minor = VMWGFX_DRIVER_MINOR,
1511 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1512};
1513
1514static struct pci_driver vmw_pci_driver = {
1515 .name = VMWGFX_DRIVER_NAME,
1516 .id_table = vmw_pci_id_list,
1517 .probe = vmw_probe,
1518 .remove = vmw_remove,
1519 .driver = {
1520 .pm = &vmw_pm_ops
1521 }
1522};
1523
1524static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1525{
1526 return drm_get_pci_dev(pdev, ent, &driver);
1527}
1528
1529static int __init vmwgfx_init(void)
1530{
1531 int ret;
1532
1533#ifdef CONFIG_VGA_CONSOLE
1534 if (vgacon_text_force())
1535 return -EINVAL;
1536#endif
1537
1538 ret = drm_pci_init(&driver, &vmw_pci_driver);
1539 if (ret)
1540 DRM_ERROR("Failed initializing DRM.\n");
1541 return ret;
1542}
1543
1544static void __exit vmwgfx_exit(void)
1545{
1546 drm_pci_exit(&driver, &vmw_pci_driver);
1547}
1548
1549module_init(vmwgfx_init);
1550module_exit(vmwgfx_exit);
1551
1552MODULE_AUTHOR("VMware Inc. and others");
1553MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1554MODULE_LICENSE("GPL and additional rights");
1555MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1556 __stringify(VMWGFX_DRIVER_MINOR) "."
1557 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1558 "0");
1/**************************************************************************
2 *
3 * Copyright © 2009-2016 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27#include <linux/module.h>
28#include <linux/console.h>
29
30#include <drm/drmP.h>
31#include "vmwgfx_drv.h"
32#include "vmwgfx_binding.h"
33#include <drm/ttm/ttm_placement.h>
34#include <drm/ttm/ttm_bo_driver.h>
35#include <drm/ttm/ttm_object.h>
36#include <drm/ttm/ttm_module.h>
37#include <linux/dma_remapping.h>
38
39#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
40#define VMWGFX_CHIP_SVGAII 0
41#define VMW_FB_RESERVATION 0
42
43#define VMW_MIN_INITIAL_WIDTH 800
44#define VMW_MIN_INITIAL_HEIGHT 600
45
46#ifndef VMWGFX_GIT_VERSION
47#define VMWGFX_GIT_VERSION "Unknown"
48#endif
49
50#define VMWGFX_REPO "In Tree"
51
52
53/**
54 * Fully encoded drm commands. Might move to vmw_drm.h
55 */
56
57#define DRM_IOCTL_VMW_GET_PARAM \
58 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
59 struct drm_vmw_getparam_arg)
60#define DRM_IOCTL_VMW_ALLOC_DMABUF \
61 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
62 union drm_vmw_alloc_dmabuf_arg)
63#define DRM_IOCTL_VMW_UNREF_DMABUF \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
65 struct drm_vmw_unref_dmabuf_arg)
66#define DRM_IOCTL_VMW_CURSOR_BYPASS \
67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
68 struct drm_vmw_cursor_bypass_arg)
69
70#define DRM_IOCTL_VMW_CONTROL_STREAM \
71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
72 struct drm_vmw_control_stream_arg)
73#define DRM_IOCTL_VMW_CLAIM_STREAM \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
75 struct drm_vmw_stream_arg)
76#define DRM_IOCTL_VMW_UNREF_STREAM \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
78 struct drm_vmw_stream_arg)
79
80#define DRM_IOCTL_VMW_CREATE_CONTEXT \
81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
82 struct drm_vmw_context_arg)
83#define DRM_IOCTL_VMW_UNREF_CONTEXT \
84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
85 struct drm_vmw_context_arg)
86#define DRM_IOCTL_VMW_CREATE_SURFACE \
87 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
88 union drm_vmw_surface_create_arg)
89#define DRM_IOCTL_VMW_UNREF_SURFACE \
90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
91 struct drm_vmw_surface_arg)
92#define DRM_IOCTL_VMW_REF_SURFACE \
93 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
94 union drm_vmw_surface_reference_arg)
95#define DRM_IOCTL_VMW_EXECBUF \
96 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
97 struct drm_vmw_execbuf_arg)
98#define DRM_IOCTL_VMW_GET_3D_CAP \
99 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
100 struct drm_vmw_get_3d_cap_arg)
101#define DRM_IOCTL_VMW_FENCE_WAIT \
102 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
103 struct drm_vmw_fence_wait_arg)
104#define DRM_IOCTL_VMW_FENCE_SIGNALED \
105 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
106 struct drm_vmw_fence_signaled_arg)
107#define DRM_IOCTL_VMW_FENCE_UNREF \
108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
109 struct drm_vmw_fence_arg)
110#define DRM_IOCTL_VMW_FENCE_EVENT \
111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
112 struct drm_vmw_fence_event_arg)
113#define DRM_IOCTL_VMW_PRESENT \
114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
115 struct drm_vmw_present_arg)
116#define DRM_IOCTL_VMW_PRESENT_READBACK \
117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
118 struct drm_vmw_present_readback_arg)
119#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
121 struct drm_vmw_update_layout_arg)
122#define DRM_IOCTL_VMW_CREATE_SHADER \
123 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
124 struct drm_vmw_shader_create_arg)
125#define DRM_IOCTL_VMW_UNREF_SHADER \
126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
127 struct drm_vmw_shader_arg)
128#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
129 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
130 union drm_vmw_gb_surface_create_arg)
131#define DRM_IOCTL_VMW_GB_SURFACE_REF \
132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
133 union drm_vmw_gb_surface_reference_arg)
134#define DRM_IOCTL_VMW_SYNCCPU \
135 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
136 struct drm_vmw_synccpu_arg)
137#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
138 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
139 struct drm_vmw_context_arg)
140
141/**
142 * The core DRM version of this macro doesn't account for
143 * DRM_COMMAND_BASE.
144 */
145
146#define VMW_IOCTL_DEF(ioctl, func, flags) \
147 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
148
149/**
150 * Ioctl definitions.
151 */
152
153static const struct drm_ioctl_desc vmw_ioctls[] = {
154 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
155 DRM_AUTH | DRM_RENDER_ALLOW),
156 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
157 DRM_AUTH | DRM_RENDER_ALLOW),
158 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
159 DRM_RENDER_ALLOW),
160 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
161 vmw_kms_cursor_bypass_ioctl,
162 DRM_MASTER | DRM_CONTROL_ALLOW),
163
164 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
165 DRM_MASTER | DRM_CONTROL_ALLOW),
166 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
167 DRM_MASTER | DRM_CONTROL_ALLOW),
168 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
169 DRM_MASTER | DRM_CONTROL_ALLOW),
170
171 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
172 DRM_AUTH | DRM_RENDER_ALLOW),
173 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
174 DRM_RENDER_ALLOW),
175 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
176 DRM_AUTH | DRM_RENDER_ALLOW),
177 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
178 DRM_RENDER_ALLOW),
179 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
180 DRM_AUTH | DRM_RENDER_ALLOW),
181 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
182 DRM_RENDER_ALLOW),
183 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
184 DRM_RENDER_ALLOW),
185 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
186 vmw_fence_obj_signaled_ioctl,
187 DRM_RENDER_ALLOW),
188 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
189 DRM_RENDER_ALLOW),
190 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
191 DRM_AUTH | DRM_RENDER_ALLOW),
192 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
193 DRM_AUTH | DRM_RENDER_ALLOW),
194
195 /* these allow direct access to the framebuffers mark as master only */
196 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
197 DRM_MASTER | DRM_AUTH),
198 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
199 vmw_present_readback_ioctl,
200 DRM_MASTER | DRM_AUTH),
201 /*
202 * The permissions of the below ioctl are overridden in
203 * vmw_generic_ioctl(). We require either
204 * DRM_MASTER or capable(CAP_SYS_ADMIN).
205 */
206 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
207 vmw_kms_update_layout_ioctl,
208 DRM_RENDER_ALLOW),
209 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
210 vmw_shader_define_ioctl,
211 DRM_AUTH | DRM_RENDER_ALLOW),
212 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
213 vmw_shader_destroy_ioctl,
214 DRM_RENDER_ALLOW),
215 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
216 vmw_gb_surface_define_ioctl,
217 DRM_AUTH | DRM_RENDER_ALLOW),
218 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
219 vmw_gb_surface_reference_ioctl,
220 DRM_AUTH | DRM_RENDER_ALLOW),
221 VMW_IOCTL_DEF(VMW_SYNCCPU,
222 vmw_user_dmabuf_synccpu_ioctl,
223 DRM_RENDER_ALLOW),
224 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
225 vmw_extended_context_define_ioctl,
226 DRM_AUTH | DRM_RENDER_ALLOW),
227};
228
229static const struct pci_device_id vmw_pci_id_list[] = {
230 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
231 {0, 0, 0}
232};
233MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
234
235static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
236static int vmw_force_iommu;
237static int vmw_restrict_iommu;
238static int vmw_force_coherent;
239static int vmw_restrict_dma_mask;
240static int vmw_assume_16bpp;
241
242static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
243static void vmw_master_init(struct vmw_master *);
244static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
245 void *ptr);
246
247MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
248module_param_named(enable_fbdev, enable_fbdev, int, 0600);
249MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
250module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
251MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
252module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
253MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
254module_param_named(force_coherent, vmw_force_coherent, int, 0600);
255MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
256module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
257MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
258module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
259
260
261static void vmw_print_capabilities(uint32_t capabilities)
262{
263 DRM_INFO("Capabilities:\n");
264 if (capabilities & SVGA_CAP_RECT_COPY)
265 DRM_INFO(" Rect copy.\n");
266 if (capabilities & SVGA_CAP_CURSOR)
267 DRM_INFO(" Cursor.\n");
268 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
269 DRM_INFO(" Cursor bypass.\n");
270 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
271 DRM_INFO(" Cursor bypass 2.\n");
272 if (capabilities & SVGA_CAP_8BIT_EMULATION)
273 DRM_INFO(" 8bit emulation.\n");
274 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
275 DRM_INFO(" Alpha cursor.\n");
276 if (capabilities & SVGA_CAP_3D)
277 DRM_INFO(" 3D.\n");
278 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
279 DRM_INFO(" Extended Fifo.\n");
280 if (capabilities & SVGA_CAP_MULTIMON)
281 DRM_INFO(" Multimon.\n");
282 if (capabilities & SVGA_CAP_PITCHLOCK)
283 DRM_INFO(" Pitchlock.\n");
284 if (capabilities & SVGA_CAP_IRQMASK)
285 DRM_INFO(" Irq mask.\n");
286 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
287 DRM_INFO(" Display Topology.\n");
288 if (capabilities & SVGA_CAP_GMR)
289 DRM_INFO(" GMR.\n");
290 if (capabilities & SVGA_CAP_TRACES)
291 DRM_INFO(" Traces.\n");
292 if (capabilities & SVGA_CAP_GMR2)
293 DRM_INFO(" GMR2.\n");
294 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
295 DRM_INFO(" Screen Object 2.\n");
296 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
297 DRM_INFO(" Command Buffers.\n");
298 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
299 DRM_INFO(" Command Buffers 2.\n");
300 if (capabilities & SVGA_CAP_GBOBJECTS)
301 DRM_INFO(" Guest Backed Resources.\n");
302 if (capabilities & SVGA_CAP_DX)
303 DRM_INFO(" DX Features.\n");
304 if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
305 DRM_INFO(" HP Command Queue.\n");
306}
307
308/**
309 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
310 *
311 * @dev_priv: A device private structure.
312 *
313 * This function creates a small buffer object that holds the query
314 * result for dummy queries emitted as query barriers.
315 * The function will then map the first page and initialize a pending
316 * occlusion query result structure, Finally it will unmap the buffer.
317 * No interruptible waits are done within this function.
318 *
319 * Returns an error if bo creation or initialization fails.
320 */
321static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
322{
323 int ret;
324 struct vmw_dma_buffer *vbo;
325 struct ttm_bo_kmap_obj map;
326 volatile SVGA3dQueryResult *result;
327 bool dummy;
328
329 /*
330 * Create the vbo as pinned, so that a tryreserve will
331 * immediately succeed. This is because we're the only
332 * user of the bo currently.
333 */
334 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
335 if (!vbo)
336 return -ENOMEM;
337
338 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
339 &vmw_sys_ne_placement, false,
340 &vmw_dmabuf_bo_free);
341 if (unlikely(ret != 0))
342 return ret;
343
344 ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
345 BUG_ON(ret != 0);
346 vmw_bo_pin_reserved(vbo, true);
347
348 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
349 if (likely(ret == 0)) {
350 result = ttm_kmap_obj_virtual(&map, &dummy);
351 result->totalSize = sizeof(*result);
352 result->state = SVGA3D_QUERYSTATE_PENDING;
353 result->result32 = 0xff;
354 ttm_bo_kunmap(&map);
355 }
356 vmw_bo_pin_reserved(vbo, false);
357 ttm_bo_unreserve(&vbo->base);
358
359 if (unlikely(ret != 0)) {
360 DRM_ERROR("Dummy query buffer map failed.\n");
361 vmw_dmabuf_unreference(&vbo);
362 } else
363 dev_priv->dummy_query_bo = vbo;
364
365 return ret;
366}
367
368/**
369 * vmw_request_device_late - Perform late device setup
370 *
371 * @dev_priv: Pointer to device private.
372 *
373 * This function performs setup of otables and enables large command
374 * buffer submission. These tasks are split out to a separate function
375 * because it reverts vmw_release_device_early and is intended to be used
376 * by an error path in the hibernation code.
377 */
378static int vmw_request_device_late(struct vmw_private *dev_priv)
379{
380 int ret;
381
382 if (dev_priv->has_mob) {
383 ret = vmw_otables_setup(dev_priv);
384 if (unlikely(ret != 0)) {
385 DRM_ERROR("Unable to initialize "
386 "guest Memory OBjects.\n");
387 return ret;
388 }
389 }
390
391 if (dev_priv->cman) {
392 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
393 256*4096, 2*4096);
394 if (ret) {
395 struct vmw_cmdbuf_man *man = dev_priv->cman;
396
397 dev_priv->cman = NULL;
398 vmw_cmdbuf_man_destroy(man);
399 }
400 }
401
402 return 0;
403}
404
405static int vmw_request_device(struct vmw_private *dev_priv)
406{
407 int ret;
408
409 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
410 if (unlikely(ret != 0)) {
411 DRM_ERROR("Unable to initialize FIFO.\n");
412 return ret;
413 }
414 vmw_fence_fifo_up(dev_priv->fman);
415 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
416 if (IS_ERR(dev_priv->cman)) {
417 dev_priv->cman = NULL;
418 dev_priv->has_dx = false;
419 }
420
421 ret = vmw_request_device_late(dev_priv);
422 if (ret)
423 goto out_no_mob;
424
425 ret = vmw_dummy_query_bo_create(dev_priv);
426 if (unlikely(ret != 0))
427 goto out_no_query_bo;
428
429 return 0;
430
431out_no_query_bo:
432 if (dev_priv->cman)
433 vmw_cmdbuf_remove_pool(dev_priv->cman);
434 if (dev_priv->has_mob) {
435 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
436 vmw_otables_takedown(dev_priv);
437 }
438 if (dev_priv->cman)
439 vmw_cmdbuf_man_destroy(dev_priv->cman);
440out_no_mob:
441 vmw_fence_fifo_down(dev_priv->fman);
442 vmw_fifo_release(dev_priv, &dev_priv->fifo);
443 return ret;
444}
445
446/**
447 * vmw_release_device_early - Early part of fifo takedown.
448 *
449 * @dev_priv: Pointer to device private struct.
450 *
451 * This is the first part of command submission takedown, to be called before
452 * buffer management is taken down.
453 */
454static void vmw_release_device_early(struct vmw_private *dev_priv)
455{
456 /*
457 * Previous destructions should've released
458 * the pinned bo.
459 */
460
461 BUG_ON(dev_priv->pinned_bo != NULL);
462
463 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
464 if (dev_priv->cman)
465 vmw_cmdbuf_remove_pool(dev_priv->cman);
466
467 if (dev_priv->has_mob) {
468 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
469 vmw_otables_takedown(dev_priv);
470 }
471}
472
473/**
474 * vmw_release_device_late - Late part of fifo takedown.
475 *
476 * @dev_priv: Pointer to device private struct.
477 *
478 * This is the last part of the command submission takedown, to be called when
479 * command submission is no longer needed. It may wait on pending fences.
480 */
481static void vmw_release_device_late(struct vmw_private *dev_priv)
482{
483 vmw_fence_fifo_down(dev_priv->fman);
484 if (dev_priv->cman)
485 vmw_cmdbuf_man_destroy(dev_priv->cman);
486
487 vmw_fifo_release(dev_priv, &dev_priv->fifo);
488}
489
490/**
491 * Sets the initial_[width|height] fields on the given vmw_private.
492 *
493 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
494 * clamping the value to fb_max_[width|height] fields and the
495 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
496 * If the values appear to be invalid, set them to
497 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
498 */
499static void vmw_get_initial_size(struct vmw_private *dev_priv)
500{
501 uint32_t width;
502 uint32_t height;
503
504 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
505 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
506
507 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
508 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
509
510 if (width > dev_priv->fb_max_width ||
511 height > dev_priv->fb_max_height) {
512
513 /*
514 * This is a host error and shouldn't occur.
515 */
516
517 width = VMW_MIN_INITIAL_WIDTH;
518 height = VMW_MIN_INITIAL_HEIGHT;
519 }
520
521 dev_priv->initial_width = width;
522 dev_priv->initial_height = height;
523}
524
525/**
526 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
527 * system.
528 *
529 * @dev_priv: Pointer to a struct vmw_private
530 *
531 * This functions tries to determine the IOMMU setup and what actions
532 * need to be taken by the driver to make system pages visible to the
533 * device.
534 * If this function decides that DMA is not possible, it returns -EINVAL.
535 * The driver may then try to disable features of the device that require
536 * DMA.
537 */
538static int vmw_dma_select_mode(struct vmw_private *dev_priv)
539{
540 static const char *names[vmw_dma_map_max] = {
541 [vmw_dma_phys] = "Using physical TTM page addresses.",
542 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
543 [vmw_dma_map_populate] = "Keeping DMA mappings.",
544 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
545#ifdef CONFIG_X86
546 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
547
548#ifdef CONFIG_INTEL_IOMMU
549 if (intel_iommu_enabled) {
550 dev_priv->map_mode = vmw_dma_map_populate;
551 goto out_fixup;
552 }
553#endif
554
555 if (!(vmw_force_iommu || vmw_force_coherent)) {
556 dev_priv->map_mode = vmw_dma_phys;
557 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
558 return 0;
559 }
560
561 dev_priv->map_mode = vmw_dma_map_populate;
562
563 if (dma_ops->sync_single_for_cpu)
564 dev_priv->map_mode = vmw_dma_alloc_coherent;
565#ifdef CONFIG_SWIOTLB
566 if (swiotlb_nr_tbl() == 0)
567 dev_priv->map_mode = vmw_dma_map_populate;
568#endif
569
570#ifdef CONFIG_INTEL_IOMMU
571out_fixup:
572#endif
573 if (dev_priv->map_mode == vmw_dma_map_populate &&
574 vmw_restrict_iommu)
575 dev_priv->map_mode = vmw_dma_map_bind;
576
577 if (vmw_force_coherent)
578 dev_priv->map_mode = vmw_dma_alloc_coherent;
579
580#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
581 /*
582 * No coherent page pool
583 */
584 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
585 return -EINVAL;
586#endif
587
588#else /* CONFIG_X86 */
589 dev_priv->map_mode = vmw_dma_map_populate;
590#endif /* CONFIG_X86 */
591
592 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
593
594 return 0;
595}
596
597/**
598 * vmw_dma_masks - set required page- and dma masks
599 *
600 * @dev: Pointer to struct drm-device
601 *
602 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
603 * restriction also for 64-bit systems.
604 */
605#ifdef CONFIG_INTEL_IOMMU
606static int vmw_dma_masks(struct vmw_private *dev_priv)
607{
608 struct drm_device *dev = dev_priv->dev;
609
610 if (intel_iommu_enabled &&
611 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
612 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
613 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
614 }
615 return 0;
616}
617#else
618static int vmw_dma_masks(struct vmw_private *dev_priv)
619{
620 return 0;
621}
622#endif
623
624static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
625{
626 struct vmw_private *dev_priv;
627 int ret;
628 uint32_t svga_id;
629 enum vmw_res_type i;
630 bool refuse_dma = false;
631 char host_log[100] = {0};
632
633 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
634 if (unlikely(!dev_priv)) {
635 DRM_ERROR("Failed allocating a device private struct.\n");
636 return -ENOMEM;
637 }
638
639 pci_set_master(dev->pdev);
640
641 dev_priv->dev = dev;
642 dev_priv->vmw_chipset = chipset;
643 dev_priv->last_read_seqno = (uint32_t) -100;
644 mutex_init(&dev_priv->cmdbuf_mutex);
645 mutex_init(&dev_priv->release_mutex);
646 mutex_init(&dev_priv->binding_mutex);
647 mutex_init(&dev_priv->global_kms_state_mutex);
648 rwlock_init(&dev_priv->resource_lock);
649 ttm_lock_init(&dev_priv->reservation_sem);
650 spin_lock_init(&dev_priv->hw_lock);
651 spin_lock_init(&dev_priv->waiter_lock);
652 spin_lock_init(&dev_priv->cap_lock);
653 spin_lock_init(&dev_priv->svga_lock);
654 spin_lock_init(&dev_priv->cursor_lock);
655
656 for (i = vmw_res_context; i < vmw_res_max; ++i) {
657 idr_init(&dev_priv->res_idr[i]);
658 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
659 }
660
661 mutex_init(&dev_priv->init_mutex);
662 init_waitqueue_head(&dev_priv->fence_queue);
663 init_waitqueue_head(&dev_priv->fifo_queue);
664 dev_priv->fence_queue_waiters = 0;
665 dev_priv->fifo_queue_waiters = 0;
666
667 dev_priv->used_memory_size = 0;
668
669 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
670 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
671 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
672
673 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
674
675 dev_priv->enable_fb = enable_fbdev;
676
677 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
678 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
679 if (svga_id != SVGA_ID_2) {
680 ret = -ENOSYS;
681 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
682 goto out_err0;
683 }
684
685 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
686 ret = vmw_dma_select_mode(dev_priv);
687 if (unlikely(ret != 0)) {
688 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
689 refuse_dma = true;
690 }
691
692 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
693 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
694 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
695 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
696
697 vmw_get_initial_size(dev_priv);
698
699 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
700 dev_priv->max_gmr_ids =
701 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
702 dev_priv->max_gmr_pages =
703 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
704 dev_priv->memory_size =
705 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
706 dev_priv->memory_size -= dev_priv->vram_size;
707 } else {
708 /*
709 * An arbitrary limit of 512MiB on surface
710 * memory. But all HWV8 hardware supports GMR2.
711 */
712 dev_priv->memory_size = 512*1024*1024;
713 }
714 dev_priv->max_mob_pages = 0;
715 dev_priv->max_mob_size = 0;
716 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
717 uint64_t mem_size =
718 vmw_read(dev_priv,
719 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
720
721 /*
722 * Workaround for low memory 2D VMs to compensate for the
723 * allocation taken by fbdev
724 */
725 if (!(dev_priv->capabilities & SVGA_CAP_3D))
726 mem_size *= 3;
727
728 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
729 dev_priv->prim_bb_mem =
730 vmw_read(dev_priv,
731 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
732 dev_priv->max_mob_size =
733 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
734 dev_priv->stdu_max_width =
735 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
736 dev_priv->stdu_max_height =
737 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
738
739 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
740 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
741 dev_priv->texture_max_width = vmw_read(dev_priv,
742 SVGA_REG_DEV_CAP);
743 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
744 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
745 dev_priv->texture_max_height = vmw_read(dev_priv,
746 SVGA_REG_DEV_CAP);
747 } else {
748 dev_priv->texture_max_width = 8192;
749 dev_priv->texture_max_height = 8192;
750 dev_priv->prim_bb_mem = dev_priv->vram_size;
751 }
752
753 vmw_print_capabilities(dev_priv->capabilities);
754
755 ret = vmw_dma_masks(dev_priv);
756 if (unlikely(ret != 0))
757 goto out_err0;
758
759 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
760 DRM_INFO("Max GMR ids is %u\n",
761 (unsigned)dev_priv->max_gmr_ids);
762 DRM_INFO("Max number of GMR pages is %u\n",
763 (unsigned)dev_priv->max_gmr_pages);
764 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
765 (unsigned)dev_priv->memory_size / 1024);
766 }
767 DRM_INFO("Maximum display memory size is %u kiB\n",
768 dev_priv->prim_bb_mem / 1024);
769 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
770 dev_priv->vram_start, dev_priv->vram_size / 1024);
771 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
772 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
773
774 ret = vmw_ttm_global_init(dev_priv);
775 if (unlikely(ret != 0))
776 goto out_err0;
777
778
779 vmw_master_init(&dev_priv->fbdev_master);
780 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
781 dev_priv->active_master = &dev_priv->fbdev_master;
782
783 dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
784 dev_priv->mmio_size, MEMREMAP_WB);
785
786 if (unlikely(dev_priv->mmio_virt == NULL)) {
787 ret = -ENOMEM;
788 DRM_ERROR("Failed mapping MMIO.\n");
789 goto out_err3;
790 }
791
792 /* Need mmio memory to check for fifo pitchlock cap. */
793 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
794 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
795 !vmw_fifo_have_pitchlock(dev_priv)) {
796 ret = -ENOSYS;
797 DRM_ERROR("Hardware has no pitchlock\n");
798 goto out_err4;
799 }
800
801 dev_priv->tdev = ttm_object_device_init
802 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
803
804 if (unlikely(dev_priv->tdev == NULL)) {
805 DRM_ERROR("Unable to initialize TTM object management.\n");
806 ret = -ENOMEM;
807 goto out_err4;
808 }
809
810 dev->dev_private = dev_priv;
811
812 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
813 dev_priv->stealth = (ret != 0);
814 if (dev_priv->stealth) {
815 /**
816 * Request at least the mmio PCI resource.
817 */
818
819 DRM_INFO("It appears like vesafb is loaded. "
820 "Ignore above error if any.\n");
821 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
822 if (unlikely(ret != 0)) {
823 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
824 goto out_no_device;
825 }
826 }
827
828 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
829 ret = vmw_irq_install(dev, dev->pdev->irq);
830 if (ret != 0) {
831 DRM_ERROR("Failed installing irq: %d\n", ret);
832 goto out_no_irq;
833 }
834 }
835
836 dev_priv->fman = vmw_fence_manager_init(dev_priv);
837 if (unlikely(dev_priv->fman == NULL)) {
838 ret = -ENOMEM;
839 goto out_no_fman;
840 }
841
842 ret = ttm_bo_device_init(&dev_priv->bdev,
843 dev_priv->bo_global_ref.ref.object,
844 &vmw_bo_driver,
845 dev->anon_inode->i_mapping,
846 VMWGFX_FILE_PAGE_OFFSET,
847 false);
848 if (unlikely(ret != 0)) {
849 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
850 goto out_no_bdev;
851 }
852
853 /*
854 * Enable VRAM, but initially don't use it until SVGA is enabled and
855 * unhidden.
856 */
857 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
858 (dev_priv->vram_size >> PAGE_SHIFT));
859 if (unlikely(ret != 0)) {
860 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
861 goto out_no_vram;
862 }
863 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
864
865 dev_priv->has_gmr = true;
866 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
867 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
868 VMW_PL_GMR) != 0) {
869 DRM_INFO("No GMR memory available. "
870 "Graphics memory resources are very limited.\n");
871 dev_priv->has_gmr = false;
872 }
873
874 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
875 dev_priv->has_mob = true;
876 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
877 VMW_PL_MOB) != 0) {
878 DRM_INFO("No MOB memory available. "
879 "3D will be disabled.\n");
880 dev_priv->has_mob = false;
881 }
882 }
883
884 if (dev_priv->has_mob) {
885 spin_lock(&dev_priv->cap_lock);
886 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
887 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
888 spin_unlock(&dev_priv->cap_lock);
889 }
890
891
892 ret = vmw_kms_init(dev_priv);
893 if (unlikely(ret != 0))
894 goto out_no_kms;
895 vmw_overlay_init(dev_priv);
896
897 ret = vmw_request_device(dev_priv);
898 if (ret)
899 goto out_no_fifo;
900
901 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
902 DRM_INFO("Atomic: %s\n",
903 (dev->driver->driver_features & DRIVER_ATOMIC) ? "yes" : "no");
904
905 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
906 VMWGFX_REPO, VMWGFX_GIT_VERSION);
907 vmw_host_log(host_log);
908
909 memset(host_log, 0, sizeof(host_log));
910 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
911 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
912 VMWGFX_DRIVER_PATCHLEVEL);
913 vmw_host_log(host_log);
914
915 if (dev_priv->enable_fb) {
916 vmw_fifo_resource_inc(dev_priv);
917 vmw_svga_enable(dev_priv);
918 vmw_fb_init(dev_priv);
919 }
920
921 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
922 register_pm_notifier(&dev_priv->pm_nb);
923
924 return 0;
925
926out_no_fifo:
927 vmw_overlay_close(dev_priv);
928 vmw_kms_close(dev_priv);
929out_no_kms:
930 if (dev_priv->has_mob)
931 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
932 if (dev_priv->has_gmr)
933 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
934 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
935out_no_vram:
936 (void)ttm_bo_device_release(&dev_priv->bdev);
937out_no_bdev:
938 vmw_fence_manager_takedown(dev_priv->fman);
939out_no_fman:
940 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
941 vmw_irq_uninstall(dev_priv->dev);
942out_no_irq:
943 if (dev_priv->stealth)
944 pci_release_region(dev->pdev, 2);
945 else
946 pci_release_regions(dev->pdev);
947out_no_device:
948 ttm_object_device_release(&dev_priv->tdev);
949out_err4:
950 memunmap(dev_priv->mmio_virt);
951out_err3:
952 vmw_ttm_global_release(dev_priv);
953out_err0:
954 for (i = vmw_res_context; i < vmw_res_max; ++i)
955 idr_destroy(&dev_priv->res_idr[i]);
956
957 if (dev_priv->ctx.staged_bindings)
958 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
959 kfree(dev_priv);
960 return ret;
961}
962
963static void vmw_driver_unload(struct drm_device *dev)
964{
965 struct vmw_private *dev_priv = vmw_priv(dev);
966 enum vmw_res_type i;
967
968 unregister_pm_notifier(&dev_priv->pm_nb);
969
970 if (dev_priv->ctx.res_ht_initialized)
971 drm_ht_remove(&dev_priv->ctx.res_ht);
972 vfree(dev_priv->ctx.cmd_bounce);
973 if (dev_priv->enable_fb) {
974 vmw_fb_off(dev_priv);
975 vmw_fb_close(dev_priv);
976 vmw_fifo_resource_dec(dev_priv);
977 vmw_svga_disable(dev_priv);
978 }
979
980 vmw_kms_close(dev_priv);
981 vmw_overlay_close(dev_priv);
982
983 if (dev_priv->has_gmr)
984 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
985 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
986
987 vmw_release_device_early(dev_priv);
988 if (dev_priv->has_mob)
989 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
990 (void) ttm_bo_device_release(&dev_priv->bdev);
991 vmw_release_device_late(dev_priv);
992 vmw_fence_manager_takedown(dev_priv->fman);
993 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
994 vmw_irq_uninstall(dev_priv->dev);
995 if (dev_priv->stealth)
996 pci_release_region(dev->pdev, 2);
997 else
998 pci_release_regions(dev->pdev);
999
1000 ttm_object_device_release(&dev_priv->tdev);
1001 memunmap(dev_priv->mmio_virt);
1002 if (dev_priv->ctx.staged_bindings)
1003 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1004 vmw_ttm_global_release(dev_priv);
1005
1006 for (i = vmw_res_context; i < vmw_res_max; ++i)
1007 idr_destroy(&dev_priv->res_idr[i]);
1008
1009 kfree(dev_priv);
1010}
1011
1012static void vmw_postclose(struct drm_device *dev,
1013 struct drm_file *file_priv)
1014{
1015 struct vmw_fpriv *vmw_fp;
1016
1017 vmw_fp = vmw_fpriv(file_priv);
1018
1019 if (vmw_fp->locked_master) {
1020 struct vmw_master *vmaster =
1021 vmw_master(vmw_fp->locked_master);
1022
1023 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1024 ttm_vt_unlock(&vmaster->lock);
1025 drm_master_put(&vmw_fp->locked_master);
1026 }
1027
1028 ttm_object_file_release(&vmw_fp->tfile);
1029 kfree(vmw_fp);
1030}
1031
1032static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1033{
1034 struct vmw_private *dev_priv = vmw_priv(dev);
1035 struct vmw_fpriv *vmw_fp;
1036 int ret = -ENOMEM;
1037
1038 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1039 if (unlikely(!vmw_fp))
1040 return ret;
1041
1042 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1043 if (unlikely(vmw_fp->tfile == NULL))
1044 goto out_no_tfile;
1045
1046 file_priv->driver_priv = vmw_fp;
1047
1048 return 0;
1049
1050out_no_tfile:
1051 kfree(vmw_fp);
1052 return ret;
1053}
1054
1055static struct vmw_master *vmw_master_check(struct drm_device *dev,
1056 struct drm_file *file_priv,
1057 unsigned int flags)
1058{
1059 int ret;
1060 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1061 struct vmw_master *vmaster;
1062
1063 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH))
1064 return NULL;
1065
1066 ret = mutex_lock_interruptible(&dev->master_mutex);
1067 if (unlikely(ret != 0))
1068 return ERR_PTR(-ERESTARTSYS);
1069
1070 if (drm_is_current_master(file_priv)) {
1071 mutex_unlock(&dev->master_mutex);
1072 return NULL;
1073 }
1074
1075 /*
1076 * Check if we were previously master, but now dropped. In that
1077 * case, allow at least render node functionality.
1078 */
1079 if (vmw_fp->locked_master) {
1080 mutex_unlock(&dev->master_mutex);
1081
1082 if (flags & DRM_RENDER_ALLOW)
1083 return NULL;
1084
1085 DRM_ERROR("Dropped master trying to access ioctl that "
1086 "requires authentication.\n");
1087 return ERR_PTR(-EACCES);
1088 }
1089 mutex_unlock(&dev->master_mutex);
1090
1091 /*
1092 * Take the TTM lock. Possibly sleep waiting for the authenticating
1093 * master to become master again, or for a SIGTERM if the
1094 * authenticating master exits.
1095 */
1096 vmaster = vmw_master(file_priv->master);
1097 ret = ttm_read_lock(&vmaster->lock, true);
1098 if (unlikely(ret != 0))
1099 vmaster = ERR_PTR(ret);
1100
1101 return vmaster;
1102}
1103
1104static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1105 unsigned long arg,
1106 long (*ioctl_func)(struct file *, unsigned int,
1107 unsigned long))
1108{
1109 struct drm_file *file_priv = filp->private_data;
1110 struct drm_device *dev = file_priv->minor->dev;
1111 unsigned int nr = DRM_IOCTL_NR(cmd);
1112 struct vmw_master *vmaster;
1113 unsigned int flags;
1114 long ret;
1115
1116 /*
1117 * Do extra checking on driver private ioctls.
1118 */
1119
1120 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1121 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1122 const struct drm_ioctl_desc *ioctl =
1123 &vmw_ioctls[nr - DRM_COMMAND_BASE];
1124
1125 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1126 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1127 if (unlikely(ret != 0))
1128 return ret;
1129
1130 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1131 goto out_io_encoding;
1132
1133 return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1134 _IOC_SIZE(cmd));
1135 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1136 if (!drm_is_current_master(file_priv) &&
1137 !capable(CAP_SYS_ADMIN))
1138 return -EACCES;
1139 }
1140
1141 if (unlikely(ioctl->cmd != cmd))
1142 goto out_io_encoding;
1143
1144 flags = ioctl->flags;
1145 } else if (!drm_ioctl_flags(nr, &flags))
1146 return -EINVAL;
1147
1148 vmaster = vmw_master_check(dev, file_priv, flags);
1149 if (IS_ERR(vmaster)) {
1150 ret = PTR_ERR(vmaster);
1151
1152 if (ret != -ERESTARTSYS)
1153 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1154 nr, ret);
1155 return ret;
1156 }
1157
1158 ret = ioctl_func(filp, cmd, arg);
1159 if (vmaster)
1160 ttm_read_unlock(&vmaster->lock);
1161
1162 return ret;
1163
1164out_io_encoding:
1165 DRM_ERROR("Invalid command format, ioctl %d\n",
1166 nr - DRM_COMMAND_BASE);
1167
1168 return -EINVAL;
1169}
1170
1171static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1172 unsigned long arg)
1173{
1174 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1175}
1176
1177#ifdef CONFIG_COMPAT
1178static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1179 unsigned long arg)
1180{
1181 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1182}
1183#endif
1184
1185static void vmw_lastclose(struct drm_device *dev)
1186{
1187}
1188
1189static void vmw_master_init(struct vmw_master *vmaster)
1190{
1191 ttm_lock_init(&vmaster->lock);
1192}
1193
1194static int vmw_master_create(struct drm_device *dev,
1195 struct drm_master *master)
1196{
1197 struct vmw_master *vmaster;
1198
1199 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1200 if (unlikely(!vmaster))
1201 return -ENOMEM;
1202
1203 vmw_master_init(vmaster);
1204 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1205 master->driver_priv = vmaster;
1206
1207 return 0;
1208}
1209
1210static void vmw_master_destroy(struct drm_device *dev,
1211 struct drm_master *master)
1212{
1213 struct vmw_master *vmaster = vmw_master(master);
1214
1215 master->driver_priv = NULL;
1216 kfree(vmaster);
1217}
1218
1219static int vmw_master_set(struct drm_device *dev,
1220 struct drm_file *file_priv,
1221 bool from_open)
1222{
1223 struct vmw_private *dev_priv = vmw_priv(dev);
1224 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1225 struct vmw_master *active = dev_priv->active_master;
1226 struct vmw_master *vmaster = vmw_master(file_priv->master);
1227 int ret = 0;
1228
1229 if (active) {
1230 BUG_ON(active != &dev_priv->fbdev_master);
1231 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1232 if (unlikely(ret != 0))
1233 return ret;
1234
1235 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1236 dev_priv->active_master = NULL;
1237 }
1238
1239 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1240 if (!from_open) {
1241 ttm_vt_unlock(&vmaster->lock);
1242 BUG_ON(vmw_fp->locked_master != file_priv->master);
1243 drm_master_put(&vmw_fp->locked_master);
1244 }
1245
1246 dev_priv->active_master = vmaster;
1247 drm_sysfs_hotplug_event(dev);
1248
1249 return 0;
1250}
1251
1252static void vmw_master_drop(struct drm_device *dev,
1253 struct drm_file *file_priv)
1254{
1255 struct vmw_private *dev_priv = vmw_priv(dev);
1256 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1257 struct vmw_master *vmaster = vmw_master(file_priv->master);
1258 int ret;
1259
1260 /**
1261 * Make sure the master doesn't disappear while we have
1262 * it locked.
1263 */
1264
1265 vmw_fp->locked_master = drm_master_get(file_priv->master);
1266 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1267 vmw_kms_legacy_hotspot_clear(dev_priv);
1268 if (unlikely((ret != 0))) {
1269 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1270 drm_master_put(&vmw_fp->locked_master);
1271 }
1272
1273 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1274
1275 if (!dev_priv->enable_fb)
1276 vmw_svga_disable(dev_priv);
1277
1278 dev_priv->active_master = &dev_priv->fbdev_master;
1279 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1280 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1281}
1282
1283/**
1284 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1285 *
1286 * @dev_priv: Pointer to device private struct.
1287 * Needs the reservation sem to be held in non-exclusive mode.
1288 */
1289static void __vmw_svga_enable(struct vmw_private *dev_priv)
1290{
1291 spin_lock(&dev_priv->svga_lock);
1292 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1293 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1294 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1295 }
1296 spin_unlock(&dev_priv->svga_lock);
1297}
1298
1299/**
1300 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1301 *
1302 * @dev_priv: Pointer to device private struct.
1303 */
1304void vmw_svga_enable(struct vmw_private *dev_priv)
1305{
1306 (void) ttm_read_lock(&dev_priv->reservation_sem, false);
1307 __vmw_svga_enable(dev_priv);
1308 ttm_read_unlock(&dev_priv->reservation_sem);
1309}
1310
1311/**
1312 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1313 *
1314 * @dev_priv: Pointer to device private struct.
1315 * Needs the reservation sem to be held in exclusive mode.
1316 * Will not empty VRAM. VRAM must be emptied by caller.
1317 */
1318static void __vmw_svga_disable(struct vmw_private *dev_priv)
1319{
1320 spin_lock(&dev_priv->svga_lock);
1321 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1322 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1323 vmw_write(dev_priv, SVGA_REG_ENABLE,
1324 SVGA_REG_ENABLE_HIDE |
1325 SVGA_REG_ENABLE_ENABLE);
1326 }
1327 spin_unlock(&dev_priv->svga_lock);
1328}
1329
1330/**
1331 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1332 * running.
1333 *
1334 * @dev_priv: Pointer to device private struct.
1335 * Will empty VRAM.
1336 */
1337void vmw_svga_disable(struct vmw_private *dev_priv)
1338{
1339 /*
1340 * Disabling SVGA will turn off device modesetting capabilities, so
1341 * notify KMS about that so that it doesn't cache atomic state that
1342 * isn't valid anymore, for example crtcs turned on.
1343 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1344 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1345 * end up with lock order reversal. Thus, a master may actually perform
1346 * a new modeset just after we call vmw_kms_lost_device() and race with
1347 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1348 * to be inconsistent with the device, causing modesetting problems.
1349 *
1350 */
1351 vmw_kms_lost_device(dev_priv->dev);
1352 ttm_write_lock(&dev_priv->reservation_sem, false);
1353 spin_lock(&dev_priv->svga_lock);
1354 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1355 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1356 spin_unlock(&dev_priv->svga_lock);
1357 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1358 DRM_ERROR("Failed evicting VRAM buffers.\n");
1359 vmw_write(dev_priv, SVGA_REG_ENABLE,
1360 SVGA_REG_ENABLE_HIDE |
1361 SVGA_REG_ENABLE_ENABLE);
1362 } else
1363 spin_unlock(&dev_priv->svga_lock);
1364 ttm_write_unlock(&dev_priv->reservation_sem);
1365}
1366
1367static void vmw_remove(struct pci_dev *pdev)
1368{
1369 struct drm_device *dev = pci_get_drvdata(pdev);
1370
1371 pci_disable_device(pdev);
1372 drm_put_dev(dev);
1373}
1374
1375static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1376 void *ptr)
1377{
1378 struct vmw_private *dev_priv =
1379 container_of(nb, struct vmw_private, pm_nb);
1380
1381 switch (val) {
1382 case PM_HIBERNATION_PREPARE:
1383 /*
1384 * Take the reservation sem in write mode, which will make sure
1385 * there are no other processes holding a buffer object
1386 * reservation, meaning we should be able to evict all buffer
1387 * objects if needed.
1388 * Once user-space processes have been frozen, we can release
1389 * the lock again.
1390 */
1391 ttm_suspend_lock(&dev_priv->reservation_sem);
1392 dev_priv->suspend_locked = true;
1393 break;
1394 case PM_POST_HIBERNATION:
1395 case PM_POST_RESTORE:
1396 if (READ_ONCE(dev_priv->suspend_locked)) {
1397 dev_priv->suspend_locked = false;
1398 ttm_suspend_unlock(&dev_priv->reservation_sem);
1399 }
1400 break;
1401 default:
1402 break;
1403 }
1404 return 0;
1405}
1406
1407static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1408{
1409 struct drm_device *dev = pci_get_drvdata(pdev);
1410 struct vmw_private *dev_priv = vmw_priv(dev);
1411
1412 if (dev_priv->refuse_hibernation)
1413 return -EBUSY;
1414
1415 pci_save_state(pdev);
1416 pci_disable_device(pdev);
1417 pci_set_power_state(pdev, PCI_D3hot);
1418 return 0;
1419}
1420
1421static int vmw_pci_resume(struct pci_dev *pdev)
1422{
1423 pci_set_power_state(pdev, PCI_D0);
1424 pci_restore_state(pdev);
1425 return pci_enable_device(pdev);
1426}
1427
1428static int vmw_pm_suspend(struct device *kdev)
1429{
1430 struct pci_dev *pdev = to_pci_dev(kdev);
1431 struct pm_message dummy;
1432
1433 dummy.event = 0;
1434
1435 return vmw_pci_suspend(pdev, dummy);
1436}
1437
1438static int vmw_pm_resume(struct device *kdev)
1439{
1440 struct pci_dev *pdev = to_pci_dev(kdev);
1441
1442 return vmw_pci_resume(pdev);
1443}
1444
1445static int vmw_pm_freeze(struct device *kdev)
1446{
1447 struct pci_dev *pdev = to_pci_dev(kdev);
1448 struct drm_device *dev = pci_get_drvdata(pdev);
1449 struct vmw_private *dev_priv = vmw_priv(dev);
1450 int ret;
1451
1452 /*
1453 * Unlock for vmw_kms_suspend.
1454 * No user-space processes should be running now.
1455 */
1456 ttm_suspend_unlock(&dev_priv->reservation_sem);
1457 ret = vmw_kms_suspend(dev_priv->dev);
1458 if (ret) {
1459 ttm_suspend_lock(&dev_priv->reservation_sem);
1460 DRM_ERROR("Failed to freeze modesetting.\n");
1461 return ret;
1462 }
1463 if (dev_priv->enable_fb)
1464 vmw_fb_off(dev_priv);
1465
1466 ttm_suspend_lock(&dev_priv->reservation_sem);
1467 vmw_execbuf_release_pinned_bo(dev_priv);
1468 vmw_resource_evict_all(dev_priv);
1469 vmw_release_device_early(dev_priv);
1470 ttm_bo_swapout_all(&dev_priv->bdev);
1471 if (dev_priv->enable_fb)
1472 vmw_fifo_resource_dec(dev_priv);
1473 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1474 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1475 if (dev_priv->enable_fb)
1476 vmw_fifo_resource_inc(dev_priv);
1477 WARN_ON(vmw_request_device_late(dev_priv));
1478 dev_priv->suspend_locked = false;
1479 ttm_suspend_unlock(&dev_priv->reservation_sem);
1480 if (dev_priv->suspend_state)
1481 vmw_kms_resume(dev);
1482 if (dev_priv->enable_fb)
1483 vmw_fb_on(dev_priv);
1484 return -EBUSY;
1485 }
1486
1487 vmw_fence_fifo_down(dev_priv->fman);
1488 __vmw_svga_disable(dev_priv);
1489
1490 vmw_release_device_late(dev_priv);
1491 return 0;
1492}
1493
1494static int vmw_pm_restore(struct device *kdev)
1495{
1496 struct pci_dev *pdev = to_pci_dev(kdev);
1497 struct drm_device *dev = pci_get_drvdata(pdev);
1498 struct vmw_private *dev_priv = vmw_priv(dev);
1499 int ret;
1500
1501 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1502 (void) vmw_read(dev_priv, SVGA_REG_ID);
1503
1504 if (dev_priv->enable_fb)
1505 vmw_fifo_resource_inc(dev_priv);
1506
1507 ret = vmw_request_device(dev_priv);
1508 if (ret)
1509 return ret;
1510
1511 if (dev_priv->enable_fb)
1512 __vmw_svga_enable(dev_priv);
1513
1514 vmw_fence_fifo_up(dev_priv->fman);
1515 dev_priv->suspend_locked = false;
1516 ttm_suspend_unlock(&dev_priv->reservation_sem);
1517 if (dev_priv->suspend_state)
1518 vmw_kms_resume(dev_priv->dev);
1519
1520 if (dev_priv->enable_fb)
1521 vmw_fb_on(dev_priv);
1522
1523 return 0;
1524}
1525
1526static const struct dev_pm_ops vmw_pm_ops = {
1527 .freeze = vmw_pm_freeze,
1528 .thaw = vmw_pm_restore,
1529 .restore = vmw_pm_restore,
1530 .suspend = vmw_pm_suspend,
1531 .resume = vmw_pm_resume,
1532};
1533
1534static const struct file_operations vmwgfx_driver_fops = {
1535 .owner = THIS_MODULE,
1536 .open = drm_open,
1537 .release = drm_release,
1538 .unlocked_ioctl = vmw_unlocked_ioctl,
1539 .mmap = vmw_mmap,
1540 .poll = vmw_fops_poll,
1541 .read = vmw_fops_read,
1542#if defined(CONFIG_COMPAT)
1543 .compat_ioctl = vmw_compat_ioctl,
1544#endif
1545 .llseek = noop_llseek,
1546};
1547
1548static struct drm_driver driver = {
1549 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1550 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
1551 .load = vmw_driver_load,
1552 .unload = vmw_driver_unload,
1553 .lastclose = vmw_lastclose,
1554 .get_vblank_counter = vmw_get_vblank_counter,
1555 .enable_vblank = vmw_enable_vblank,
1556 .disable_vblank = vmw_disable_vblank,
1557 .ioctls = vmw_ioctls,
1558 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1559 .master_create = vmw_master_create,
1560 .master_destroy = vmw_master_destroy,
1561 .master_set = vmw_master_set,
1562 .master_drop = vmw_master_drop,
1563 .open = vmw_driver_open,
1564 .postclose = vmw_postclose,
1565
1566 .dumb_create = vmw_dumb_create,
1567 .dumb_map_offset = vmw_dumb_map_offset,
1568 .dumb_destroy = vmw_dumb_destroy,
1569
1570 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1571 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1572
1573 .fops = &vmwgfx_driver_fops,
1574 .name = VMWGFX_DRIVER_NAME,
1575 .desc = VMWGFX_DRIVER_DESC,
1576 .date = VMWGFX_DRIVER_DATE,
1577 .major = VMWGFX_DRIVER_MAJOR,
1578 .minor = VMWGFX_DRIVER_MINOR,
1579 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1580};
1581
1582static struct pci_driver vmw_pci_driver = {
1583 .name = VMWGFX_DRIVER_NAME,
1584 .id_table = vmw_pci_id_list,
1585 .probe = vmw_probe,
1586 .remove = vmw_remove,
1587 .driver = {
1588 .pm = &vmw_pm_ops
1589 }
1590};
1591
1592static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1593{
1594 return drm_get_pci_dev(pdev, ent, &driver);
1595}
1596
1597static int __init vmwgfx_init(void)
1598{
1599 int ret;
1600
1601 if (vgacon_text_force())
1602 return -EINVAL;
1603
1604 ret = pci_register_driver(&vmw_pci_driver);
1605 if (ret)
1606 DRM_ERROR("Failed initializing DRM.\n");
1607 return ret;
1608}
1609
1610static void __exit vmwgfx_exit(void)
1611{
1612 pci_unregister_driver(&vmw_pci_driver);
1613}
1614
1615module_init(vmwgfx_init);
1616module_exit(vmwgfx_exit);
1617
1618MODULE_AUTHOR("VMware Inc. and others");
1619MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1620MODULE_LICENSE("GPL and additional rights");
1621MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1622 __stringify(VMWGFX_DRIVER_MINOR) "."
1623 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1624 "0");