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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <linux/swiotlb.h>
32
33#include "nouveau_drm.h"
34#include "nouveau_dma.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40
41/*
42 * NV10-NV40 tiling helpers
43 */
44
45static void
46nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
47 u32 addr, u32 size, u32 pitch, u32 flags)
48{
49 struct nouveau_drm *drm = nouveau_drm(dev);
50 int i = reg - drm->tile.reg;
51 struct nvkm_device *device = nvxx_device(&drm->device);
52 struct nvkm_fb *fb = device->fb;
53 struct nvkm_fb_tile *tile = &fb->tile.region[i];
54
55 nouveau_fence_unref(®->fence);
56
57 if (tile->pitch)
58 nvkm_fb_tile_fini(fb, i, tile);
59
60 if (pitch)
61 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
62
63 nvkm_fb_tile_prog(fb, i, tile);
64}
65
66static struct nouveau_drm_tile *
67nv10_bo_get_tile_region(struct drm_device *dev, int i)
68{
69 struct nouveau_drm *drm = nouveau_drm(dev);
70 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
71
72 spin_lock(&drm->tile.lock);
73
74 if (!tile->used &&
75 (!tile->fence || nouveau_fence_done(tile->fence)))
76 tile->used = true;
77 else
78 tile = NULL;
79
80 spin_unlock(&drm->tile.lock);
81 return tile;
82}
83
84static void
85nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
86 struct fence *fence)
87{
88 struct nouveau_drm *drm = nouveau_drm(dev);
89
90 if (tile) {
91 spin_lock(&drm->tile.lock);
92 tile->fence = (struct nouveau_fence *)fence_get(fence);
93 tile->used = false;
94 spin_unlock(&drm->tile.lock);
95 }
96}
97
98static struct nouveau_drm_tile *
99nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
100 u32 size, u32 pitch, u32 flags)
101{
102 struct nouveau_drm *drm = nouveau_drm(dev);
103 struct nvkm_fb *fb = nvxx_fb(&drm->device);
104 struct nouveau_drm_tile *tile, *found = NULL;
105 int i;
106
107 for (i = 0; i < fb->tile.regions; i++) {
108 tile = nv10_bo_get_tile_region(dev, i);
109
110 if (pitch && !found) {
111 found = tile;
112 continue;
113
114 } else if (tile && fb->tile.region[i].pitch) {
115 /* Kill an unused tile region. */
116 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
117 }
118
119 nv10_bo_put_tile_region(dev, tile, NULL);
120 }
121
122 if (found)
123 nv10_bo_update_tile_region(dev, found, addr, size,
124 pitch, flags);
125 return found;
126}
127
128static void
129nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
130{
131 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
132 struct drm_device *dev = drm->dev;
133 struct nouveau_bo *nvbo = nouveau_bo(bo);
134
135 if (unlikely(nvbo->gem.filp))
136 DRM_ERROR("bo %p still attached to GEM object\n", bo);
137 WARN_ON(nvbo->pin_refcnt > 0);
138 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
139 kfree(nvbo);
140}
141
142static void
143nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
144 int *align, int *size)
145{
146 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
147 struct nvif_device *device = &drm->device;
148
149 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
150 if (nvbo->tile_mode) {
151 if (device->info.chipset >= 0x40) {
152 *align = 65536;
153 *size = roundup(*size, 64 * nvbo->tile_mode);
154
155 } else if (device->info.chipset >= 0x30) {
156 *align = 32768;
157 *size = roundup(*size, 64 * nvbo->tile_mode);
158
159 } else if (device->info.chipset >= 0x20) {
160 *align = 16384;
161 *size = roundup(*size, 64 * nvbo->tile_mode);
162
163 } else if (device->info.chipset >= 0x10) {
164 *align = 16384;
165 *size = roundup(*size, 32 * nvbo->tile_mode);
166 }
167 }
168 } else {
169 *size = roundup(*size, (1 << nvbo->page_shift));
170 *align = max((1 << nvbo->page_shift), *align);
171 }
172
173 *size = roundup(*size, PAGE_SIZE);
174}
175
176int
177nouveau_bo_new(struct drm_device *dev, int size, int align,
178 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
179 struct sg_table *sg, struct reservation_object *robj,
180 struct nouveau_bo **pnvbo)
181{
182 struct nouveau_drm *drm = nouveau_drm(dev);
183 struct nouveau_bo *nvbo;
184 size_t acc_size;
185 int ret;
186 int type = ttm_bo_type_device;
187 int lpg_shift = 12;
188 int max_size;
189
190 if (drm->client.vm)
191 lpg_shift = drm->client.vm->mmu->lpg_shift;
192 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
193
194 if (size <= 0 || size > max_size) {
195 NV_WARN(drm, "skipped size %x\n", (u32)size);
196 return -EINVAL;
197 }
198
199 if (sg)
200 type = ttm_bo_type_sg;
201
202 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
203 if (!nvbo)
204 return -ENOMEM;
205 INIT_LIST_HEAD(&nvbo->head);
206 INIT_LIST_HEAD(&nvbo->entry);
207 INIT_LIST_HEAD(&nvbo->vma_list);
208 nvbo->tile_mode = tile_mode;
209 nvbo->tile_flags = tile_flags;
210 nvbo->bo.bdev = &drm->ttm.bdev;
211
212 if (!nvxx_device(&drm->device)->func->cpu_coherent)
213 nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
214
215 nvbo->page_shift = 12;
216 if (drm->client.vm) {
217 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
218 nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
219 }
220
221 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
222 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
223 nouveau_bo_placement_set(nvbo, flags, 0);
224
225 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
226 sizeof(struct nouveau_bo));
227
228 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
229 type, &nvbo->placement,
230 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
231 robj, nouveau_bo_del_ttm);
232 if (ret) {
233 /* ttm will call nouveau_bo_del_ttm if it fails.. */
234 return ret;
235 }
236
237 *pnvbo = nvbo;
238 return 0;
239}
240
241static void
242set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
243{
244 *n = 0;
245
246 if (type & TTM_PL_FLAG_VRAM)
247 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
248 if (type & TTM_PL_FLAG_TT)
249 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
250 if (type & TTM_PL_FLAG_SYSTEM)
251 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
252}
253
254static void
255set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
256{
257 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
258 u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT;
259 unsigned i, fpfn, lpfn;
260
261 if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
262 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
263 nvbo->bo.mem.num_pages < vram_pages / 4) {
264 /*
265 * Make sure that the color and depth buffers are handled
266 * by independent memory controller units. Up to a 9x
267 * speed up when alpha-blending and depth-test are enabled
268 * at the same time.
269 */
270 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
271 fpfn = vram_pages / 2;
272 lpfn = ~0;
273 } else {
274 fpfn = 0;
275 lpfn = vram_pages / 2;
276 }
277 for (i = 0; i < nvbo->placement.num_placement; ++i) {
278 nvbo->placements[i].fpfn = fpfn;
279 nvbo->placements[i].lpfn = lpfn;
280 }
281 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
282 nvbo->busy_placements[i].fpfn = fpfn;
283 nvbo->busy_placements[i].lpfn = lpfn;
284 }
285 }
286}
287
288void
289nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
290{
291 struct ttm_placement *pl = &nvbo->placement;
292 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
293 TTM_PL_MASK_CACHING) |
294 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
295
296 pl->placement = nvbo->placements;
297 set_placement_list(nvbo->placements, &pl->num_placement,
298 type, flags);
299
300 pl->busy_placement = nvbo->busy_placements;
301 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
302 type | busy, flags);
303
304 set_placement_range(nvbo, type);
305}
306
307int
308nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
309{
310 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
311 struct ttm_buffer_object *bo = &nvbo->bo;
312 bool force = false, evict = false;
313 int ret;
314
315 ret = ttm_bo_reserve(bo, false, false, false, NULL);
316 if (ret)
317 return ret;
318
319 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
320 memtype == TTM_PL_FLAG_VRAM && contig) {
321 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
322 if (bo->mem.mem_type == TTM_PL_VRAM) {
323 struct nvkm_mem *mem = bo->mem.mm_node;
324 if (!list_is_singular(&mem->regions))
325 evict = true;
326 }
327 nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG;
328 force = true;
329 }
330 }
331
332 if (nvbo->pin_refcnt) {
333 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
334 NV_ERROR(drm, "bo %p pinned elsewhere: "
335 "0x%08x vs 0x%08x\n", bo,
336 1 << bo->mem.mem_type, memtype);
337 ret = -EBUSY;
338 }
339 nvbo->pin_refcnt++;
340 goto out;
341 }
342
343 if (evict) {
344 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
345 ret = nouveau_bo_validate(nvbo, false, false);
346 if (ret)
347 goto out;
348 }
349
350 nvbo->pin_refcnt++;
351 nouveau_bo_placement_set(nvbo, memtype, 0);
352
353 /* drop pin_refcnt temporarily, so we don't trip the assertion
354 * in nouveau_bo_move() that makes sure we're not trying to
355 * move a pinned buffer
356 */
357 nvbo->pin_refcnt--;
358 ret = nouveau_bo_validate(nvbo, false, false);
359 if (ret)
360 goto out;
361 nvbo->pin_refcnt++;
362
363 switch (bo->mem.mem_type) {
364 case TTM_PL_VRAM:
365 drm->gem.vram_available -= bo->mem.size;
366 break;
367 case TTM_PL_TT:
368 drm->gem.gart_available -= bo->mem.size;
369 break;
370 default:
371 break;
372 }
373
374out:
375 if (force && ret)
376 nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG;
377 ttm_bo_unreserve(bo);
378 return ret;
379}
380
381int
382nouveau_bo_unpin(struct nouveau_bo *nvbo)
383{
384 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
385 struct ttm_buffer_object *bo = &nvbo->bo;
386 int ret, ref;
387
388 ret = ttm_bo_reserve(bo, false, false, false, NULL);
389 if (ret)
390 return ret;
391
392 ref = --nvbo->pin_refcnt;
393 WARN_ON_ONCE(ref < 0);
394 if (ref)
395 goto out;
396
397 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
398
399 ret = nouveau_bo_validate(nvbo, false, false);
400 if (ret == 0) {
401 switch (bo->mem.mem_type) {
402 case TTM_PL_VRAM:
403 drm->gem.vram_available += bo->mem.size;
404 break;
405 case TTM_PL_TT:
406 drm->gem.gart_available += bo->mem.size;
407 break;
408 default:
409 break;
410 }
411 }
412
413out:
414 ttm_bo_unreserve(bo);
415 return ret;
416}
417
418int
419nouveau_bo_map(struct nouveau_bo *nvbo)
420{
421 int ret;
422
423 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL);
424 if (ret)
425 return ret;
426
427 /*
428 * TTM buffers allocated using the DMA API already have a mapping, let's
429 * use it instead.
430 */
431 if (!nvbo->force_coherent)
432 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages,
433 &nvbo->kmap);
434
435 ttm_bo_unreserve(&nvbo->bo);
436 return ret;
437}
438
439void
440nouveau_bo_unmap(struct nouveau_bo *nvbo)
441{
442 if (!nvbo)
443 return;
444
445 /*
446 * TTM buffers allocated using the DMA API already had a coherent
447 * mapping which we used, no need to unmap.
448 */
449 if (!nvbo->force_coherent)
450 ttm_bo_kunmap(&nvbo->kmap);
451}
452
453void
454nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
455{
456 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
457 struct nvkm_device *device = nvxx_device(&drm->device);
458 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
459 int i;
460
461 if (!ttm_dma)
462 return;
463
464 /* Don't waste time looping if the object is coherent */
465 if (nvbo->force_coherent)
466 return;
467
468 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
469 dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i],
470 PAGE_SIZE, DMA_TO_DEVICE);
471}
472
473void
474nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
475{
476 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
477 struct nvkm_device *device = nvxx_device(&drm->device);
478 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
479 int i;
480
481 if (!ttm_dma)
482 return;
483
484 /* Don't waste time looping if the object is coherent */
485 if (nvbo->force_coherent)
486 return;
487
488 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
489 dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i],
490 PAGE_SIZE, DMA_FROM_DEVICE);
491}
492
493int
494nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
495 bool no_wait_gpu)
496{
497 int ret;
498
499 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
500 interruptible, no_wait_gpu);
501 if (ret)
502 return ret;
503
504 nouveau_bo_sync_for_device(nvbo);
505
506 return 0;
507}
508
509static inline void *
510_nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)
511{
512 struct ttm_dma_tt *dma_tt;
513 u8 *m = mem;
514
515 index *= sz;
516
517 if (m) {
518 /* kmap'd address, return the corresponding offset */
519 m += index;
520 } else {
521 /* DMA-API mapping, lookup the right address */
522 dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm;
523 m = dma_tt->cpu_address[index / PAGE_SIZE];
524 m += index % PAGE_SIZE;
525 }
526
527 return m;
528}
529#define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
530
531void
532nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
533{
534 bool is_iomem;
535 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
536
537 mem = nouveau_bo_mem_index(nvbo, index, mem);
538
539 if (is_iomem)
540 iowrite16_native(val, (void __force __iomem *)mem);
541 else
542 *mem = val;
543}
544
545u32
546nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
547{
548 bool is_iomem;
549 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
550
551 mem = nouveau_bo_mem_index(nvbo, index, mem);
552
553 if (is_iomem)
554 return ioread32_native((void __force __iomem *)mem);
555 else
556 return *mem;
557}
558
559void
560nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
561{
562 bool is_iomem;
563 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
564
565 mem = nouveau_bo_mem_index(nvbo, index, mem);
566
567 if (is_iomem)
568 iowrite32_native(val, (void __force __iomem *)mem);
569 else
570 *mem = val;
571}
572
573static struct ttm_tt *
574nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
575 uint32_t page_flags, struct page *dummy_read)
576{
577#if IS_ENABLED(CONFIG_AGP)
578 struct nouveau_drm *drm = nouveau_bdev(bdev);
579
580 if (drm->agp.bridge) {
581 return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
582 page_flags, dummy_read);
583 }
584#endif
585
586 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
587}
588
589static int
590nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
591{
592 /* We'll do this from user space. */
593 return 0;
594}
595
596static int
597nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
598 struct ttm_mem_type_manager *man)
599{
600 struct nouveau_drm *drm = nouveau_bdev(bdev);
601
602 switch (type) {
603 case TTM_PL_SYSTEM:
604 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
605 man->available_caching = TTM_PL_MASK_CACHING;
606 man->default_caching = TTM_PL_FLAG_CACHED;
607 break;
608 case TTM_PL_VRAM:
609 man->flags = TTM_MEMTYPE_FLAG_FIXED |
610 TTM_MEMTYPE_FLAG_MAPPABLE;
611 man->available_caching = TTM_PL_FLAG_UNCACHED |
612 TTM_PL_FLAG_WC;
613 man->default_caching = TTM_PL_FLAG_WC;
614
615 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
616 /* Some BARs do not support being ioremapped WC */
617 if (nvxx_bar(&drm->device)->iomap_uncached) {
618 man->available_caching = TTM_PL_FLAG_UNCACHED;
619 man->default_caching = TTM_PL_FLAG_UNCACHED;
620 }
621
622 man->func = &nouveau_vram_manager;
623 man->io_reserve_fastpath = false;
624 man->use_io_reserve_lru = true;
625 } else {
626 man->func = &ttm_bo_manager_func;
627 }
628 break;
629 case TTM_PL_TT:
630 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
631 man->func = &nouveau_gart_manager;
632 else
633 if (!drm->agp.bridge)
634 man->func = &nv04_gart_manager;
635 else
636 man->func = &ttm_bo_manager_func;
637
638 if (drm->agp.bridge) {
639 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
640 man->available_caching = TTM_PL_FLAG_UNCACHED |
641 TTM_PL_FLAG_WC;
642 man->default_caching = TTM_PL_FLAG_WC;
643 } else {
644 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
645 TTM_MEMTYPE_FLAG_CMA;
646 man->available_caching = TTM_PL_MASK_CACHING;
647 man->default_caching = TTM_PL_FLAG_CACHED;
648 }
649
650 break;
651 default:
652 return -EINVAL;
653 }
654 return 0;
655}
656
657static void
658nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
659{
660 struct nouveau_bo *nvbo = nouveau_bo(bo);
661
662 switch (bo->mem.mem_type) {
663 case TTM_PL_VRAM:
664 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
665 TTM_PL_FLAG_SYSTEM);
666 break;
667 default:
668 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
669 break;
670 }
671
672 *pl = nvbo->placement;
673}
674
675
676static int
677nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
678{
679 int ret = RING_SPACE(chan, 2);
680 if (ret == 0) {
681 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
682 OUT_RING (chan, handle & 0x0000ffff);
683 FIRE_RING (chan);
684 }
685 return ret;
686}
687
688static int
689nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
690 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
691{
692 struct nvkm_mem *node = old_mem->mm_node;
693 int ret = RING_SPACE(chan, 10);
694 if (ret == 0) {
695 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
696 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
697 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
698 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
699 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
700 OUT_RING (chan, PAGE_SIZE);
701 OUT_RING (chan, PAGE_SIZE);
702 OUT_RING (chan, PAGE_SIZE);
703 OUT_RING (chan, new_mem->num_pages);
704 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
705 }
706 return ret;
707}
708
709static int
710nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
711{
712 int ret = RING_SPACE(chan, 2);
713 if (ret == 0) {
714 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
715 OUT_RING (chan, handle);
716 }
717 return ret;
718}
719
720static int
721nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
722 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
723{
724 struct nvkm_mem *node = old_mem->mm_node;
725 u64 src_offset = node->vma[0].offset;
726 u64 dst_offset = node->vma[1].offset;
727 u32 page_count = new_mem->num_pages;
728 int ret;
729
730 page_count = new_mem->num_pages;
731 while (page_count) {
732 int line_count = (page_count > 8191) ? 8191 : page_count;
733
734 ret = RING_SPACE(chan, 11);
735 if (ret)
736 return ret;
737
738 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
739 OUT_RING (chan, upper_32_bits(src_offset));
740 OUT_RING (chan, lower_32_bits(src_offset));
741 OUT_RING (chan, upper_32_bits(dst_offset));
742 OUT_RING (chan, lower_32_bits(dst_offset));
743 OUT_RING (chan, PAGE_SIZE);
744 OUT_RING (chan, PAGE_SIZE);
745 OUT_RING (chan, PAGE_SIZE);
746 OUT_RING (chan, line_count);
747 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
748 OUT_RING (chan, 0x00000110);
749
750 page_count -= line_count;
751 src_offset += (PAGE_SIZE * line_count);
752 dst_offset += (PAGE_SIZE * line_count);
753 }
754
755 return 0;
756}
757
758static int
759nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
760 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
761{
762 struct nvkm_mem *node = old_mem->mm_node;
763 u64 src_offset = node->vma[0].offset;
764 u64 dst_offset = node->vma[1].offset;
765 u32 page_count = new_mem->num_pages;
766 int ret;
767
768 page_count = new_mem->num_pages;
769 while (page_count) {
770 int line_count = (page_count > 2047) ? 2047 : page_count;
771
772 ret = RING_SPACE(chan, 12);
773 if (ret)
774 return ret;
775
776 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
777 OUT_RING (chan, upper_32_bits(dst_offset));
778 OUT_RING (chan, lower_32_bits(dst_offset));
779 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
780 OUT_RING (chan, upper_32_bits(src_offset));
781 OUT_RING (chan, lower_32_bits(src_offset));
782 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
783 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
784 OUT_RING (chan, PAGE_SIZE); /* line_length */
785 OUT_RING (chan, line_count);
786 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
787 OUT_RING (chan, 0x00100110);
788
789 page_count -= line_count;
790 src_offset += (PAGE_SIZE * line_count);
791 dst_offset += (PAGE_SIZE * line_count);
792 }
793
794 return 0;
795}
796
797static int
798nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
799 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
800{
801 struct nvkm_mem *node = old_mem->mm_node;
802 u64 src_offset = node->vma[0].offset;
803 u64 dst_offset = node->vma[1].offset;
804 u32 page_count = new_mem->num_pages;
805 int ret;
806
807 page_count = new_mem->num_pages;
808 while (page_count) {
809 int line_count = (page_count > 8191) ? 8191 : page_count;
810
811 ret = RING_SPACE(chan, 11);
812 if (ret)
813 return ret;
814
815 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
816 OUT_RING (chan, upper_32_bits(src_offset));
817 OUT_RING (chan, lower_32_bits(src_offset));
818 OUT_RING (chan, upper_32_bits(dst_offset));
819 OUT_RING (chan, lower_32_bits(dst_offset));
820 OUT_RING (chan, PAGE_SIZE);
821 OUT_RING (chan, PAGE_SIZE);
822 OUT_RING (chan, PAGE_SIZE);
823 OUT_RING (chan, line_count);
824 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
825 OUT_RING (chan, 0x00000110);
826
827 page_count -= line_count;
828 src_offset += (PAGE_SIZE * line_count);
829 dst_offset += (PAGE_SIZE * line_count);
830 }
831
832 return 0;
833}
834
835static int
836nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
837 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
838{
839 struct nvkm_mem *node = old_mem->mm_node;
840 int ret = RING_SPACE(chan, 7);
841 if (ret == 0) {
842 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
843 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
844 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
845 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
846 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
847 OUT_RING (chan, 0x00000000 /* COPY */);
848 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
849 }
850 return ret;
851}
852
853static int
854nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
855 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
856{
857 struct nvkm_mem *node = old_mem->mm_node;
858 int ret = RING_SPACE(chan, 7);
859 if (ret == 0) {
860 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
861 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
862 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
863 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
864 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
865 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
866 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
867 }
868 return ret;
869}
870
871static int
872nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
873{
874 int ret = RING_SPACE(chan, 6);
875 if (ret == 0) {
876 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
877 OUT_RING (chan, handle);
878 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
879 OUT_RING (chan, chan->drm->ntfy.handle);
880 OUT_RING (chan, chan->vram.handle);
881 OUT_RING (chan, chan->vram.handle);
882 }
883
884 return ret;
885}
886
887static int
888nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
889 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
890{
891 struct nvkm_mem *node = old_mem->mm_node;
892 u64 length = (new_mem->num_pages << PAGE_SHIFT);
893 u64 src_offset = node->vma[0].offset;
894 u64 dst_offset = node->vma[1].offset;
895 int src_tiled = !!node->memtype;
896 int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype;
897 int ret;
898
899 while (length) {
900 u32 amount, stride, height;
901
902 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
903 if (ret)
904 return ret;
905
906 amount = min(length, (u64)(4 * 1024 * 1024));
907 stride = 16 * 4;
908 height = amount / stride;
909
910 if (src_tiled) {
911 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
912 OUT_RING (chan, 0);
913 OUT_RING (chan, 0);
914 OUT_RING (chan, stride);
915 OUT_RING (chan, height);
916 OUT_RING (chan, 1);
917 OUT_RING (chan, 0);
918 OUT_RING (chan, 0);
919 } else {
920 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
921 OUT_RING (chan, 1);
922 }
923 if (dst_tiled) {
924 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
925 OUT_RING (chan, 0);
926 OUT_RING (chan, 0);
927 OUT_RING (chan, stride);
928 OUT_RING (chan, height);
929 OUT_RING (chan, 1);
930 OUT_RING (chan, 0);
931 OUT_RING (chan, 0);
932 } else {
933 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
934 OUT_RING (chan, 1);
935 }
936
937 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
938 OUT_RING (chan, upper_32_bits(src_offset));
939 OUT_RING (chan, upper_32_bits(dst_offset));
940 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
941 OUT_RING (chan, lower_32_bits(src_offset));
942 OUT_RING (chan, lower_32_bits(dst_offset));
943 OUT_RING (chan, stride);
944 OUT_RING (chan, stride);
945 OUT_RING (chan, stride);
946 OUT_RING (chan, height);
947 OUT_RING (chan, 0x00000101);
948 OUT_RING (chan, 0x00000000);
949 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
950 OUT_RING (chan, 0);
951
952 length -= amount;
953 src_offset += amount;
954 dst_offset += amount;
955 }
956
957 return 0;
958}
959
960static int
961nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
962{
963 int ret = RING_SPACE(chan, 4);
964 if (ret == 0) {
965 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
966 OUT_RING (chan, handle);
967 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
968 OUT_RING (chan, chan->drm->ntfy.handle);
969 }
970
971 return ret;
972}
973
974static inline uint32_t
975nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
976 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
977{
978 if (mem->mem_type == TTM_PL_TT)
979 return NvDmaTT;
980 return chan->vram.handle;
981}
982
983static int
984nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
985 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
986{
987 u32 src_offset = old_mem->start << PAGE_SHIFT;
988 u32 dst_offset = new_mem->start << PAGE_SHIFT;
989 u32 page_count = new_mem->num_pages;
990 int ret;
991
992 ret = RING_SPACE(chan, 3);
993 if (ret)
994 return ret;
995
996 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
997 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
998 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
999
1000 page_count = new_mem->num_pages;
1001 while (page_count) {
1002 int line_count = (page_count > 2047) ? 2047 : page_count;
1003
1004 ret = RING_SPACE(chan, 11);
1005 if (ret)
1006 return ret;
1007
1008 BEGIN_NV04(chan, NvSubCopy,
1009 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1010 OUT_RING (chan, src_offset);
1011 OUT_RING (chan, dst_offset);
1012 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
1013 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
1014 OUT_RING (chan, PAGE_SIZE); /* line_length */
1015 OUT_RING (chan, line_count);
1016 OUT_RING (chan, 0x00000101);
1017 OUT_RING (chan, 0x00000000);
1018 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1019 OUT_RING (chan, 0);
1020
1021 page_count -= line_count;
1022 src_offset += (PAGE_SIZE * line_count);
1023 dst_offset += (PAGE_SIZE * line_count);
1024 }
1025
1026 return 0;
1027}
1028
1029static int
1030nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1031 struct ttm_mem_reg *mem)
1032{
1033 struct nvkm_mem *old_node = bo->mem.mm_node;
1034 struct nvkm_mem *new_node = mem->mm_node;
1035 u64 size = (u64)mem->num_pages << PAGE_SHIFT;
1036 int ret;
1037
1038 ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift,
1039 NV_MEM_ACCESS_RW, &old_node->vma[0]);
1040 if (ret)
1041 return ret;
1042
1043 ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift,
1044 NV_MEM_ACCESS_RW, &old_node->vma[1]);
1045 if (ret) {
1046 nvkm_vm_put(&old_node->vma[0]);
1047 return ret;
1048 }
1049
1050 nvkm_vm_map(&old_node->vma[0], old_node);
1051 nvkm_vm_map(&old_node->vma[1], new_node);
1052 return 0;
1053}
1054
1055static int
1056nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1057 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1058{
1059 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1060 struct nouveau_channel *chan = drm->ttm.chan;
1061 struct nouveau_cli *cli = (void *)chan->user.client;
1062 struct nouveau_fence *fence;
1063 int ret;
1064
1065 /* create temporary vmas for the transfer and attach them to the
1066 * old nvkm_mem node, these will get cleaned up after ttm has
1067 * destroyed the ttm_mem_reg
1068 */
1069 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1070 ret = nouveau_bo_move_prep(drm, bo, new_mem);
1071 if (ret)
1072 return ret;
1073 }
1074
1075 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1076 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1077 if (ret == 0) {
1078 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1079 if (ret == 0) {
1080 ret = nouveau_fence_new(chan, false, &fence);
1081 if (ret == 0) {
1082 ret = ttm_bo_move_accel_cleanup(bo,
1083 &fence->base,
1084 evict,
1085 no_wait_gpu,
1086 new_mem);
1087 nouveau_fence_unref(&fence);
1088 }
1089 }
1090 }
1091 mutex_unlock(&cli->mutex);
1092 return ret;
1093}
1094
1095void
1096nouveau_bo_move_init(struct nouveau_drm *drm)
1097{
1098 static const struct {
1099 const char *name;
1100 int engine;
1101 s32 oclass;
1102 int (*exec)(struct nouveau_channel *,
1103 struct ttm_buffer_object *,
1104 struct ttm_mem_reg *, struct ttm_mem_reg *);
1105 int (*init)(struct nouveau_channel *, u32 handle);
1106 } _methods[] = {
1107 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1108 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1109 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1110 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1111 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1112 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1113 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1114 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1115 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1116 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1117 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1118 {},
1119 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1120 }, *mthd = _methods;
1121 const char *name = "CPU";
1122 int ret;
1123
1124 do {
1125 struct nouveau_channel *chan;
1126
1127 if (mthd->engine)
1128 chan = drm->cechan;
1129 else
1130 chan = drm->channel;
1131 if (chan == NULL)
1132 continue;
1133
1134 ret = nvif_object_init(&chan->user,
1135 mthd->oclass | (mthd->engine << 16),
1136 mthd->oclass, NULL, 0,
1137 &drm->ttm.copy);
1138 if (ret == 0) {
1139 ret = mthd->init(chan, drm->ttm.copy.handle);
1140 if (ret) {
1141 nvif_object_fini(&drm->ttm.copy);
1142 continue;
1143 }
1144
1145 drm->ttm.move = mthd->exec;
1146 drm->ttm.chan = chan;
1147 name = mthd->name;
1148 break;
1149 }
1150 } while ((++mthd)->exec);
1151
1152 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1153}
1154
1155static int
1156nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1157 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1158{
1159 struct ttm_place placement_memtype = {
1160 .fpfn = 0,
1161 .lpfn = 0,
1162 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1163 };
1164 struct ttm_placement placement;
1165 struct ttm_mem_reg tmp_mem;
1166 int ret;
1167
1168 placement.num_placement = placement.num_busy_placement = 1;
1169 placement.placement = placement.busy_placement = &placement_memtype;
1170
1171 tmp_mem = *new_mem;
1172 tmp_mem.mm_node = NULL;
1173 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1174 if (ret)
1175 return ret;
1176
1177 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1178 if (ret)
1179 goto out;
1180
1181 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1182 if (ret)
1183 goto out;
1184
1185 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1186out:
1187 ttm_bo_mem_put(bo, &tmp_mem);
1188 return ret;
1189}
1190
1191static int
1192nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1193 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1194{
1195 struct ttm_place placement_memtype = {
1196 .fpfn = 0,
1197 .lpfn = 0,
1198 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1199 };
1200 struct ttm_placement placement;
1201 struct ttm_mem_reg tmp_mem;
1202 int ret;
1203
1204 placement.num_placement = placement.num_busy_placement = 1;
1205 placement.placement = placement.busy_placement = &placement_memtype;
1206
1207 tmp_mem = *new_mem;
1208 tmp_mem.mm_node = NULL;
1209 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1210 if (ret)
1211 return ret;
1212
1213 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1214 if (ret)
1215 goto out;
1216
1217 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1218 if (ret)
1219 goto out;
1220
1221out:
1222 ttm_bo_mem_put(bo, &tmp_mem);
1223 return ret;
1224}
1225
1226static void
1227nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1228{
1229 struct nouveau_bo *nvbo = nouveau_bo(bo);
1230 struct nvkm_vma *vma;
1231
1232 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1233 if (bo->destroy != nouveau_bo_del_ttm)
1234 return;
1235
1236 list_for_each_entry(vma, &nvbo->vma_list, head) {
1237 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1238 (new_mem->mem_type == TTM_PL_VRAM ||
1239 nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
1240 nvkm_vm_map(vma, new_mem->mm_node);
1241 } else {
1242 nvkm_vm_unmap(vma);
1243 }
1244 }
1245}
1246
1247static int
1248nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1249 struct nouveau_drm_tile **new_tile)
1250{
1251 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1252 struct drm_device *dev = drm->dev;
1253 struct nouveau_bo *nvbo = nouveau_bo(bo);
1254 u64 offset = new_mem->start << PAGE_SHIFT;
1255
1256 *new_tile = NULL;
1257 if (new_mem->mem_type != TTM_PL_VRAM)
1258 return 0;
1259
1260 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1261 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1262 nvbo->tile_mode,
1263 nvbo->tile_flags);
1264 }
1265
1266 return 0;
1267}
1268
1269static void
1270nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1271 struct nouveau_drm_tile *new_tile,
1272 struct nouveau_drm_tile **old_tile)
1273{
1274 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1275 struct drm_device *dev = drm->dev;
1276 struct fence *fence = reservation_object_get_excl(bo->resv);
1277
1278 nv10_bo_put_tile_region(dev, *old_tile, fence);
1279 *old_tile = new_tile;
1280}
1281
1282static int
1283nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1284 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1285{
1286 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1287 struct nouveau_bo *nvbo = nouveau_bo(bo);
1288 struct ttm_mem_reg *old_mem = &bo->mem;
1289 struct nouveau_drm_tile *new_tile = NULL;
1290 int ret = 0;
1291
1292 if (nvbo->pin_refcnt)
1293 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1294
1295 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1296 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1297 if (ret)
1298 return ret;
1299 }
1300
1301 /* Fake bo copy. */
1302 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1303 BUG_ON(bo->mem.mm_node != NULL);
1304 bo->mem = *new_mem;
1305 new_mem->mm_node = NULL;
1306 goto out;
1307 }
1308
1309 /* Hardware assisted copy. */
1310 if (drm->ttm.move) {
1311 if (new_mem->mem_type == TTM_PL_SYSTEM)
1312 ret = nouveau_bo_move_flipd(bo, evict, intr,
1313 no_wait_gpu, new_mem);
1314 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1315 ret = nouveau_bo_move_flips(bo, evict, intr,
1316 no_wait_gpu, new_mem);
1317 else
1318 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1319 no_wait_gpu, new_mem);
1320 if (!ret)
1321 goto out;
1322 }
1323
1324 /* Fallback to software copy. */
1325 ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1326 if (ret == 0)
1327 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1328
1329out:
1330 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1331 if (ret)
1332 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1333 else
1334 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1335 }
1336
1337 return ret;
1338}
1339
1340static int
1341nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1342{
1343 struct nouveau_bo *nvbo = nouveau_bo(bo);
1344
1345 return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1346}
1347
1348static int
1349nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1350{
1351 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1352 struct nouveau_drm *drm = nouveau_bdev(bdev);
1353 struct nvkm_device *device = nvxx_device(&drm->device);
1354 struct nvkm_mem *node = mem->mm_node;
1355 int ret;
1356
1357 mem->bus.addr = NULL;
1358 mem->bus.offset = 0;
1359 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1360 mem->bus.base = 0;
1361 mem->bus.is_iomem = false;
1362 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1363 return -EINVAL;
1364 switch (mem->mem_type) {
1365 case TTM_PL_SYSTEM:
1366 /* System memory */
1367 return 0;
1368 case TTM_PL_TT:
1369#if IS_ENABLED(CONFIG_AGP)
1370 if (drm->agp.bridge) {
1371 mem->bus.offset = mem->start << PAGE_SHIFT;
1372 mem->bus.base = drm->agp.base;
1373 mem->bus.is_iomem = !drm->agp.cma;
1374 }
1375#endif
1376 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
1377 /* untiled */
1378 break;
1379 /* fallthrough, tiled memory */
1380 case TTM_PL_VRAM:
1381 mem->bus.offset = mem->start << PAGE_SHIFT;
1382 mem->bus.base = device->func->resource_addr(device, 1);
1383 mem->bus.is_iomem = true;
1384 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1385 struct nvkm_bar *bar = nvxx_bar(&drm->device);
1386 int page_shift = 12;
1387 if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
1388 page_shift = node->page_shift;
1389
1390 ret = nvkm_bar_umap(bar, node->size << 12, page_shift,
1391 &node->bar_vma);
1392 if (ret)
1393 return ret;
1394
1395 nvkm_vm_map(&node->bar_vma, node);
1396 mem->bus.offset = node->bar_vma.offset;
1397 }
1398 break;
1399 default:
1400 return -EINVAL;
1401 }
1402 return 0;
1403}
1404
1405static void
1406nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1407{
1408 struct nvkm_mem *node = mem->mm_node;
1409
1410 if (!node->bar_vma.node)
1411 return;
1412
1413 nvkm_vm_unmap(&node->bar_vma);
1414 nvkm_vm_put(&node->bar_vma);
1415}
1416
1417static int
1418nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1419{
1420 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1421 struct nouveau_bo *nvbo = nouveau_bo(bo);
1422 struct nvkm_device *device = nvxx_device(&drm->device);
1423 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1424 int i, ret;
1425
1426 /* as long as the bo isn't in vram, and isn't tiled, we've got
1427 * nothing to do here.
1428 */
1429 if (bo->mem.mem_type != TTM_PL_VRAM) {
1430 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1431 !nouveau_bo_tile_layout(nvbo))
1432 return 0;
1433
1434 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1435 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1436
1437 ret = nouveau_bo_validate(nvbo, false, false);
1438 if (ret)
1439 return ret;
1440 }
1441 return 0;
1442 }
1443
1444 /* make sure bo is in mappable vram */
1445 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1446 bo->mem.start + bo->mem.num_pages < mappable)
1447 return 0;
1448
1449 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1450 nvbo->placements[i].fpfn = 0;
1451 nvbo->placements[i].lpfn = mappable;
1452 }
1453
1454 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1455 nvbo->busy_placements[i].fpfn = 0;
1456 nvbo->busy_placements[i].lpfn = mappable;
1457 }
1458
1459 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1460 return nouveau_bo_validate(nvbo, false, false);
1461}
1462
1463static int
1464nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1465{
1466 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1467 struct nouveau_drm *drm;
1468 struct nvkm_device *device;
1469 struct drm_device *dev;
1470 struct device *pdev;
1471 unsigned i;
1472 int r;
1473 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1474
1475 if (ttm->state != tt_unpopulated)
1476 return 0;
1477
1478 if (slave && ttm->sg) {
1479 /* make userspace faulting work */
1480 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1481 ttm_dma->dma_address, ttm->num_pages);
1482 ttm->state = tt_unbound;
1483 return 0;
1484 }
1485
1486 drm = nouveau_bdev(ttm->bdev);
1487 device = nvxx_device(&drm->device);
1488 dev = drm->dev;
1489 pdev = device->dev;
1490
1491 /*
1492 * Objects matching this condition have been marked as force_coherent,
1493 * so use the DMA API for them.
1494 */
1495 if (!nvxx_device(&drm->device)->func->cpu_coherent &&
1496 ttm->caching_state == tt_uncached)
1497 return ttm_dma_populate(ttm_dma, dev->dev);
1498
1499#if IS_ENABLED(CONFIG_AGP)
1500 if (drm->agp.bridge) {
1501 return ttm_agp_tt_populate(ttm);
1502 }
1503#endif
1504
1505#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1506 if (swiotlb_nr_tbl()) {
1507 return ttm_dma_populate((void *)ttm, dev->dev);
1508 }
1509#endif
1510
1511 r = ttm_pool_populate(ttm);
1512 if (r) {
1513 return r;
1514 }
1515
1516 for (i = 0; i < ttm->num_pages; i++) {
1517 dma_addr_t addr;
1518
1519 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1520 DMA_BIDIRECTIONAL);
1521
1522 if (dma_mapping_error(pdev, addr)) {
1523 while (i--) {
1524 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1525 PAGE_SIZE, DMA_BIDIRECTIONAL);
1526 ttm_dma->dma_address[i] = 0;
1527 }
1528 ttm_pool_unpopulate(ttm);
1529 return -EFAULT;
1530 }
1531
1532 ttm_dma->dma_address[i] = addr;
1533 }
1534 return 0;
1535}
1536
1537static void
1538nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1539{
1540 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1541 struct nouveau_drm *drm;
1542 struct nvkm_device *device;
1543 struct drm_device *dev;
1544 struct device *pdev;
1545 unsigned i;
1546 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1547
1548 if (slave)
1549 return;
1550
1551 drm = nouveau_bdev(ttm->bdev);
1552 device = nvxx_device(&drm->device);
1553 dev = drm->dev;
1554 pdev = device->dev;
1555
1556 /*
1557 * Objects matching this condition have been marked as force_coherent,
1558 * so use the DMA API for them.
1559 */
1560 if (!nvxx_device(&drm->device)->func->cpu_coherent &&
1561 ttm->caching_state == tt_uncached) {
1562 ttm_dma_unpopulate(ttm_dma, dev->dev);
1563 return;
1564 }
1565
1566#if IS_ENABLED(CONFIG_AGP)
1567 if (drm->agp.bridge) {
1568 ttm_agp_tt_unpopulate(ttm);
1569 return;
1570 }
1571#endif
1572
1573#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1574 if (swiotlb_nr_tbl()) {
1575 ttm_dma_unpopulate((void *)ttm, dev->dev);
1576 return;
1577 }
1578#endif
1579
1580 for (i = 0; i < ttm->num_pages; i++) {
1581 if (ttm_dma->dma_address[i]) {
1582 dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1583 DMA_BIDIRECTIONAL);
1584 }
1585 }
1586
1587 ttm_pool_unpopulate(ttm);
1588}
1589
1590void
1591nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1592{
1593 struct reservation_object *resv = nvbo->bo.resv;
1594
1595 if (exclusive)
1596 reservation_object_add_excl_fence(resv, &fence->base);
1597 else if (fence)
1598 reservation_object_add_shared_fence(resv, &fence->base);
1599}
1600
1601struct ttm_bo_driver nouveau_bo_driver = {
1602 .ttm_tt_create = &nouveau_ttm_tt_create,
1603 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1604 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1605 .invalidate_caches = nouveau_bo_invalidate_caches,
1606 .init_mem_type = nouveau_bo_init_mem_type,
1607 .evict_flags = nouveau_bo_evict_flags,
1608 .move_notify = nouveau_bo_move_ntfy,
1609 .move = nouveau_bo_move,
1610 .verify_access = nouveau_bo_verify_access,
1611 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1612 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1613 .io_mem_free = &nouveau_ttm_io_mem_free,
1614};
1615
1616struct nvkm_vma *
1617nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm)
1618{
1619 struct nvkm_vma *vma;
1620 list_for_each_entry(vma, &nvbo->vma_list, head) {
1621 if (vma->vm == vm)
1622 return vma;
1623 }
1624
1625 return NULL;
1626}
1627
1628int
1629nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm,
1630 struct nvkm_vma *vma)
1631{
1632 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1633 int ret;
1634
1635 ret = nvkm_vm_get(vm, size, nvbo->page_shift,
1636 NV_MEM_ACCESS_RW, vma);
1637 if (ret)
1638 return ret;
1639
1640 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1641 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1642 nvbo->page_shift != vma->vm->mmu->lpg_shift))
1643 nvkm_vm_map(vma, nvbo->bo.mem.mm_node);
1644
1645 list_add_tail(&vma->head, &nvbo->vma_list);
1646 vma->refcount = 1;
1647 return 0;
1648}
1649
1650void
1651nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma)
1652{
1653 if (vma->node) {
1654 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1655 nvkm_vm_unmap(vma);
1656 nvkm_vm_put(vma);
1657 list_del(&vma->head);
1658 }
1659}
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31
32#include "nouveau_drv.h"
33#include "nouveau_chan.h"
34#include "nouveau_fence.h"
35
36#include "nouveau_bo.h"
37#include "nouveau_ttm.h"
38#include "nouveau_gem.h"
39#include "nouveau_mem.h"
40#include "nouveau_vmm.h"
41
42#include <nvif/class.h>
43#include <nvif/if500b.h>
44#include <nvif/if900b.h>
45
46static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
47 struct ttm_resource *reg);
48static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
49
50/*
51 * NV10-NV40 tiling helpers
52 */
53
54static void
55nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 u32 addr, u32 size, u32 pitch, u32 flags)
57{
58 struct nouveau_drm *drm = nouveau_drm(dev);
59 int i = reg - drm->tile.reg;
60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 struct nvkm_fb_tile *tile = &fb->tile.region[i];
62
63 nouveau_fence_unref(®->fence);
64
65 if (tile->pitch)
66 nvkm_fb_tile_fini(fb, i, tile);
67
68 if (pitch)
69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
70
71 nvkm_fb_tile_prog(fb, i, tile);
72}
73
74static struct nouveau_drm_tile *
75nv10_bo_get_tile_region(struct drm_device *dev, int i)
76{
77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
79
80 spin_lock(&drm->tile.lock);
81
82 if (!tile->used &&
83 (!tile->fence || nouveau_fence_done(tile->fence)))
84 tile->used = true;
85 else
86 tile = NULL;
87
88 spin_unlock(&drm->tile.lock);
89 return tile;
90}
91
92static void
93nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct dma_fence *fence)
95{
96 struct nouveau_drm *drm = nouveau_drm(dev);
97
98 if (tile) {
99 spin_lock(&drm->tile.lock);
100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
101 tile->used = false;
102 spin_unlock(&drm->tile.lock);
103 }
104}
105
106static struct nouveau_drm_tile *
107nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 u32 size, u32 pitch, u32 zeta)
109{
110 struct nouveau_drm *drm = nouveau_drm(dev);
111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 struct nouveau_drm_tile *tile, *found = NULL;
113 int i;
114
115 for (i = 0; i < fb->tile.regions; i++) {
116 tile = nv10_bo_get_tile_region(dev, i);
117
118 if (pitch && !found) {
119 found = tile;
120 continue;
121
122 } else if (tile && fb->tile.region[i].pitch) {
123 /* Kill an unused tile region. */
124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
125 }
126
127 nv10_bo_put_tile_region(dev, tile, NULL);
128 }
129
130 if (found)
131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
132 return found;
133}
134
135static void
136nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
137{
138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 struct drm_device *dev = drm->dev;
140 struct nouveau_bo *nvbo = nouveau_bo(bo);
141
142 WARN_ON(nvbo->bo.pin_count > 0);
143 nouveau_bo_del_io_reserve_lru(bo);
144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
145
146 /*
147 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 * initialized, so don't attempt to release it.
149 */
150 if (bo->base.dev)
151 drm_gem_object_release(&bo->base);
152 else
153 dma_resv_fini(&bo->base._resv);
154
155 kfree(nvbo);
156}
157
158static inline u64
159roundup_64(u64 x, u32 y)
160{
161 x += y - 1;
162 do_div(x, y);
163 return x * y;
164}
165
166static void
167nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
168{
169 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
170 struct nvif_device *device = &drm->client.device;
171
172 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
173 if (nvbo->mode) {
174 if (device->info.chipset >= 0x40) {
175 *align = 65536;
176 *size = roundup_64(*size, 64 * nvbo->mode);
177
178 } else if (device->info.chipset >= 0x30) {
179 *align = 32768;
180 *size = roundup_64(*size, 64 * nvbo->mode);
181
182 } else if (device->info.chipset >= 0x20) {
183 *align = 16384;
184 *size = roundup_64(*size, 64 * nvbo->mode);
185
186 } else if (device->info.chipset >= 0x10) {
187 *align = 16384;
188 *size = roundup_64(*size, 32 * nvbo->mode);
189 }
190 }
191 } else {
192 *size = roundup_64(*size, (1 << nvbo->page));
193 *align = max((1 << nvbo->page), *align);
194 }
195
196 *size = roundup_64(*size, PAGE_SIZE);
197}
198
199struct nouveau_bo *
200nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
201 u32 tile_mode, u32 tile_flags)
202{
203 struct nouveau_drm *drm = cli->drm;
204 struct nouveau_bo *nvbo;
205 struct nvif_mmu *mmu = &cli->mmu;
206 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
207 int i, pi = -1;
208
209 if (!*size) {
210 NV_WARN(drm, "skipped size %016llx\n", *size);
211 return ERR_PTR(-EINVAL);
212 }
213
214 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
215 if (!nvbo)
216 return ERR_PTR(-ENOMEM);
217 INIT_LIST_HEAD(&nvbo->head);
218 INIT_LIST_HEAD(&nvbo->entry);
219 INIT_LIST_HEAD(&nvbo->vma_list);
220 nvbo->bo.bdev = &drm->ttm.bdev;
221
222 /* This is confusing, and doesn't actually mean we want an uncached
223 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
224 * into in nouveau_gem_new().
225 */
226 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
227 /* Determine if we can get a cache-coherent map, forcing
228 * uncached mapping if we can't.
229 */
230 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
231 nvbo->force_coherent = true;
232 }
233
234 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
235 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
236 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
237 kfree(nvbo);
238 return ERR_PTR(-EINVAL);
239 }
240
241 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
242 } else
243 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
244 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
245 nvbo->comp = (tile_flags & 0x00030000) >> 16;
246 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
247 kfree(nvbo);
248 return ERR_PTR(-EINVAL);
249 }
250 } else {
251 nvbo->zeta = (tile_flags & 0x00000007);
252 }
253 nvbo->mode = tile_mode;
254 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
255
256 /* Determine the desirable target GPU page size for the buffer. */
257 for (i = 0; i < vmm->page_nr; i++) {
258 /* Because we cannot currently allow VMM maps to fail
259 * during buffer migration, we need to determine page
260 * size for the buffer up-front, and pre-allocate its
261 * page tables.
262 *
263 * Skip page sizes that can't support needed domains.
264 */
265 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
266 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
267 continue;
268 if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
269 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
270 continue;
271
272 /* Select this page size if it's the first that supports
273 * the potential memory domains, or when it's compatible
274 * with the requested compression settings.
275 */
276 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
277 pi = i;
278
279 /* Stop once the buffer is larger than the current page size. */
280 if (*size >= 1ULL << vmm->page[i].shift)
281 break;
282 }
283
284 if (WARN_ON(pi < 0)) {
285 kfree(nvbo);
286 return ERR_PTR(-EINVAL);
287 }
288
289 /* Disable compression if suitable settings couldn't be found. */
290 if (nvbo->comp && !vmm->page[pi].comp) {
291 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
292 nvbo->kind = mmu->kind[nvbo->kind];
293 nvbo->comp = 0;
294 }
295 nvbo->page = vmm->page[pi].shift;
296
297 nouveau_bo_fixup_align(nvbo, align, size);
298
299 return nvbo;
300}
301
302int
303nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
304 struct sg_table *sg, struct dma_resv *robj)
305{
306 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
307 int ret;
308
309 nouveau_bo_placement_set(nvbo, domain, 0);
310 INIT_LIST_HEAD(&nvbo->io_reserve_lru);
311
312 ret = ttm_bo_init_validate(nvbo->bo.bdev, &nvbo->bo, type,
313 &nvbo->placement, align >> PAGE_SHIFT, false,
314 sg, robj, nouveau_bo_del_ttm);
315 if (ret) {
316 /* ttm will call nouveau_bo_del_ttm if it fails.. */
317 return ret;
318 }
319
320 return 0;
321}
322
323int
324nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
325 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
326 struct sg_table *sg, struct dma_resv *robj,
327 struct nouveau_bo **pnvbo)
328{
329 struct nouveau_bo *nvbo;
330 int ret;
331
332 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
333 tile_flags);
334 if (IS_ERR(nvbo))
335 return PTR_ERR(nvbo);
336
337 nvbo->bo.base.size = size;
338 dma_resv_init(&nvbo->bo.base._resv);
339 drm_vma_node_reset(&nvbo->bo.base.vma_node);
340
341 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
342 if (ret)
343 return ret;
344
345 *pnvbo = nvbo;
346 return 0;
347}
348
349static void
350set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
351{
352 *n = 0;
353
354 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
355 pl[*n].mem_type = TTM_PL_VRAM;
356 pl[*n].flags = 0;
357 (*n)++;
358 }
359 if (domain & NOUVEAU_GEM_DOMAIN_GART) {
360 pl[*n].mem_type = TTM_PL_TT;
361 pl[*n].flags = 0;
362 (*n)++;
363 }
364 if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
365 pl[*n].mem_type = TTM_PL_SYSTEM;
366 pl[(*n)++].flags = 0;
367 }
368}
369
370static void
371set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
372{
373 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
374 u64 vram_size = drm->client.device.info.ram_size;
375 unsigned i, fpfn, lpfn;
376
377 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
378 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
379 nvbo->bo.base.size < vram_size / 4) {
380 /*
381 * Make sure that the color and depth buffers are handled
382 * by independent memory controller units. Up to a 9x
383 * speed up when alpha-blending and depth-test are enabled
384 * at the same time.
385 */
386 if (nvbo->zeta) {
387 fpfn = (vram_size / 2) >> PAGE_SHIFT;
388 lpfn = ~0;
389 } else {
390 fpfn = 0;
391 lpfn = (vram_size / 2) >> PAGE_SHIFT;
392 }
393 for (i = 0; i < nvbo->placement.num_placement; ++i) {
394 nvbo->placements[i].fpfn = fpfn;
395 nvbo->placements[i].lpfn = lpfn;
396 }
397 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
398 nvbo->busy_placements[i].fpfn = fpfn;
399 nvbo->busy_placements[i].lpfn = lpfn;
400 }
401 }
402}
403
404void
405nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
406 uint32_t busy)
407{
408 struct ttm_placement *pl = &nvbo->placement;
409
410 pl->placement = nvbo->placements;
411 set_placement_list(nvbo->placements, &pl->num_placement, domain);
412
413 pl->busy_placement = nvbo->busy_placements;
414 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
415 domain | busy);
416
417 set_placement_range(nvbo, domain);
418}
419
420int
421nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
422{
423 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
424 struct ttm_buffer_object *bo = &nvbo->bo;
425 bool force = false, evict = false;
426 int ret;
427
428 ret = ttm_bo_reserve(bo, false, false, NULL);
429 if (ret)
430 return ret;
431
432 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
433 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
434 if (!nvbo->contig) {
435 nvbo->contig = true;
436 force = true;
437 evict = true;
438 }
439 }
440
441 if (nvbo->bo.pin_count) {
442 bool error = evict;
443
444 switch (bo->resource->mem_type) {
445 case TTM_PL_VRAM:
446 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
447 break;
448 case TTM_PL_TT:
449 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
450 break;
451 default:
452 break;
453 }
454
455 if (error) {
456 NV_ERROR(drm, "bo %p pinned elsewhere: "
457 "0x%08x vs 0x%08x\n", bo,
458 bo->resource->mem_type, domain);
459 ret = -EBUSY;
460 }
461 ttm_bo_pin(&nvbo->bo);
462 goto out;
463 }
464
465 if (evict) {
466 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
467 ret = nouveau_bo_validate(nvbo, false, false);
468 if (ret)
469 goto out;
470 }
471
472 nouveau_bo_placement_set(nvbo, domain, 0);
473 ret = nouveau_bo_validate(nvbo, false, false);
474 if (ret)
475 goto out;
476
477 ttm_bo_pin(&nvbo->bo);
478
479 switch (bo->resource->mem_type) {
480 case TTM_PL_VRAM:
481 drm->gem.vram_available -= bo->base.size;
482 break;
483 case TTM_PL_TT:
484 drm->gem.gart_available -= bo->base.size;
485 break;
486 default:
487 break;
488 }
489
490out:
491 if (force && ret)
492 nvbo->contig = false;
493 ttm_bo_unreserve(bo);
494 return ret;
495}
496
497int
498nouveau_bo_unpin(struct nouveau_bo *nvbo)
499{
500 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
501 struct ttm_buffer_object *bo = &nvbo->bo;
502 int ret;
503
504 ret = ttm_bo_reserve(bo, false, false, NULL);
505 if (ret)
506 return ret;
507
508 ttm_bo_unpin(&nvbo->bo);
509 if (!nvbo->bo.pin_count) {
510 switch (bo->resource->mem_type) {
511 case TTM_PL_VRAM:
512 drm->gem.vram_available += bo->base.size;
513 break;
514 case TTM_PL_TT:
515 drm->gem.gart_available += bo->base.size;
516 break;
517 default:
518 break;
519 }
520 }
521
522 ttm_bo_unreserve(bo);
523 return 0;
524}
525
526int
527nouveau_bo_map(struct nouveau_bo *nvbo)
528{
529 int ret;
530
531 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
532 if (ret)
533 return ret;
534
535 ret = ttm_bo_kmap(&nvbo->bo, 0, PFN_UP(nvbo->bo.base.size), &nvbo->kmap);
536
537 ttm_bo_unreserve(&nvbo->bo);
538 return ret;
539}
540
541void
542nouveau_bo_unmap(struct nouveau_bo *nvbo)
543{
544 if (!nvbo)
545 return;
546
547 ttm_bo_kunmap(&nvbo->kmap);
548}
549
550void
551nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
552{
553 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
554 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
555 int i, j;
556
557 if (!ttm_dma || !ttm_dma->dma_address)
558 return;
559 if (!ttm_dma->pages) {
560 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
561 return;
562 }
563
564 /* Don't waste time looping if the object is coherent */
565 if (nvbo->force_coherent)
566 return;
567
568 i = 0;
569 while (i < ttm_dma->num_pages) {
570 struct page *p = ttm_dma->pages[i];
571 size_t num_pages = 1;
572
573 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
574 if (++p != ttm_dma->pages[j])
575 break;
576
577 ++num_pages;
578 }
579 dma_sync_single_for_device(drm->dev->dev,
580 ttm_dma->dma_address[i],
581 num_pages * PAGE_SIZE, DMA_TO_DEVICE);
582 i += num_pages;
583 }
584}
585
586void
587nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
588{
589 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
590 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
591 int i, j;
592
593 if (!ttm_dma || !ttm_dma->dma_address)
594 return;
595 if (!ttm_dma->pages) {
596 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
597 return;
598 }
599
600 /* Don't waste time looping if the object is coherent */
601 if (nvbo->force_coherent)
602 return;
603
604 i = 0;
605 while (i < ttm_dma->num_pages) {
606 struct page *p = ttm_dma->pages[i];
607 size_t num_pages = 1;
608
609 for (j = i + 1; j < ttm_dma->num_pages; ++j) {
610 if (++p != ttm_dma->pages[j])
611 break;
612
613 ++num_pages;
614 }
615
616 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
617 num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
618 i += num_pages;
619 }
620}
621
622void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
623{
624 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
625 struct nouveau_bo *nvbo = nouveau_bo(bo);
626
627 mutex_lock(&drm->ttm.io_reserve_mutex);
628 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
629 mutex_unlock(&drm->ttm.io_reserve_mutex);
630}
631
632void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
633{
634 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
635 struct nouveau_bo *nvbo = nouveau_bo(bo);
636
637 mutex_lock(&drm->ttm.io_reserve_mutex);
638 list_del_init(&nvbo->io_reserve_lru);
639 mutex_unlock(&drm->ttm.io_reserve_mutex);
640}
641
642int
643nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
644 bool no_wait_gpu)
645{
646 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
647 int ret;
648
649 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
650 if (ret)
651 return ret;
652
653 nouveau_bo_sync_for_device(nvbo);
654
655 return 0;
656}
657
658void
659nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
660{
661 bool is_iomem;
662 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
663
664 mem += index;
665
666 if (is_iomem)
667 iowrite16_native(val, (void __force __iomem *)mem);
668 else
669 *mem = val;
670}
671
672u32
673nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
674{
675 bool is_iomem;
676 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
677
678 mem += index;
679
680 if (is_iomem)
681 return ioread32_native((void __force __iomem *)mem);
682 else
683 return *mem;
684}
685
686void
687nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
688{
689 bool is_iomem;
690 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
691
692 mem += index;
693
694 if (is_iomem)
695 iowrite32_native(val, (void __force __iomem *)mem);
696 else
697 *mem = val;
698}
699
700static struct ttm_tt *
701nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
702{
703#if IS_ENABLED(CONFIG_AGP)
704 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
705
706 if (drm->agp.bridge) {
707 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
708 }
709#endif
710
711 return nouveau_sgdma_create_ttm(bo, page_flags);
712}
713
714static int
715nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
716 struct ttm_resource *reg)
717{
718#if IS_ENABLED(CONFIG_AGP)
719 struct nouveau_drm *drm = nouveau_bdev(bdev);
720#endif
721 if (!reg)
722 return -EINVAL;
723#if IS_ENABLED(CONFIG_AGP)
724 if (drm->agp.bridge)
725 return ttm_agp_bind(ttm, reg);
726#endif
727 return nouveau_sgdma_bind(bdev, ttm, reg);
728}
729
730static void
731nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
732{
733#if IS_ENABLED(CONFIG_AGP)
734 struct nouveau_drm *drm = nouveau_bdev(bdev);
735
736 if (drm->agp.bridge) {
737 ttm_agp_unbind(ttm);
738 return;
739 }
740#endif
741 nouveau_sgdma_unbind(bdev, ttm);
742}
743
744static void
745nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
746{
747 struct nouveau_bo *nvbo = nouveau_bo(bo);
748
749 switch (bo->resource->mem_type) {
750 case TTM_PL_VRAM:
751 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
752 NOUVEAU_GEM_DOMAIN_CPU);
753 break;
754 default:
755 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
756 break;
757 }
758
759 *pl = nvbo->placement;
760}
761
762static int
763nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
764 struct ttm_resource *reg)
765{
766 struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
767 struct nouveau_mem *new_mem = nouveau_mem(reg);
768 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
769 int ret;
770
771 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
772 old_mem->mem.size, &old_mem->vma[0]);
773 if (ret)
774 return ret;
775
776 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
777 new_mem->mem.size, &old_mem->vma[1]);
778 if (ret)
779 goto done;
780
781 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
782 if (ret)
783 goto done;
784
785 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
786done:
787 if (ret) {
788 nvif_vmm_put(vmm, &old_mem->vma[1]);
789 nvif_vmm_put(vmm, &old_mem->vma[0]);
790 }
791 return 0;
792}
793
794static int
795nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
796 struct ttm_operation_ctx *ctx,
797 struct ttm_resource *new_reg)
798{
799 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
800 struct nouveau_channel *chan = drm->ttm.chan;
801 struct nouveau_cli *cli = (void *)chan->user.client;
802 struct nouveau_fence *fence;
803 int ret;
804
805 /* create temporary vmas for the transfer and attach them to the
806 * old nvkm_mem node, these will get cleaned up after ttm has
807 * destroyed the ttm_resource
808 */
809 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
810 ret = nouveau_bo_move_prep(drm, bo, new_reg);
811 if (ret)
812 return ret;
813 }
814
815 if (drm_drv_uses_atomic_modeset(drm->dev))
816 mutex_lock(&cli->mutex);
817 else
818 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
819 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
820 if (ret == 0) {
821 ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
822 if (ret == 0) {
823 ret = nouveau_fence_new(chan, false, &fence);
824 if (ret == 0) {
825 /* TODO: figure out a better solution here
826 *
827 * wait on the fence here explicitly as going through
828 * ttm_bo_move_accel_cleanup somehow doesn't seem to do it.
829 *
830 * Without this the operation can timeout and we'll fallback to a
831 * software copy, which might take several minutes to finish.
832 */
833 nouveau_fence_wait(fence, false, false);
834 ret = ttm_bo_move_accel_cleanup(bo,
835 &fence->base,
836 evict, false,
837 new_reg);
838 nouveau_fence_unref(&fence);
839 }
840 }
841 }
842 mutex_unlock(&cli->mutex);
843 return ret;
844}
845
846void
847nouveau_bo_move_init(struct nouveau_drm *drm)
848{
849 static const struct _method_table {
850 const char *name;
851 int engine;
852 s32 oclass;
853 int (*exec)(struct nouveau_channel *,
854 struct ttm_buffer_object *,
855 struct ttm_resource *, struct ttm_resource *);
856 int (*init)(struct nouveau_channel *, u32 handle);
857 } _methods[] = {
858 { "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
859 { "GRCE", 0, 0xc7b5, nve0_bo_move_copy, nvc0_bo_move_init },
860 { "COPY", 4, 0xc6b5, nve0_bo_move_copy, nve0_bo_move_init },
861 { "GRCE", 0, 0xc6b5, nve0_bo_move_copy, nvc0_bo_move_init },
862 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
863 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
864 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
865 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
866 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
867 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
868 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
869 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
870 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
871 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
872 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
873 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
874 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
875 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
876 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
877 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
878 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
879 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
880 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
881 {},
882 };
883 const struct _method_table *mthd = _methods;
884 const char *name = "CPU";
885 int ret;
886
887 do {
888 struct nouveau_channel *chan;
889
890 if (mthd->engine)
891 chan = drm->cechan;
892 else
893 chan = drm->channel;
894 if (chan == NULL)
895 continue;
896
897 ret = nvif_object_ctor(&chan->user, "ttmBoMove",
898 mthd->oclass | (mthd->engine << 16),
899 mthd->oclass, NULL, 0,
900 &drm->ttm.copy);
901 if (ret == 0) {
902 ret = mthd->init(chan, drm->ttm.copy.handle);
903 if (ret) {
904 nvif_object_dtor(&drm->ttm.copy);
905 continue;
906 }
907
908 drm->ttm.move = mthd->exec;
909 drm->ttm.chan = chan;
910 name = mthd->name;
911 break;
912 }
913 } while ((++mthd)->exec);
914
915 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
916}
917
918static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
919 struct ttm_resource *new_reg)
920{
921 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
922 struct nouveau_bo *nvbo = nouveau_bo(bo);
923 struct nouveau_vma *vma;
924
925 /* ttm can now (stupidly) pass the driver bos it didn't create... */
926 if (bo->destroy != nouveau_bo_del_ttm)
927 return;
928
929 nouveau_bo_del_io_reserve_lru(bo);
930
931 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
932 mem->mem.page == nvbo->page) {
933 list_for_each_entry(vma, &nvbo->vma_list, head) {
934 nouveau_vma_map(vma, mem);
935 }
936 } else {
937 list_for_each_entry(vma, &nvbo->vma_list, head) {
938 WARN_ON(ttm_bo_wait(bo, false, false));
939 nouveau_vma_unmap(vma);
940 }
941 }
942
943 if (new_reg)
944 nvbo->offset = (new_reg->start << PAGE_SHIFT);
945
946}
947
948static int
949nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
950 struct nouveau_drm_tile **new_tile)
951{
952 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
953 struct drm_device *dev = drm->dev;
954 struct nouveau_bo *nvbo = nouveau_bo(bo);
955 u64 offset = new_reg->start << PAGE_SHIFT;
956
957 *new_tile = NULL;
958 if (new_reg->mem_type != TTM_PL_VRAM)
959 return 0;
960
961 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
962 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
963 nvbo->mode, nvbo->zeta);
964 }
965
966 return 0;
967}
968
969static void
970nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
971 struct nouveau_drm_tile *new_tile,
972 struct nouveau_drm_tile **old_tile)
973{
974 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
975 struct drm_device *dev = drm->dev;
976 struct dma_fence *fence;
977 int ret;
978
979 ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
980 &fence);
981 if (ret)
982 dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
983 false, MAX_SCHEDULE_TIMEOUT);
984
985 nv10_bo_put_tile_region(dev, *old_tile, fence);
986 *old_tile = new_tile;
987}
988
989static int
990nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
991 struct ttm_operation_ctx *ctx,
992 struct ttm_resource *new_reg,
993 struct ttm_place *hop)
994{
995 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
996 struct nouveau_bo *nvbo = nouveau_bo(bo);
997 struct ttm_resource *old_reg = bo->resource;
998 struct nouveau_drm_tile *new_tile = NULL;
999 int ret = 0;
1000
1001
1002 if (new_reg->mem_type == TTM_PL_TT) {
1003 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
1004 if (ret)
1005 return ret;
1006 }
1007
1008 nouveau_bo_move_ntfy(bo, new_reg);
1009 ret = ttm_bo_wait_ctx(bo, ctx);
1010 if (ret)
1011 goto out_ntfy;
1012
1013 if (nvbo->bo.pin_count)
1014 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1015
1016 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1017 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1018 if (ret)
1019 goto out_ntfy;
1020 }
1021
1022 /* Fake bo copy. */
1023 if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1024 !bo->ttm)) {
1025 ttm_bo_move_null(bo, new_reg);
1026 goto out;
1027 }
1028
1029 if (old_reg->mem_type == TTM_PL_SYSTEM &&
1030 new_reg->mem_type == TTM_PL_TT) {
1031 ttm_bo_move_null(bo, new_reg);
1032 goto out;
1033 }
1034
1035 if (old_reg->mem_type == TTM_PL_TT &&
1036 new_reg->mem_type == TTM_PL_SYSTEM) {
1037 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1038 ttm_resource_free(bo, &bo->resource);
1039 ttm_bo_assign_mem(bo, new_reg);
1040 goto out;
1041 }
1042
1043 /* Hardware assisted copy. */
1044 if (drm->ttm.move) {
1045 if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1046 new_reg->mem_type == TTM_PL_VRAM) ||
1047 (old_reg->mem_type == TTM_PL_VRAM &&
1048 new_reg->mem_type == TTM_PL_SYSTEM)) {
1049 hop->fpfn = 0;
1050 hop->lpfn = 0;
1051 hop->mem_type = TTM_PL_TT;
1052 hop->flags = 0;
1053 return -EMULTIHOP;
1054 }
1055 ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1056 new_reg);
1057 } else
1058 ret = -ENODEV;
1059
1060 if (ret) {
1061 /* Fallback to software copy. */
1062 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1063 }
1064
1065out:
1066 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1067 if (ret)
1068 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1069 else
1070 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1071 }
1072out_ntfy:
1073 if (ret) {
1074 nouveau_bo_move_ntfy(bo, bo->resource);
1075 }
1076 return ret;
1077}
1078
1079static void
1080nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1081 struct ttm_resource *reg)
1082{
1083 struct nouveau_mem *mem = nouveau_mem(reg);
1084
1085 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1086 switch (reg->mem_type) {
1087 case TTM_PL_TT:
1088 if (mem->kind)
1089 nvif_object_unmap_handle(&mem->mem.object);
1090 break;
1091 case TTM_PL_VRAM:
1092 nvif_object_unmap_handle(&mem->mem.object);
1093 break;
1094 default:
1095 break;
1096 }
1097 }
1098}
1099
1100static int
1101nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1102{
1103 struct nouveau_drm *drm = nouveau_bdev(bdev);
1104 struct nvkm_device *device = nvxx_device(&drm->client.device);
1105 struct nouveau_mem *mem = nouveau_mem(reg);
1106 struct nvif_mmu *mmu = &drm->client.mmu;
1107 int ret;
1108
1109 mutex_lock(&drm->ttm.io_reserve_mutex);
1110retry:
1111 switch (reg->mem_type) {
1112 case TTM_PL_SYSTEM:
1113 /* System memory */
1114 ret = 0;
1115 goto out;
1116 case TTM_PL_TT:
1117#if IS_ENABLED(CONFIG_AGP)
1118 if (drm->agp.bridge) {
1119 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1120 drm->agp.base;
1121 reg->bus.is_iomem = !drm->agp.cma;
1122 reg->bus.caching = ttm_write_combined;
1123 }
1124#endif
1125 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1126 !mem->kind) {
1127 /* untiled */
1128 ret = 0;
1129 break;
1130 }
1131 fallthrough; /* tiled memory */
1132 case TTM_PL_VRAM:
1133 reg->bus.offset = (reg->start << PAGE_SHIFT) +
1134 device->func->resource_addr(device, 1);
1135 reg->bus.is_iomem = true;
1136
1137 /* Some BARs do not support being ioremapped WC */
1138 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1139 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1140 reg->bus.caching = ttm_uncached;
1141 else
1142 reg->bus.caching = ttm_write_combined;
1143
1144 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1145 union {
1146 struct nv50_mem_map_v0 nv50;
1147 struct gf100_mem_map_v0 gf100;
1148 } args;
1149 u64 handle, length;
1150 u32 argc = 0;
1151
1152 switch (mem->mem.object.oclass) {
1153 case NVIF_CLASS_MEM_NV50:
1154 args.nv50.version = 0;
1155 args.nv50.ro = 0;
1156 args.nv50.kind = mem->kind;
1157 args.nv50.comp = mem->comp;
1158 argc = sizeof(args.nv50);
1159 break;
1160 case NVIF_CLASS_MEM_GF100:
1161 args.gf100.version = 0;
1162 args.gf100.ro = 0;
1163 args.gf100.kind = mem->kind;
1164 argc = sizeof(args.gf100);
1165 break;
1166 default:
1167 WARN_ON(1);
1168 break;
1169 }
1170
1171 ret = nvif_object_map_handle(&mem->mem.object,
1172 &args, argc,
1173 &handle, &length);
1174 if (ret != 1) {
1175 if (WARN_ON(ret == 0))
1176 ret = -EINVAL;
1177 goto out;
1178 }
1179
1180 reg->bus.offset = handle;
1181 }
1182 ret = 0;
1183 break;
1184 default:
1185 ret = -EINVAL;
1186 }
1187
1188out:
1189 if (ret == -ENOSPC) {
1190 struct nouveau_bo *nvbo;
1191
1192 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1193 typeof(*nvbo),
1194 io_reserve_lru);
1195 if (nvbo) {
1196 list_del_init(&nvbo->io_reserve_lru);
1197 drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1198 bdev->dev_mapping);
1199 nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1200 goto retry;
1201 }
1202
1203 }
1204 mutex_unlock(&drm->ttm.io_reserve_mutex);
1205 return ret;
1206}
1207
1208static void
1209nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1210{
1211 struct nouveau_drm *drm = nouveau_bdev(bdev);
1212
1213 mutex_lock(&drm->ttm.io_reserve_mutex);
1214 nouveau_ttm_io_mem_free_locked(drm, reg);
1215 mutex_unlock(&drm->ttm.io_reserve_mutex);
1216}
1217
1218vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1219{
1220 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1221 struct nouveau_bo *nvbo = nouveau_bo(bo);
1222 struct nvkm_device *device = nvxx_device(&drm->client.device);
1223 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1224 int i, ret;
1225
1226 /* as long as the bo isn't in vram, and isn't tiled, we've got
1227 * nothing to do here.
1228 */
1229 if (bo->resource->mem_type != TTM_PL_VRAM) {
1230 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1231 !nvbo->kind)
1232 return 0;
1233
1234 if (bo->resource->mem_type != TTM_PL_SYSTEM)
1235 return 0;
1236
1237 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1238
1239 } else {
1240 /* make sure bo is in mappable vram */
1241 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1242 bo->resource->start + PFN_UP(bo->resource->size) < mappable)
1243 return 0;
1244
1245 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1246 nvbo->placements[i].fpfn = 0;
1247 nvbo->placements[i].lpfn = mappable;
1248 }
1249
1250 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1251 nvbo->busy_placements[i].fpfn = 0;
1252 nvbo->busy_placements[i].lpfn = mappable;
1253 }
1254
1255 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1256 }
1257
1258 ret = nouveau_bo_validate(nvbo, false, false);
1259 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1260 return VM_FAULT_NOPAGE;
1261 else if (unlikely(ret))
1262 return VM_FAULT_SIGBUS;
1263
1264 ttm_bo_move_to_lru_tail_unlocked(bo);
1265 return 0;
1266}
1267
1268static int
1269nouveau_ttm_tt_populate(struct ttm_device *bdev,
1270 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1271{
1272 struct ttm_tt *ttm_dma = (void *)ttm;
1273 struct nouveau_drm *drm;
1274 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1275
1276 if (ttm_tt_is_populated(ttm))
1277 return 0;
1278
1279 if (slave && ttm->sg) {
1280 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1281 ttm->num_pages);
1282 return 0;
1283 }
1284
1285 drm = nouveau_bdev(bdev);
1286
1287 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1288}
1289
1290static void
1291nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1292 struct ttm_tt *ttm)
1293{
1294 struct nouveau_drm *drm;
1295 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1296
1297 if (slave)
1298 return;
1299
1300 nouveau_ttm_tt_unbind(bdev, ttm);
1301
1302 drm = nouveau_bdev(bdev);
1303
1304 return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1305}
1306
1307static void
1308nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1309 struct ttm_tt *ttm)
1310{
1311#if IS_ENABLED(CONFIG_AGP)
1312 struct nouveau_drm *drm = nouveau_bdev(bdev);
1313 if (drm->agp.bridge) {
1314 ttm_agp_destroy(ttm);
1315 return;
1316 }
1317#endif
1318 nouveau_sgdma_destroy(bdev, ttm);
1319}
1320
1321void
1322nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1323{
1324 struct dma_resv *resv = nvbo->bo.base.resv;
1325
1326 if (!fence)
1327 return;
1328
1329 dma_resv_add_fence(resv, &fence->base, exclusive ?
1330 DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1331}
1332
1333static void
1334nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1335{
1336 nouveau_bo_move_ntfy(bo, NULL);
1337}
1338
1339struct ttm_device_funcs nouveau_bo_driver = {
1340 .ttm_tt_create = &nouveau_ttm_tt_create,
1341 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1342 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1343 .ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1344 .eviction_valuable = ttm_bo_eviction_valuable,
1345 .evict_flags = nouveau_bo_evict_flags,
1346 .delete_mem_notify = nouveau_bo_delete_mem_notify,
1347 .move = nouveau_bo_move,
1348 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1349 .io_mem_free = &nouveau_ttm_io_mem_free,
1350};