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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <linux/swiotlb.h>
32
33#include "nouveau_drm.h"
34#include "nouveau_dma.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40
41/*
42 * NV10-NV40 tiling helpers
43 */
44
45static void
46nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
47 u32 addr, u32 size, u32 pitch, u32 flags)
48{
49 struct nouveau_drm *drm = nouveau_drm(dev);
50 int i = reg - drm->tile.reg;
51 struct nvkm_device *device = nvxx_device(&drm->device);
52 struct nvkm_fb *fb = device->fb;
53 struct nvkm_fb_tile *tile = &fb->tile.region[i];
54
55 nouveau_fence_unref(®->fence);
56
57 if (tile->pitch)
58 nvkm_fb_tile_fini(fb, i, tile);
59
60 if (pitch)
61 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
62
63 nvkm_fb_tile_prog(fb, i, tile);
64}
65
66static struct nouveau_drm_tile *
67nv10_bo_get_tile_region(struct drm_device *dev, int i)
68{
69 struct nouveau_drm *drm = nouveau_drm(dev);
70 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
71
72 spin_lock(&drm->tile.lock);
73
74 if (!tile->used &&
75 (!tile->fence || nouveau_fence_done(tile->fence)))
76 tile->used = true;
77 else
78 tile = NULL;
79
80 spin_unlock(&drm->tile.lock);
81 return tile;
82}
83
84static void
85nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
86 struct fence *fence)
87{
88 struct nouveau_drm *drm = nouveau_drm(dev);
89
90 if (tile) {
91 spin_lock(&drm->tile.lock);
92 tile->fence = (struct nouveau_fence *)fence_get(fence);
93 tile->used = false;
94 spin_unlock(&drm->tile.lock);
95 }
96}
97
98static struct nouveau_drm_tile *
99nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
100 u32 size, u32 pitch, u32 flags)
101{
102 struct nouveau_drm *drm = nouveau_drm(dev);
103 struct nvkm_fb *fb = nvxx_fb(&drm->device);
104 struct nouveau_drm_tile *tile, *found = NULL;
105 int i;
106
107 for (i = 0; i < fb->tile.regions; i++) {
108 tile = nv10_bo_get_tile_region(dev, i);
109
110 if (pitch && !found) {
111 found = tile;
112 continue;
113
114 } else if (tile && fb->tile.region[i].pitch) {
115 /* Kill an unused tile region. */
116 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
117 }
118
119 nv10_bo_put_tile_region(dev, tile, NULL);
120 }
121
122 if (found)
123 nv10_bo_update_tile_region(dev, found, addr, size,
124 pitch, flags);
125 return found;
126}
127
128static void
129nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
130{
131 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
132 struct drm_device *dev = drm->dev;
133 struct nouveau_bo *nvbo = nouveau_bo(bo);
134
135 if (unlikely(nvbo->gem.filp))
136 DRM_ERROR("bo %p still attached to GEM object\n", bo);
137 WARN_ON(nvbo->pin_refcnt > 0);
138 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
139 kfree(nvbo);
140}
141
142static void
143nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
144 int *align, int *size)
145{
146 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
147 struct nvif_device *device = &drm->device;
148
149 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
150 if (nvbo->tile_mode) {
151 if (device->info.chipset >= 0x40) {
152 *align = 65536;
153 *size = roundup(*size, 64 * nvbo->tile_mode);
154
155 } else if (device->info.chipset >= 0x30) {
156 *align = 32768;
157 *size = roundup(*size, 64 * nvbo->tile_mode);
158
159 } else if (device->info.chipset >= 0x20) {
160 *align = 16384;
161 *size = roundup(*size, 64 * nvbo->tile_mode);
162
163 } else if (device->info.chipset >= 0x10) {
164 *align = 16384;
165 *size = roundup(*size, 32 * nvbo->tile_mode);
166 }
167 }
168 } else {
169 *size = roundup(*size, (1 << nvbo->page_shift));
170 *align = max((1 << nvbo->page_shift), *align);
171 }
172
173 *size = roundup(*size, PAGE_SIZE);
174}
175
176int
177nouveau_bo_new(struct drm_device *dev, int size, int align,
178 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
179 struct sg_table *sg, struct reservation_object *robj,
180 struct nouveau_bo **pnvbo)
181{
182 struct nouveau_drm *drm = nouveau_drm(dev);
183 struct nouveau_bo *nvbo;
184 size_t acc_size;
185 int ret;
186 int type = ttm_bo_type_device;
187 int lpg_shift = 12;
188 int max_size;
189
190 if (drm->client.vm)
191 lpg_shift = drm->client.vm->mmu->lpg_shift;
192 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
193
194 if (size <= 0 || size > max_size) {
195 NV_WARN(drm, "skipped size %x\n", (u32)size);
196 return -EINVAL;
197 }
198
199 if (sg)
200 type = ttm_bo_type_sg;
201
202 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
203 if (!nvbo)
204 return -ENOMEM;
205 INIT_LIST_HEAD(&nvbo->head);
206 INIT_LIST_HEAD(&nvbo->entry);
207 INIT_LIST_HEAD(&nvbo->vma_list);
208 nvbo->tile_mode = tile_mode;
209 nvbo->tile_flags = tile_flags;
210 nvbo->bo.bdev = &drm->ttm.bdev;
211
212 if (!nvxx_device(&drm->device)->func->cpu_coherent)
213 nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
214
215 nvbo->page_shift = 12;
216 if (drm->client.vm) {
217 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
218 nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
219 }
220
221 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
222 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
223 nouveau_bo_placement_set(nvbo, flags, 0);
224
225 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
226 sizeof(struct nouveau_bo));
227
228 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
229 type, &nvbo->placement,
230 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
231 robj, nouveau_bo_del_ttm);
232 if (ret) {
233 /* ttm will call nouveau_bo_del_ttm if it fails.. */
234 return ret;
235 }
236
237 *pnvbo = nvbo;
238 return 0;
239}
240
241static void
242set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
243{
244 *n = 0;
245
246 if (type & TTM_PL_FLAG_VRAM)
247 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
248 if (type & TTM_PL_FLAG_TT)
249 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
250 if (type & TTM_PL_FLAG_SYSTEM)
251 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
252}
253
254static void
255set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
256{
257 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
258 u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT;
259 unsigned i, fpfn, lpfn;
260
261 if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
262 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
263 nvbo->bo.mem.num_pages < vram_pages / 4) {
264 /*
265 * Make sure that the color and depth buffers are handled
266 * by independent memory controller units. Up to a 9x
267 * speed up when alpha-blending and depth-test are enabled
268 * at the same time.
269 */
270 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
271 fpfn = vram_pages / 2;
272 lpfn = ~0;
273 } else {
274 fpfn = 0;
275 lpfn = vram_pages / 2;
276 }
277 for (i = 0; i < nvbo->placement.num_placement; ++i) {
278 nvbo->placements[i].fpfn = fpfn;
279 nvbo->placements[i].lpfn = lpfn;
280 }
281 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
282 nvbo->busy_placements[i].fpfn = fpfn;
283 nvbo->busy_placements[i].lpfn = lpfn;
284 }
285 }
286}
287
288void
289nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
290{
291 struct ttm_placement *pl = &nvbo->placement;
292 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
293 TTM_PL_MASK_CACHING) |
294 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
295
296 pl->placement = nvbo->placements;
297 set_placement_list(nvbo->placements, &pl->num_placement,
298 type, flags);
299
300 pl->busy_placement = nvbo->busy_placements;
301 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
302 type | busy, flags);
303
304 set_placement_range(nvbo, type);
305}
306
307int
308nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
309{
310 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
311 struct ttm_buffer_object *bo = &nvbo->bo;
312 bool force = false, evict = false;
313 int ret;
314
315 ret = ttm_bo_reserve(bo, false, false, false, NULL);
316 if (ret)
317 return ret;
318
319 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
320 memtype == TTM_PL_FLAG_VRAM && contig) {
321 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
322 if (bo->mem.mem_type == TTM_PL_VRAM) {
323 struct nvkm_mem *mem = bo->mem.mm_node;
324 if (!list_is_singular(&mem->regions))
325 evict = true;
326 }
327 nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG;
328 force = true;
329 }
330 }
331
332 if (nvbo->pin_refcnt) {
333 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
334 NV_ERROR(drm, "bo %p pinned elsewhere: "
335 "0x%08x vs 0x%08x\n", bo,
336 1 << bo->mem.mem_type, memtype);
337 ret = -EBUSY;
338 }
339 nvbo->pin_refcnt++;
340 goto out;
341 }
342
343 if (evict) {
344 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
345 ret = nouveau_bo_validate(nvbo, false, false);
346 if (ret)
347 goto out;
348 }
349
350 nvbo->pin_refcnt++;
351 nouveau_bo_placement_set(nvbo, memtype, 0);
352
353 /* drop pin_refcnt temporarily, so we don't trip the assertion
354 * in nouveau_bo_move() that makes sure we're not trying to
355 * move a pinned buffer
356 */
357 nvbo->pin_refcnt--;
358 ret = nouveau_bo_validate(nvbo, false, false);
359 if (ret)
360 goto out;
361 nvbo->pin_refcnt++;
362
363 switch (bo->mem.mem_type) {
364 case TTM_PL_VRAM:
365 drm->gem.vram_available -= bo->mem.size;
366 break;
367 case TTM_PL_TT:
368 drm->gem.gart_available -= bo->mem.size;
369 break;
370 default:
371 break;
372 }
373
374out:
375 if (force && ret)
376 nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG;
377 ttm_bo_unreserve(bo);
378 return ret;
379}
380
381int
382nouveau_bo_unpin(struct nouveau_bo *nvbo)
383{
384 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
385 struct ttm_buffer_object *bo = &nvbo->bo;
386 int ret, ref;
387
388 ret = ttm_bo_reserve(bo, false, false, false, NULL);
389 if (ret)
390 return ret;
391
392 ref = --nvbo->pin_refcnt;
393 WARN_ON_ONCE(ref < 0);
394 if (ref)
395 goto out;
396
397 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
398
399 ret = nouveau_bo_validate(nvbo, false, false);
400 if (ret == 0) {
401 switch (bo->mem.mem_type) {
402 case TTM_PL_VRAM:
403 drm->gem.vram_available += bo->mem.size;
404 break;
405 case TTM_PL_TT:
406 drm->gem.gart_available += bo->mem.size;
407 break;
408 default:
409 break;
410 }
411 }
412
413out:
414 ttm_bo_unreserve(bo);
415 return ret;
416}
417
418int
419nouveau_bo_map(struct nouveau_bo *nvbo)
420{
421 int ret;
422
423 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL);
424 if (ret)
425 return ret;
426
427 /*
428 * TTM buffers allocated using the DMA API already have a mapping, let's
429 * use it instead.
430 */
431 if (!nvbo->force_coherent)
432 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages,
433 &nvbo->kmap);
434
435 ttm_bo_unreserve(&nvbo->bo);
436 return ret;
437}
438
439void
440nouveau_bo_unmap(struct nouveau_bo *nvbo)
441{
442 if (!nvbo)
443 return;
444
445 /*
446 * TTM buffers allocated using the DMA API already had a coherent
447 * mapping which we used, no need to unmap.
448 */
449 if (!nvbo->force_coherent)
450 ttm_bo_kunmap(&nvbo->kmap);
451}
452
453void
454nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
455{
456 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
457 struct nvkm_device *device = nvxx_device(&drm->device);
458 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
459 int i;
460
461 if (!ttm_dma)
462 return;
463
464 /* Don't waste time looping if the object is coherent */
465 if (nvbo->force_coherent)
466 return;
467
468 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
469 dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i],
470 PAGE_SIZE, DMA_TO_DEVICE);
471}
472
473void
474nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
475{
476 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
477 struct nvkm_device *device = nvxx_device(&drm->device);
478 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
479 int i;
480
481 if (!ttm_dma)
482 return;
483
484 /* Don't waste time looping if the object is coherent */
485 if (nvbo->force_coherent)
486 return;
487
488 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
489 dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i],
490 PAGE_SIZE, DMA_FROM_DEVICE);
491}
492
493int
494nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
495 bool no_wait_gpu)
496{
497 int ret;
498
499 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
500 interruptible, no_wait_gpu);
501 if (ret)
502 return ret;
503
504 nouveau_bo_sync_for_device(nvbo);
505
506 return 0;
507}
508
509static inline void *
510_nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)
511{
512 struct ttm_dma_tt *dma_tt;
513 u8 *m = mem;
514
515 index *= sz;
516
517 if (m) {
518 /* kmap'd address, return the corresponding offset */
519 m += index;
520 } else {
521 /* DMA-API mapping, lookup the right address */
522 dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm;
523 m = dma_tt->cpu_address[index / PAGE_SIZE];
524 m += index % PAGE_SIZE;
525 }
526
527 return m;
528}
529#define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
530
531void
532nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
533{
534 bool is_iomem;
535 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
536
537 mem = nouveau_bo_mem_index(nvbo, index, mem);
538
539 if (is_iomem)
540 iowrite16_native(val, (void __force __iomem *)mem);
541 else
542 *mem = val;
543}
544
545u32
546nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
547{
548 bool is_iomem;
549 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
550
551 mem = nouveau_bo_mem_index(nvbo, index, mem);
552
553 if (is_iomem)
554 return ioread32_native((void __force __iomem *)mem);
555 else
556 return *mem;
557}
558
559void
560nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
561{
562 bool is_iomem;
563 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
564
565 mem = nouveau_bo_mem_index(nvbo, index, mem);
566
567 if (is_iomem)
568 iowrite32_native(val, (void __force __iomem *)mem);
569 else
570 *mem = val;
571}
572
573static struct ttm_tt *
574nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
575 uint32_t page_flags, struct page *dummy_read)
576{
577#if IS_ENABLED(CONFIG_AGP)
578 struct nouveau_drm *drm = nouveau_bdev(bdev);
579
580 if (drm->agp.bridge) {
581 return ttm_agp_tt_create(bdev, drm->agp.bridge, size,
582 page_flags, dummy_read);
583 }
584#endif
585
586 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
587}
588
589static int
590nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
591{
592 /* We'll do this from user space. */
593 return 0;
594}
595
596static int
597nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
598 struct ttm_mem_type_manager *man)
599{
600 struct nouveau_drm *drm = nouveau_bdev(bdev);
601
602 switch (type) {
603 case TTM_PL_SYSTEM:
604 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
605 man->available_caching = TTM_PL_MASK_CACHING;
606 man->default_caching = TTM_PL_FLAG_CACHED;
607 break;
608 case TTM_PL_VRAM:
609 man->flags = TTM_MEMTYPE_FLAG_FIXED |
610 TTM_MEMTYPE_FLAG_MAPPABLE;
611 man->available_caching = TTM_PL_FLAG_UNCACHED |
612 TTM_PL_FLAG_WC;
613 man->default_caching = TTM_PL_FLAG_WC;
614
615 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
616 /* Some BARs do not support being ioremapped WC */
617 if (nvxx_bar(&drm->device)->iomap_uncached) {
618 man->available_caching = TTM_PL_FLAG_UNCACHED;
619 man->default_caching = TTM_PL_FLAG_UNCACHED;
620 }
621
622 man->func = &nouveau_vram_manager;
623 man->io_reserve_fastpath = false;
624 man->use_io_reserve_lru = true;
625 } else {
626 man->func = &ttm_bo_manager_func;
627 }
628 break;
629 case TTM_PL_TT:
630 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
631 man->func = &nouveau_gart_manager;
632 else
633 if (!drm->agp.bridge)
634 man->func = &nv04_gart_manager;
635 else
636 man->func = &ttm_bo_manager_func;
637
638 if (drm->agp.bridge) {
639 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
640 man->available_caching = TTM_PL_FLAG_UNCACHED |
641 TTM_PL_FLAG_WC;
642 man->default_caching = TTM_PL_FLAG_WC;
643 } else {
644 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
645 TTM_MEMTYPE_FLAG_CMA;
646 man->available_caching = TTM_PL_MASK_CACHING;
647 man->default_caching = TTM_PL_FLAG_CACHED;
648 }
649
650 break;
651 default:
652 return -EINVAL;
653 }
654 return 0;
655}
656
657static void
658nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
659{
660 struct nouveau_bo *nvbo = nouveau_bo(bo);
661
662 switch (bo->mem.mem_type) {
663 case TTM_PL_VRAM:
664 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
665 TTM_PL_FLAG_SYSTEM);
666 break;
667 default:
668 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
669 break;
670 }
671
672 *pl = nvbo->placement;
673}
674
675
676static int
677nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
678{
679 int ret = RING_SPACE(chan, 2);
680 if (ret == 0) {
681 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
682 OUT_RING (chan, handle & 0x0000ffff);
683 FIRE_RING (chan);
684 }
685 return ret;
686}
687
688static int
689nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
690 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
691{
692 struct nvkm_mem *node = old_mem->mm_node;
693 int ret = RING_SPACE(chan, 10);
694 if (ret == 0) {
695 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
696 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
697 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
698 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
699 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
700 OUT_RING (chan, PAGE_SIZE);
701 OUT_RING (chan, PAGE_SIZE);
702 OUT_RING (chan, PAGE_SIZE);
703 OUT_RING (chan, new_mem->num_pages);
704 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
705 }
706 return ret;
707}
708
709static int
710nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
711{
712 int ret = RING_SPACE(chan, 2);
713 if (ret == 0) {
714 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
715 OUT_RING (chan, handle);
716 }
717 return ret;
718}
719
720static int
721nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
722 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
723{
724 struct nvkm_mem *node = old_mem->mm_node;
725 u64 src_offset = node->vma[0].offset;
726 u64 dst_offset = node->vma[1].offset;
727 u32 page_count = new_mem->num_pages;
728 int ret;
729
730 page_count = new_mem->num_pages;
731 while (page_count) {
732 int line_count = (page_count > 8191) ? 8191 : page_count;
733
734 ret = RING_SPACE(chan, 11);
735 if (ret)
736 return ret;
737
738 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
739 OUT_RING (chan, upper_32_bits(src_offset));
740 OUT_RING (chan, lower_32_bits(src_offset));
741 OUT_RING (chan, upper_32_bits(dst_offset));
742 OUT_RING (chan, lower_32_bits(dst_offset));
743 OUT_RING (chan, PAGE_SIZE);
744 OUT_RING (chan, PAGE_SIZE);
745 OUT_RING (chan, PAGE_SIZE);
746 OUT_RING (chan, line_count);
747 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
748 OUT_RING (chan, 0x00000110);
749
750 page_count -= line_count;
751 src_offset += (PAGE_SIZE * line_count);
752 dst_offset += (PAGE_SIZE * line_count);
753 }
754
755 return 0;
756}
757
758static int
759nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
760 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
761{
762 struct nvkm_mem *node = old_mem->mm_node;
763 u64 src_offset = node->vma[0].offset;
764 u64 dst_offset = node->vma[1].offset;
765 u32 page_count = new_mem->num_pages;
766 int ret;
767
768 page_count = new_mem->num_pages;
769 while (page_count) {
770 int line_count = (page_count > 2047) ? 2047 : page_count;
771
772 ret = RING_SPACE(chan, 12);
773 if (ret)
774 return ret;
775
776 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
777 OUT_RING (chan, upper_32_bits(dst_offset));
778 OUT_RING (chan, lower_32_bits(dst_offset));
779 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
780 OUT_RING (chan, upper_32_bits(src_offset));
781 OUT_RING (chan, lower_32_bits(src_offset));
782 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
783 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
784 OUT_RING (chan, PAGE_SIZE); /* line_length */
785 OUT_RING (chan, line_count);
786 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
787 OUT_RING (chan, 0x00100110);
788
789 page_count -= line_count;
790 src_offset += (PAGE_SIZE * line_count);
791 dst_offset += (PAGE_SIZE * line_count);
792 }
793
794 return 0;
795}
796
797static int
798nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
799 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
800{
801 struct nvkm_mem *node = old_mem->mm_node;
802 u64 src_offset = node->vma[0].offset;
803 u64 dst_offset = node->vma[1].offset;
804 u32 page_count = new_mem->num_pages;
805 int ret;
806
807 page_count = new_mem->num_pages;
808 while (page_count) {
809 int line_count = (page_count > 8191) ? 8191 : page_count;
810
811 ret = RING_SPACE(chan, 11);
812 if (ret)
813 return ret;
814
815 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
816 OUT_RING (chan, upper_32_bits(src_offset));
817 OUT_RING (chan, lower_32_bits(src_offset));
818 OUT_RING (chan, upper_32_bits(dst_offset));
819 OUT_RING (chan, lower_32_bits(dst_offset));
820 OUT_RING (chan, PAGE_SIZE);
821 OUT_RING (chan, PAGE_SIZE);
822 OUT_RING (chan, PAGE_SIZE);
823 OUT_RING (chan, line_count);
824 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
825 OUT_RING (chan, 0x00000110);
826
827 page_count -= line_count;
828 src_offset += (PAGE_SIZE * line_count);
829 dst_offset += (PAGE_SIZE * line_count);
830 }
831
832 return 0;
833}
834
835static int
836nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
837 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
838{
839 struct nvkm_mem *node = old_mem->mm_node;
840 int ret = RING_SPACE(chan, 7);
841 if (ret == 0) {
842 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
843 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
844 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
845 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
846 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
847 OUT_RING (chan, 0x00000000 /* COPY */);
848 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
849 }
850 return ret;
851}
852
853static int
854nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
855 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
856{
857 struct nvkm_mem *node = old_mem->mm_node;
858 int ret = RING_SPACE(chan, 7);
859 if (ret == 0) {
860 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
861 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
862 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
863 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
864 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
865 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
866 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
867 }
868 return ret;
869}
870
871static int
872nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
873{
874 int ret = RING_SPACE(chan, 6);
875 if (ret == 0) {
876 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
877 OUT_RING (chan, handle);
878 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
879 OUT_RING (chan, chan->drm->ntfy.handle);
880 OUT_RING (chan, chan->vram.handle);
881 OUT_RING (chan, chan->vram.handle);
882 }
883
884 return ret;
885}
886
887static int
888nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
889 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
890{
891 struct nvkm_mem *node = old_mem->mm_node;
892 u64 length = (new_mem->num_pages << PAGE_SHIFT);
893 u64 src_offset = node->vma[0].offset;
894 u64 dst_offset = node->vma[1].offset;
895 int src_tiled = !!node->memtype;
896 int dst_tiled = !!((struct nvkm_mem *)new_mem->mm_node)->memtype;
897 int ret;
898
899 while (length) {
900 u32 amount, stride, height;
901
902 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
903 if (ret)
904 return ret;
905
906 amount = min(length, (u64)(4 * 1024 * 1024));
907 stride = 16 * 4;
908 height = amount / stride;
909
910 if (src_tiled) {
911 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
912 OUT_RING (chan, 0);
913 OUT_RING (chan, 0);
914 OUT_RING (chan, stride);
915 OUT_RING (chan, height);
916 OUT_RING (chan, 1);
917 OUT_RING (chan, 0);
918 OUT_RING (chan, 0);
919 } else {
920 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
921 OUT_RING (chan, 1);
922 }
923 if (dst_tiled) {
924 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
925 OUT_RING (chan, 0);
926 OUT_RING (chan, 0);
927 OUT_RING (chan, stride);
928 OUT_RING (chan, height);
929 OUT_RING (chan, 1);
930 OUT_RING (chan, 0);
931 OUT_RING (chan, 0);
932 } else {
933 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
934 OUT_RING (chan, 1);
935 }
936
937 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
938 OUT_RING (chan, upper_32_bits(src_offset));
939 OUT_RING (chan, upper_32_bits(dst_offset));
940 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
941 OUT_RING (chan, lower_32_bits(src_offset));
942 OUT_RING (chan, lower_32_bits(dst_offset));
943 OUT_RING (chan, stride);
944 OUT_RING (chan, stride);
945 OUT_RING (chan, stride);
946 OUT_RING (chan, height);
947 OUT_RING (chan, 0x00000101);
948 OUT_RING (chan, 0x00000000);
949 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
950 OUT_RING (chan, 0);
951
952 length -= amount;
953 src_offset += amount;
954 dst_offset += amount;
955 }
956
957 return 0;
958}
959
960static int
961nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
962{
963 int ret = RING_SPACE(chan, 4);
964 if (ret == 0) {
965 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
966 OUT_RING (chan, handle);
967 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
968 OUT_RING (chan, chan->drm->ntfy.handle);
969 }
970
971 return ret;
972}
973
974static inline uint32_t
975nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
976 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
977{
978 if (mem->mem_type == TTM_PL_TT)
979 return NvDmaTT;
980 return chan->vram.handle;
981}
982
983static int
984nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
985 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
986{
987 u32 src_offset = old_mem->start << PAGE_SHIFT;
988 u32 dst_offset = new_mem->start << PAGE_SHIFT;
989 u32 page_count = new_mem->num_pages;
990 int ret;
991
992 ret = RING_SPACE(chan, 3);
993 if (ret)
994 return ret;
995
996 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
997 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
998 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
999
1000 page_count = new_mem->num_pages;
1001 while (page_count) {
1002 int line_count = (page_count > 2047) ? 2047 : page_count;
1003
1004 ret = RING_SPACE(chan, 11);
1005 if (ret)
1006 return ret;
1007
1008 BEGIN_NV04(chan, NvSubCopy,
1009 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1010 OUT_RING (chan, src_offset);
1011 OUT_RING (chan, dst_offset);
1012 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
1013 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
1014 OUT_RING (chan, PAGE_SIZE); /* line_length */
1015 OUT_RING (chan, line_count);
1016 OUT_RING (chan, 0x00000101);
1017 OUT_RING (chan, 0x00000000);
1018 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1019 OUT_RING (chan, 0);
1020
1021 page_count -= line_count;
1022 src_offset += (PAGE_SIZE * line_count);
1023 dst_offset += (PAGE_SIZE * line_count);
1024 }
1025
1026 return 0;
1027}
1028
1029static int
1030nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1031 struct ttm_mem_reg *mem)
1032{
1033 struct nvkm_mem *old_node = bo->mem.mm_node;
1034 struct nvkm_mem *new_node = mem->mm_node;
1035 u64 size = (u64)mem->num_pages << PAGE_SHIFT;
1036 int ret;
1037
1038 ret = nvkm_vm_get(drm->client.vm, size, old_node->page_shift,
1039 NV_MEM_ACCESS_RW, &old_node->vma[0]);
1040 if (ret)
1041 return ret;
1042
1043 ret = nvkm_vm_get(drm->client.vm, size, new_node->page_shift,
1044 NV_MEM_ACCESS_RW, &old_node->vma[1]);
1045 if (ret) {
1046 nvkm_vm_put(&old_node->vma[0]);
1047 return ret;
1048 }
1049
1050 nvkm_vm_map(&old_node->vma[0], old_node);
1051 nvkm_vm_map(&old_node->vma[1], new_node);
1052 return 0;
1053}
1054
1055static int
1056nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1057 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1058{
1059 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1060 struct nouveau_channel *chan = drm->ttm.chan;
1061 struct nouveau_cli *cli = (void *)chan->user.client;
1062 struct nouveau_fence *fence;
1063 int ret;
1064
1065 /* create temporary vmas for the transfer and attach them to the
1066 * old nvkm_mem node, these will get cleaned up after ttm has
1067 * destroyed the ttm_mem_reg
1068 */
1069 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1070 ret = nouveau_bo_move_prep(drm, bo, new_mem);
1071 if (ret)
1072 return ret;
1073 }
1074
1075 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1076 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1077 if (ret == 0) {
1078 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1079 if (ret == 0) {
1080 ret = nouveau_fence_new(chan, false, &fence);
1081 if (ret == 0) {
1082 ret = ttm_bo_move_accel_cleanup(bo,
1083 &fence->base,
1084 evict,
1085 no_wait_gpu,
1086 new_mem);
1087 nouveau_fence_unref(&fence);
1088 }
1089 }
1090 }
1091 mutex_unlock(&cli->mutex);
1092 return ret;
1093}
1094
1095void
1096nouveau_bo_move_init(struct nouveau_drm *drm)
1097{
1098 static const struct {
1099 const char *name;
1100 int engine;
1101 s32 oclass;
1102 int (*exec)(struct nouveau_channel *,
1103 struct ttm_buffer_object *,
1104 struct ttm_mem_reg *, struct ttm_mem_reg *);
1105 int (*init)(struct nouveau_channel *, u32 handle);
1106 } _methods[] = {
1107 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1108 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1109 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1110 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1111 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1112 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1113 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1114 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1115 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1116 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1117 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1118 {},
1119 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1120 }, *mthd = _methods;
1121 const char *name = "CPU";
1122 int ret;
1123
1124 do {
1125 struct nouveau_channel *chan;
1126
1127 if (mthd->engine)
1128 chan = drm->cechan;
1129 else
1130 chan = drm->channel;
1131 if (chan == NULL)
1132 continue;
1133
1134 ret = nvif_object_init(&chan->user,
1135 mthd->oclass | (mthd->engine << 16),
1136 mthd->oclass, NULL, 0,
1137 &drm->ttm.copy);
1138 if (ret == 0) {
1139 ret = mthd->init(chan, drm->ttm.copy.handle);
1140 if (ret) {
1141 nvif_object_fini(&drm->ttm.copy);
1142 continue;
1143 }
1144
1145 drm->ttm.move = mthd->exec;
1146 drm->ttm.chan = chan;
1147 name = mthd->name;
1148 break;
1149 }
1150 } while ((++mthd)->exec);
1151
1152 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1153}
1154
1155static int
1156nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1157 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1158{
1159 struct ttm_place placement_memtype = {
1160 .fpfn = 0,
1161 .lpfn = 0,
1162 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1163 };
1164 struct ttm_placement placement;
1165 struct ttm_mem_reg tmp_mem;
1166 int ret;
1167
1168 placement.num_placement = placement.num_busy_placement = 1;
1169 placement.placement = placement.busy_placement = &placement_memtype;
1170
1171 tmp_mem = *new_mem;
1172 tmp_mem.mm_node = NULL;
1173 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1174 if (ret)
1175 return ret;
1176
1177 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1178 if (ret)
1179 goto out;
1180
1181 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1182 if (ret)
1183 goto out;
1184
1185 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1186out:
1187 ttm_bo_mem_put(bo, &tmp_mem);
1188 return ret;
1189}
1190
1191static int
1192nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1193 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1194{
1195 struct ttm_place placement_memtype = {
1196 .fpfn = 0,
1197 .lpfn = 0,
1198 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1199 };
1200 struct ttm_placement placement;
1201 struct ttm_mem_reg tmp_mem;
1202 int ret;
1203
1204 placement.num_placement = placement.num_busy_placement = 1;
1205 placement.placement = placement.busy_placement = &placement_memtype;
1206
1207 tmp_mem = *new_mem;
1208 tmp_mem.mm_node = NULL;
1209 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1210 if (ret)
1211 return ret;
1212
1213 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1214 if (ret)
1215 goto out;
1216
1217 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1218 if (ret)
1219 goto out;
1220
1221out:
1222 ttm_bo_mem_put(bo, &tmp_mem);
1223 return ret;
1224}
1225
1226static void
1227nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1228{
1229 struct nouveau_bo *nvbo = nouveau_bo(bo);
1230 struct nvkm_vma *vma;
1231
1232 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1233 if (bo->destroy != nouveau_bo_del_ttm)
1234 return;
1235
1236 list_for_each_entry(vma, &nvbo->vma_list, head) {
1237 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1238 (new_mem->mem_type == TTM_PL_VRAM ||
1239 nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
1240 nvkm_vm_map(vma, new_mem->mm_node);
1241 } else {
1242 nvkm_vm_unmap(vma);
1243 }
1244 }
1245}
1246
1247static int
1248nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1249 struct nouveau_drm_tile **new_tile)
1250{
1251 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1252 struct drm_device *dev = drm->dev;
1253 struct nouveau_bo *nvbo = nouveau_bo(bo);
1254 u64 offset = new_mem->start << PAGE_SHIFT;
1255
1256 *new_tile = NULL;
1257 if (new_mem->mem_type != TTM_PL_VRAM)
1258 return 0;
1259
1260 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1261 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1262 nvbo->tile_mode,
1263 nvbo->tile_flags);
1264 }
1265
1266 return 0;
1267}
1268
1269static void
1270nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1271 struct nouveau_drm_tile *new_tile,
1272 struct nouveau_drm_tile **old_tile)
1273{
1274 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1275 struct drm_device *dev = drm->dev;
1276 struct fence *fence = reservation_object_get_excl(bo->resv);
1277
1278 nv10_bo_put_tile_region(dev, *old_tile, fence);
1279 *old_tile = new_tile;
1280}
1281
1282static int
1283nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1284 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1285{
1286 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1287 struct nouveau_bo *nvbo = nouveau_bo(bo);
1288 struct ttm_mem_reg *old_mem = &bo->mem;
1289 struct nouveau_drm_tile *new_tile = NULL;
1290 int ret = 0;
1291
1292 if (nvbo->pin_refcnt)
1293 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1294
1295 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1296 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1297 if (ret)
1298 return ret;
1299 }
1300
1301 /* Fake bo copy. */
1302 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1303 BUG_ON(bo->mem.mm_node != NULL);
1304 bo->mem = *new_mem;
1305 new_mem->mm_node = NULL;
1306 goto out;
1307 }
1308
1309 /* Hardware assisted copy. */
1310 if (drm->ttm.move) {
1311 if (new_mem->mem_type == TTM_PL_SYSTEM)
1312 ret = nouveau_bo_move_flipd(bo, evict, intr,
1313 no_wait_gpu, new_mem);
1314 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1315 ret = nouveau_bo_move_flips(bo, evict, intr,
1316 no_wait_gpu, new_mem);
1317 else
1318 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1319 no_wait_gpu, new_mem);
1320 if (!ret)
1321 goto out;
1322 }
1323
1324 /* Fallback to software copy. */
1325 ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1326 if (ret == 0)
1327 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1328
1329out:
1330 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1331 if (ret)
1332 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1333 else
1334 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1335 }
1336
1337 return ret;
1338}
1339
1340static int
1341nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1342{
1343 struct nouveau_bo *nvbo = nouveau_bo(bo);
1344
1345 return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1346}
1347
1348static int
1349nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1350{
1351 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1352 struct nouveau_drm *drm = nouveau_bdev(bdev);
1353 struct nvkm_device *device = nvxx_device(&drm->device);
1354 struct nvkm_mem *node = mem->mm_node;
1355 int ret;
1356
1357 mem->bus.addr = NULL;
1358 mem->bus.offset = 0;
1359 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1360 mem->bus.base = 0;
1361 mem->bus.is_iomem = false;
1362 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1363 return -EINVAL;
1364 switch (mem->mem_type) {
1365 case TTM_PL_SYSTEM:
1366 /* System memory */
1367 return 0;
1368 case TTM_PL_TT:
1369#if IS_ENABLED(CONFIG_AGP)
1370 if (drm->agp.bridge) {
1371 mem->bus.offset = mem->start << PAGE_SHIFT;
1372 mem->bus.base = drm->agp.base;
1373 mem->bus.is_iomem = !drm->agp.cma;
1374 }
1375#endif
1376 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
1377 /* untiled */
1378 break;
1379 /* fallthrough, tiled memory */
1380 case TTM_PL_VRAM:
1381 mem->bus.offset = mem->start << PAGE_SHIFT;
1382 mem->bus.base = device->func->resource_addr(device, 1);
1383 mem->bus.is_iomem = true;
1384 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1385 struct nvkm_bar *bar = nvxx_bar(&drm->device);
1386 int page_shift = 12;
1387 if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
1388 page_shift = node->page_shift;
1389
1390 ret = nvkm_bar_umap(bar, node->size << 12, page_shift,
1391 &node->bar_vma);
1392 if (ret)
1393 return ret;
1394
1395 nvkm_vm_map(&node->bar_vma, node);
1396 mem->bus.offset = node->bar_vma.offset;
1397 }
1398 break;
1399 default:
1400 return -EINVAL;
1401 }
1402 return 0;
1403}
1404
1405static void
1406nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1407{
1408 struct nvkm_mem *node = mem->mm_node;
1409
1410 if (!node->bar_vma.node)
1411 return;
1412
1413 nvkm_vm_unmap(&node->bar_vma);
1414 nvkm_vm_put(&node->bar_vma);
1415}
1416
1417static int
1418nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1419{
1420 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1421 struct nouveau_bo *nvbo = nouveau_bo(bo);
1422 struct nvkm_device *device = nvxx_device(&drm->device);
1423 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1424 int i, ret;
1425
1426 /* as long as the bo isn't in vram, and isn't tiled, we've got
1427 * nothing to do here.
1428 */
1429 if (bo->mem.mem_type != TTM_PL_VRAM) {
1430 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1431 !nouveau_bo_tile_layout(nvbo))
1432 return 0;
1433
1434 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1435 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1436
1437 ret = nouveau_bo_validate(nvbo, false, false);
1438 if (ret)
1439 return ret;
1440 }
1441 return 0;
1442 }
1443
1444 /* make sure bo is in mappable vram */
1445 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1446 bo->mem.start + bo->mem.num_pages < mappable)
1447 return 0;
1448
1449 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1450 nvbo->placements[i].fpfn = 0;
1451 nvbo->placements[i].lpfn = mappable;
1452 }
1453
1454 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1455 nvbo->busy_placements[i].fpfn = 0;
1456 nvbo->busy_placements[i].lpfn = mappable;
1457 }
1458
1459 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1460 return nouveau_bo_validate(nvbo, false, false);
1461}
1462
1463static int
1464nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1465{
1466 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1467 struct nouveau_drm *drm;
1468 struct nvkm_device *device;
1469 struct drm_device *dev;
1470 struct device *pdev;
1471 unsigned i;
1472 int r;
1473 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1474
1475 if (ttm->state != tt_unpopulated)
1476 return 0;
1477
1478 if (slave && ttm->sg) {
1479 /* make userspace faulting work */
1480 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1481 ttm_dma->dma_address, ttm->num_pages);
1482 ttm->state = tt_unbound;
1483 return 0;
1484 }
1485
1486 drm = nouveau_bdev(ttm->bdev);
1487 device = nvxx_device(&drm->device);
1488 dev = drm->dev;
1489 pdev = device->dev;
1490
1491 /*
1492 * Objects matching this condition have been marked as force_coherent,
1493 * so use the DMA API for them.
1494 */
1495 if (!nvxx_device(&drm->device)->func->cpu_coherent &&
1496 ttm->caching_state == tt_uncached)
1497 return ttm_dma_populate(ttm_dma, dev->dev);
1498
1499#if IS_ENABLED(CONFIG_AGP)
1500 if (drm->agp.bridge) {
1501 return ttm_agp_tt_populate(ttm);
1502 }
1503#endif
1504
1505#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1506 if (swiotlb_nr_tbl()) {
1507 return ttm_dma_populate((void *)ttm, dev->dev);
1508 }
1509#endif
1510
1511 r = ttm_pool_populate(ttm);
1512 if (r) {
1513 return r;
1514 }
1515
1516 for (i = 0; i < ttm->num_pages; i++) {
1517 dma_addr_t addr;
1518
1519 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1520 DMA_BIDIRECTIONAL);
1521
1522 if (dma_mapping_error(pdev, addr)) {
1523 while (i--) {
1524 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1525 PAGE_SIZE, DMA_BIDIRECTIONAL);
1526 ttm_dma->dma_address[i] = 0;
1527 }
1528 ttm_pool_unpopulate(ttm);
1529 return -EFAULT;
1530 }
1531
1532 ttm_dma->dma_address[i] = addr;
1533 }
1534 return 0;
1535}
1536
1537static void
1538nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1539{
1540 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1541 struct nouveau_drm *drm;
1542 struct nvkm_device *device;
1543 struct drm_device *dev;
1544 struct device *pdev;
1545 unsigned i;
1546 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1547
1548 if (slave)
1549 return;
1550
1551 drm = nouveau_bdev(ttm->bdev);
1552 device = nvxx_device(&drm->device);
1553 dev = drm->dev;
1554 pdev = device->dev;
1555
1556 /*
1557 * Objects matching this condition have been marked as force_coherent,
1558 * so use the DMA API for them.
1559 */
1560 if (!nvxx_device(&drm->device)->func->cpu_coherent &&
1561 ttm->caching_state == tt_uncached) {
1562 ttm_dma_unpopulate(ttm_dma, dev->dev);
1563 return;
1564 }
1565
1566#if IS_ENABLED(CONFIG_AGP)
1567 if (drm->agp.bridge) {
1568 ttm_agp_tt_unpopulate(ttm);
1569 return;
1570 }
1571#endif
1572
1573#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1574 if (swiotlb_nr_tbl()) {
1575 ttm_dma_unpopulate((void *)ttm, dev->dev);
1576 return;
1577 }
1578#endif
1579
1580 for (i = 0; i < ttm->num_pages; i++) {
1581 if (ttm_dma->dma_address[i]) {
1582 dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1583 DMA_BIDIRECTIONAL);
1584 }
1585 }
1586
1587 ttm_pool_unpopulate(ttm);
1588}
1589
1590void
1591nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1592{
1593 struct reservation_object *resv = nvbo->bo.resv;
1594
1595 if (exclusive)
1596 reservation_object_add_excl_fence(resv, &fence->base);
1597 else if (fence)
1598 reservation_object_add_shared_fence(resv, &fence->base);
1599}
1600
1601struct ttm_bo_driver nouveau_bo_driver = {
1602 .ttm_tt_create = &nouveau_ttm_tt_create,
1603 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1604 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1605 .invalidate_caches = nouveau_bo_invalidate_caches,
1606 .init_mem_type = nouveau_bo_init_mem_type,
1607 .evict_flags = nouveau_bo_evict_flags,
1608 .move_notify = nouveau_bo_move_ntfy,
1609 .move = nouveau_bo_move,
1610 .verify_access = nouveau_bo_verify_access,
1611 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1612 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1613 .io_mem_free = &nouveau_ttm_io_mem_free,
1614};
1615
1616struct nvkm_vma *
1617nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nvkm_vm *vm)
1618{
1619 struct nvkm_vma *vma;
1620 list_for_each_entry(vma, &nvbo->vma_list, head) {
1621 if (vma->vm == vm)
1622 return vma;
1623 }
1624
1625 return NULL;
1626}
1627
1628int
1629nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nvkm_vm *vm,
1630 struct nvkm_vma *vma)
1631{
1632 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1633 int ret;
1634
1635 ret = nvkm_vm_get(vm, size, nvbo->page_shift,
1636 NV_MEM_ACCESS_RW, vma);
1637 if (ret)
1638 return ret;
1639
1640 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1641 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1642 nvbo->page_shift != vma->vm->mmu->lpg_shift))
1643 nvkm_vm_map(vma, nvbo->bo.mem.mm_node);
1644
1645 list_add_tail(&vma->head, &nvbo->vma_list);
1646 vma->refcount = 1;
1647 return 0;
1648}
1649
1650void
1651nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nvkm_vma *vma)
1652{
1653 if (vma->node) {
1654 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1655 nvkm_vm_unmap(vma);
1656 nvkm_vm_put(vma);
1657 list_del(&vma->head);
1658 }
1659}
1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include <linux/dma-mapping.h>
31#include <linux/swiotlb.h>
32
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35#include "nouveau_fence.h"
36
37#include "nouveau_bo.h"
38#include "nouveau_ttm.h"
39#include "nouveau_gem.h"
40#include "nouveau_mem.h"
41#include "nouveau_vmm.h"
42
43#include <nvif/class.h>
44#include <nvif/if500b.h>
45#include <nvif/if900b.h>
46
47/*
48 * NV10-NV40 tiling helpers
49 */
50
51static void
52nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
53 u32 addr, u32 size, u32 pitch, u32 flags)
54{
55 struct nouveau_drm *drm = nouveau_drm(dev);
56 int i = reg - drm->tile.reg;
57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
58 struct nvkm_fb_tile *tile = &fb->tile.region[i];
59
60 nouveau_fence_unref(®->fence);
61
62 if (tile->pitch)
63 nvkm_fb_tile_fini(fb, i, tile);
64
65 if (pitch)
66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
67
68 nvkm_fb_tile_prog(fb, i, tile);
69}
70
71static struct nouveau_drm_tile *
72nv10_bo_get_tile_region(struct drm_device *dev, int i)
73{
74 struct nouveau_drm *drm = nouveau_drm(dev);
75 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
76
77 spin_lock(&drm->tile.lock);
78
79 if (!tile->used &&
80 (!tile->fence || nouveau_fence_done(tile->fence)))
81 tile->used = true;
82 else
83 tile = NULL;
84
85 spin_unlock(&drm->tile.lock);
86 return tile;
87}
88
89static void
90nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
91 struct dma_fence *fence)
92{
93 struct nouveau_drm *drm = nouveau_drm(dev);
94
95 if (tile) {
96 spin_lock(&drm->tile.lock);
97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
98 tile->used = false;
99 spin_unlock(&drm->tile.lock);
100 }
101}
102
103static struct nouveau_drm_tile *
104nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
105 u32 size, u32 pitch, u32 zeta)
106{
107 struct nouveau_drm *drm = nouveau_drm(dev);
108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
109 struct nouveau_drm_tile *tile, *found = NULL;
110 int i;
111
112 for (i = 0; i < fb->tile.regions; i++) {
113 tile = nv10_bo_get_tile_region(dev, i);
114
115 if (pitch && !found) {
116 found = tile;
117 continue;
118
119 } else if (tile && fb->tile.region[i].pitch) {
120 /* Kill an unused tile region. */
121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
122 }
123
124 nv10_bo_put_tile_region(dev, tile, NULL);
125 }
126
127 if (found)
128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
129 return found;
130}
131
132static void
133nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
134{
135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
136 struct drm_device *dev = drm->dev;
137 struct nouveau_bo *nvbo = nouveau_bo(bo);
138
139 if (unlikely(nvbo->gem.filp))
140 DRM_ERROR("bo %p still attached to GEM object\n", bo);
141 WARN_ON(nvbo->pin_refcnt > 0);
142 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
143 kfree(nvbo);
144}
145
146static inline u64
147roundup_64(u64 x, u32 y)
148{
149 x += y - 1;
150 do_div(x, y);
151 return x * y;
152}
153
154static void
155nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
156 int *align, u64 *size)
157{
158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
159 struct nvif_device *device = &drm->client.device;
160
161 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
162 if (nvbo->mode) {
163 if (device->info.chipset >= 0x40) {
164 *align = 65536;
165 *size = roundup_64(*size, 64 * nvbo->mode);
166
167 } else if (device->info.chipset >= 0x30) {
168 *align = 32768;
169 *size = roundup_64(*size, 64 * nvbo->mode);
170
171 } else if (device->info.chipset >= 0x20) {
172 *align = 16384;
173 *size = roundup_64(*size, 64 * nvbo->mode);
174
175 } else if (device->info.chipset >= 0x10) {
176 *align = 16384;
177 *size = roundup_64(*size, 32 * nvbo->mode);
178 }
179 }
180 } else {
181 *size = roundup_64(*size, (1 << nvbo->page));
182 *align = max((1 << nvbo->page), *align);
183 }
184
185 *size = roundup_64(*size, PAGE_SIZE);
186}
187
188int
189nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
190 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
191 struct sg_table *sg, struct reservation_object *robj,
192 struct nouveau_bo **pnvbo)
193{
194 struct nouveau_drm *drm = cli->drm;
195 struct nouveau_bo *nvbo;
196 struct nvif_mmu *mmu = &cli->mmu;
197 struct nvif_vmm *vmm = &cli->vmm.vmm;
198 size_t acc_size;
199 int type = ttm_bo_type_device;
200 int ret, i, pi = -1;
201
202 if (!size) {
203 NV_WARN(drm, "skipped size %016llx\n", size);
204 return -EINVAL;
205 }
206
207 if (sg)
208 type = ttm_bo_type_sg;
209
210 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
211 if (!nvbo)
212 return -ENOMEM;
213 INIT_LIST_HEAD(&nvbo->head);
214 INIT_LIST_HEAD(&nvbo->entry);
215 INIT_LIST_HEAD(&nvbo->vma_list);
216 nvbo->bo.bdev = &drm->ttm.bdev;
217
218 /* This is confusing, and doesn't actually mean we want an uncached
219 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
220 * into in nouveau_gem_new().
221 */
222 if (flags & TTM_PL_FLAG_UNCACHED) {
223 /* Determine if we can get a cache-coherent map, forcing
224 * uncached mapping if we can't.
225 */
226 if (!nouveau_drm_use_coherent_gpu_mapping(drm))
227 nvbo->force_coherent = true;
228 }
229
230 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
231 nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
232 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
233 kfree(nvbo);
234 return -EINVAL;
235 }
236
237 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
238 } else
239 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
240 nvbo->kind = (tile_flags & 0x00007f00) >> 8;
241 nvbo->comp = (tile_flags & 0x00030000) >> 16;
242 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
243 kfree(nvbo);
244 return -EINVAL;
245 }
246 } else {
247 nvbo->zeta = (tile_flags & 0x00000007);
248 }
249 nvbo->mode = tile_mode;
250 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
251
252 /* Determine the desirable target GPU page size for the buffer. */
253 for (i = 0; i < vmm->page_nr; i++) {
254 /* Because we cannot currently allow VMM maps to fail
255 * during buffer migration, we need to determine page
256 * size for the buffer up-front, and pre-allocate its
257 * page tables.
258 *
259 * Skip page sizes that can't support needed domains.
260 */
261 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
262 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram)
263 continue;
264 if ((flags & TTM_PL_FLAG_TT) &&
265 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
266 continue;
267
268 /* Select this page size if it's the first that supports
269 * the potential memory domains, or when it's compatible
270 * with the requested compression settings.
271 */
272 if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
273 pi = i;
274
275 /* Stop once the buffer is larger than the current page size. */
276 if (size >= 1ULL << vmm->page[i].shift)
277 break;
278 }
279
280 if (WARN_ON(pi < 0))
281 return -EINVAL;
282
283 /* Disable compression if suitable settings couldn't be found. */
284 if (nvbo->comp && !vmm->page[pi].comp) {
285 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
286 nvbo->kind = mmu->kind[nvbo->kind];
287 nvbo->comp = 0;
288 }
289 nvbo->page = vmm->page[pi].shift;
290
291 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
292 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
293 nouveau_bo_placement_set(nvbo, flags, 0);
294
295 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
296 sizeof(struct nouveau_bo));
297
298 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
299 type, &nvbo->placement,
300 align >> PAGE_SHIFT, false, acc_size, sg,
301 robj, nouveau_bo_del_ttm);
302 if (ret) {
303 /* ttm will call nouveau_bo_del_ttm if it fails.. */
304 return ret;
305 }
306
307 *pnvbo = nvbo;
308 return 0;
309}
310
311static void
312set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
313{
314 *n = 0;
315
316 if (type & TTM_PL_FLAG_VRAM)
317 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
318 if (type & TTM_PL_FLAG_TT)
319 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
320 if (type & TTM_PL_FLAG_SYSTEM)
321 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
322}
323
324static void
325set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
326{
327 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
328 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
329 unsigned i, fpfn, lpfn;
330
331 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
332 nvbo->mode && (type & TTM_PL_FLAG_VRAM) &&
333 nvbo->bo.mem.num_pages < vram_pages / 4) {
334 /*
335 * Make sure that the color and depth buffers are handled
336 * by independent memory controller units. Up to a 9x
337 * speed up when alpha-blending and depth-test are enabled
338 * at the same time.
339 */
340 if (nvbo->zeta) {
341 fpfn = vram_pages / 2;
342 lpfn = ~0;
343 } else {
344 fpfn = 0;
345 lpfn = vram_pages / 2;
346 }
347 for (i = 0; i < nvbo->placement.num_placement; ++i) {
348 nvbo->placements[i].fpfn = fpfn;
349 nvbo->placements[i].lpfn = lpfn;
350 }
351 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
352 nvbo->busy_placements[i].fpfn = fpfn;
353 nvbo->busy_placements[i].lpfn = lpfn;
354 }
355 }
356}
357
358void
359nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
360{
361 struct ttm_placement *pl = &nvbo->placement;
362 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
363 TTM_PL_MASK_CACHING) |
364 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
365
366 pl->placement = nvbo->placements;
367 set_placement_list(nvbo->placements, &pl->num_placement,
368 type, flags);
369
370 pl->busy_placement = nvbo->busy_placements;
371 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
372 type | busy, flags);
373
374 set_placement_range(nvbo, type);
375}
376
377int
378nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
379{
380 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
381 struct ttm_buffer_object *bo = &nvbo->bo;
382 bool force = false, evict = false;
383 int ret;
384
385 ret = ttm_bo_reserve(bo, false, false, NULL);
386 if (ret)
387 return ret;
388
389 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
390 memtype == TTM_PL_FLAG_VRAM && contig) {
391 if (!nvbo->contig) {
392 nvbo->contig = true;
393 force = true;
394 evict = true;
395 }
396 }
397
398 if (nvbo->pin_refcnt) {
399 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
400 NV_ERROR(drm, "bo %p pinned elsewhere: "
401 "0x%08x vs 0x%08x\n", bo,
402 1 << bo->mem.mem_type, memtype);
403 ret = -EBUSY;
404 }
405 nvbo->pin_refcnt++;
406 goto out;
407 }
408
409 if (evict) {
410 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
411 ret = nouveau_bo_validate(nvbo, false, false);
412 if (ret)
413 goto out;
414 }
415
416 nvbo->pin_refcnt++;
417 nouveau_bo_placement_set(nvbo, memtype, 0);
418
419 /* drop pin_refcnt temporarily, so we don't trip the assertion
420 * in nouveau_bo_move() that makes sure we're not trying to
421 * move a pinned buffer
422 */
423 nvbo->pin_refcnt--;
424 ret = nouveau_bo_validate(nvbo, false, false);
425 if (ret)
426 goto out;
427 nvbo->pin_refcnt++;
428
429 switch (bo->mem.mem_type) {
430 case TTM_PL_VRAM:
431 drm->gem.vram_available -= bo->mem.size;
432 break;
433 case TTM_PL_TT:
434 drm->gem.gart_available -= bo->mem.size;
435 break;
436 default:
437 break;
438 }
439
440out:
441 if (force && ret)
442 nvbo->contig = false;
443 ttm_bo_unreserve(bo);
444 return ret;
445}
446
447int
448nouveau_bo_unpin(struct nouveau_bo *nvbo)
449{
450 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
451 struct ttm_buffer_object *bo = &nvbo->bo;
452 int ret, ref;
453
454 ret = ttm_bo_reserve(bo, false, false, NULL);
455 if (ret)
456 return ret;
457
458 ref = --nvbo->pin_refcnt;
459 WARN_ON_ONCE(ref < 0);
460 if (ref)
461 goto out;
462
463 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
464
465 ret = nouveau_bo_validate(nvbo, false, false);
466 if (ret == 0) {
467 switch (bo->mem.mem_type) {
468 case TTM_PL_VRAM:
469 drm->gem.vram_available += bo->mem.size;
470 break;
471 case TTM_PL_TT:
472 drm->gem.gart_available += bo->mem.size;
473 break;
474 default:
475 break;
476 }
477 }
478
479out:
480 ttm_bo_unreserve(bo);
481 return ret;
482}
483
484int
485nouveau_bo_map(struct nouveau_bo *nvbo)
486{
487 int ret;
488
489 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
490 if (ret)
491 return ret;
492
493 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
494
495 ttm_bo_unreserve(&nvbo->bo);
496 return ret;
497}
498
499void
500nouveau_bo_unmap(struct nouveau_bo *nvbo)
501{
502 if (!nvbo)
503 return;
504
505 ttm_bo_kunmap(&nvbo->kmap);
506}
507
508void
509nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
510{
511 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
512 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
513 int i;
514
515 if (!ttm_dma)
516 return;
517
518 /* Don't waste time looping if the object is coherent */
519 if (nvbo->force_coherent)
520 return;
521
522 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
523 dma_sync_single_for_device(drm->dev->dev,
524 ttm_dma->dma_address[i],
525 PAGE_SIZE, DMA_TO_DEVICE);
526}
527
528void
529nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
530{
531 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
532 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
533 int i;
534
535 if (!ttm_dma)
536 return;
537
538 /* Don't waste time looping if the object is coherent */
539 if (nvbo->force_coherent)
540 return;
541
542 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
543 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
544 PAGE_SIZE, DMA_FROM_DEVICE);
545}
546
547int
548nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
549 bool no_wait_gpu)
550{
551 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
552 int ret;
553
554 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
555 if (ret)
556 return ret;
557
558 nouveau_bo_sync_for_device(nvbo);
559
560 return 0;
561}
562
563void
564nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
565{
566 bool is_iomem;
567 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
568
569 mem += index;
570
571 if (is_iomem)
572 iowrite16_native(val, (void __force __iomem *)mem);
573 else
574 *mem = val;
575}
576
577u32
578nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
579{
580 bool is_iomem;
581 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
582
583 mem += index;
584
585 if (is_iomem)
586 return ioread32_native((void __force __iomem *)mem);
587 else
588 return *mem;
589}
590
591void
592nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
593{
594 bool is_iomem;
595 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
596
597 mem += index;
598
599 if (is_iomem)
600 iowrite32_native(val, (void __force __iomem *)mem);
601 else
602 *mem = val;
603}
604
605static struct ttm_tt *
606nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
607{
608#if IS_ENABLED(CONFIG_AGP)
609 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
610
611 if (drm->agp.bridge) {
612 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
613 }
614#endif
615
616 return nouveau_sgdma_create_ttm(bo, page_flags);
617}
618
619static int
620nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
621{
622 /* We'll do this from user space. */
623 return 0;
624}
625
626static int
627nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
628 struct ttm_mem_type_manager *man)
629{
630 struct nouveau_drm *drm = nouveau_bdev(bdev);
631 struct nvif_mmu *mmu = &drm->client.mmu;
632
633 switch (type) {
634 case TTM_PL_SYSTEM:
635 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
636 man->available_caching = TTM_PL_MASK_CACHING;
637 man->default_caching = TTM_PL_FLAG_CACHED;
638 break;
639 case TTM_PL_VRAM:
640 man->flags = TTM_MEMTYPE_FLAG_FIXED |
641 TTM_MEMTYPE_FLAG_MAPPABLE;
642 man->available_caching = TTM_PL_FLAG_UNCACHED |
643 TTM_PL_FLAG_WC;
644 man->default_caching = TTM_PL_FLAG_WC;
645
646 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
647 /* Some BARs do not support being ioremapped WC */
648 const u8 type = mmu->type[drm->ttm.type_vram].type;
649 if (type & NVIF_MEM_UNCACHED) {
650 man->available_caching = TTM_PL_FLAG_UNCACHED;
651 man->default_caching = TTM_PL_FLAG_UNCACHED;
652 }
653
654 man->func = &nouveau_vram_manager;
655 man->io_reserve_fastpath = false;
656 man->use_io_reserve_lru = true;
657 } else {
658 man->func = &ttm_bo_manager_func;
659 }
660 break;
661 case TTM_PL_TT:
662 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA)
663 man->func = &nouveau_gart_manager;
664 else
665 if (!drm->agp.bridge)
666 man->func = &nv04_gart_manager;
667 else
668 man->func = &ttm_bo_manager_func;
669
670 if (drm->agp.bridge) {
671 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
672 man->available_caching = TTM_PL_FLAG_UNCACHED |
673 TTM_PL_FLAG_WC;
674 man->default_caching = TTM_PL_FLAG_WC;
675 } else {
676 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
677 TTM_MEMTYPE_FLAG_CMA;
678 man->available_caching = TTM_PL_MASK_CACHING;
679 man->default_caching = TTM_PL_FLAG_CACHED;
680 }
681
682 break;
683 default:
684 return -EINVAL;
685 }
686 return 0;
687}
688
689static void
690nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
691{
692 struct nouveau_bo *nvbo = nouveau_bo(bo);
693
694 switch (bo->mem.mem_type) {
695 case TTM_PL_VRAM:
696 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
697 TTM_PL_FLAG_SYSTEM);
698 break;
699 default:
700 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
701 break;
702 }
703
704 *pl = nvbo->placement;
705}
706
707
708static int
709nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
710{
711 int ret = RING_SPACE(chan, 2);
712 if (ret == 0) {
713 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
714 OUT_RING (chan, handle & 0x0000ffff);
715 FIRE_RING (chan);
716 }
717 return ret;
718}
719
720static int
721nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
722 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
723{
724 struct nouveau_mem *mem = nouveau_mem(old_reg);
725 int ret = RING_SPACE(chan, 10);
726 if (ret == 0) {
727 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
728 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
729 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
730 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
731 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
732 OUT_RING (chan, PAGE_SIZE);
733 OUT_RING (chan, PAGE_SIZE);
734 OUT_RING (chan, PAGE_SIZE);
735 OUT_RING (chan, new_reg->num_pages);
736 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
737 }
738 return ret;
739}
740
741static int
742nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
743{
744 int ret = RING_SPACE(chan, 2);
745 if (ret == 0) {
746 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
747 OUT_RING (chan, handle);
748 }
749 return ret;
750}
751
752static int
753nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
754 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
755{
756 struct nouveau_mem *mem = nouveau_mem(old_reg);
757 u64 src_offset = mem->vma[0].addr;
758 u64 dst_offset = mem->vma[1].addr;
759 u32 page_count = new_reg->num_pages;
760 int ret;
761
762 page_count = new_reg->num_pages;
763 while (page_count) {
764 int line_count = (page_count > 8191) ? 8191 : page_count;
765
766 ret = RING_SPACE(chan, 11);
767 if (ret)
768 return ret;
769
770 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
771 OUT_RING (chan, upper_32_bits(src_offset));
772 OUT_RING (chan, lower_32_bits(src_offset));
773 OUT_RING (chan, upper_32_bits(dst_offset));
774 OUT_RING (chan, lower_32_bits(dst_offset));
775 OUT_RING (chan, PAGE_SIZE);
776 OUT_RING (chan, PAGE_SIZE);
777 OUT_RING (chan, PAGE_SIZE);
778 OUT_RING (chan, line_count);
779 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
780 OUT_RING (chan, 0x00000110);
781
782 page_count -= line_count;
783 src_offset += (PAGE_SIZE * line_count);
784 dst_offset += (PAGE_SIZE * line_count);
785 }
786
787 return 0;
788}
789
790static int
791nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
792 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
793{
794 struct nouveau_mem *mem = nouveau_mem(old_reg);
795 u64 src_offset = mem->vma[0].addr;
796 u64 dst_offset = mem->vma[1].addr;
797 u32 page_count = new_reg->num_pages;
798 int ret;
799
800 page_count = new_reg->num_pages;
801 while (page_count) {
802 int line_count = (page_count > 2047) ? 2047 : page_count;
803
804 ret = RING_SPACE(chan, 12);
805 if (ret)
806 return ret;
807
808 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
809 OUT_RING (chan, upper_32_bits(dst_offset));
810 OUT_RING (chan, lower_32_bits(dst_offset));
811 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
812 OUT_RING (chan, upper_32_bits(src_offset));
813 OUT_RING (chan, lower_32_bits(src_offset));
814 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
815 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
816 OUT_RING (chan, PAGE_SIZE); /* line_length */
817 OUT_RING (chan, line_count);
818 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
819 OUT_RING (chan, 0x00100110);
820
821 page_count -= line_count;
822 src_offset += (PAGE_SIZE * line_count);
823 dst_offset += (PAGE_SIZE * line_count);
824 }
825
826 return 0;
827}
828
829static int
830nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
831 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
832{
833 struct nouveau_mem *mem = nouveau_mem(old_reg);
834 u64 src_offset = mem->vma[0].addr;
835 u64 dst_offset = mem->vma[1].addr;
836 u32 page_count = new_reg->num_pages;
837 int ret;
838
839 page_count = new_reg->num_pages;
840 while (page_count) {
841 int line_count = (page_count > 8191) ? 8191 : page_count;
842
843 ret = RING_SPACE(chan, 11);
844 if (ret)
845 return ret;
846
847 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
848 OUT_RING (chan, upper_32_bits(src_offset));
849 OUT_RING (chan, lower_32_bits(src_offset));
850 OUT_RING (chan, upper_32_bits(dst_offset));
851 OUT_RING (chan, lower_32_bits(dst_offset));
852 OUT_RING (chan, PAGE_SIZE);
853 OUT_RING (chan, PAGE_SIZE);
854 OUT_RING (chan, PAGE_SIZE);
855 OUT_RING (chan, line_count);
856 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
857 OUT_RING (chan, 0x00000110);
858
859 page_count -= line_count;
860 src_offset += (PAGE_SIZE * line_count);
861 dst_offset += (PAGE_SIZE * line_count);
862 }
863
864 return 0;
865}
866
867static int
868nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
869 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
870{
871 struct nouveau_mem *mem = nouveau_mem(old_reg);
872 int ret = RING_SPACE(chan, 7);
873 if (ret == 0) {
874 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
875 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
876 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
877 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
878 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
879 OUT_RING (chan, 0x00000000 /* COPY */);
880 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
881 }
882 return ret;
883}
884
885static int
886nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
887 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
888{
889 struct nouveau_mem *mem = nouveau_mem(old_reg);
890 int ret = RING_SPACE(chan, 7);
891 if (ret == 0) {
892 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
893 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
894 OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
895 OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
896 OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
897 OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
898 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
899 }
900 return ret;
901}
902
903static int
904nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
905{
906 int ret = RING_SPACE(chan, 6);
907 if (ret == 0) {
908 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
909 OUT_RING (chan, handle);
910 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
911 OUT_RING (chan, chan->drm->ntfy.handle);
912 OUT_RING (chan, chan->vram.handle);
913 OUT_RING (chan, chan->vram.handle);
914 }
915
916 return ret;
917}
918
919static int
920nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
921 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
922{
923 struct nouveau_mem *mem = nouveau_mem(old_reg);
924 u64 length = (new_reg->num_pages << PAGE_SHIFT);
925 u64 src_offset = mem->vma[0].addr;
926 u64 dst_offset = mem->vma[1].addr;
927 int src_tiled = !!mem->kind;
928 int dst_tiled = !!nouveau_mem(new_reg)->kind;
929 int ret;
930
931 while (length) {
932 u32 amount, stride, height;
933
934 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
935 if (ret)
936 return ret;
937
938 amount = min(length, (u64)(4 * 1024 * 1024));
939 stride = 16 * 4;
940 height = amount / stride;
941
942 if (src_tiled) {
943 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
944 OUT_RING (chan, 0);
945 OUT_RING (chan, 0);
946 OUT_RING (chan, stride);
947 OUT_RING (chan, height);
948 OUT_RING (chan, 1);
949 OUT_RING (chan, 0);
950 OUT_RING (chan, 0);
951 } else {
952 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
953 OUT_RING (chan, 1);
954 }
955 if (dst_tiled) {
956 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
957 OUT_RING (chan, 0);
958 OUT_RING (chan, 0);
959 OUT_RING (chan, stride);
960 OUT_RING (chan, height);
961 OUT_RING (chan, 1);
962 OUT_RING (chan, 0);
963 OUT_RING (chan, 0);
964 } else {
965 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
966 OUT_RING (chan, 1);
967 }
968
969 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
970 OUT_RING (chan, upper_32_bits(src_offset));
971 OUT_RING (chan, upper_32_bits(dst_offset));
972 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
973 OUT_RING (chan, lower_32_bits(src_offset));
974 OUT_RING (chan, lower_32_bits(dst_offset));
975 OUT_RING (chan, stride);
976 OUT_RING (chan, stride);
977 OUT_RING (chan, stride);
978 OUT_RING (chan, height);
979 OUT_RING (chan, 0x00000101);
980 OUT_RING (chan, 0x00000000);
981 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
982 OUT_RING (chan, 0);
983
984 length -= amount;
985 src_offset += amount;
986 dst_offset += amount;
987 }
988
989 return 0;
990}
991
992static int
993nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
994{
995 int ret = RING_SPACE(chan, 4);
996 if (ret == 0) {
997 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
998 OUT_RING (chan, handle);
999 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
1000 OUT_RING (chan, chan->drm->ntfy.handle);
1001 }
1002
1003 return ret;
1004}
1005
1006static inline uint32_t
1007nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
1008 struct nouveau_channel *chan, struct ttm_mem_reg *reg)
1009{
1010 if (reg->mem_type == TTM_PL_TT)
1011 return NvDmaTT;
1012 return chan->vram.handle;
1013}
1014
1015static int
1016nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
1017 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
1018{
1019 u32 src_offset = old_reg->start << PAGE_SHIFT;
1020 u32 dst_offset = new_reg->start << PAGE_SHIFT;
1021 u32 page_count = new_reg->num_pages;
1022 int ret;
1023
1024 ret = RING_SPACE(chan, 3);
1025 if (ret)
1026 return ret;
1027
1028 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
1029 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg));
1030 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg));
1031
1032 page_count = new_reg->num_pages;
1033 while (page_count) {
1034 int line_count = (page_count > 2047) ? 2047 : page_count;
1035
1036 ret = RING_SPACE(chan, 11);
1037 if (ret)
1038 return ret;
1039
1040 BEGIN_NV04(chan, NvSubCopy,
1041 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1042 OUT_RING (chan, src_offset);
1043 OUT_RING (chan, dst_offset);
1044 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
1045 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
1046 OUT_RING (chan, PAGE_SIZE); /* line_length */
1047 OUT_RING (chan, line_count);
1048 OUT_RING (chan, 0x00000101);
1049 OUT_RING (chan, 0x00000000);
1050 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1051 OUT_RING (chan, 0);
1052
1053 page_count -= line_count;
1054 src_offset += (PAGE_SIZE * line_count);
1055 dst_offset += (PAGE_SIZE * line_count);
1056 }
1057
1058 return 0;
1059}
1060
1061static int
1062nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1063 struct ttm_mem_reg *reg)
1064{
1065 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
1066 struct nouveau_mem *new_mem = nouveau_mem(reg);
1067 struct nvif_vmm *vmm = &drm->client.vmm.vmm;
1068 int ret;
1069
1070 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
1071 old_mem->mem.size, &old_mem->vma[0]);
1072 if (ret)
1073 return ret;
1074
1075 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
1076 new_mem->mem.size, &old_mem->vma[1]);
1077 if (ret)
1078 goto done;
1079
1080 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
1081 if (ret)
1082 goto done;
1083
1084 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
1085done:
1086 if (ret) {
1087 nvif_vmm_put(vmm, &old_mem->vma[1]);
1088 nvif_vmm_put(vmm, &old_mem->vma[0]);
1089 }
1090 return 0;
1091}
1092
1093static int
1094nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1095 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1096{
1097 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1098 struct nouveau_channel *chan = drm->ttm.chan;
1099 struct nouveau_cli *cli = (void *)chan->user.client;
1100 struct nouveau_fence *fence;
1101 int ret;
1102
1103 /* create temporary vmas for the transfer and attach them to the
1104 * old nvkm_mem node, these will get cleaned up after ttm has
1105 * destroyed the ttm_mem_reg
1106 */
1107 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1108 ret = nouveau_bo_move_prep(drm, bo, new_reg);
1109 if (ret)
1110 return ret;
1111 }
1112
1113 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1114 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1115 if (ret == 0) {
1116 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
1117 if (ret == 0) {
1118 ret = nouveau_fence_new(chan, false, &fence);
1119 if (ret == 0) {
1120 ret = ttm_bo_move_accel_cleanup(bo,
1121 &fence->base,
1122 evict,
1123 new_reg);
1124 nouveau_fence_unref(&fence);
1125 }
1126 }
1127 }
1128 mutex_unlock(&cli->mutex);
1129 return ret;
1130}
1131
1132void
1133nouveau_bo_move_init(struct nouveau_drm *drm)
1134{
1135 static const struct {
1136 const char *name;
1137 int engine;
1138 s32 oclass;
1139 int (*exec)(struct nouveau_channel *,
1140 struct ttm_buffer_object *,
1141 struct ttm_mem_reg *, struct ttm_mem_reg *);
1142 int (*init)(struct nouveau_channel *, u32 handle);
1143 } _methods[] = {
1144 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
1145 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
1146 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
1147 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1148 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
1149 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1150 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1151 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1152 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1153 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1154 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1155 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1156 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1157 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1158 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1159 {},
1160 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1161 }, *mthd = _methods;
1162 const char *name = "CPU";
1163 int ret;
1164
1165 do {
1166 struct nouveau_channel *chan;
1167
1168 if (mthd->engine)
1169 chan = drm->cechan;
1170 else
1171 chan = drm->channel;
1172 if (chan == NULL)
1173 continue;
1174
1175 ret = nvif_object_init(&chan->user,
1176 mthd->oclass | (mthd->engine << 16),
1177 mthd->oclass, NULL, 0,
1178 &drm->ttm.copy);
1179 if (ret == 0) {
1180 ret = mthd->init(chan, drm->ttm.copy.handle);
1181 if (ret) {
1182 nvif_object_fini(&drm->ttm.copy);
1183 continue;
1184 }
1185
1186 drm->ttm.move = mthd->exec;
1187 drm->ttm.chan = chan;
1188 name = mthd->name;
1189 break;
1190 }
1191 } while ((++mthd)->exec);
1192
1193 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1194}
1195
1196static int
1197nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1198 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1199{
1200 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
1201 struct ttm_place placement_memtype = {
1202 .fpfn = 0,
1203 .lpfn = 0,
1204 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1205 };
1206 struct ttm_placement placement;
1207 struct ttm_mem_reg tmp_reg;
1208 int ret;
1209
1210 placement.num_placement = placement.num_busy_placement = 1;
1211 placement.placement = placement.busy_placement = &placement_memtype;
1212
1213 tmp_reg = *new_reg;
1214 tmp_reg.mm_node = NULL;
1215 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
1216 if (ret)
1217 return ret;
1218
1219 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx);
1220 if (ret)
1221 goto out;
1222
1223 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
1224 if (ret)
1225 goto out;
1226
1227 ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
1228out:
1229 ttm_bo_mem_put(bo, &tmp_reg);
1230 return ret;
1231}
1232
1233static int
1234nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1235 bool no_wait_gpu, struct ttm_mem_reg *new_reg)
1236{
1237 struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
1238 struct ttm_place placement_memtype = {
1239 .fpfn = 0,
1240 .lpfn = 0,
1241 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1242 };
1243 struct ttm_placement placement;
1244 struct ttm_mem_reg tmp_reg;
1245 int ret;
1246
1247 placement.num_placement = placement.num_busy_placement = 1;
1248 placement.placement = placement.busy_placement = &placement_memtype;
1249
1250 tmp_reg = *new_reg;
1251 tmp_reg.mm_node = NULL;
1252 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
1253 if (ret)
1254 return ret;
1255
1256 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
1257 if (ret)
1258 goto out;
1259
1260 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
1261 if (ret)
1262 goto out;
1263
1264out:
1265 ttm_bo_mem_put(bo, &tmp_reg);
1266 return ret;
1267}
1268
1269static void
1270nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
1271 struct ttm_mem_reg *new_reg)
1272{
1273 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
1274 struct nouveau_bo *nvbo = nouveau_bo(bo);
1275 struct nouveau_vma *vma;
1276
1277 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1278 if (bo->destroy != nouveau_bo_del_ttm)
1279 return;
1280
1281 if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
1282 mem->mem.page == nvbo->page) {
1283 list_for_each_entry(vma, &nvbo->vma_list, head) {
1284 nouveau_vma_map(vma, mem);
1285 }
1286 } else {
1287 list_for_each_entry(vma, &nvbo->vma_list, head) {
1288 WARN_ON(ttm_bo_wait(bo, false, false));
1289 nouveau_vma_unmap(vma);
1290 }
1291 }
1292}
1293
1294static int
1295nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg,
1296 struct nouveau_drm_tile **new_tile)
1297{
1298 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1299 struct drm_device *dev = drm->dev;
1300 struct nouveau_bo *nvbo = nouveau_bo(bo);
1301 u64 offset = new_reg->start << PAGE_SHIFT;
1302
1303 *new_tile = NULL;
1304 if (new_reg->mem_type != TTM_PL_VRAM)
1305 return 0;
1306
1307 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1308 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
1309 nvbo->mode, nvbo->zeta);
1310 }
1311
1312 return 0;
1313}
1314
1315static void
1316nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1317 struct nouveau_drm_tile *new_tile,
1318 struct nouveau_drm_tile **old_tile)
1319{
1320 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1321 struct drm_device *dev = drm->dev;
1322 struct dma_fence *fence = reservation_object_get_excl(bo->resv);
1323
1324 nv10_bo_put_tile_region(dev, *old_tile, fence);
1325 *old_tile = new_tile;
1326}
1327
1328static int
1329nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
1330 struct ttm_operation_ctx *ctx,
1331 struct ttm_mem_reg *new_reg)
1332{
1333 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1334 struct nouveau_bo *nvbo = nouveau_bo(bo);
1335 struct ttm_mem_reg *old_reg = &bo->mem;
1336 struct nouveau_drm_tile *new_tile = NULL;
1337 int ret = 0;
1338
1339 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1340 if (ret)
1341 return ret;
1342
1343 if (nvbo->pin_refcnt)
1344 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1345
1346 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1347 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1348 if (ret)
1349 return ret;
1350 }
1351
1352 /* Fake bo copy. */
1353 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1354 BUG_ON(bo->mem.mm_node != NULL);
1355 bo->mem = *new_reg;
1356 new_reg->mm_node = NULL;
1357 goto out;
1358 }
1359
1360 /* Hardware assisted copy. */
1361 if (drm->ttm.move) {
1362 if (new_reg->mem_type == TTM_PL_SYSTEM)
1363 ret = nouveau_bo_move_flipd(bo, evict,
1364 ctx->interruptible,
1365 ctx->no_wait_gpu, new_reg);
1366 else if (old_reg->mem_type == TTM_PL_SYSTEM)
1367 ret = nouveau_bo_move_flips(bo, evict,
1368 ctx->interruptible,
1369 ctx->no_wait_gpu, new_reg);
1370 else
1371 ret = nouveau_bo_move_m2mf(bo, evict,
1372 ctx->interruptible,
1373 ctx->no_wait_gpu, new_reg);
1374 if (!ret)
1375 goto out;
1376 }
1377
1378 /* Fallback to software copy. */
1379 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
1380 if (ret == 0)
1381 ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1382
1383out:
1384 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1385 if (ret)
1386 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1387 else
1388 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1389 }
1390
1391 return ret;
1392}
1393
1394static int
1395nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1396{
1397 struct nouveau_bo *nvbo = nouveau_bo(bo);
1398
1399 return drm_vma_node_verify_access(&nvbo->gem.vma_node,
1400 filp->private_data);
1401}
1402
1403static int
1404nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1405{
1406 struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type];
1407 struct nouveau_drm *drm = nouveau_bdev(bdev);
1408 struct nvkm_device *device = nvxx_device(&drm->client.device);
1409 struct nouveau_mem *mem = nouveau_mem(reg);
1410
1411 reg->bus.addr = NULL;
1412 reg->bus.offset = 0;
1413 reg->bus.size = reg->num_pages << PAGE_SHIFT;
1414 reg->bus.base = 0;
1415 reg->bus.is_iomem = false;
1416 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1417 return -EINVAL;
1418 switch (reg->mem_type) {
1419 case TTM_PL_SYSTEM:
1420 /* System memory */
1421 return 0;
1422 case TTM_PL_TT:
1423#if IS_ENABLED(CONFIG_AGP)
1424 if (drm->agp.bridge) {
1425 reg->bus.offset = reg->start << PAGE_SHIFT;
1426 reg->bus.base = drm->agp.base;
1427 reg->bus.is_iomem = !drm->agp.cma;
1428 }
1429#endif
1430 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind)
1431 /* untiled */
1432 break;
1433 /* fallthrough, tiled memory */
1434 case TTM_PL_VRAM:
1435 reg->bus.offset = reg->start << PAGE_SHIFT;
1436 reg->bus.base = device->func->resource_addr(device, 1);
1437 reg->bus.is_iomem = true;
1438 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1439 union {
1440 struct nv50_mem_map_v0 nv50;
1441 struct gf100_mem_map_v0 gf100;
1442 } args;
1443 u64 handle, length;
1444 u32 argc = 0;
1445 int ret;
1446
1447 switch (mem->mem.object.oclass) {
1448 case NVIF_CLASS_MEM_NV50:
1449 args.nv50.version = 0;
1450 args.nv50.ro = 0;
1451 args.nv50.kind = mem->kind;
1452 args.nv50.comp = mem->comp;
1453 argc = sizeof(args.nv50);
1454 break;
1455 case NVIF_CLASS_MEM_GF100:
1456 args.gf100.version = 0;
1457 args.gf100.ro = 0;
1458 args.gf100.kind = mem->kind;
1459 argc = sizeof(args.gf100);
1460 break;
1461 default:
1462 WARN_ON(1);
1463 break;
1464 }
1465
1466 ret = nvif_object_map_handle(&mem->mem.object,
1467 &args, argc,
1468 &handle, &length);
1469 if (ret != 1)
1470 return ret ? ret : -EINVAL;
1471
1472 reg->bus.base = 0;
1473 reg->bus.offset = handle;
1474 }
1475 break;
1476 default:
1477 return -EINVAL;
1478 }
1479 return 0;
1480}
1481
1482static void
1483nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
1484{
1485 struct nouveau_drm *drm = nouveau_bdev(bdev);
1486 struct nouveau_mem *mem = nouveau_mem(reg);
1487
1488 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1489 switch (reg->mem_type) {
1490 case TTM_PL_TT:
1491 if (mem->kind)
1492 nvif_object_unmap_handle(&mem->mem.object);
1493 break;
1494 case TTM_PL_VRAM:
1495 nvif_object_unmap_handle(&mem->mem.object);
1496 break;
1497 default:
1498 break;
1499 }
1500 }
1501}
1502
1503static int
1504nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1505{
1506 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1507 struct nouveau_bo *nvbo = nouveau_bo(bo);
1508 struct nvkm_device *device = nvxx_device(&drm->client.device);
1509 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1510 int i, ret;
1511
1512 /* as long as the bo isn't in vram, and isn't tiled, we've got
1513 * nothing to do here.
1514 */
1515 if (bo->mem.mem_type != TTM_PL_VRAM) {
1516 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1517 !nvbo->kind)
1518 return 0;
1519
1520 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1521 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1522
1523 ret = nouveau_bo_validate(nvbo, false, false);
1524 if (ret)
1525 return ret;
1526 }
1527 return 0;
1528 }
1529
1530 /* make sure bo is in mappable vram */
1531 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1532 bo->mem.start + bo->mem.num_pages < mappable)
1533 return 0;
1534
1535 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1536 nvbo->placements[i].fpfn = 0;
1537 nvbo->placements[i].lpfn = mappable;
1538 }
1539
1540 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1541 nvbo->busy_placements[i].fpfn = 0;
1542 nvbo->busy_placements[i].lpfn = mappable;
1543 }
1544
1545 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1546 return nouveau_bo_validate(nvbo, false, false);
1547}
1548
1549static int
1550nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1551{
1552 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1553 struct nouveau_drm *drm;
1554 struct device *dev;
1555 unsigned i;
1556 int r;
1557 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1558
1559 if (ttm->state != tt_unpopulated)
1560 return 0;
1561
1562 if (slave && ttm->sg) {
1563 /* make userspace faulting work */
1564 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1565 ttm_dma->dma_address, ttm->num_pages);
1566 ttm->state = tt_unbound;
1567 return 0;
1568 }
1569
1570 drm = nouveau_bdev(ttm->bdev);
1571 dev = drm->dev->dev;
1572
1573#if IS_ENABLED(CONFIG_AGP)
1574 if (drm->agp.bridge) {
1575 return ttm_agp_tt_populate(ttm, ctx);
1576 }
1577#endif
1578
1579#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1580 if (swiotlb_nr_tbl()) {
1581 return ttm_dma_populate((void *)ttm, dev, ctx);
1582 }
1583#endif
1584
1585 r = ttm_pool_populate(ttm, ctx);
1586 if (r) {
1587 return r;
1588 }
1589
1590 for (i = 0; i < ttm->num_pages; i++) {
1591 dma_addr_t addr;
1592
1593 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE,
1594 DMA_BIDIRECTIONAL);
1595
1596 if (dma_mapping_error(dev, addr)) {
1597 while (i--) {
1598 dma_unmap_page(dev, ttm_dma->dma_address[i],
1599 PAGE_SIZE, DMA_BIDIRECTIONAL);
1600 ttm_dma->dma_address[i] = 0;
1601 }
1602 ttm_pool_unpopulate(ttm);
1603 return -EFAULT;
1604 }
1605
1606 ttm_dma->dma_address[i] = addr;
1607 }
1608 return 0;
1609}
1610
1611static void
1612nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1613{
1614 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1615 struct nouveau_drm *drm;
1616 struct device *dev;
1617 unsigned i;
1618 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1619
1620 if (slave)
1621 return;
1622
1623 drm = nouveau_bdev(ttm->bdev);
1624 dev = drm->dev->dev;
1625
1626#if IS_ENABLED(CONFIG_AGP)
1627 if (drm->agp.bridge) {
1628 ttm_agp_tt_unpopulate(ttm);
1629 return;
1630 }
1631#endif
1632
1633#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
1634 if (swiotlb_nr_tbl()) {
1635 ttm_dma_unpopulate((void *)ttm, dev);
1636 return;
1637 }
1638#endif
1639
1640 for (i = 0; i < ttm->num_pages; i++) {
1641 if (ttm_dma->dma_address[i]) {
1642 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE,
1643 DMA_BIDIRECTIONAL);
1644 }
1645 }
1646
1647 ttm_pool_unpopulate(ttm);
1648}
1649
1650void
1651nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1652{
1653 struct reservation_object *resv = nvbo->bo.resv;
1654
1655 if (exclusive)
1656 reservation_object_add_excl_fence(resv, &fence->base);
1657 else if (fence)
1658 reservation_object_add_shared_fence(resv, &fence->base);
1659}
1660
1661struct ttm_bo_driver nouveau_bo_driver = {
1662 .ttm_tt_create = &nouveau_ttm_tt_create,
1663 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1664 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1665 .invalidate_caches = nouveau_bo_invalidate_caches,
1666 .init_mem_type = nouveau_bo_init_mem_type,
1667 .eviction_valuable = ttm_bo_eviction_valuable,
1668 .evict_flags = nouveau_bo_evict_flags,
1669 .move_notify = nouveau_bo_move_ntfy,
1670 .move = nouveau_bo_move,
1671 .verify_access = nouveau_bo_verify_access,
1672 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1673 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1674 .io_mem_free = &nouveau_ttm_io_mem_free,
1675};