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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2008-2015 Intel Corporation
4 */
5
6#include <linux/highmem.h>
7
8#include "i915_drv.h"
9#include "i915_reg.h"
10#include "i915_scatterlist.h"
11#include "i915_pvinfo.h"
12#include "i915_vgpu.h"
13#include "intel_gt_regs.h"
14#include "intel_mchbar_regs.h"
15
16/**
17 * DOC: fence register handling
18 *
19 * Important to avoid confusions: "fences" in the i915 driver are not execution
20 * fences used to track command completion but hardware detiler objects which
21 * wrap a given range of the global GTT. Each platform has only a fairly limited
22 * set of these objects.
23 *
24 * Fences are used to detile GTT memory mappings. They're also connected to the
25 * hardware frontbuffer render tracking and hence interact with frontbuffer
26 * compression. Furthermore on older platforms fences are required for tiled
27 * objects used by the display engine. They can also be used by the render
28 * engine - they're required for blitter commands and are optional for render
29 * commands. But on gen4+ both display (with the exception of fbc) and rendering
30 * have their own tiling state bits and don't need fences.
31 *
32 * Also note that fences only support X and Y tiling and hence can't be used for
33 * the fancier new tiling formats like W, Ys and Yf.
34 *
35 * Finally note that because fences are such a restricted resource they're
36 * dynamically associated with objects. Furthermore fence state is committed to
37 * the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
38 * explicitly call i915_gem_object_get_fence() to synchronize fencing status
39 * for cpu access. Also note that some code wants an unfenced view, for those
40 * cases the fence can be removed forcefully with i915_gem_object_put_fence().
41 *
42 * Internally these functions will synchronize with userspace access by removing
43 * CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
44 */
45
46#define pipelined 0
47
48static struct drm_i915_private *fence_to_i915(struct i915_fence_reg *fence)
49{
50 return fence->ggtt->vm.i915;
51}
52
53static struct intel_uncore *fence_to_uncore(struct i915_fence_reg *fence)
54{
55 return fence->ggtt->vm.gt->uncore;
56}
57
58static void i965_write_fence_reg(struct i915_fence_reg *fence)
59{
60 i915_reg_t fence_reg_lo, fence_reg_hi;
61 int fence_pitch_shift;
62 u64 val;
63
64 if (GRAPHICS_VER(fence_to_i915(fence)) >= 6) {
65 fence_reg_lo = FENCE_REG_GEN6_LO(fence->id);
66 fence_reg_hi = FENCE_REG_GEN6_HI(fence->id);
67 fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
68
69 } else {
70 fence_reg_lo = FENCE_REG_965_LO(fence->id);
71 fence_reg_hi = FENCE_REG_965_HI(fence->id);
72 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
73 }
74
75 val = 0;
76 if (fence->tiling) {
77 unsigned int stride = fence->stride;
78
79 GEM_BUG_ON(!IS_ALIGNED(stride, 128));
80
81 val = fence->start + fence->size - I965_FENCE_PAGE;
82 val <<= 32;
83 val |= fence->start;
84 val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
85 if (fence->tiling == I915_TILING_Y)
86 val |= BIT(I965_FENCE_TILING_Y_SHIFT);
87 val |= I965_FENCE_REG_VALID;
88 }
89
90 if (!pipelined) {
91 struct intel_uncore *uncore = fence_to_uncore(fence);
92
93 /*
94 * To w/a incoherency with non-atomic 64-bit register updates,
95 * we split the 64-bit update into two 32-bit writes. In order
96 * for a partial fence not to be evaluated between writes, we
97 * precede the update with write to turn off the fence register,
98 * and only enable the fence as the last step.
99 *
100 * For extra levels of paranoia, we make sure each step lands
101 * before applying the next step.
102 */
103 intel_uncore_write_fw(uncore, fence_reg_lo, 0);
104 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
105
106 intel_uncore_write_fw(uncore, fence_reg_hi, upper_32_bits(val));
107 intel_uncore_write_fw(uncore, fence_reg_lo, lower_32_bits(val));
108 intel_uncore_posting_read_fw(uncore, fence_reg_lo);
109 }
110}
111
112static void i915_write_fence_reg(struct i915_fence_reg *fence)
113{
114 u32 val;
115
116 val = 0;
117 if (fence->tiling) {
118 unsigned int stride = fence->stride;
119 unsigned int tiling = fence->tiling;
120 bool is_y_tiled = tiling == I915_TILING_Y;
121
122 if (is_y_tiled && HAS_128_BYTE_Y_TILING(fence_to_i915(fence)))
123 stride /= 128;
124 else
125 stride /= 512;
126 GEM_BUG_ON(!is_power_of_2(stride));
127
128 val = fence->start;
129 if (is_y_tiled)
130 val |= BIT(I830_FENCE_TILING_Y_SHIFT);
131 val |= I915_FENCE_SIZE_BITS(fence->size);
132 val |= ilog2(stride) << I830_FENCE_PITCH_SHIFT;
133
134 val |= I830_FENCE_REG_VALID;
135 }
136
137 if (!pipelined) {
138 struct intel_uncore *uncore = fence_to_uncore(fence);
139 i915_reg_t reg = FENCE_REG(fence->id);
140
141 intel_uncore_write_fw(uncore, reg, val);
142 intel_uncore_posting_read_fw(uncore, reg);
143 }
144}
145
146static void i830_write_fence_reg(struct i915_fence_reg *fence)
147{
148 u32 val;
149
150 val = 0;
151 if (fence->tiling) {
152 unsigned int stride = fence->stride;
153
154 val = fence->start;
155 if (fence->tiling == I915_TILING_Y)
156 val |= BIT(I830_FENCE_TILING_Y_SHIFT);
157 val |= I830_FENCE_SIZE_BITS(fence->size);
158 val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
159 val |= I830_FENCE_REG_VALID;
160 }
161
162 if (!pipelined) {
163 struct intel_uncore *uncore = fence_to_uncore(fence);
164 i915_reg_t reg = FENCE_REG(fence->id);
165
166 intel_uncore_write_fw(uncore, reg, val);
167 intel_uncore_posting_read_fw(uncore, reg);
168 }
169}
170
171static void fence_write(struct i915_fence_reg *fence)
172{
173 struct drm_i915_private *i915 = fence_to_i915(fence);
174
175 /*
176 * Previous access through the fence register is marshalled by
177 * the mb() inside the fault handlers (i915_gem_release_mmaps)
178 * and explicitly managed for internal users.
179 */
180
181 if (GRAPHICS_VER(i915) == 2)
182 i830_write_fence_reg(fence);
183 else if (GRAPHICS_VER(i915) == 3)
184 i915_write_fence_reg(fence);
185 else
186 i965_write_fence_reg(fence);
187
188 /*
189 * Access through the fenced region afterwards is
190 * ordered by the posting reads whilst writing the registers.
191 */
192}
193
194static bool gpu_uses_fence_registers(struct i915_fence_reg *fence)
195{
196 return GRAPHICS_VER(fence_to_i915(fence)) < 4;
197}
198
199static int fence_update(struct i915_fence_reg *fence,
200 struct i915_vma *vma)
201{
202 struct i915_ggtt *ggtt = fence->ggtt;
203 struct intel_uncore *uncore = fence_to_uncore(fence);
204 intel_wakeref_t wakeref;
205 struct i915_vma *old;
206 int ret;
207
208 fence->tiling = 0;
209 if (vma) {
210 GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) ||
211 !i915_gem_object_get_tiling(vma->obj));
212
213 if (!i915_vma_is_map_and_fenceable(vma))
214 return -EINVAL;
215
216 if (gpu_uses_fence_registers(fence)) {
217 /* implicit 'unfenced' GPU blits */
218 ret = i915_vma_sync(vma);
219 if (ret)
220 return ret;
221 }
222
223 fence->start = vma->node.start;
224 fence->size = vma->fence_size;
225 fence->stride = i915_gem_object_get_stride(vma->obj);
226 fence->tiling = i915_gem_object_get_tiling(vma->obj);
227 }
228 WRITE_ONCE(fence->dirty, false);
229
230 old = xchg(&fence->vma, NULL);
231 if (old) {
232 /* XXX Ideally we would move the waiting to outside the mutex */
233 ret = i915_active_wait(&fence->active);
234 if (ret) {
235 fence->vma = old;
236 return ret;
237 }
238
239 i915_vma_flush_writes(old);
240
241 /*
242 * Ensure that all userspace CPU access is completed before
243 * stealing the fence.
244 */
245 if (old != vma) {
246 GEM_BUG_ON(old->fence != fence);
247 i915_vma_revoke_mmap(old);
248 old->fence = NULL;
249 }
250
251 list_move(&fence->link, &ggtt->fence_list);
252 }
253
254 /*
255 * We only need to update the register itself if the device is awake.
256 * If the device is currently powered down, we will defer the write
257 * to the runtime resume, see intel_ggtt_restore_fences().
258 *
259 * This only works for removing the fence register, on acquisition
260 * the caller must hold the rpm wakeref. The fence register must
261 * be cleared before we can use any other fences to ensure that
262 * the new fences do not overlap the elided clears, confusing HW.
263 */
264 wakeref = intel_runtime_pm_get_if_in_use(uncore->rpm);
265 if (!wakeref) {
266 GEM_BUG_ON(vma);
267 return 0;
268 }
269
270 WRITE_ONCE(fence->vma, vma);
271 fence_write(fence);
272
273 if (vma) {
274 vma->fence = fence;
275 list_move_tail(&fence->link, &ggtt->fence_list);
276 }
277
278 intel_runtime_pm_put(uncore->rpm, wakeref);
279 return 0;
280}
281
282/**
283 * i915_vma_revoke_fence - force-remove fence for a VMA
284 * @vma: vma to map linearly (not through a fence reg)
285 *
286 * This function force-removes any fence from the given object, which is useful
287 * if the kernel wants to do untiled GTT access.
288 */
289void i915_vma_revoke_fence(struct i915_vma *vma)
290{
291 struct i915_fence_reg *fence = vma->fence;
292 intel_wakeref_t wakeref;
293
294 lockdep_assert_held(&vma->vm->mutex);
295 if (!fence)
296 return;
297
298 GEM_BUG_ON(fence->vma != vma);
299 GEM_BUG_ON(!i915_active_is_idle(&fence->active));
300 GEM_BUG_ON(atomic_read(&fence->pin_count));
301
302 fence->tiling = 0;
303 WRITE_ONCE(fence->vma, NULL);
304 vma->fence = NULL;
305
306 /*
307 * Skip the write to HW if and only if the device is currently
308 * suspended.
309 *
310 * If the driver does not currently hold a wakeref (if_in_use == 0),
311 * the device may currently be runtime suspended, or it may be woken
312 * up before the suspend takes place. If the device is not suspended
313 * (powered down) and we skip clearing the fence register, the HW is
314 * left in an undefined state where we may end up with multiple
315 * registers overlapping.
316 */
317 with_intel_runtime_pm_if_active(fence_to_uncore(fence)->rpm, wakeref)
318 fence_write(fence);
319}
320
321static bool fence_is_active(const struct i915_fence_reg *fence)
322{
323 return fence->vma && i915_vma_is_active(fence->vma);
324}
325
326static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt)
327{
328 struct i915_fence_reg *active = NULL;
329 struct i915_fence_reg *fence, *fn;
330
331 list_for_each_entry_safe(fence, fn, &ggtt->fence_list, link) {
332 GEM_BUG_ON(fence->vma && fence->vma->fence != fence);
333
334 if (fence == active) /* now seen this fence twice */
335 active = ERR_PTR(-EAGAIN);
336
337 /* Prefer idle fences so we do not have to wait on the GPU */
338 if (active != ERR_PTR(-EAGAIN) && fence_is_active(fence)) {
339 if (!active)
340 active = fence;
341
342 list_move_tail(&fence->link, &ggtt->fence_list);
343 continue;
344 }
345
346 if (atomic_read(&fence->pin_count))
347 continue;
348
349 return fence;
350 }
351
352 /* Wait for completion of pending flips which consume fences */
353 if (intel_has_pending_fb_unpin(ggtt->vm.i915))
354 return ERR_PTR(-EAGAIN);
355
356 return ERR_PTR(-ENOBUFS);
357}
358
359int __i915_vma_pin_fence(struct i915_vma *vma)
360{
361 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vma->vm);
362 struct i915_fence_reg *fence;
363 struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
364 int err;
365
366 lockdep_assert_held(&vma->vm->mutex);
367
368 /* Just update our place in the LRU if our fence is getting reused. */
369 if (vma->fence) {
370 fence = vma->fence;
371 GEM_BUG_ON(fence->vma != vma);
372 atomic_inc(&fence->pin_count);
373 if (!fence->dirty) {
374 list_move_tail(&fence->link, &ggtt->fence_list);
375 return 0;
376 }
377 } else if (set) {
378 fence = fence_find(ggtt);
379 if (IS_ERR(fence))
380 return PTR_ERR(fence);
381
382 GEM_BUG_ON(atomic_read(&fence->pin_count));
383 atomic_inc(&fence->pin_count);
384 } else {
385 return 0;
386 }
387
388 err = fence_update(fence, set);
389 if (err)
390 goto out_unpin;
391
392 GEM_BUG_ON(fence->vma != set);
393 GEM_BUG_ON(vma->fence != (set ? fence : NULL));
394
395 if (set)
396 return 0;
397
398out_unpin:
399 atomic_dec(&fence->pin_count);
400 return err;
401}
402
403/**
404 * i915_vma_pin_fence - set up fencing for a vma
405 * @vma: vma to map through a fence reg
406 *
407 * When mapping objects through the GTT, userspace wants to be able to write
408 * to them without having to worry about swizzling if the object is tiled.
409 * This function walks the fence regs looking for a free one for @obj,
410 * stealing one if it can't find any.
411 *
412 * It then sets up the reg based on the object's properties: address, pitch
413 * and tiling format.
414 *
415 * For an untiled surface, this removes any existing fence.
416 *
417 * Returns:
418 *
419 * 0 on success, negative error code on failure.
420 */
421int i915_vma_pin_fence(struct i915_vma *vma)
422{
423 int err;
424
425 if (!vma->fence && !i915_gem_object_is_tiled(vma->obj))
426 return 0;
427
428 /*
429 * Note that we revoke fences on runtime suspend. Therefore the user
430 * must keep the device awake whilst using the fence.
431 */
432 assert_rpm_wakelock_held(vma->vm->gt->uncore->rpm);
433 GEM_BUG_ON(!i915_vma_is_ggtt(vma));
434
435 err = mutex_lock_interruptible(&vma->vm->mutex);
436 if (err)
437 return err;
438
439 err = __i915_vma_pin_fence(vma);
440 mutex_unlock(&vma->vm->mutex);
441
442 return err;
443}
444
445/**
446 * i915_reserve_fence - Reserve a fence for vGPU
447 * @ggtt: Global GTT
448 *
449 * This function walks the fence regs looking for a free one and remove
450 * it from the fence_list. It is used to reserve fence for vGPU to use.
451 */
452struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt)
453{
454 struct i915_fence_reg *fence;
455 int count;
456 int ret;
457
458 lockdep_assert_held(&ggtt->vm.mutex);
459
460 /* Keep at least one fence available for the display engine. */
461 count = 0;
462 list_for_each_entry(fence, &ggtt->fence_list, link)
463 count += !atomic_read(&fence->pin_count);
464 if (count <= 1)
465 return ERR_PTR(-ENOSPC);
466
467 fence = fence_find(ggtt);
468 if (IS_ERR(fence))
469 return fence;
470
471 if (fence->vma) {
472 /* Force-remove fence from VMA */
473 ret = fence_update(fence, NULL);
474 if (ret)
475 return ERR_PTR(ret);
476 }
477
478 list_del(&fence->link);
479
480 return fence;
481}
482
483/**
484 * i915_unreserve_fence - Reclaim a reserved fence
485 * @fence: the fence reg
486 *
487 * This function add a reserved fence register from vGPU to the fence_list.
488 */
489void i915_unreserve_fence(struct i915_fence_reg *fence)
490{
491 struct i915_ggtt *ggtt = fence->ggtt;
492
493 lockdep_assert_held(&ggtt->vm.mutex);
494
495 list_add(&fence->link, &ggtt->fence_list);
496}
497
498/**
499 * intel_ggtt_restore_fences - restore fence state
500 * @ggtt: Global GTT
501 *
502 * Restore the hw fence state to match the software tracking again, to be called
503 * after a gpu reset and on resume. Note that on runtime suspend we only cancel
504 * the fences, to be reacquired by the user later.
505 */
506void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)
507{
508 int i;
509
510 for (i = 0; i < ggtt->num_fences; i++)
511 fence_write(&ggtt->fence_regs[i]);
512}
513
514/**
515 * DOC: tiling swizzling details
516 *
517 * The idea behind tiling is to increase cache hit rates by rearranging
518 * pixel data so that a group of pixel accesses are in the same cacheline.
519 * Performance improvement from doing this on the back/depth buffer are on
520 * the order of 30%.
521 *
522 * Intel architectures make this somewhat more complicated, though, by
523 * adjustments made to addressing of data when the memory is in interleaved
524 * mode (matched pairs of DIMMS) to improve memory bandwidth.
525 * For interleaved memory, the CPU sends every sequential 64 bytes
526 * to an alternate memory channel so it can get the bandwidth from both.
527 *
528 * The GPU also rearranges its accesses for increased bandwidth to interleaved
529 * memory, and it matches what the CPU does for non-tiled. However, when tiled
530 * it does it a little differently, since one walks addresses not just in the
531 * X direction but also Y. So, along with alternating channels when bit
532 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
533 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
534 * are common to both the 915 and 965-class hardware.
535 *
536 * The CPU also sometimes XORs in higher bits as well, to improve
537 * bandwidth doing strided access like we do so frequently in graphics. This
538 * is called "Channel XOR Randomization" in the MCH documentation. The result
539 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
540 * decode.
541 *
542 * All of this bit 6 XORing has an effect on our memory management,
543 * as we need to make sure that the 3d driver can correctly address object
544 * contents.
545 *
546 * If we don't have interleaved memory, all tiling is safe and no swizzling is
547 * required.
548 *
549 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
550 * 17 is not just a page offset, so as we page an object out and back in,
551 * individual pages in it will have different bit 17 addresses, resulting in
552 * each 64 bytes being swapped with its neighbor!
553 *
554 * Otherwise, if interleaved, we have to tell the 3d driver what the address
555 * swizzling it needs to do is, since it's writing with the CPU to the pages
556 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
557 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
558 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
559 * to match what the GPU expects.
560 */
561
562/**
563 * detect_bit_6_swizzle - detect bit 6 swizzling pattern
564 * @ggtt: Global GGTT
565 *
566 * Detects bit 6 swizzling of address lookup between IGD access and CPU
567 * access through main memory.
568 */
569static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
570{
571 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
572 struct drm_i915_private *i915 = ggtt->vm.i915;
573 u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
574 u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
575
576 if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) {
577 /*
578 * On BDW+, swizzling is not used. We leave the CPU memory
579 * controller in charge of optimizing memory accesses without
580 * the extra address manipulation GPU side.
581 *
582 * VLV and CHV don't have GPU swizzling.
583 */
584 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
585 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
586 } else if (GRAPHICS_VER(i915) >= 6) {
587 if (i915->preserve_bios_swizzle) {
588 if (intel_uncore_read(uncore, DISP_ARB_CTL) &
589 DISP_TILE_SURFACE_SWIZZLING) {
590 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
591 swizzle_y = I915_BIT_6_SWIZZLE_9;
592 } else {
593 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
594 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
595 }
596 } else {
597 u32 dimm_c0, dimm_c1;
598
599 dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0);
600 dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1);
601 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
602 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
603 /*
604 * Enable swizzling when the channels are populated
605 * with identically sized dimms. We don't need to check
606 * the 3rd channel because no cpu with gpu attached
607 * ships in that configuration. Also, swizzling only
608 * makes sense for 2 channels anyway.
609 */
610 if (dimm_c0 == dimm_c1) {
611 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
612 swizzle_y = I915_BIT_6_SWIZZLE_9;
613 } else {
614 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
615 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
616 }
617 }
618 } else if (GRAPHICS_VER(i915) == 5) {
619 /*
620 * On Ironlake whatever DRAM config, GPU always do
621 * same swizzling setup.
622 */
623 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
624 swizzle_y = I915_BIT_6_SWIZZLE_9;
625 } else if (GRAPHICS_VER(i915) == 2) {
626 /*
627 * As far as we know, the 865 doesn't have these bit 6
628 * swizzling issues.
629 */
630 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
631 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
632 } else if (IS_G45(i915) || IS_I965G(i915) || IS_G33(i915)) {
633 /*
634 * The 965, G33, and newer, have a very flexible memory
635 * configuration. It will enable dual-channel mode
636 * (interleaving) on as much memory as it can, and the GPU
637 * will additionally sometimes enable different bit 6
638 * swizzling for tiled objects from the CPU.
639 *
640 * Here's what I found on the G965:
641 * slot fill memory size swizzling
642 * 0A 0B 1A 1B 1-ch 2-ch
643 * 512 0 0 0 512 0 O
644 * 512 0 512 0 16 1008 X
645 * 512 0 0 512 16 1008 X
646 * 0 512 0 512 16 1008 X
647 * 1024 1024 1024 0 2048 1024 O
648 *
649 * We could probably detect this based on either the DRB
650 * matching, which was the case for the swizzling required in
651 * the table above, or from the 1-ch value being less than
652 * the minimum size of a rank.
653 *
654 * Reports indicate that the swizzling actually
655 * varies depending upon page placement inside the
656 * channels, i.e. we see swizzled pages where the
657 * banks of memory are paired and unswizzled on the
658 * uneven portion, so leave that as unknown.
659 */
660 if (intel_uncore_read16(uncore, C0DRB3_BW) ==
661 intel_uncore_read16(uncore, C1DRB3_BW)) {
662 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
663 swizzle_y = I915_BIT_6_SWIZZLE_9;
664 }
665 } else {
666 u32 dcc = intel_uncore_read(uncore, DCC);
667
668 /*
669 * On 9xx chipsets, channel interleave by the CPU is
670 * determined by DCC. For single-channel, neither the CPU
671 * nor the GPU do swizzling. For dual channel interleaved,
672 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
673 * 9 for Y tiled. The CPU's interleave is independent, and
674 * can be based on either bit 11 (haven't seen this yet) or
675 * bit 17 (common).
676 */
677 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
678 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
679 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
680 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
681 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
682 break;
683 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
684 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
685 /*
686 * This is the base swizzling by the GPU for
687 * tiled buffers.
688 */
689 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
690 swizzle_y = I915_BIT_6_SWIZZLE_9;
691 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
692 /* Bit 11 swizzling by the CPU in addition. */
693 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
694 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
695 } else {
696 /* Bit 17 swizzling by the CPU in addition. */
697 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
698 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
699 }
700 break;
701 }
702
703 /* check for L-shaped memory aka modified enhanced addressing */
704 if (GRAPHICS_VER(i915) == 4 &&
705 !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
706 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
707 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
708 }
709
710 if (dcc == 0xffffffff) {
711 drm_err(&i915->drm, "Couldn't read from MCHBAR. "
712 "Disabling tiling.\n");
713 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
714 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
715 }
716 }
717
718 if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
719 swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
720 /*
721 * Userspace likes to explode if it sees unknown swizzling,
722 * so lie. We will finish the lie when reporting through
723 * the get-tiling-ioctl by reporting the physical swizzle
724 * mode as unknown instead.
725 *
726 * As we don't strictly know what the swizzling is, it may be
727 * bit17 dependent, and so we need to also prevent the pages
728 * from being moved.
729 */
730 i915->gem_quirks |= GEM_QUIRK_PIN_SWIZZLED_PAGES;
731 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
732 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
733 }
734
735 to_gt(i915)->ggtt->bit_6_swizzle_x = swizzle_x;
736 to_gt(i915)->ggtt->bit_6_swizzle_y = swizzle_y;
737}
738
739/*
740 * Swap every 64 bytes of this page around, to account for it having a new
741 * bit 17 of its physical address and therefore being interpreted differently
742 * by the GPU.
743 */
744static void swizzle_page(struct page *page)
745{
746 char temp[64];
747 char *vaddr;
748 int i;
749
750 vaddr = kmap(page);
751
752 for (i = 0; i < PAGE_SIZE; i += 128) {
753 memcpy(temp, &vaddr[i], 64);
754 memcpy(&vaddr[i], &vaddr[i + 64], 64);
755 memcpy(&vaddr[i + 64], temp, 64);
756 }
757
758 kunmap(page);
759}
760
761/**
762 * i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
763 * @obj: i915 GEM buffer object
764 * @pages: the scattergather list of physical pages
765 *
766 * This function fixes up the swizzling in case any page frame number for this
767 * object has changed in bit 17 since that state has been saved with
768 * i915_gem_object_save_bit_17_swizzle().
769 *
770 * This is called when pinning backing storage again, since the kernel is free
771 * to move unpinned backing storage around (either by directly moving pages or
772 * by swapping them out and back in again).
773 */
774void
775i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
776 struct sg_table *pages)
777{
778 struct sgt_iter sgt_iter;
779 struct page *page;
780 int i;
781
782 if (obj->bit_17 == NULL)
783 return;
784
785 i = 0;
786 for_each_sgt_page(page, sgt_iter, pages) {
787 char new_bit_17 = page_to_phys(page) >> 17;
788
789 if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
790 swizzle_page(page);
791 set_page_dirty(page);
792 }
793
794 i++;
795 }
796}
797
798/**
799 * i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
800 * @obj: i915 GEM buffer object
801 * @pages: the scattergather list of physical pages
802 *
803 * This function saves the bit 17 of each page frame number so that swizzling
804 * can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
805 * be called before the backing storage can be unpinned.
806 */
807void
808i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
809 struct sg_table *pages)
810{
811 const unsigned int page_count = obj->base.size >> PAGE_SHIFT;
812 struct sgt_iter sgt_iter;
813 struct page *page;
814 int i;
815
816 if (obj->bit_17 == NULL) {
817 obj->bit_17 = bitmap_zalloc(page_count, GFP_KERNEL);
818 if (obj->bit_17 == NULL) {
819 drm_err(&to_i915(obj->base.dev)->drm,
820 "Failed to allocate memory for bit 17 record\n");
821 return;
822 }
823 }
824
825 i = 0;
826
827 for_each_sgt_page(page, sgt_iter, pages) {
828 if (page_to_phys(page) & (1 << 17))
829 __set_bit(i, obj->bit_17);
830 else
831 __clear_bit(i, obj->bit_17);
832 i++;
833 }
834}
835
836void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
837{
838 struct drm_i915_private *i915 = ggtt->vm.i915;
839 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
840 int num_fences;
841 int i;
842
843 INIT_LIST_HEAD(&ggtt->fence_list);
844 INIT_LIST_HEAD(&ggtt->userfault_list);
845
846 detect_bit_6_swizzle(ggtt);
847
848 if (!i915_ggtt_has_aperture(ggtt))
849 num_fences = 0;
850 else if (GRAPHICS_VER(i915) >= 7 &&
851 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)))
852 num_fences = 32;
853 else if (GRAPHICS_VER(i915) >= 4 ||
854 IS_I945G(i915) || IS_I945GM(i915) ||
855 IS_G33(i915) || IS_PINEVIEW(i915))
856 num_fences = 16;
857 else
858 num_fences = 8;
859
860 if (intel_vgpu_active(i915))
861 num_fences = intel_uncore_read(uncore,
862 vgtif_reg(avail_rs.fence_num));
863 ggtt->fence_regs = kcalloc(num_fences,
864 sizeof(*ggtt->fence_regs),
865 GFP_KERNEL);
866 if (!ggtt->fence_regs)
867 num_fences = 0;
868
869 /* Initialize fence registers to zero */
870 for (i = 0; i < num_fences; i++) {
871 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
872
873 i915_active_init(&fence->active, NULL, NULL, 0);
874 fence->ggtt = ggtt;
875 fence->id = i;
876 list_add_tail(&fence->link, &ggtt->fence_list);
877 }
878 ggtt->num_fences = num_fences;
879
880 intel_ggtt_restore_fences(ggtt);
881}
882
883void intel_ggtt_fini_fences(struct i915_ggtt *ggtt)
884{
885 int i;
886
887 for (i = 0; i < ggtt->num_fences; i++) {
888 struct i915_fence_reg *fence = &ggtt->fence_regs[i];
889
890 i915_active_fini(&fence->active);
891 }
892
893 kfree(ggtt->fence_regs);
894}
895
896void intel_gt_init_swizzling(struct intel_gt *gt)
897{
898 struct drm_i915_private *i915 = gt->i915;
899 struct intel_uncore *uncore = gt->uncore;
900
901 if (GRAPHICS_VER(i915) < 5 ||
902 to_gt(i915)->ggtt->bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
903 return;
904
905 intel_uncore_rmw(uncore, DISP_ARB_CTL, 0, DISP_TILE_SURFACE_SWIZZLING);
906
907 if (GRAPHICS_VER(i915) == 5)
908 return;
909
910 intel_uncore_rmw(uncore, TILECTL, 0, TILECTL_SWZCTL);
911
912 if (GRAPHICS_VER(i915) == 6)
913 intel_uncore_write(uncore,
914 ARB_MODE,
915 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
916 else if (GRAPHICS_VER(i915) == 7)
917 intel_uncore_write(uncore,
918 ARB_MODE,
919 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
920 else if (GRAPHICS_VER(i915) == 8)
921 intel_uncore_write(uncore,
922 GAMTARBMODE,
923 _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
924 else
925 MISSING_CASE(GRAPHICS_VER(i915));
926}