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1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/gpio.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/ioport.h>
24#include <linux/irq.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/spinlock.h>
31#include <linux/slab.h>
32
33struct gpio_rcar_priv {
34 void __iomem *base;
35 spinlock_t lock;
36 struct platform_device *pdev;
37 struct gpio_chip gpio_chip;
38 struct irq_chip irq_chip;
39 struct clk *clk;
40 unsigned int irq_parent;
41 bool has_both_edge_trigger;
42 bool needs_clk;
43};
44
45#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
46#define INOUTSEL 0x04 /* General Input/Output Switching Register */
47#define OUTDT 0x08 /* General Output Register */
48#define INDT 0x0c /* General Input Register */
49#define INTDT 0x10 /* Interrupt Display Register */
50#define INTCLR 0x14 /* Interrupt Clear Register */
51#define INTMSK 0x18 /* Interrupt Mask Register */
52#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
53#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
54#define EDGLEVEL 0x24 /* Edge/level Select Register */
55#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
56#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
57
58#define RCAR_MAX_GPIO_PER_BANK 32
59
60static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61{
62 return ioread32(p->base + offs);
63}
64
65static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
66 u32 value)
67{
68 iowrite32(value, p->base + offs);
69}
70
71static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
72 int bit, bool value)
73{
74 u32 tmp = gpio_rcar_read(p, offs);
75
76 if (value)
77 tmp |= BIT(bit);
78 else
79 tmp &= ~BIT(bit);
80
81 gpio_rcar_write(p, offs, tmp);
82}
83
84static void gpio_rcar_irq_disable(struct irq_data *d)
85{
86 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
88
89 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
90}
91
92static void gpio_rcar_irq_enable(struct irq_data *d)
93{
94 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
95 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
96
97 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
98}
99
100static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
101 unsigned int hwirq,
102 bool active_high_rising_edge,
103 bool level_trigger,
104 bool both)
105{
106 unsigned long flags;
107
108 /* follow steps in the GPIO documentation for
109 * "Setting Edge-Sensitive Interrupt Input Mode" and
110 * "Setting Level-Sensitive Interrupt Input Mode"
111 */
112
113 spin_lock_irqsave(&p->lock, flags);
114
115 /* Configure postive or negative logic in POSNEG */
116 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
117
118 /* Configure edge or level trigger in EDGLEVEL */
119 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
120
121 /* Select one edge or both edges in BOTHEDGE */
122 if (p->has_both_edge_trigger)
123 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
124
125 /* Select "Interrupt Input Mode" in IOINTSEL */
126 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
127
128 /* Write INTCLR in case of edge trigger */
129 if (!level_trigger)
130 gpio_rcar_write(p, INTCLR, BIT(hwirq));
131
132 spin_unlock_irqrestore(&p->lock, flags);
133}
134
135static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
136{
137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
138 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
139 unsigned int hwirq = irqd_to_hwirq(d);
140
141 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
142
143 switch (type & IRQ_TYPE_SENSE_MASK) {
144 case IRQ_TYPE_LEVEL_HIGH:
145 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
146 false);
147 break;
148 case IRQ_TYPE_LEVEL_LOW:
149 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
150 false);
151 break;
152 case IRQ_TYPE_EDGE_RISING:
153 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
154 false);
155 break;
156 case IRQ_TYPE_EDGE_FALLING:
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
158 false);
159 break;
160 case IRQ_TYPE_EDGE_BOTH:
161 if (!p->has_both_edge_trigger)
162 return -EINVAL;
163 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 true);
165 break;
166 default:
167 return -EINVAL;
168 }
169 return 0;
170}
171
172static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
173{
174 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
175 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
176 int error;
177
178 if (p->irq_parent) {
179 error = irq_set_irq_wake(p->irq_parent, on);
180 if (error) {
181 dev_dbg(&p->pdev->dev,
182 "irq %u doesn't support irq_set_wake\n",
183 p->irq_parent);
184 p->irq_parent = 0;
185 }
186 }
187
188 if (!p->clk)
189 return 0;
190
191 if (on)
192 clk_enable(p->clk);
193 else
194 clk_disable(p->clk);
195
196 return 0;
197}
198
199static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
200{
201 struct gpio_rcar_priv *p = dev_id;
202 u32 pending;
203 unsigned int offset, irqs_handled = 0;
204
205 while ((pending = gpio_rcar_read(p, INTDT) &
206 gpio_rcar_read(p, INTMSK))) {
207 offset = __ffs(pending);
208 gpio_rcar_write(p, INTCLR, BIT(offset));
209 generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
210 offset));
211 irqs_handled++;
212 }
213
214 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
215}
216
217static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
218 unsigned int gpio,
219 bool output)
220{
221 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
222 unsigned long flags;
223
224 /* follow steps in the GPIO documentation for
225 * "Setting General Output Mode" and
226 * "Setting General Input Mode"
227 */
228
229 spin_lock_irqsave(&p->lock, flags);
230
231 /* Configure postive logic in POSNEG */
232 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
233
234 /* Select "General Input/Output Mode" in IOINTSEL */
235 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
236
237 /* Select Input Mode or Output Mode in INOUTSEL */
238 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
239
240 spin_unlock_irqrestore(&p->lock, flags);
241}
242
243static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
244{
245 return pinctrl_request_gpio(chip->base + offset);
246}
247
248static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
249{
250 pinctrl_free_gpio(chip->base + offset);
251
252 /*
253 * Set the GPIO as an input to ensure that the next GPIO request won't
254 * drive the GPIO pin as an output.
255 */
256 gpio_rcar_config_general_input_output_mode(chip, offset, false);
257}
258
259static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
260{
261 gpio_rcar_config_general_input_output_mode(chip, offset, false);
262 return 0;
263}
264
265static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
266{
267 u32 bit = BIT(offset);
268
269 /* testing on r8a7790 shows that INDT does not show correct pin state
270 * when configured as output, so use OUTDT in case of output pins */
271 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
272 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
273 else
274 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
275}
276
277static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
278{
279 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
280 unsigned long flags;
281
282 spin_lock_irqsave(&p->lock, flags);
283 gpio_rcar_modify_bit(p, OUTDT, offset, value);
284 spin_unlock_irqrestore(&p->lock, flags);
285}
286
287static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
288 int value)
289{
290 /* write GPIO value to output before selecting output mode of pin */
291 gpio_rcar_set(chip, offset, value);
292 gpio_rcar_config_general_input_output_mode(chip, offset, true);
293 return 0;
294}
295
296struct gpio_rcar_info {
297 bool has_both_edge_trigger;
298 bool needs_clk;
299};
300
301static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
302 .has_both_edge_trigger = false,
303 .needs_clk = false,
304};
305
306static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
307 .has_both_edge_trigger = true,
308 .needs_clk = true,
309};
310
311static const struct of_device_id gpio_rcar_of_table[] = {
312 {
313 .compatible = "renesas,gpio-r8a7790",
314 .data = &gpio_rcar_info_gen2,
315 }, {
316 .compatible = "renesas,gpio-r8a7791",
317 .data = &gpio_rcar_info_gen2,
318 }, {
319 .compatible = "renesas,gpio-r8a7793",
320 .data = &gpio_rcar_info_gen2,
321 }, {
322 .compatible = "renesas,gpio-r8a7794",
323 .data = &gpio_rcar_info_gen2,
324 }, {
325 .compatible = "renesas,gpio-r8a7795",
326 /* Gen3 GPIO is identical to Gen2. */
327 .data = &gpio_rcar_info_gen2,
328 }, {
329 .compatible = "renesas,gpio-rcar",
330 .data = &gpio_rcar_info_gen1,
331 }, {
332 /* Terminator */
333 },
334};
335
336MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
337
338static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
339{
340 struct device_node *np = p->pdev->dev.of_node;
341 const struct of_device_id *match;
342 const struct gpio_rcar_info *info;
343 struct of_phandle_args args;
344 int ret;
345
346 match = of_match_node(gpio_rcar_of_table, np);
347 if (!match)
348 return -EINVAL;
349
350 info = match->data;
351
352 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
353 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
354 p->has_both_edge_trigger = info->has_both_edge_trigger;
355 p->needs_clk = info->needs_clk;
356
357 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
358 dev_warn(&p->pdev->dev,
359 "Invalid number of gpio lines %u, using %u\n", *npins,
360 RCAR_MAX_GPIO_PER_BANK);
361 *npins = RCAR_MAX_GPIO_PER_BANK;
362 }
363
364 return 0;
365}
366
367static int gpio_rcar_probe(struct platform_device *pdev)
368{
369 struct gpio_rcar_priv *p;
370 struct resource *io, *irq;
371 struct gpio_chip *gpio_chip;
372 struct irq_chip *irq_chip;
373 struct device *dev = &pdev->dev;
374 const char *name = dev_name(dev);
375 unsigned int npins;
376 int ret;
377
378 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
379 if (!p)
380 return -ENOMEM;
381
382 p->pdev = pdev;
383 spin_lock_init(&p->lock);
384
385 /* Get device configuration from DT node */
386 ret = gpio_rcar_parse_dt(p, &npins);
387 if (ret < 0)
388 return ret;
389
390 platform_set_drvdata(pdev, p);
391
392 p->clk = devm_clk_get(dev, NULL);
393 if (IS_ERR(p->clk)) {
394 if (p->needs_clk) {
395 dev_err(dev, "unable to get clock\n");
396 ret = PTR_ERR(p->clk);
397 goto err0;
398 }
399 p->clk = NULL;
400 }
401
402 pm_runtime_enable(dev);
403 pm_runtime_get_sync(dev);
404
405 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
406 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
407
408 if (!io || !irq) {
409 dev_err(dev, "missing IRQ or IOMEM\n");
410 ret = -EINVAL;
411 goto err0;
412 }
413
414 p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
415 if (!p->base) {
416 dev_err(dev, "failed to remap I/O memory\n");
417 ret = -ENXIO;
418 goto err0;
419 }
420
421 gpio_chip = &p->gpio_chip;
422 gpio_chip->request = gpio_rcar_request;
423 gpio_chip->free = gpio_rcar_free;
424 gpio_chip->direction_input = gpio_rcar_direction_input;
425 gpio_chip->get = gpio_rcar_get;
426 gpio_chip->direction_output = gpio_rcar_direction_output;
427 gpio_chip->set = gpio_rcar_set;
428 gpio_chip->label = name;
429 gpio_chip->parent = dev;
430 gpio_chip->owner = THIS_MODULE;
431 gpio_chip->base = -1;
432 gpio_chip->ngpio = npins;
433
434 irq_chip = &p->irq_chip;
435 irq_chip->name = name;
436 irq_chip->irq_mask = gpio_rcar_irq_disable;
437 irq_chip->irq_unmask = gpio_rcar_irq_enable;
438 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
439 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
440 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
441
442 ret = gpiochip_add_data(gpio_chip, p);
443 if (ret) {
444 dev_err(dev, "failed to add GPIO controller\n");
445 goto err0;
446 }
447
448 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
449 IRQ_TYPE_NONE);
450 if (ret) {
451 dev_err(dev, "cannot add irqchip\n");
452 goto err1;
453 }
454
455 p->irq_parent = irq->start;
456 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
457 IRQF_SHARED, name, p)) {
458 dev_err(dev, "failed to request IRQ\n");
459 ret = -ENOENT;
460 goto err1;
461 }
462
463 dev_info(dev, "driving %d GPIOs\n", npins);
464
465 return 0;
466
467err1:
468 gpiochip_remove(gpio_chip);
469err0:
470 pm_runtime_put(dev);
471 pm_runtime_disable(dev);
472 return ret;
473}
474
475static int gpio_rcar_remove(struct platform_device *pdev)
476{
477 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
478
479 gpiochip_remove(&p->gpio_chip);
480
481 pm_runtime_put(&pdev->dev);
482 pm_runtime_disable(&pdev->dev);
483 return 0;
484}
485
486static struct platform_driver gpio_rcar_device_driver = {
487 .probe = gpio_rcar_probe,
488 .remove = gpio_rcar_remove,
489 .driver = {
490 .name = "gpio_rcar",
491 .of_match_table = of_match_ptr(gpio_rcar_of_table),
492 }
493};
494
495module_platform_driver(gpio_rcar_device_driver);
496
497MODULE_AUTHOR("Magnus Damm");
498MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
499MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas R-Car GPIO Support
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 */
8
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/spinlock.h>
22#include <linux/slab.h>
23
24struct gpio_rcar_bank_info {
25 u32 iointsel;
26 u32 inoutsel;
27 u32 outdt;
28 u32 posneg;
29 u32 edglevel;
30 u32 bothedge;
31 u32 intmsk;
32};
33
34struct gpio_rcar_info {
35 bool has_outdtsel;
36 bool has_both_edge_trigger;
37 bool has_always_in;
38 bool has_inen;
39};
40
41struct gpio_rcar_priv {
42 void __iomem *base;
43 raw_spinlock_t lock;
44 struct device *dev;
45 struct gpio_chip gpio_chip;
46 unsigned int irq_parent;
47 atomic_t wakeup_path;
48 struct gpio_rcar_info info;
49 struct gpio_rcar_bank_info bank_info;
50};
51
52#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
53#define INOUTSEL 0x04 /* General Input/Output Switching Register */
54#define OUTDT 0x08 /* General Output Register */
55#define INDT 0x0c /* General Input Register */
56#define INTDT 0x10 /* Interrupt Display Register */
57#define INTCLR 0x14 /* Interrupt Clear Register */
58#define INTMSK 0x18 /* Interrupt Mask Register */
59#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
60#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
61#define EDGLEVEL 0x24 /* Edge/level Select Register */
62#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
63#define OUTDTSEL 0x40 /* Output Data Select Register */
64#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
65#define INEN 0x50 /* General Input Enable Register */
66
67#define RCAR_MAX_GPIO_PER_BANK 32
68
69static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
70{
71 return ioread32(p->base + offs);
72}
73
74static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
75 u32 value)
76{
77 iowrite32(value, p->base + offs);
78}
79
80static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
81 int bit, bool value)
82{
83 u32 tmp = gpio_rcar_read(p, offs);
84
85 if (value)
86 tmp |= BIT(bit);
87 else
88 tmp &= ~BIT(bit);
89
90 gpio_rcar_write(p, offs, tmp);
91}
92
93static void gpio_rcar_irq_disable(struct irq_data *d)
94{
95 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
96 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
97 irq_hw_number_t hwirq = irqd_to_hwirq(d);
98
99 gpio_rcar_write(p, INTMSK, ~BIT(hwirq));
100 gpiochip_disable_irq(gc, hwirq);
101}
102
103static void gpio_rcar_irq_enable(struct irq_data *d)
104{
105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
106 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
107 irq_hw_number_t hwirq = irqd_to_hwirq(d);
108
109 gpiochip_enable_irq(gc, hwirq);
110 gpio_rcar_write(p, MSKCLR, BIT(hwirq));
111}
112
113static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
114 unsigned int hwirq,
115 bool active_high_rising_edge,
116 bool level_trigger,
117 bool both)
118{
119 unsigned long flags;
120
121 /* follow steps in the GPIO documentation for
122 * "Setting Edge-Sensitive Interrupt Input Mode" and
123 * "Setting Level-Sensitive Interrupt Input Mode"
124 */
125
126 raw_spin_lock_irqsave(&p->lock, flags);
127
128 /* Configure positive or negative logic in POSNEG */
129 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
130
131 /* Configure edge or level trigger in EDGLEVEL */
132 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
133
134 /* Select one edge or both edges in BOTHEDGE */
135 if (p->info.has_both_edge_trigger)
136 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
137
138 /* Select "Interrupt Input Mode" in IOINTSEL */
139 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
140
141 /* Write INTCLR in case of edge trigger */
142 if (!level_trigger)
143 gpio_rcar_write(p, INTCLR, BIT(hwirq));
144
145 raw_spin_unlock_irqrestore(&p->lock, flags);
146}
147
148static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
149{
150 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
151 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
152 unsigned int hwirq = irqd_to_hwirq(d);
153
154 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
155
156 switch (type & IRQ_TYPE_SENSE_MASK) {
157 case IRQ_TYPE_LEVEL_HIGH:
158 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
159 false);
160 break;
161 case IRQ_TYPE_LEVEL_LOW:
162 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
163 false);
164 break;
165 case IRQ_TYPE_EDGE_RISING:
166 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
167 false);
168 break;
169 case IRQ_TYPE_EDGE_FALLING:
170 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
171 false);
172 break;
173 case IRQ_TYPE_EDGE_BOTH:
174 if (!p->info.has_both_edge_trigger)
175 return -EINVAL;
176 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
177 true);
178 break;
179 default:
180 return -EINVAL;
181 }
182 return 0;
183}
184
185static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
186{
187 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
188 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
189 int error;
190
191 if (p->irq_parent) {
192 error = irq_set_irq_wake(p->irq_parent, on);
193 if (error) {
194 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
195 p->irq_parent);
196 p->irq_parent = 0;
197 }
198 }
199
200 if (on)
201 atomic_inc(&p->wakeup_path);
202 else
203 atomic_dec(&p->wakeup_path);
204
205 return 0;
206}
207
208static const struct irq_chip gpio_rcar_irq_chip = {
209 .name = "gpio-rcar",
210 .irq_mask = gpio_rcar_irq_disable,
211 .irq_unmask = gpio_rcar_irq_enable,
212 .irq_set_type = gpio_rcar_irq_set_type,
213 .irq_set_wake = gpio_rcar_irq_set_wake,
214 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED |
215 IRQCHIP_MASK_ON_SUSPEND,
216 GPIOCHIP_IRQ_RESOURCE_HELPERS,
217};
218
219static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
220{
221 struct gpio_rcar_priv *p = dev_id;
222 u32 pending;
223 unsigned int offset, irqs_handled = 0;
224
225 while ((pending = gpio_rcar_read(p, INTDT) &
226 gpio_rcar_read(p, INTMSK))) {
227 offset = __ffs(pending);
228 gpio_rcar_write(p, INTCLR, BIT(offset));
229 generic_handle_domain_irq(p->gpio_chip.irq.domain,
230 offset);
231 irqs_handled++;
232 }
233
234 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
235}
236
237static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
238 unsigned int gpio,
239 bool output)
240{
241 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
242 unsigned long flags;
243
244 /* follow steps in the GPIO documentation for
245 * "Setting General Output Mode" and
246 * "Setting General Input Mode"
247 */
248
249 raw_spin_lock_irqsave(&p->lock, flags);
250
251 /* Configure positive logic in POSNEG */
252 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
253
254 /* Select "General Input/Output Mode" in IOINTSEL */
255 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
256
257 /* Select Input Mode or Output Mode in INOUTSEL */
258 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
259
260 /* Select General Output Register to output data in OUTDTSEL */
261 if (p->info.has_outdtsel && output)
262 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
263
264 raw_spin_unlock_irqrestore(&p->lock, flags);
265}
266
267static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
268{
269 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
270 int error;
271
272 error = pm_runtime_get_sync(p->dev);
273 if (error < 0) {
274 pm_runtime_put(p->dev);
275 return error;
276 }
277
278 error = pinctrl_gpio_request(chip, offset);
279 if (error)
280 pm_runtime_put(p->dev);
281
282 return error;
283}
284
285static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
286{
287 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
288
289 pinctrl_gpio_free(chip, offset);
290
291 /*
292 * Set the GPIO as an input to ensure that the next GPIO request won't
293 * drive the GPIO pin as an output.
294 */
295 gpio_rcar_config_general_input_output_mode(chip, offset, false);
296
297 pm_runtime_put(p->dev);
298}
299
300static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
301{
302 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
303
304 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
305 return GPIO_LINE_DIRECTION_OUT;
306
307 return GPIO_LINE_DIRECTION_IN;
308}
309
310static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
311{
312 gpio_rcar_config_general_input_output_mode(chip, offset, false);
313 return 0;
314}
315
316static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
317{
318 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
319 u32 bit = BIT(offset);
320
321 /*
322 * Before R-Car Gen3, INDT does not show correct pin state when
323 * configured as output, so use OUTDT in case of output pins
324 */
325 if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit))
326 return !!(gpio_rcar_read(p, OUTDT) & bit);
327 else
328 return !!(gpio_rcar_read(p, INDT) & bit);
329}
330
331static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
332 unsigned long *bits)
333{
334 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
335 u32 bankmask, outputs, m, val = 0;
336 unsigned long flags;
337
338 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
339 if (chip->valid_mask)
340 bankmask &= chip->valid_mask[0];
341
342 if (!bankmask)
343 return 0;
344
345 if (p->info.has_always_in) {
346 bits[0] = gpio_rcar_read(p, INDT) & bankmask;
347 return 0;
348 }
349
350 raw_spin_lock_irqsave(&p->lock, flags);
351 outputs = gpio_rcar_read(p, INOUTSEL);
352 m = outputs & bankmask;
353 if (m)
354 val |= gpio_rcar_read(p, OUTDT) & m;
355
356 m = ~outputs & bankmask;
357 if (m)
358 val |= gpio_rcar_read(p, INDT) & m;
359 raw_spin_unlock_irqrestore(&p->lock, flags);
360
361 bits[0] = val;
362 return 0;
363}
364
365static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
366{
367 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
368 unsigned long flags;
369
370 raw_spin_lock_irqsave(&p->lock, flags);
371 gpio_rcar_modify_bit(p, OUTDT, offset, value);
372 raw_spin_unlock_irqrestore(&p->lock, flags);
373}
374
375static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
376 unsigned long *bits)
377{
378 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
379 unsigned long flags;
380 u32 val, bankmask;
381
382 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
383 if (chip->valid_mask)
384 bankmask &= chip->valid_mask[0];
385
386 if (!bankmask)
387 return;
388
389 raw_spin_lock_irqsave(&p->lock, flags);
390 val = gpio_rcar_read(p, OUTDT);
391 val &= ~bankmask;
392 val |= (bankmask & bits[0]);
393 gpio_rcar_write(p, OUTDT, val);
394 raw_spin_unlock_irqrestore(&p->lock, flags);
395}
396
397static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
398 int value)
399{
400 /* write GPIO value to output before selecting output mode of pin */
401 gpio_rcar_set(chip, offset, value);
402 gpio_rcar_config_general_input_output_mode(chip, offset, true);
403 return 0;
404}
405
406static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
407 .has_outdtsel = false,
408 .has_both_edge_trigger = false,
409 .has_always_in = false,
410 .has_inen = false,
411};
412
413static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
414 .has_outdtsel = true,
415 .has_both_edge_trigger = true,
416 .has_always_in = false,
417 .has_inen = false,
418};
419
420static const struct gpio_rcar_info gpio_rcar_info_gen3 = {
421 .has_outdtsel = true,
422 .has_both_edge_trigger = true,
423 .has_always_in = true,
424 .has_inen = false,
425};
426
427static const struct gpio_rcar_info gpio_rcar_info_gen4 = {
428 .has_outdtsel = true,
429 .has_both_edge_trigger = true,
430 .has_always_in = true,
431 .has_inen = true,
432};
433
434static const struct of_device_id gpio_rcar_of_table[] = {
435 {
436 .compatible = "renesas,gpio-r8a779a0",
437 .data = &gpio_rcar_info_gen4,
438 }, {
439 .compatible = "renesas,rcar-gen1-gpio",
440 .data = &gpio_rcar_info_gen1,
441 }, {
442 .compatible = "renesas,rcar-gen2-gpio",
443 .data = &gpio_rcar_info_gen2,
444 }, {
445 .compatible = "renesas,rcar-gen3-gpio",
446 .data = &gpio_rcar_info_gen3,
447 }, {
448 .compatible = "renesas,rcar-gen4-gpio",
449 .data = &gpio_rcar_info_gen4,
450 }, {
451 .compatible = "renesas,gpio-rcar",
452 .data = &gpio_rcar_info_gen1,
453 }, {
454 /* Terminator */
455 },
456};
457
458MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
459
460static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
461{
462 struct device_node *np = p->dev->of_node;
463 const struct gpio_rcar_info *info;
464 struct of_phandle_args args;
465 int ret;
466
467 info = of_device_get_match_data(p->dev);
468 p->info = *info;
469
470 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
471 if (ret) {
472 *npins = RCAR_MAX_GPIO_PER_BANK;
473 } else {
474 *npins = args.args[2];
475 of_node_put(args.np);
476 }
477
478 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
479 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
480 *npins, RCAR_MAX_GPIO_PER_BANK);
481 *npins = RCAR_MAX_GPIO_PER_BANK;
482 }
483
484 return 0;
485}
486
487static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p)
488{
489 u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0);
490
491 /* Select "Input Enable" in INEN */
492 if (p->gpio_chip.valid_mask)
493 mask &= p->gpio_chip.valid_mask[0];
494 if (mask)
495 gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask);
496}
497
498static int gpio_rcar_probe(struct platform_device *pdev)
499{
500 struct gpio_rcar_priv *p;
501 struct gpio_chip *gpio_chip;
502 struct gpio_irq_chip *girq;
503 struct device *dev = &pdev->dev;
504 const char *name = dev_name(dev);
505 unsigned int npins;
506 int ret;
507
508 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
509 if (!p)
510 return -ENOMEM;
511
512 p->dev = dev;
513 raw_spin_lock_init(&p->lock);
514
515 /* Get device configuration from DT node */
516 ret = gpio_rcar_parse_dt(p, &npins);
517 if (ret < 0)
518 return ret;
519
520 platform_set_drvdata(pdev, p);
521
522 pm_runtime_enable(dev);
523
524 ret = platform_get_irq(pdev, 0);
525 if (ret < 0)
526 goto err0;
527 p->irq_parent = ret;
528
529 p->base = devm_platform_ioremap_resource(pdev, 0);
530 if (IS_ERR(p->base)) {
531 ret = PTR_ERR(p->base);
532 goto err0;
533 }
534
535 gpio_chip = &p->gpio_chip;
536 gpio_chip->request = gpio_rcar_request;
537 gpio_chip->free = gpio_rcar_free;
538 gpio_chip->get_direction = gpio_rcar_get_direction;
539 gpio_chip->direction_input = gpio_rcar_direction_input;
540 gpio_chip->get = gpio_rcar_get;
541 gpio_chip->get_multiple = gpio_rcar_get_multiple;
542 gpio_chip->direction_output = gpio_rcar_direction_output;
543 gpio_chip->set = gpio_rcar_set;
544 gpio_chip->set_multiple = gpio_rcar_set_multiple;
545 gpio_chip->label = name;
546 gpio_chip->parent = dev;
547 gpio_chip->owner = THIS_MODULE;
548 gpio_chip->base = -1;
549 gpio_chip->ngpio = npins;
550
551 girq = &gpio_chip->irq;
552 gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip);
553 /* This will let us handle the parent IRQ in the driver */
554 girq->parent_handler = NULL;
555 girq->num_parents = 0;
556 girq->parents = NULL;
557 girq->default_type = IRQ_TYPE_NONE;
558 girq->handler = handle_level_irq;
559
560 ret = gpiochip_add_data(gpio_chip, p);
561 if (ret) {
562 dev_err(dev, "failed to add GPIO controller\n");
563 goto err0;
564 }
565
566 irq_domain_set_pm_device(gpio_chip->irq.domain, dev);
567 ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler,
568 IRQF_SHARED, name, p);
569 if (ret) {
570 dev_err(dev, "failed to request IRQ\n");
571 goto err1;
572 }
573
574 if (p->info.has_inen) {
575 pm_runtime_get_sync(dev);
576 gpio_rcar_enable_inputs(p);
577 pm_runtime_put(dev);
578 }
579
580 dev_info(dev, "driving %d GPIOs\n", npins);
581
582 return 0;
583
584err1:
585 gpiochip_remove(gpio_chip);
586err0:
587 pm_runtime_disable(dev);
588 return ret;
589}
590
591static void gpio_rcar_remove(struct platform_device *pdev)
592{
593 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
594
595 gpiochip_remove(&p->gpio_chip);
596
597 pm_runtime_disable(&pdev->dev);
598}
599
600#ifdef CONFIG_PM_SLEEP
601static int gpio_rcar_suspend(struct device *dev)
602{
603 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
604
605 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
606 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
607 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
608 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
609 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
610 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
611 if (p->info.has_both_edge_trigger)
612 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
613
614 if (atomic_read(&p->wakeup_path))
615 device_set_wakeup_path(dev);
616
617 return 0;
618}
619
620static int gpio_rcar_resume(struct device *dev)
621{
622 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
623 unsigned int offset;
624 u32 mask;
625
626 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
627 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
628 continue;
629
630 mask = BIT(offset);
631 /* I/O pin */
632 if (!(p->bank_info.iointsel & mask)) {
633 if (p->bank_info.inoutsel & mask)
634 gpio_rcar_direction_output(
635 &p->gpio_chip, offset,
636 !!(p->bank_info.outdt & mask));
637 else
638 gpio_rcar_direction_input(&p->gpio_chip,
639 offset);
640 } else {
641 /* Interrupt pin */
642 gpio_rcar_config_interrupt_input_mode(
643 p,
644 offset,
645 !(p->bank_info.posneg & mask),
646 !(p->bank_info.edglevel & mask),
647 !!(p->bank_info.bothedge & mask));
648
649 if (p->bank_info.intmsk & mask)
650 gpio_rcar_write(p, MSKCLR, mask);
651 }
652 }
653
654 if (p->info.has_inen)
655 gpio_rcar_enable_inputs(p);
656
657 return 0;
658}
659#endif /* CONFIG_PM_SLEEP*/
660
661static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
662
663static struct platform_driver gpio_rcar_device_driver = {
664 .probe = gpio_rcar_probe,
665 .remove = gpio_rcar_remove,
666 .driver = {
667 .name = "gpio_rcar",
668 .pm = &gpio_rcar_pm_ops,
669 .of_match_table = gpio_rcar_of_table,
670 }
671};
672
673module_platform_driver(gpio_rcar_device_driver);
674
675MODULE_AUTHOR("Magnus Damm");
676MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
677MODULE_LICENSE("GPL v2");