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1/*
2 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
3 *
4 * Copyright 2015 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/cpu.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/irqchip.h>
21#include <linux/irqdomain.h>
22#include <asm/exception.h>
23
24#define LOCAL_CONTROL 0x000
25#define LOCAL_PRESCALER 0x008
26
27/*
28 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
29 * next 2 bits identify the CPU that the GPU FIQ goes to.
30 */
31#define LOCAL_GPU_ROUTING 0x00c
32/* When setting bits 0-3, enables PMU interrupts on that CPU. */
33#define LOCAL_PM_ROUTING_SET 0x010
34/* When setting bits 0-3, disables PMU interrupts on that CPU. */
35#define LOCAL_PM_ROUTING_CLR 0x014
36/*
37 * The low 4 bits of this are the CPU's timer IRQ enables, and the
38 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
39 * bits).
40 */
41#define LOCAL_TIMER_INT_CONTROL0 0x040
42/*
43 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
44 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
45 * override the IRQ bits).
46 */
47#define LOCAL_MAILBOX_INT_CONTROL0 0x050
48/*
49 * The CPU's interrupt status register. Bits are defined by the the
50 * LOCAL_IRQ_* bits below.
51 */
52#define LOCAL_IRQ_PENDING0 0x060
53/* Same status bits as above, but for FIQ. */
54#define LOCAL_FIQ_PENDING0 0x070
55/*
56 * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and
57 * these bits are organized by mailbox number and then CPU number. We
58 * use mailbox 0 for IPIs. The mailbox's interrupt is raised while
59 * any bit is set.
60 */
61#define LOCAL_MAILBOX0_SET0 0x080
62#define LOCAL_MAILBOX3_SET0 0x08c
63/* Mailbox write-to-clear bits. */
64#define LOCAL_MAILBOX0_CLR0 0x0c0
65#define LOCAL_MAILBOX3_CLR0 0x0cc
66
67#define LOCAL_IRQ_CNTPSIRQ 0
68#define LOCAL_IRQ_CNTPNSIRQ 1
69#define LOCAL_IRQ_CNTHPIRQ 2
70#define LOCAL_IRQ_CNTVIRQ 3
71#define LOCAL_IRQ_MAILBOX0 4
72#define LOCAL_IRQ_MAILBOX1 5
73#define LOCAL_IRQ_MAILBOX2 6
74#define LOCAL_IRQ_MAILBOX3 7
75#define LOCAL_IRQ_GPU_FAST 8
76#define LOCAL_IRQ_PMU_FAST 9
77#define LAST_IRQ LOCAL_IRQ_PMU_FAST
78
79struct bcm2836_arm_irqchip_intc {
80 struct irq_domain *domain;
81 void __iomem *base;
82};
83
84static struct bcm2836_arm_irqchip_intc intc __read_mostly;
85
86static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
87 unsigned int bit,
88 int cpu)
89{
90 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
91
92 writel(readl(reg) & ~BIT(bit), reg);
93}
94
95static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
96 unsigned int bit,
97 int cpu)
98{
99 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
100
101 writel(readl(reg) | BIT(bit), reg);
102}
103
104static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
105{
106 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
107 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
108 smp_processor_id());
109}
110
111static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
112{
113 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
114 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
115 smp_processor_id());
116}
117
118static struct irq_chip bcm2836_arm_irqchip_timer = {
119 .name = "bcm2836-timer",
120 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
121 .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
122};
123
124static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
125{
126 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
127}
128
129static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
130{
131 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
132}
133
134static struct irq_chip bcm2836_arm_irqchip_pmu = {
135 .name = "bcm2836-pmu",
136 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
137 .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
138};
139
140static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
141{
142}
143
144static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
145{
146}
147
148static struct irq_chip bcm2836_arm_irqchip_gpu = {
149 .name = "bcm2836-gpu",
150 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
151 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
152};
153
154static void bcm2836_arm_irqchip_register_irq(int hwirq, struct irq_chip *chip)
155{
156 int irq = irq_create_mapping(intc.domain, hwirq);
157
158 irq_set_percpu_devid(irq);
159 irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
160 irq_set_status_flags(irq, IRQ_NOAUTOEN);
161}
162
163static void
164__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
165{
166 int cpu = smp_processor_id();
167 u32 stat;
168
169 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
170 if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
171#ifdef CONFIG_SMP
172 void __iomem *mailbox0 = (intc.base +
173 LOCAL_MAILBOX0_CLR0 + 16 * cpu);
174 u32 mbox_val = readl(mailbox0);
175 u32 ipi = ffs(mbox_val) - 1;
176
177 writel(1 << ipi, mailbox0);
178 handle_IPI(ipi, regs);
179#endif
180 } else if (stat) {
181 u32 hwirq = ffs(stat) - 1;
182
183 handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
184 }
185}
186
187#ifdef CONFIG_SMP
188static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask,
189 unsigned int ipi)
190{
191 int cpu;
192 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
193
194 /*
195 * Ensure that stores to normal memory are visible to the
196 * other CPUs before issuing the IPI.
197 */
198 dsb();
199
200 for_each_cpu(cpu, mask) {
201 writel(1 << ipi, mailbox0_base + 16 * cpu);
202 }
203}
204
205/* Unmasks the IPI on the CPU when it's online. */
206static int bcm2836_arm_irqchip_cpu_notify(struct notifier_block *nfb,
207 unsigned long action, void *hcpu)
208{
209 unsigned int cpu = (unsigned long)hcpu;
210 unsigned int int_reg = LOCAL_MAILBOX_INT_CONTROL0;
211 unsigned int mailbox = 0;
212
213 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
214 bcm2836_arm_irqchip_unmask_per_cpu_irq(int_reg, mailbox, cpu);
215 else if (action == CPU_DYING)
216 bcm2836_arm_irqchip_mask_per_cpu_irq(int_reg, mailbox, cpu);
217
218 return NOTIFY_OK;
219}
220
221static struct notifier_block bcm2836_arm_irqchip_cpu_notifier = {
222 .notifier_call = bcm2836_arm_irqchip_cpu_notify,
223 .priority = 100,
224};
225
226int __init bcm2836_smp_boot_secondary(unsigned int cpu,
227 struct task_struct *idle)
228{
229 unsigned long secondary_startup_phys =
230 (unsigned long)virt_to_phys((void *)secondary_startup);
231
232 writel(secondary_startup_phys,
233 intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
234
235 return 0;
236}
237
238static const struct smp_operations bcm2836_smp_ops __initconst = {
239 .smp_boot_secondary = bcm2836_smp_boot_secondary,
240};
241
242#endif
243
244static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
245 .xlate = irq_domain_xlate_onecell
246};
247
248static void
249bcm2836_arm_irqchip_smp_init(void)
250{
251#ifdef CONFIG_SMP
252 /* Unmask IPIs to the boot CPU. */
253 bcm2836_arm_irqchip_cpu_notify(&bcm2836_arm_irqchip_cpu_notifier,
254 CPU_STARTING,
255 (void *)smp_processor_id());
256 register_cpu_notifier(&bcm2836_arm_irqchip_cpu_notifier);
257
258 set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
259 smp_set_ops(&bcm2836_smp_ops);
260#endif
261}
262
263/*
264 * The LOCAL_IRQ_CNT* timer firings are based off of the external
265 * oscillator with some scaling. The firmware sets up CNTFRQ to
266 * report 19.2Mhz, but doesn't set up the scaling registers.
267 */
268static void bcm2835_init_local_timer_frequency(void)
269{
270 /*
271 * Set the timer to source from the 19.2Mhz crystal clock (bit
272 * 8 unset), and only increment by 1 instead of 2 (bit 9
273 * unset).
274 */
275 writel(0, intc.base + LOCAL_CONTROL);
276
277 /*
278 * Set the timer prescaler to 1:1 (timer freq = input freq *
279 * 2**31 / prescaler)
280 */
281 writel(0x80000000, intc.base + LOCAL_PRESCALER);
282}
283
284static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
285 struct device_node *parent)
286{
287 intc.base = of_iomap(node, 0);
288 if (!intc.base) {
289 panic("%s: unable to map local interrupt registers\n",
290 node->full_name);
291 }
292
293 bcm2835_init_local_timer_frequency();
294
295 intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
296 &bcm2836_arm_irqchip_intc_ops,
297 NULL);
298 if (!intc.domain)
299 panic("%s: unable to create IRQ domain\n", node->full_name);
300
301 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
302 &bcm2836_arm_irqchip_timer);
303 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ,
304 &bcm2836_arm_irqchip_timer);
305 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ,
306 &bcm2836_arm_irqchip_timer);
307 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ,
308 &bcm2836_arm_irqchip_timer);
309 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST,
310 &bcm2836_arm_irqchip_gpu);
311 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST,
312 &bcm2836_arm_irqchip_pmu);
313
314 bcm2836_arm_irqchip_smp_init();
315
316 set_handle_irq(bcm2836_arm_irqchip_handle_irq);
317 return 0;
318}
319
320IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
321 bcm2836_arm_irqchip_l1_intc_of_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
4 *
5 * Copyright 2015 Broadcom
6 */
7
8#include <linux/cpu.h>
9#include <linux/of_address.h>
10#include <linux/of_irq.h>
11#include <linux/irqchip.h>
12#include <linux/irqdomain.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqchip/irq-bcm2836.h>
15
16#include <asm/exception.h>
17
18struct bcm2836_arm_irqchip_intc {
19 struct irq_domain *domain;
20 void __iomem *base;
21};
22
23static struct bcm2836_arm_irqchip_intc intc __read_mostly;
24
25static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
26 unsigned int bit,
27 int cpu)
28{
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
30
31 writel(readl(reg) & ~BIT(bit), reg);
32}
33
34static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
35 unsigned int bit,
36 int cpu)
37{
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
39
40 writel(readl(reg) | BIT(bit), reg);
41}
42
43static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
44{
45 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
47 smp_processor_id());
48}
49
50static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
51{
52 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
54 smp_processor_id());
55}
56
57static struct irq_chip bcm2836_arm_irqchip_timer = {
58 .name = "bcm2836-timer",
59 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
60 .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
61 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
62};
63
64static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
65{
66 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
67}
68
69static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
70{
71 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
72}
73
74static struct irq_chip bcm2836_arm_irqchip_pmu = {
75 .name = "bcm2836-pmu",
76 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
77 .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
78 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
79};
80
81static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
82{
83}
84
85static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
86{
87}
88
89static struct irq_chip bcm2836_arm_irqchip_gpu = {
90 .name = "bcm2836-gpu",
91 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
92 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
93 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
94};
95
96static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
97{
98}
99
100static struct irq_chip bcm2836_arm_irqchip_dummy = {
101 .name = "bcm2836-dummy",
102 .irq_eoi = bcm2836_arm_irqchip_dummy_op,
103};
104
105static int bcm2836_map(struct irq_domain *d, unsigned int irq,
106 irq_hw_number_t hw)
107{
108 struct irq_chip *chip;
109
110 switch (hw) {
111 case LOCAL_IRQ_MAILBOX0:
112 chip = &bcm2836_arm_irqchip_dummy;
113 break;
114 case LOCAL_IRQ_CNTPSIRQ:
115 case LOCAL_IRQ_CNTPNSIRQ:
116 case LOCAL_IRQ_CNTHPIRQ:
117 case LOCAL_IRQ_CNTVIRQ:
118 chip = &bcm2836_arm_irqchip_timer;
119 break;
120 case LOCAL_IRQ_GPU_FAST:
121 chip = &bcm2836_arm_irqchip_gpu;
122 break;
123 case LOCAL_IRQ_PMU_FAST:
124 chip = &bcm2836_arm_irqchip_pmu;
125 break;
126 default:
127 pr_warn_once("Unexpected hw irq: %lu\n", hw);
128 return -EINVAL;
129 }
130
131 irq_set_percpu_devid(irq);
132 irq_domain_set_info(d, irq, hw, chip, d->host_data,
133 handle_percpu_devid_irq, NULL, NULL);
134 irq_set_status_flags(irq, IRQ_NOAUTOEN);
135
136 return 0;
137}
138
139static void
140__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
141{
142 int cpu = smp_processor_id();
143 u32 stat;
144
145 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
146 if (stat) {
147 u32 hwirq = ffs(stat) - 1;
148
149 generic_handle_domain_irq(intc.domain, hwirq);
150 }
151}
152
153#ifdef CONFIG_SMP
154static struct irq_domain *ipi_domain;
155
156static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
157{
158 struct irq_chip *chip = irq_desc_get_chip(desc);
159 int cpu = smp_processor_id();
160 u32 mbox_val;
161
162 chained_irq_enter(chip, desc);
163
164 mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
165 if (mbox_val) {
166 int hwirq = ffs(mbox_val) - 1;
167 generic_handle_domain_irq(ipi_domain, hwirq);
168 }
169
170 chained_irq_exit(chip, desc);
171}
172
173static void bcm2836_arm_irqchip_ipi_ack(struct irq_data *d)
174{
175 int cpu = smp_processor_id();
176
177 writel_relaxed(BIT(d->hwirq),
178 intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
179}
180
181static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
182 const struct cpumask *mask)
183{
184 int cpu;
185 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
186
187 /*
188 * Ensure that stores to normal memory are visible to the
189 * other CPUs before issuing the IPI.
190 */
191 smp_wmb();
192
193 for_each_cpu(cpu, mask)
194 writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
195}
196
197static struct irq_chip bcm2836_arm_irqchip_ipi = {
198 .name = "IPI",
199 .irq_mask = bcm2836_arm_irqchip_dummy_op,
200 .irq_unmask = bcm2836_arm_irqchip_dummy_op,
201 .irq_ack = bcm2836_arm_irqchip_ipi_ack,
202 .ipi_send_mask = bcm2836_arm_irqchip_ipi_send_mask,
203};
204
205static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
206 unsigned int virq,
207 unsigned int nr_irqs, void *args)
208{
209 int i;
210
211 for (i = 0; i < nr_irqs; i++) {
212 irq_set_percpu_devid(virq + i);
213 irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
214 d->host_data,
215 handle_percpu_devid_irq,
216 NULL, NULL);
217 }
218
219 return 0;
220}
221
222static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
223 unsigned int virq,
224 unsigned int nr_irqs)
225{
226 /* Not freeing IPIs */
227}
228
229static const struct irq_domain_ops ipi_domain_ops = {
230 .alloc = bcm2836_arm_irqchip_ipi_alloc,
231 .free = bcm2836_arm_irqchip_ipi_free,
232};
233
234static int bcm2836_cpu_starting(unsigned int cpu)
235{
236 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
237 cpu);
238 return 0;
239}
240
241static int bcm2836_cpu_dying(unsigned int cpu)
242{
243 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
244 cpu);
245 return 0;
246}
247
248#define BITS_PER_MBOX 32
249
250static void __init bcm2836_arm_irqchip_smp_init(void)
251{
252 struct irq_fwspec ipi_fwspec = {
253 .fwnode = intc.domain->fwnode,
254 .param_count = 1,
255 .param = {
256 [0] = LOCAL_IRQ_MAILBOX0,
257 },
258 };
259 int base_ipi, mux_irq;
260
261 mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
262 if (WARN_ON(mux_irq <= 0))
263 return;
264
265 ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
266 BITS_PER_MBOX, &ipi_domain_ops,
267 NULL);
268 if (WARN_ON(!ipi_domain))
269 return;
270
271 ipi_domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
272 irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
273
274 base_ipi = irq_domain_alloc_irqs(ipi_domain, BITS_PER_MBOX, NUMA_NO_NODE, NULL);
275 if (WARN_ON(!base_ipi))
276 return;
277
278 set_smp_ipi_range(base_ipi, BITS_PER_MBOX);
279
280 irq_set_chained_handler_and_data(mux_irq,
281 bcm2836_arm_irqchip_handle_ipi, NULL);
282
283 /* Unmask IPIs to the boot CPU. */
284 cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
285 "irqchip/bcm2836:starting", bcm2836_cpu_starting,
286 bcm2836_cpu_dying);
287}
288#else
289#define bcm2836_arm_irqchip_smp_init() do { } while(0)
290#endif
291
292static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
293 .xlate = irq_domain_xlate_onetwocell,
294 .map = bcm2836_map,
295};
296
297/*
298 * The LOCAL_IRQ_CNT* timer firings are based off of the external
299 * oscillator with some scaling. The firmware sets up CNTFRQ to
300 * report 19.2Mhz, but doesn't set up the scaling registers.
301 */
302static void bcm2835_init_local_timer_frequency(void)
303{
304 /*
305 * Set the timer to source from the 19.2Mhz crystal clock (bit
306 * 8 unset), and only increment by 1 instead of 2 (bit 9
307 * unset).
308 */
309 writel(0, intc.base + LOCAL_CONTROL);
310
311 /*
312 * Set the timer prescaler to 1:1 (timer freq = input freq *
313 * 2**31 / prescaler)
314 */
315 writel(0x80000000, intc.base + LOCAL_PRESCALER);
316}
317
318static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
319 struct device_node *parent)
320{
321 intc.base = of_iomap(node, 0);
322 if (!intc.base) {
323 panic("%pOF: unable to map local interrupt registers\n", node);
324 }
325
326 bcm2835_init_local_timer_frequency();
327
328 intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
329 &bcm2836_arm_irqchip_intc_ops,
330 NULL);
331 if (!intc.domain)
332 panic("%pOF: unable to create IRQ domain\n", node);
333
334 irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);
335
336 bcm2836_arm_irqchip_smp_init();
337
338 set_handle_irq(bcm2836_arm_irqchip_handle_irq);
339 return 0;
340}
341
342IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
343 bcm2836_arm_irqchip_l1_intc_of_init);