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1/*
2 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
3 *
4 * Copyright 2015 Broadcom
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/cpu.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/irqchip.h>
21#include <linux/irqdomain.h>
22#include <asm/exception.h>
23
24#define LOCAL_CONTROL 0x000
25#define LOCAL_PRESCALER 0x008
26
27/*
28 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
29 * next 2 bits identify the CPU that the GPU FIQ goes to.
30 */
31#define LOCAL_GPU_ROUTING 0x00c
32/* When setting bits 0-3, enables PMU interrupts on that CPU. */
33#define LOCAL_PM_ROUTING_SET 0x010
34/* When setting bits 0-3, disables PMU interrupts on that CPU. */
35#define LOCAL_PM_ROUTING_CLR 0x014
36/*
37 * The low 4 bits of this are the CPU's timer IRQ enables, and the
38 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
39 * bits).
40 */
41#define LOCAL_TIMER_INT_CONTROL0 0x040
42/*
43 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
44 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
45 * override the IRQ bits).
46 */
47#define LOCAL_MAILBOX_INT_CONTROL0 0x050
48/*
49 * The CPU's interrupt status register. Bits are defined by the the
50 * LOCAL_IRQ_* bits below.
51 */
52#define LOCAL_IRQ_PENDING0 0x060
53/* Same status bits as above, but for FIQ. */
54#define LOCAL_FIQ_PENDING0 0x070
55/*
56 * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and
57 * these bits are organized by mailbox number and then CPU number. We
58 * use mailbox 0 for IPIs. The mailbox's interrupt is raised while
59 * any bit is set.
60 */
61#define LOCAL_MAILBOX0_SET0 0x080
62#define LOCAL_MAILBOX3_SET0 0x08c
63/* Mailbox write-to-clear bits. */
64#define LOCAL_MAILBOX0_CLR0 0x0c0
65#define LOCAL_MAILBOX3_CLR0 0x0cc
66
67#define LOCAL_IRQ_CNTPSIRQ 0
68#define LOCAL_IRQ_CNTPNSIRQ 1
69#define LOCAL_IRQ_CNTHPIRQ 2
70#define LOCAL_IRQ_CNTVIRQ 3
71#define LOCAL_IRQ_MAILBOX0 4
72#define LOCAL_IRQ_MAILBOX1 5
73#define LOCAL_IRQ_MAILBOX2 6
74#define LOCAL_IRQ_MAILBOX3 7
75#define LOCAL_IRQ_GPU_FAST 8
76#define LOCAL_IRQ_PMU_FAST 9
77#define LAST_IRQ LOCAL_IRQ_PMU_FAST
78
79struct bcm2836_arm_irqchip_intc {
80 struct irq_domain *domain;
81 void __iomem *base;
82};
83
84static struct bcm2836_arm_irqchip_intc intc __read_mostly;
85
86static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
87 unsigned int bit,
88 int cpu)
89{
90 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
91
92 writel(readl(reg) & ~BIT(bit), reg);
93}
94
95static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
96 unsigned int bit,
97 int cpu)
98{
99 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
100
101 writel(readl(reg) | BIT(bit), reg);
102}
103
104static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
105{
106 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
107 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
108 smp_processor_id());
109}
110
111static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
112{
113 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
114 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
115 smp_processor_id());
116}
117
118static struct irq_chip bcm2836_arm_irqchip_timer = {
119 .name = "bcm2836-timer",
120 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
121 .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
122};
123
124static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
125{
126 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
127}
128
129static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
130{
131 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
132}
133
134static struct irq_chip bcm2836_arm_irqchip_pmu = {
135 .name = "bcm2836-pmu",
136 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
137 .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
138};
139
140static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
141{
142}
143
144static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
145{
146}
147
148static struct irq_chip bcm2836_arm_irqchip_gpu = {
149 .name = "bcm2836-gpu",
150 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
151 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
152};
153
154static void bcm2836_arm_irqchip_register_irq(int hwirq, struct irq_chip *chip)
155{
156 int irq = irq_create_mapping(intc.domain, hwirq);
157
158 irq_set_percpu_devid(irq);
159 irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
160 irq_set_status_flags(irq, IRQ_NOAUTOEN);
161}
162
163static void
164__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
165{
166 int cpu = smp_processor_id();
167 u32 stat;
168
169 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
170 if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
171#ifdef CONFIG_SMP
172 void __iomem *mailbox0 = (intc.base +
173 LOCAL_MAILBOX0_CLR0 + 16 * cpu);
174 u32 mbox_val = readl(mailbox0);
175 u32 ipi = ffs(mbox_val) - 1;
176
177 writel(1 << ipi, mailbox0);
178 handle_IPI(ipi, regs);
179#endif
180 } else if (stat) {
181 u32 hwirq = ffs(stat) - 1;
182
183 handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
184 }
185}
186
187#ifdef CONFIG_SMP
188static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask,
189 unsigned int ipi)
190{
191 int cpu;
192 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
193
194 /*
195 * Ensure that stores to normal memory are visible to the
196 * other CPUs before issuing the IPI.
197 */
198 dsb();
199
200 for_each_cpu(cpu, mask) {
201 writel(1 << ipi, mailbox0_base + 16 * cpu);
202 }
203}
204
205/* Unmasks the IPI on the CPU when it's online. */
206static int bcm2836_arm_irqchip_cpu_notify(struct notifier_block *nfb,
207 unsigned long action, void *hcpu)
208{
209 unsigned int cpu = (unsigned long)hcpu;
210 unsigned int int_reg = LOCAL_MAILBOX_INT_CONTROL0;
211 unsigned int mailbox = 0;
212
213 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
214 bcm2836_arm_irqchip_unmask_per_cpu_irq(int_reg, mailbox, cpu);
215 else if (action == CPU_DYING)
216 bcm2836_arm_irqchip_mask_per_cpu_irq(int_reg, mailbox, cpu);
217
218 return NOTIFY_OK;
219}
220
221static struct notifier_block bcm2836_arm_irqchip_cpu_notifier = {
222 .notifier_call = bcm2836_arm_irqchip_cpu_notify,
223 .priority = 100,
224};
225
226int __init bcm2836_smp_boot_secondary(unsigned int cpu,
227 struct task_struct *idle)
228{
229 unsigned long secondary_startup_phys =
230 (unsigned long)virt_to_phys((void *)secondary_startup);
231
232 writel(secondary_startup_phys,
233 intc.base + LOCAL_MAILBOX3_SET0 + 16 * cpu);
234
235 return 0;
236}
237
238static const struct smp_operations bcm2836_smp_ops __initconst = {
239 .smp_boot_secondary = bcm2836_smp_boot_secondary,
240};
241
242#endif
243
244static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
245 .xlate = irq_domain_xlate_onecell
246};
247
248static void
249bcm2836_arm_irqchip_smp_init(void)
250{
251#ifdef CONFIG_SMP
252 /* Unmask IPIs to the boot CPU. */
253 bcm2836_arm_irqchip_cpu_notify(&bcm2836_arm_irqchip_cpu_notifier,
254 CPU_STARTING,
255 (void *)smp_processor_id());
256 register_cpu_notifier(&bcm2836_arm_irqchip_cpu_notifier);
257
258 set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
259 smp_set_ops(&bcm2836_smp_ops);
260#endif
261}
262
263/*
264 * The LOCAL_IRQ_CNT* timer firings are based off of the external
265 * oscillator with some scaling. The firmware sets up CNTFRQ to
266 * report 19.2Mhz, but doesn't set up the scaling registers.
267 */
268static void bcm2835_init_local_timer_frequency(void)
269{
270 /*
271 * Set the timer to source from the 19.2Mhz crystal clock (bit
272 * 8 unset), and only increment by 1 instead of 2 (bit 9
273 * unset).
274 */
275 writel(0, intc.base + LOCAL_CONTROL);
276
277 /*
278 * Set the timer prescaler to 1:1 (timer freq = input freq *
279 * 2**31 / prescaler)
280 */
281 writel(0x80000000, intc.base + LOCAL_PRESCALER);
282}
283
284static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
285 struct device_node *parent)
286{
287 intc.base = of_iomap(node, 0);
288 if (!intc.base) {
289 panic("%s: unable to map local interrupt registers\n",
290 node->full_name);
291 }
292
293 bcm2835_init_local_timer_frequency();
294
295 intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
296 &bcm2836_arm_irqchip_intc_ops,
297 NULL);
298 if (!intc.domain)
299 panic("%s: unable to create IRQ domain\n", node->full_name);
300
301 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
302 &bcm2836_arm_irqchip_timer);
303 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ,
304 &bcm2836_arm_irqchip_timer);
305 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ,
306 &bcm2836_arm_irqchip_timer);
307 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ,
308 &bcm2836_arm_irqchip_timer);
309 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST,
310 &bcm2836_arm_irqchip_gpu);
311 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST,
312 &bcm2836_arm_irqchip_pmu);
313
314 bcm2836_arm_irqchip_smp_init();
315
316 set_handle_irq(bcm2836_arm_irqchip_handle_irq);
317 return 0;
318}
319
320IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
321 bcm2836_arm_irqchip_l1_intc_of_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
4 *
5 * Copyright 2015 Broadcom
6 */
7
8#include <linux/cpu.h>
9#include <linux/of_address.h>
10#include <linux/of_irq.h>
11#include <linux/irqchip.h>
12#include <linux/irqdomain.h>
13#include <linux/irqchip/irq-bcm2836.h>
14
15#include <asm/exception.h>
16
17struct bcm2836_arm_irqchip_intc {
18 struct irq_domain *domain;
19 void __iomem *base;
20};
21
22static struct bcm2836_arm_irqchip_intc intc __read_mostly;
23
24static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
25 unsigned int bit,
26 int cpu)
27{
28 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
29
30 writel(readl(reg) & ~BIT(bit), reg);
31}
32
33static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
34 unsigned int bit,
35 int cpu)
36{
37 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
38
39 writel(readl(reg) | BIT(bit), reg);
40}
41
42static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
43{
44 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
45 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
46 smp_processor_id());
47}
48
49static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
50{
51 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
52 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
53 smp_processor_id());
54}
55
56static struct irq_chip bcm2836_arm_irqchip_timer = {
57 .name = "bcm2836-timer",
58 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
59 .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
60};
61
62static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
63{
64 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
65}
66
67static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
68{
69 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
70}
71
72static struct irq_chip bcm2836_arm_irqchip_pmu = {
73 .name = "bcm2836-pmu",
74 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
75 .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
76};
77
78static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
79{
80}
81
82static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
83{
84}
85
86static struct irq_chip bcm2836_arm_irqchip_gpu = {
87 .name = "bcm2836-gpu",
88 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
89 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
90};
91
92static int bcm2836_map(struct irq_domain *d, unsigned int irq,
93 irq_hw_number_t hw)
94{
95 struct irq_chip *chip;
96
97 switch (hw) {
98 case LOCAL_IRQ_CNTPSIRQ:
99 case LOCAL_IRQ_CNTPNSIRQ:
100 case LOCAL_IRQ_CNTHPIRQ:
101 case LOCAL_IRQ_CNTVIRQ:
102 chip = &bcm2836_arm_irqchip_timer;
103 break;
104 case LOCAL_IRQ_GPU_FAST:
105 chip = &bcm2836_arm_irqchip_gpu;
106 break;
107 case LOCAL_IRQ_PMU_FAST:
108 chip = &bcm2836_arm_irqchip_pmu;
109 break;
110 default:
111 pr_warn_once("Unexpected hw irq: %lu\n", hw);
112 return -EINVAL;
113 }
114
115 irq_set_percpu_devid(irq);
116 irq_domain_set_info(d, irq, hw, chip, d->host_data,
117 handle_percpu_devid_irq, NULL, NULL);
118 irq_set_status_flags(irq, IRQ_NOAUTOEN);
119
120 return 0;
121}
122
123static void
124__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
125{
126 int cpu = smp_processor_id();
127 u32 stat;
128
129 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
130 if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
131#ifdef CONFIG_SMP
132 void __iomem *mailbox0 = (intc.base +
133 LOCAL_MAILBOX0_CLR0 + 16 * cpu);
134 u32 mbox_val = readl(mailbox0);
135 u32 ipi = ffs(mbox_val) - 1;
136
137 writel(1 << ipi, mailbox0);
138 handle_IPI(ipi, regs);
139#endif
140 } else if (stat) {
141 u32 hwirq = ffs(stat) - 1;
142
143 handle_domain_irq(intc.domain, hwirq, regs);
144 }
145}
146
147#ifdef CONFIG_SMP
148static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask,
149 unsigned int ipi)
150{
151 int cpu;
152 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
153
154 /*
155 * Ensure that stores to normal memory are visible to the
156 * other CPUs before issuing the IPI.
157 */
158 smp_wmb();
159
160 for_each_cpu(cpu, mask) {
161 writel(1 << ipi, mailbox0_base + 16 * cpu);
162 }
163}
164
165static int bcm2836_cpu_starting(unsigned int cpu)
166{
167 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
168 cpu);
169 return 0;
170}
171
172static int bcm2836_cpu_dying(unsigned int cpu)
173{
174 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
175 cpu);
176 return 0;
177}
178#endif
179
180static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
181 .xlate = irq_domain_xlate_onetwocell,
182 .map = bcm2836_map,
183};
184
185static void
186bcm2836_arm_irqchip_smp_init(void)
187{
188#ifdef CONFIG_SMP
189 /* Unmask IPIs to the boot CPU. */
190 cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
191 "irqchip/bcm2836:starting", bcm2836_cpu_starting,
192 bcm2836_cpu_dying);
193
194 set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
195#endif
196}
197
198/*
199 * The LOCAL_IRQ_CNT* timer firings are based off of the external
200 * oscillator with some scaling. The firmware sets up CNTFRQ to
201 * report 19.2Mhz, but doesn't set up the scaling registers.
202 */
203static void bcm2835_init_local_timer_frequency(void)
204{
205 /*
206 * Set the timer to source from the 19.2Mhz crystal clock (bit
207 * 8 unset), and only increment by 1 instead of 2 (bit 9
208 * unset).
209 */
210 writel(0, intc.base + LOCAL_CONTROL);
211
212 /*
213 * Set the timer prescaler to 1:1 (timer freq = input freq *
214 * 2**31 / prescaler)
215 */
216 writel(0x80000000, intc.base + LOCAL_PRESCALER);
217}
218
219static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
220 struct device_node *parent)
221{
222 intc.base = of_iomap(node, 0);
223 if (!intc.base) {
224 panic("%pOF: unable to map local interrupt registers\n", node);
225 }
226
227 bcm2835_init_local_timer_frequency();
228
229 intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
230 &bcm2836_arm_irqchip_intc_ops,
231 NULL);
232 if (!intc.domain)
233 panic("%pOF: unable to create IRQ domain\n", node);
234
235 bcm2836_arm_irqchip_smp_init();
236
237 set_handle_irq(bcm2836_arm_irqchip_handle_irq);
238 return 0;
239}
240
241IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
242 bcm2836_arm_irqchip_l1_intc_of_init);