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1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2000, 2001 Kanoj Sarcar
17 * Copyright (C) 2000, 2001 Ralf Baechle
18 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
19 * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
20 */
21#include <linux/cache.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/smp.h>
26#include <linux/spinlock.h>
27#include <linux/threads.h>
28#include <linux/module.h>
29#include <linux/time.h>
30#include <linux/timex.h>
31#include <linux/sched.h>
32#include <linux/cpumask.h>
33#include <linux/cpu.h>
34#include <linux/err.h>
35#include <linux/ftrace.h>
36#include <linux/irqdomain.h>
37#include <linux/of.h>
38#include <linux/of_irq.h>
39
40#include <linux/atomic.h>
41#include <asm/cpu.h>
42#include <asm/processor.h>
43#include <asm/idle.h>
44#include <asm/r4k-timer.h>
45#include <asm/mips-cpc.h>
46#include <asm/mmu_context.h>
47#include <asm/time.h>
48#include <asm/setup.h>
49#include <asm/maar.h>
50
51cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
52
53int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
54EXPORT_SYMBOL(__cpu_number_map);
55
56int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
57EXPORT_SYMBOL(__cpu_logical_map);
58
59/* Number of TCs (or siblings in Intel speak) per CPU core */
60int smp_num_siblings = 1;
61EXPORT_SYMBOL(smp_num_siblings);
62
63/* representing the TCs (or siblings in Intel speak) of each logical CPU */
64cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
65EXPORT_SYMBOL(cpu_sibling_map);
66
67/* representing the core map of multi-core chips of each logical CPU */
68cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
69EXPORT_SYMBOL(cpu_core_map);
70
71/*
72 * A logcal cpu mask containing only one VPE per core to
73 * reduce the number of IPIs on large MT systems.
74 */
75cpumask_t cpu_foreign_map __read_mostly;
76EXPORT_SYMBOL(cpu_foreign_map);
77
78/* representing cpus for which sibling maps can be computed */
79static cpumask_t cpu_sibling_setup_map;
80
81/* representing cpus for which core maps can be computed */
82static cpumask_t cpu_core_setup_map;
83
84cpumask_t cpu_coherent_mask;
85
86#ifdef CONFIG_GENERIC_IRQ_IPI
87static struct irq_desc *call_desc;
88static struct irq_desc *sched_desc;
89#endif
90
91static inline void set_cpu_sibling_map(int cpu)
92{
93 int i;
94
95 cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
96
97 if (smp_num_siblings > 1) {
98 for_each_cpu(i, &cpu_sibling_setup_map) {
99 if (cpu_data[cpu].package == cpu_data[i].package &&
100 cpu_data[cpu].core == cpu_data[i].core) {
101 cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
102 cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
103 }
104 }
105 } else
106 cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
107}
108
109static inline void set_cpu_core_map(int cpu)
110{
111 int i;
112
113 cpumask_set_cpu(cpu, &cpu_core_setup_map);
114
115 for_each_cpu(i, &cpu_core_setup_map) {
116 if (cpu_data[cpu].package == cpu_data[i].package) {
117 cpumask_set_cpu(i, &cpu_core_map[cpu]);
118 cpumask_set_cpu(cpu, &cpu_core_map[i]);
119 }
120 }
121}
122
123/*
124 * Calculate a new cpu_foreign_map mask whenever a
125 * new cpu appears or disappears.
126 */
127static inline void calculate_cpu_foreign_map(void)
128{
129 int i, k, core_present;
130 cpumask_t temp_foreign_map;
131
132 /* Re-calculate the mask */
133 cpumask_clear(&temp_foreign_map);
134 for_each_online_cpu(i) {
135 core_present = 0;
136 for_each_cpu(k, &temp_foreign_map)
137 if (cpu_data[i].package == cpu_data[k].package &&
138 cpu_data[i].core == cpu_data[k].core)
139 core_present = 1;
140 if (!core_present)
141 cpumask_set_cpu(i, &temp_foreign_map);
142 }
143
144 cpumask_copy(&cpu_foreign_map, &temp_foreign_map);
145}
146
147struct plat_smp_ops *mp_ops;
148EXPORT_SYMBOL(mp_ops);
149
150void register_smp_ops(struct plat_smp_ops *ops)
151{
152 if (mp_ops)
153 printk(KERN_WARNING "Overriding previously set SMP ops\n");
154
155 mp_ops = ops;
156}
157
158#ifdef CONFIG_GENERIC_IRQ_IPI
159void mips_smp_send_ipi_single(int cpu, unsigned int action)
160{
161 mips_smp_send_ipi_mask(cpumask_of(cpu), action);
162}
163
164void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
165{
166 unsigned long flags;
167 unsigned int core;
168 int cpu;
169
170 local_irq_save(flags);
171
172 switch (action) {
173 case SMP_CALL_FUNCTION:
174 __ipi_send_mask(call_desc, mask);
175 break;
176
177 case SMP_RESCHEDULE_YOURSELF:
178 __ipi_send_mask(sched_desc, mask);
179 break;
180
181 default:
182 BUG();
183 }
184
185 if (mips_cpc_present()) {
186 for_each_cpu(cpu, mask) {
187 core = cpu_data[cpu].core;
188
189 if (core == current_cpu_data.core)
190 continue;
191
192 while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
193 mips_cpc_lock_other(core);
194 write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
195 mips_cpc_unlock_other();
196 }
197 }
198 }
199
200 local_irq_restore(flags);
201}
202
203
204static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
205{
206 scheduler_ipi();
207
208 return IRQ_HANDLED;
209}
210
211static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
212{
213 generic_smp_call_function_interrupt();
214
215 return IRQ_HANDLED;
216}
217
218static struct irqaction irq_resched = {
219 .handler = ipi_resched_interrupt,
220 .flags = IRQF_PERCPU,
221 .name = "IPI resched"
222};
223
224static struct irqaction irq_call = {
225 .handler = ipi_call_interrupt,
226 .flags = IRQF_PERCPU,
227 .name = "IPI call"
228};
229
230static __init void smp_ipi_init_one(unsigned int virq,
231 struct irqaction *action)
232{
233 int ret;
234
235 irq_set_handler(virq, handle_percpu_irq);
236 ret = setup_irq(virq, action);
237 BUG_ON(ret);
238}
239
240static int __init mips_smp_ipi_init(void)
241{
242 unsigned int call_virq, sched_virq;
243 struct irq_domain *ipidomain;
244 struct device_node *node;
245
246 /*
247 * In some cases like qemu-malta, it is desired to try SMP with
248 * a single core. Qemu-malta has no GIC, so an attempt to set any IPIs
249 * would cause a BUG_ON() to be triggered since there's no ipidomain.
250 *
251 * Since for a single core system IPIs aren't required really, skip the
252 * initialisation which should generally keep any such configurations
253 * happy and only fail hard when trying to truely run SMP.
254 */
255 if (cpumask_weight(cpu_possible_mask) == 1)
256 return 0;
257
258 node = of_irq_find_parent(of_root);
259 ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
260
261 /*
262 * Some platforms have half DT setup. So if we found irq node but
263 * didn't find an ipidomain, try to search for one that is not in the
264 * DT.
265 */
266 if (node && !ipidomain)
267 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
268
269 BUG_ON(!ipidomain);
270
271 call_virq = irq_reserve_ipi(ipidomain, cpu_possible_mask);
272 BUG_ON(!call_virq);
273
274 sched_virq = irq_reserve_ipi(ipidomain, cpu_possible_mask);
275 BUG_ON(!sched_virq);
276
277 if (irq_domain_is_ipi_per_cpu(ipidomain)) {
278 int cpu;
279
280 for_each_cpu(cpu, cpu_possible_mask) {
281 smp_ipi_init_one(call_virq + cpu, &irq_call);
282 smp_ipi_init_one(sched_virq + cpu, &irq_resched);
283 }
284 } else {
285 smp_ipi_init_one(call_virq, &irq_call);
286 smp_ipi_init_one(sched_virq, &irq_resched);
287 }
288
289 call_desc = irq_to_desc(call_virq);
290 sched_desc = irq_to_desc(sched_virq);
291
292 return 0;
293}
294early_initcall(mips_smp_ipi_init);
295#endif
296
297/*
298 * First C code run on the secondary CPUs after being started up by
299 * the master.
300 */
301asmlinkage void start_secondary(void)
302{
303 unsigned int cpu;
304
305 cpu_probe();
306 per_cpu_trap_init(false);
307 mips_clockevent_init();
308 mp_ops->init_secondary();
309 cpu_report();
310 maar_init();
311
312 /*
313 * XXX parity protection should be folded in here when it's converted
314 * to an option instead of something based on .cputype
315 */
316
317 calibrate_delay();
318 preempt_disable();
319 cpu = smp_processor_id();
320 cpu_data[cpu].udelay_val = loops_per_jiffy;
321
322 cpumask_set_cpu(cpu, &cpu_coherent_mask);
323 notify_cpu_starting(cpu);
324
325 set_cpu_online(cpu, true);
326
327 set_cpu_sibling_map(cpu);
328 set_cpu_core_map(cpu);
329
330 calculate_cpu_foreign_map();
331
332 cpumask_set_cpu(cpu, &cpu_callin_map);
333
334 synchronise_count_slave(cpu);
335
336 /*
337 * irq will be enabled in ->smp_finish(), enabling it too early
338 * is dangerous.
339 */
340 WARN_ON_ONCE(!irqs_disabled());
341 mp_ops->smp_finish();
342
343 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
344}
345
346static void stop_this_cpu(void *dummy)
347{
348 /*
349 * Remove this CPU. Be a bit slow here and
350 * set the bits for every online CPU so we don't miss
351 * any IPI whilst taking this VPE down.
352 */
353
354 cpumask_copy(&cpu_foreign_map, cpu_online_mask);
355
356 /* Make it visible to every other CPU */
357 smp_mb();
358
359 set_cpu_online(smp_processor_id(), false);
360 calculate_cpu_foreign_map();
361 local_irq_disable();
362 while (1);
363}
364
365void smp_send_stop(void)
366{
367 smp_call_function(stop_this_cpu, NULL, 0);
368}
369
370void __init smp_cpus_done(unsigned int max_cpus)
371{
372}
373
374/* called from main before smp_init() */
375void __init smp_prepare_cpus(unsigned int max_cpus)
376{
377 init_new_context(current, &init_mm);
378 current_thread_info()->cpu = 0;
379 mp_ops->prepare_cpus(max_cpus);
380 set_cpu_sibling_map(0);
381 set_cpu_core_map(0);
382 calculate_cpu_foreign_map();
383#ifndef CONFIG_HOTPLUG_CPU
384 init_cpu_present(cpu_possible_mask);
385#endif
386 cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
387}
388
389/* preload SMP state for boot cpu */
390void smp_prepare_boot_cpu(void)
391{
392 set_cpu_possible(0, true);
393 set_cpu_online(0, true);
394 cpumask_set_cpu(0, &cpu_callin_map);
395}
396
397int __cpu_up(unsigned int cpu, struct task_struct *tidle)
398{
399 mp_ops->boot_secondary(cpu, tidle);
400
401 /*
402 * Trust is futile. We should really have timeouts ...
403 */
404 while (!cpumask_test_cpu(cpu, &cpu_callin_map)) {
405 udelay(100);
406 schedule();
407 }
408
409 synchronise_count_master(cpu);
410 return 0;
411}
412
413/* Not really SMP stuff ... */
414int setup_profiling_timer(unsigned int multiplier)
415{
416 return 0;
417}
418
419static void flush_tlb_all_ipi(void *info)
420{
421 local_flush_tlb_all();
422}
423
424void flush_tlb_all(void)
425{
426 on_each_cpu(flush_tlb_all_ipi, NULL, 1);
427}
428
429static void flush_tlb_mm_ipi(void *mm)
430{
431 local_flush_tlb_mm((struct mm_struct *)mm);
432}
433
434/*
435 * Special Variant of smp_call_function for use by TLB functions:
436 *
437 * o No return value
438 * o collapses to normal function call on UP kernels
439 * o collapses to normal function call on systems with a single shared
440 * primary cache.
441 */
442static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
443{
444 smp_call_function(func, info, 1);
445}
446
447static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
448{
449 preempt_disable();
450
451 smp_on_other_tlbs(func, info);
452 func(info);
453
454 preempt_enable();
455}
456
457/*
458 * The following tlb flush calls are invoked when old translations are
459 * being torn down, or pte attributes are changing. For single threaded
460 * address spaces, a new context is obtained on the current cpu, and tlb
461 * context on other cpus are invalidated to force a new context allocation
462 * at switch_mm time, should the mm ever be used on other cpus. For
463 * multithreaded address spaces, intercpu interrupts have to be sent.
464 * Another case where intercpu interrupts are required is when the target
465 * mm might be active on another cpu (eg debuggers doing the flushes on
466 * behalf of debugees, kswapd stealing pages from another process etc).
467 * Kanoj 07/00.
468 */
469
470void flush_tlb_mm(struct mm_struct *mm)
471{
472 preempt_disable();
473
474 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
475 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
476 } else {
477 unsigned int cpu;
478
479 for_each_online_cpu(cpu) {
480 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
481 cpu_context(cpu, mm) = 0;
482 }
483 }
484 local_flush_tlb_mm(mm);
485
486 preempt_enable();
487}
488
489struct flush_tlb_data {
490 struct vm_area_struct *vma;
491 unsigned long addr1;
492 unsigned long addr2;
493};
494
495static void flush_tlb_range_ipi(void *info)
496{
497 struct flush_tlb_data *fd = info;
498
499 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
500}
501
502void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
503{
504 struct mm_struct *mm = vma->vm_mm;
505
506 preempt_disable();
507 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
508 struct flush_tlb_data fd = {
509 .vma = vma,
510 .addr1 = start,
511 .addr2 = end,
512 };
513
514 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
515 } else {
516 unsigned int cpu;
517
518 for_each_online_cpu(cpu) {
519 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
520 cpu_context(cpu, mm) = 0;
521 }
522 }
523 local_flush_tlb_range(vma, start, end);
524 preempt_enable();
525}
526
527static void flush_tlb_kernel_range_ipi(void *info)
528{
529 struct flush_tlb_data *fd = info;
530
531 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
532}
533
534void flush_tlb_kernel_range(unsigned long start, unsigned long end)
535{
536 struct flush_tlb_data fd = {
537 .addr1 = start,
538 .addr2 = end,
539 };
540
541 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
542}
543
544static void flush_tlb_page_ipi(void *info)
545{
546 struct flush_tlb_data *fd = info;
547
548 local_flush_tlb_page(fd->vma, fd->addr1);
549}
550
551void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
552{
553 preempt_disable();
554 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
555 struct flush_tlb_data fd = {
556 .vma = vma,
557 .addr1 = page,
558 };
559
560 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
561 } else {
562 unsigned int cpu;
563
564 for_each_online_cpu(cpu) {
565 if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
566 cpu_context(cpu, vma->vm_mm) = 0;
567 }
568 }
569 local_flush_tlb_page(vma, page);
570 preempt_enable();
571}
572
573static void flush_tlb_one_ipi(void *info)
574{
575 unsigned long vaddr = (unsigned long) info;
576
577 local_flush_tlb_one(vaddr);
578}
579
580void flush_tlb_one(unsigned long vaddr)
581{
582 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
583}
584
585EXPORT_SYMBOL(flush_tlb_page);
586EXPORT_SYMBOL(flush_tlb_one);
587
588#if defined(CONFIG_KEXEC)
589void (*dump_ipi_function_ptr)(void *) = NULL;
590void dump_send_ipi(void (*dump_ipi_callback)(void *))
591{
592 int i;
593 int cpu = smp_processor_id();
594
595 dump_ipi_function_ptr = dump_ipi_callback;
596 smp_mb();
597 for_each_online_cpu(i)
598 if (i != cpu)
599 mp_ops->send_ipi_single(i, SMP_DUMP);
600
601}
602EXPORT_SYMBOL(dump_send_ipi);
603#endif
604
605#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
606
607static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);
608static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd);
609
610void tick_broadcast(const struct cpumask *mask)
611{
612 atomic_t *count;
613 struct call_single_data *csd;
614 int cpu;
615
616 for_each_cpu(cpu, mask) {
617 count = &per_cpu(tick_broadcast_count, cpu);
618 csd = &per_cpu(tick_broadcast_csd, cpu);
619
620 if (atomic_inc_return(count) == 1)
621 smp_call_function_single_async(cpu, csd);
622 }
623}
624
625static void tick_broadcast_callee(void *info)
626{
627 int cpu = smp_processor_id();
628 tick_receive_broadcast();
629 atomic_set(&per_cpu(tick_broadcast_count, cpu), 0);
630}
631
632static int __init tick_broadcast_init(void)
633{
634 struct call_single_data *csd;
635 int cpu;
636
637 for (cpu = 0; cpu < NR_CPUS; cpu++) {
638 csd = &per_cpu(tick_broadcast_csd, cpu);
639 csd->func = tick_broadcast_callee;
640 }
641
642 return 0;
643}
644early_initcall(tick_broadcast_init);
645
646#endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Copyright (C) 2000, 2001 Kanoj Sarcar
5 * Copyright (C) 2000, 2001 Ralf Baechle
6 * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
7 * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
8 */
9#include <linux/cache.h>
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/profile.h>
14#include <linux/smp.h>
15#include <linux/spinlock.h>
16#include <linux/threads.h>
17#include <linux/export.h>
18#include <linux/time.h>
19#include <linux/timex.h>
20#include <linux/sched/mm.h>
21#include <linux/cpumask.h>
22#include <linux/cpu.h>
23#include <linux/err.h>
24#include <linux/ftrace.h>
25#include <linux/irqdomain.h>
26#include <linux/of.h>
27#include <linux/of_irq.h>
28
29#include <linux/atomic.h>
30#include <asm/cpu.h>
31#include <asm/ginvt.h>
32#include <asm/processor.h>
33#include <asm/idle.h>
34#include <asm/r4k-timer.h>
35#include <asm/mips-cps.h>
36#include <asm/mmu_context.h>
37#include <asm/time.h>
38#include <asm/setup.h>
39#include <asm/maar.h>
40
41int __cpu_number_map[CONFIG_MIPS_NR_CPU_NR_MAP]; /* Map physical to logical */
42EXPORT_SYMBOL(__cpu_number_map);
43
44int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
45EXPORT_SYMBOL(__cpu_logical_map);
46
47/* Number of TCs (or siblings in Intel speak) per CPU core */
48int smp_num_siblings = 1;
49EXPORT_SYMBOL(smp_num_siblings);
50
51/* representing the TCs (or siblings in Intel speak) of each logical CPU */
52cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
53EXPORT_SYMBOL(cpu_sibling_map);
54
55/* representing the core map of multi-core chips of each logical CPU */
56cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
57EXPORT_SYMBOL(cpu_core_map);
58
59static DECLARE_COMPLETION(cpu_starting);
60static DECLARE_COMPLETION(cpu_running);
61
62/*
63 * A logical cpu mask containing only one VPE per core to
64 * reduce the number of IPIs on large MT systems.
65 */
66cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
67EXPORT_SYMBOL(cpu_foreign_map);
68
69/* representing cpus for which sibling maps can be computed */
70static cpumask_t cpu_sibling_setup_map;
71
72/* representing cpus for which core maps can be computed */
73static cpumask_t cpu_core_setup_map;
74
75cpumask_t cpu_coherent_mask;
76
77unsigned int smp_max_threads __initdata = UINT_MAX;
78
79static int __init early_nosmt(char *s)
80{
81 smp_max_threads = 1;
82 return 0;
83}
84early_param("nosmt", early_nosmt);
85
86static int __init early_smt(char *s)
87{
88 get_option(&s, &smp_max_threads);
89 /* Ensure at least one thread is available */
90 smp_max_threads = clamp_val(smp_max_threads, 1U, UINT_MAX);
91 return 0;
92}
93early_param("smt", early_smt);
94
95#ifdef CONFIG_GENERIC_IRQ_IPI
96static struct irq_desc *call_desc;
97static struct irq_desc *sched_desc;
98#endif
99
100static inline void set_cpu_sibling_map(int cpu)
101{
102 int i;
103
104 cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
105
106 if (smp_num_siblings > 1) {
107 for_each_cpu(i, &cpu_sibling_setup_map) {
108 if (cpus_are_siblings(cpu, i)) {
109 cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
110 cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
111 }
112 }
113 } else
114 cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
115}
116
117static inline void set_cpu_core_map(int cpu)
118{
119 int i;
120
121 cpumask_set_cpu(cpu, &cpu_core_setup_map);
122
123 for_each_cpu(i, &cpu_core_setup_map) {
124 if (cpu_data[cpu].package == cpu_data[i].package) {
125 cpumask_set_cpu(i, &cpu_core_map[cpu]);
126 cpumask_set_cpu(cpu, &cpu_core_map[i]);
127 }
128 }
129}
130
131/*
132 * Calculate a new cpu_foreign_map mask whenever a
133 * new cpu appears or disappears.
134 */
135void calculate_cpu_foreign_map(void)
136{
137 int i, k, core_present;
138 cpumask_t temp_foreign_map;
139
140 /* Re-calculate the mask */
141 cpumask_clear(&temp_foreign_map);
142 for_each_online_cpu(i) {
143 core_present = 0;
144 for_each_cpu(k, &temp_foreign_map)
145 if (cpus_are_siblings(i, k))
146 core_present = 1;
147 if (!core_present)
148 cpumask_set_cpu(i, &temp_foreign_map);
149 }
150
151 for_each_online_cpu(i)
152 cpumask_andnot(&cpu_foreign_map[i],
153 &temp_foreign_map, &cpu_sibling_map[i]);
154}
155
156const struct plat_smp_ops *mp_ops;
157EXPORT_SYMBOL(mp_ops);
158
159void register_smp_ops(const struct plat_smp_ops *ops)
160{
161 if (mp_ops)
162 printk(KERN_WARNING "Overriding previously set SMP ops\n");
163
164 mp_ops = ops;
165}
166
167#ifdef CONFIG_GENERIC_IRQ_IPI
168void mips_smp_send_ipi_single(int cpu, unsigned int action)
169{
170 mips_smp_send_ipi_mask(cpumask_of(cpu), action);
171}
172
173void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
174{
175 unsigned long flags;
176 unsigned int core;
177 int cpu;
178
179 local_irq_save(flags);
180
181 switch (action) {
182 case SMP_CALL_FUNCTION:
183 __ipi_send_mask(call_desc, mask);
184 break;
185
186 case SMP_RESCHEDULE_YOURSELF:
187 __ipi_send_mask(sched_desc, mask);
188 break;
189
190 default:
191 BUG();
192 }
193
194 if (mips_cpc_present()) {
195 for_each_cpu(cpu, mask) {
196 if (cpus_are_siblings(cpu, smp_processor_id()))
197 continue;
198
199 core = cpu_core(&cpu_data[cpu]);
200
201 while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
202 mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
203 mips_cpc_lock_other(core);
204 write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
205 mips_cpc_unlock_other();
206 mips_cm_unlock_other();
207 }
208 }
209 }
210
211 local_irq_restore(flags);
212}
213
214
215static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
216{
217 scheduler_ipi();
218
219 return IRQ_HANDLED;
220}
221
222static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
223{
224 generic_smp_call_function_interrupt();
225
226 return IRQ_HANDLED;
227}
228
229static void smp_ipi_init_one(unsigned int virq, const char *name,
230 irq_handler_t handler)
231{
232 int ret;
233
234 irq_set_handler(virq, handle_percpu_irq);
235 ret = request_irq(virq, handler, IRQF_PERCPU, name, NULL);
236 BUG_ON(ret);
237}
238
239static unsigned int call_virq, sched_virq;
240
241int mips_smp_ipi_allocate(const struct cpumask *mask)
242{
243 int virq;
244 struct irq_domain *ipidomain;
245 struct device_node *node;
246
247 node = of_irq_find_parent(of_root);
248 ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
249
250 /*
251 * Some platforms have half DT setup. So if we found irq node but
252 * didn't find an ipidomain, try to search for one that is not in the
253 * DT.
254 */
255 if (node && !ipidomain)
256 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
257
258 /*
259 * There are systems which use IPI IRQ domains, but only have one
260 * registered when some runtime condition is met. For example a Malta
261 * kernel may include support for GIC & CPU interrupt controller IPI
262 * IRQ domains, but if run on a system with no GIC & no MT ASE then
263 * neither will be supported or registered.
264 *
265 * We only have a problem if we're actually using multiple CPUs so fail
266 * loudly if that is the case. Otherwise simply return, skipping IPI
267 * setup, if we're running with only a single CPU.
268 */
269 if (!ipidomain) {
270 BUG_ON(num_present_cpus() > 1);
271 return 0;
272 }
273
274 virq = irq_reserve_ipi(ipidomain, mask);
275 BUG_ON(!virq);
276 if (!call_virq)
277 call_virq = virq;
278
279 virq = irq_reserve_ipi(ipidomain, mask);
280 BUG_ON(!virq);
281 if (!sched_virq)
282 sched_virq = virq;
283
284 if (irq_domain_is_ipi_per_cpu(ipidomain)) {
285 int cpu;
286
287 for_each_cpu(cpu, mask) {
288 smp_ipi_init_one(call_virq + cpu, "IPI call",
289 ipi_call_interrupt);
290 smp_ipi_init_one(sched_virq + cpu, "IPI resched",
291 ipi_resched_interrupt);
292 }
293 } else {
294 smp_ipi_init_one(call_virq, "IPI call", ipi_call_interrupt);
295 smp_ipi_init_one(sched_virq, "IPI resched",
296 ipi_resched_interrupt);
297 }
298
299 return 0;
300}
301
302int mips_smp_ipi_free(const struct cpumask *mask)
303{
304 struct irq_domain *ipidomain;
305 struct device_node *node;
306
307 node = of_irq_find_parent(of_root);
308 ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
309
310 /*
311 * Some platforms have half DT setup. So if we found irq node but
312 * didn't find an ipidomain, try to search for one that is not in the
313 * DT.
314 */
315 if (node && !ipidomain)
316 ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
317
318 BUG_ON(!ipidomain);
319
320 if (irq_domain_is_ipi_per_cpu(ipidomain)) {
321 int cpu;
322
323 for_each_cpu(cpu, mask) {
324 free_irq(call_virq + cpu, NULL);
325 free_irq(sched_virq + cpu, NULL);
326 }
327 }
328 irq_destroy_ipi(call_virq, mask);
329 irq_destroy_ipi(sched_virq, mask);
330 return 0;
331}
332
333
334static int __init mips_smp_ipi_init(void)
335{
336 if (num_possible_cpus() == 1)
337 return 0;
338
339 mips_smp_ipi_allocate(cpu_possible_mask);
340
341 call_desc = irq_to_desc(call_virq);
342 sched_desc = irq_to_desc(sched_virq);
343
344 return 0;
345}
346early_initcall(mips_smp_ipi_init);
347#endif
348
349/*
350 * First C code run on the secondary CPUs after being started up by
351 * the master.
352 */
353asmlinkage void start_secondary(void)
354{
355 unsigned int cpu = raw_smp_processor_id();
356
357 cpu_probe();
358 per_cpu_trap_init(false);
359 rcutree_report_cpu_starting(cpu);
360 mips_clockevent_init();
361 mp_ops->init_secondary();
362 cpu_report();
363 maar_init();
364
365 /*
366 * XXX parity protection should be folded in here when it's converted
367 * to an option instead of something based on .cputype
368 */
369
370 calibrate_delay();
371 cpu_data[cpu].udelay_val = loops_per_jiffy;
372
373 set_cpu_sibling_map(cpu);
374 set_cpu_core_map(cpu);
375
376 cpumask_set_cpu(cpu, &cpu_coherent_mask);
377 notify_cpu_starting(cpu);
378
379 /* Notify boot CPU that we're starting & ready to sync counters */
380 complete(&cpu_starting);
381
382 synchronise_count_slave(cpu);
383
384 /* The CPU is running and counters synchronised, now mark it online */
385 set_cpu_online(cpu, true);
386
387 calculate_cpu_foreign_map();
388
389 /*
390 * Notify boot CPU that we're up & online and it can safely return
391 * from __cpu_up
392 */
393 complete(&cpu_running);
394
395 /*
396 * irq will be enabled in ->smp_finish(), enabling it too early
397 * is dangerous.
398 */
399 WARN_ON_ONCE(!irqs_disabled());
400 mp_ops->smp_finish();
401
402 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
403}
404
405static void stop_this_cpu(void *dummy)
406{
407 /*
408 * Remove this CPU:
409 */
410
411 set_cpu_online(smp_processor_id(), false);
412 calculate_cpu_foreign_map();
413 local_irq_disable();
414 while (1);
415}
416
417void smp_send_stop(void)
418{
419 smp_call_function(stop_this_cpu, NULL, 0);
420}
421
422void __init smp_cpus_done(unsigned int max_cpus)
423{
424}
425
426/* called from main before smp_init() */
427void __init smp_prepare_cpus(unsigned int max_cpus)
428{
429 init_new_context(current, &init_mm);
430 current_thread_info()->cpu = 0;
431 mp_ops->prepare_cpus(max_cpus);
432 set_cpu_sibling_map(0);
433 set_cpu_core_map(0);
434 calculate_cpu_foreign_map();
435#ifndef CONFIG_HOTPLUG_CPU
436 init_cpu_present(cpu_possible_mask);
437#endif
438 cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
439}
440
441/* preload SMP state for boot cpu */
442void __init smp_prepare_boot_cpu(void)
443{
444 if (mp_ops->prepare_boot_cpu)
445 mp_ops->prepare_boot_cpu();
446 set_cpu_possible(0, true);
447 set_cpu_online(0, true);
448}
449
450int __cpu_up(unsigned int cpu, struct task_struct *tidle)
451{
452 int err;
453
454 err = mp_ops->boot_secondary(cpu, tidle);
455 if (err)
456 return err;
457
458 /* Wait for CPU to start and be ready to sync counters */
459 if (!wait_for_completion_timeout(&cpu_starting,
460 msecs_to_jiffies(1000))) {
461 pr_crit("CPU%u: failed to start\n", cpu);
462 return -EIO;
463 }
464
465 /* Wait for CPU to finish startup & mark itself online before return */
466 wait_for_completion(&cpu_running);
467 return 0;
468}
469
470#ifdef CONFIG_PROFILING
471/* Not really SMP stuff ... */
472int setup_profiling_timer(unsigned int multiplier)
473{
474 return 0;
475}
476#endif
477
478static void flush_tlb_all_ipi(void *info)
479{
480 local_flush_tlb_all();
481}
482
483void flush_tlb_all(void)
484{
485 if (cpu_has_mmid) {
486 htw_stop();
487 ginvt_full();
488 sync_ginv();
489 instruction_hazard();
490 htw_start();
491 return;
492 }
493
494 on_each_cpu(flush_tlb_all_ipi, NULL, 1);
495}
496
497static void flush_tlb_mm_ipi(void *mm)
498{
499 drop_mmu_context((struct mm_struct *)mm);
500}
501
502/*
503 * Special Variant of smp_call_function for use by TLB functions:
504 *
505 * o No return value
506 * o collapses to normal function call on UP kernels
507 * o collapses to normal function call on systems with a single shared
508 * primary cache.
509 */
510static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
511{
512 smp_call_function(func, info, 1);
513}
514
515static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
516{
517 preempt_disable();
518
519 smp_on_other_tlbs(func, info);
520 func(info);
521
522 preempt_enable();
523}
524
525/*
526 * The following tlb flush calls are invoked when old translations are
527 * being torn down, or pte attributes are changing. For single threaded
528 * address spaces, a new context is obtained on the current cpu, and tlb
529 * context on other cpus are invalidated to force a new context allocation
530 * at switch_mm time, should the mm ever be used on other cpus. For
531 * multithreaded address spaces, inter-CPU interrupts have to be sent.
532 * Another case where inter-CPU interrupts are required is when the target
533 * mm might be active on another cpu (eg debuggers doing the flushes on
534 * behalf of debugees, kswapd stealing pages from another process etc).
535 * Kanoj 07/00.
536 */
537
538void flush_tlb_mm(struct mm_struct *mm)
539{
540 if (!mm)
541 return;
542
543 if (atomic_read(&mm->mm_users) == 0)
544 return; /* happens as a result of exit_mmap() */
545
546 preempt_disable();
547
548 if (cpu_has_mmid) {
549 /*
550 * No need to worry about other CPUs - the ginvt in
551 * drop_mmu_context() will be globalized.
552 */
553 } else if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
554 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
555 } else {
556 unsigned int cpu;
557
558 for_each_online_cpu(cpu) {
559 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
560 set_cpu_context(cpu, mm, 0);
561 }
562 }
563 drop_mmu_context(mm);
564
565 preempt_enable();
566}
567
568struct flush_tlb_data {
569 struct vm_area_struct *vma;
570 unsigned long addr1;
571 unsigned long addr2;
572};
573
574static void flush_tlb_range_ipi(void *info)
575{
576 struct flush_tlb_data *fd = info;
577
578 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
579}
580
581void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
582{
583 struct mm_struct *mm = vma->vm_mm;
584 unsigned long addr;
585 u32 old_mmid;
586
587 preempt_disable();
588 if (cpu_has_mmid) {
589 htw_stop();
590 old_mmid = read_c0_memorymapid();
591 write_c0_memorymapid(cpu_asid(0, mm));
592 mtc0_tlbw_hazard();
593 addr = round_down(start, PAGE_SIZE * 2);
594 end = round_up(end, PAGE_SIZE * 2);
595 do {
596 ginvt_va_mmid(addr);
597 sync_ginv();
598 addr += PAGE_SIZE * 2;
599 } while (addr < end);
600 write_c0_memorymapid(old_mmid);
601 instruction_hazard();
602 htw_start();
603 } else if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
604 struct flush_tlb_data fd = {
605 .vma = vma,
606 .addr1 = start,
607 .addr2 = end,
608 };
609
610 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
611 local_flush_tlb_range(vma, start, end);
612 } else {
613 unsigned int cpu;
614 int exec = vma->vm_flags & VM_EXEC;
615
616 for_each_online_cpu(cpu) {
617 /*
618 * flush_cache_range() will only fully flush icache if
619 * the VMA is executable, otherwise we must invalidate
620 * ASID without it appearing to has_valid_asid() as if
621 * mm has been completely unused by that CPU.
622 */
623 if (cpu != smp_processor_id() && cpu_context(cpu, mm))
624 set_cpu_context(cpu, mm, !exec);
625 }
626 local_flush_tlb_range(vma, start, end);
627 }
628 preempt_enable();
629}
630
631static void flush_tlb_kernel_range_ipi(void *info)
632{
633 struct flush_tlb_data *fd = info;
634
635 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
636}
637
638void flush_tlb_kernel_range(unsigned long start, unsigned long end)
639{
640 struct flush_tlb_data fd = {
641 .addr1 = start,
642 .addr2 = end,
643 };
644
645 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
646}
647
648static void flush_tlb_page_ipi(void *info)
649{
650 struct flush_tlb_data *fd = info;
651
652 local_flush_tlb_page(fd->vma, fd->addr1);
653}
654
655void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
656{
657 u32 old_mmid;
658
659 preempt_disable();
660 if (cpu_has_mmid) {
661 htw_stop();
662 old_mmid = read_c0_memorymapid();
663 write_c0_memorymapid(cpu_asid(0, vma->vm_mm));
664 mtc0_tlbw_hazard();
665 ginvt_va_mmid(page);
666 sync_ginv();
667 write_c0_memorymapid(old_mmid);
668 instruction_hazard();
669 htw_start();
670 } else if ((atomic_read(&vma->vm_mm->mm_users) != 1) ||
671 (current->mm != vma->vm_mm)) {
672 struct flush_tlb_data fd = {
673 .vma = vma,
674 .addr1 = page,
675 };
676
677 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
678 local_flush_tlb_page(vma, page);
679 } else {
680 unsigned int cpu;
681
682 for_each_online_cpu(cpu) {
683 /*
684 * flush_cache_page() only does partial flushes, so
685 * invalidate ASID without it appearing to
686 * has_valid_asid() as if mm has been completely unused
687 * by that CPU.
688 */
689 if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
690 set_cpu_context(cpu, vma->vm_mm, 1);
691 }
692 local_flush_tlb_page(vma, page);
693 }
694 preempt_enable();
695}
696
697static void flush_tlb_one_ipi(void *info)
698{
699 unsigned long vaddr = (unsigned long) info;
700
701 local_flush_tlb_one(vaddr);
702}
703
704void flush_tlb_one(unsigned long vaddr)
705{
706 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
707}
708
709EXPORT_SYMBOL(flush_tlb_page);
710EXPORT_SYMBOL(flush_tlb_one);
711
712#ifdef CONFIG_HOTPLUG_CORE_SYNC_DEAD
713void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
714{
715 if (mp_ops->cleanup_dead_cpu)
716 mp_ops->cleanup_dead_cpu(cpu);
717}
718#endif
719
720#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
721
722static void tick_broadcast_callee(void *info)
723{
724 tick_receive_broadcast();
725}
726
727static DEFINE_PER_CPU(call_single_data_t, tick_broadcast_csd) =
728 CSD_INIT(tick_broadcast_callee, NULL);
729
730void tick_broadcast(const struct cpumask *mask)
731{
732 call_single_data_t *csd;
733 int cpu;
734
735 for_each_cpu(cpu, mask) {
736 csd = &per_cpu(tick_broadcast_csd, cpu);
737 smp_call_function_single_async(cpu, csd);
738 }
739}
740
741#endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */