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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/iommu.h>
13#include <linux/reset.h>
14
15#include <soc/tegra/pmc.h>
16
17#include "dc.h"
18#include "drm.h"
19#include "gem.h"
20
21#include <drm/drm_atomic.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_plane_helper.h>
24
25struct tegra_dc_soc_info {
26 bool supports_border_color;
27 bool supports_interlacing;
28 bool supports_cursor;
29 bool supports_block_linear;
30 unsigned int pitch_align;
31 bool has_powergate;
32};
33
34struct tegra_plane {
35 struct drm_plane base;
36 unsigned int index;
37};
38
39static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
40{
41 return container_of(plane, struct tegra_plane, base);
42}
43
44struct tegra_dc_state {
45 struct drm_crtc_state base;
46
47 struct clk *clk;
48 unsigned long pclk;
49 unsigned int div;
50
51 u32 planes;
52};
53
54static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
55{
56 if (state)
57 return container_of(state, struct tegra_dc_state, base);
58
59 return NULL;
60}
61
62struct tegra_plane_state {
63 struct drm_plane_state base;
64
65 struct tegra_bo_tiling tiling;
66 u32 format;
67 u32 swap;
68};
69
70static inline struct tegra_plane_state *
71to_tegra_plane_state(struct drm_plane_state *state)
72{
73 if (state)
74 return container_of(state, struct tegra_plane_state, base);
75
76 return NULL;
77}
78
79static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
80{
81 stats->frames = 0;
82 stats->vblank = 0;
83 stats->underflow = 0;
84 stats->overflow = 0;
85}
86
87/*
88 * Reads the active copy of a register. This takes the dc->lock spinlock to
89 * prevent races with the VBLANK processing which also needs access to the
90 * active copy of some registers.
91 */
92static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
93{
94 unsigned long flags;
95 u32 value;
96
97 spin_lock_irqsave(&dc->lock, flags);
98
99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
100 value = tegra_dc_readl(dc, offset);
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
102
103 spin_unlock_irqrestore(&dc->lock, flags);
104 return value;
105}
106
107/*
108 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
109 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
110 * Latching happens mmediately if the display controller is in STOP mode or
111 * on the next frame boundary otherwise.
112 *
113 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
114 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
115 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
116 * into the ACTIVE copy, either immediately if the display controller is in
117 * STOP mode, or at the next frame boundary otherwise.
118 */
119void tegra_dc_commit(struct tegra_dc *dc)
120{
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
123}
124
125static int tegra_dc_format(u32 fourcc, u32 *format, u32 *swap)
126{
127 /* assume no swapping of fetched data */
128 if (swap)
129 *swap = BYTE_SWAP_NOSWAP;
130
131 switch (fourcc) {
132 case DRM_FORMAT_XBGR8888:
133 *format = WIN_COLOR_DEPTH_R8G8B8A8;
134 break;
135
136 case DRM_FORMAT_XRGB8888:
137 *format = WIN_COLOR_DEPTH_B8G8R8A8;
138 break;
139
140 case DRM_FORMAT_RGB565:
141 *format = WIN_COLOR_DEPTH_B5G6R5;
142 break;
143
144 case DRM_FORMAT_UYVY:
145 *format = WIN_COLOR_DEPTH_YCbCr422;
146 break;
147
148 case DRM_FORMAT_YUYV:
149 if (swap)
150 *swap = BYTE_SWAP_SWAP2;
151
152 *format = WIN_COLOR_DEPTH_YCbCr422;
153 break;
154
155 case DRM_FORMAT_YUV420:
156 *format = WIN_COLOR_DEPTH_YCbCr420P;
157 break;
158
159 case DRM_FORMAT_YUV422:
160 *format = WIN_COLOR_DEPTH_YCbCr422P;
161 break;
162
163 default:
164 return -EINVAL;
165 }
166
167 return 0;
168}
169
170static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
171{
172 switch (format) {
173 case WIN_COLOR_DEPTH_YCbCr422:
174 case WIN_COLOR_DEPTH_YUV422:
175 if (planar)
176 *planar = false;
177
178 return true;
179
180 case WIN_COLOR_DEPTH_YCbCr420P:
181 case WIN_COLOR_DEPTH_YUV420P:
182 case WIN_COLOR_DEPTH_YCbCr422P:
183 case WIN_COLOR_DEPTH_YUV422P:
184 case WIN_COLOR_DEPTH_YCbCr422R:
185 case WIN_COLOR_DEPTH_YUV422R:
186 case WIN_COLOR_DEPTH_YCbCr422RA:
187 case WIN_COLOR_DEPTH_YUV422RA:
188 if (planar)
189 *planar = true;
190
191 return true;
192 }
193
194 if (planar)
195 *planar = false;
196
197 return false;
198}
199
200static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
201 unsigned int bpp)
202{
203 fixed20_12 outf = dfixed_init(out);
204 fixed20_12 inf = dfixed_init(in);
205 u32 dda_inc;
206 int max;
207
208 if (v)
209 max = 15;
210 else {
211 switch (bpp) {
212 case 2:
213 max = 8;
214 break;
215
216 default:
217 WARN_ON_ONCE(1);
218 /* fallthrough */
219 case 4:
220 max = 4;
221 break;
222 }
223 }
224
225 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
226 inf.full -= dfixed_const(1);
227
228 dda_inc = dfixed_div(inf, outf);
229 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
230
231 return dda_inc;
232}
233
234static inline u32 compute_initial_dda(unsigned int in)
235{
236 fixed20_12 inf = dfixed_init(in);
237 return dfixed_frac(inf);
238}
239
240static void tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
241 const struct tegra_dc_window *window)
242{
243 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
244 unsigned long value, flags;
245 bool yuv, planar;
246
247 /*
248 * For YUV planar modes, the number of bytes per pixel takes into
249 * account only the luma component and therefore is 1.
250 */
251 yuv = tegra_dc_format_is_yuv(window->format, &planar);
252 if (!yuv)
253 bpp = window->bits_per_pixel / 8;
254 else
255 bpp = planar ? 1 : 2;
256
257 spin_lock_irqsave(&dc->lock, flags);
258
259 value = WINDOW_A_SELECT << index;
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
261
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
264
265 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
266 tegra_dc_writel(dc, value, DC_WIN_POSITION);
267
268 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
269 tegra_dc_writel(dc, value, DC_WIN_SIZE);
270
271 h_offset = window->src.x * bpp;
272 v_offset = window->src.y;
273 h_size = window->src.w * bpp;
274 v_size = window->src.h;
275
276 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
278
279 /*
280 * For DDA computations the number of bytes per pixel for YUV planar
281 * modes needs to take into account all Y, U and V components.
282 */
283 if (yuv && planar)
284 bpp = 2;
285
286 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
287 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
288
289 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
290 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
291
292 h_dda = compute_initial_dda(window->src.x);
293 v_dda = compute_initial_dda(window->src.y);
294
295 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
296 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
297
298 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
299 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
300
301 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
302
303 if (yuv && planar) {
304 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
305 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
306 value = window->stride[1] << 16 | window->stride[0];
307 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
308 } else {
309 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
310 }
311
312 if (window->bottom_up)
313 v_offset += window->src.h - 1;
314
315 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
316 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
317
318 if (dc->soc->supports_block_linear) {
319 unsigned long height = window->tiling.value;
320
321 switch (window->tiling.mode) {
322 case TEGRA_BO_TILING_MODE_PITCH:
323 value = DC_WINBUF_SURFACE_KIND_PITCH;
324 break;
325
326 case TEGRA_BO_TILING_MODE_TILED:
327 value = DC_WINBUF_SURFACE_KIND_TILED;
328 break;
329
330 case TEGRA_BO_TILING_MODE_BLOCK:
331 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
332 DC_WINBUF_SURFACE_KIND_BLOCK;
333 break;
334 }
335
336 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
337 } else {
338 switch (window->tiling.mode) {
339 case TEGRA_BO_TILING_MODE_PITCH:
340 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
341 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
342 break;
343
344 case TEGRA_BO_TILING_MODE_TILED:
345 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
346 DC_WIN_BUFFER_ADDR_MODE_TILE;
347 break;
348
349 case TEGRA_BO_TILING_MODE_BLOCK:
350 /*
351 * No need to handle this here because ->atomic_check
352 * will already have filtered it out.
353 */
354 break;
355 }
356
357 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
358 }
359
360 value = WIN_ENABLE;
361
362 if (yuv) {
363 /* setup default colorspace conversion coefficients */
364 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
365 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
366 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
367 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
368 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
369 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
370 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
371 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
372
373 value |= CSC_ENABLE;
374 } else if (window->bits_per_pixel < 24) {
375 value |= COLOR_EXPAND;
376 }
377
378 if (window->bottom_up)
379 value |= V_DIRECTION;
380
381 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
382
383 /*
384 * Disable blending and assume Window A is the bottom-most window,
385 * Window C is the top-most window and Window B is in the middle.
386 */
387 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
388 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
389
390 switch (index) {
391 case 0:
392 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
393 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
394 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
395 break;
396
397 case 1:
398 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
399 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
400 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
401 break;
402
403 case 2:
404 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
405 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
406 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
407 break;
408 }
409
410 spin_unlock_irqrestore(&dc->lock, flags);
411}
412
413static void tegra_plane_destroy(struct drm_plane *plane)
414{
415 struct tegra_plane *p = to_tegra_plane(plane);
416
417 drm_plane_cleanup(plane);
418 kfree(p);
419}
420
421static const u32 tegra_primary_plane_formats[] = {
422 DRM_FORMAT_XBGR8888,
423 DRM_FORMAT_XRGB8888,
424 DRM_FORMAT_RGB565,
425};
426
427static void tegra_primary_plane_destroy(struct drm_plane *plane)
428{
429 tegra_plane_destroy(plane);
430}
431
432static void tegra_plane_reset(struct drm_plane *plane)
433{
434 struct tegra_plane_state *state;
435
436 if (plane->state)
437 __drm_atomic_helper_plane_destroy_state(plane, plane->state);
438
439 kfree(plane->state);
440 plane->state = NULL;
441
442 state = kzalloc(sizeof(*state), GFP_KERNEL);
443 if (state) {
444 plane->state = &state->base;
445 plane->state->plane = plane;
446 }
447}
448
449static struct drm_plane_state *tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
450{
451 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
452 struct tegra_plane_state *copy;
453
454 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
455 if (!copy)
456 return NULL;
457
458 __drm_atomic_helper_plane_duplicate_state(plane, ©->base);
459 copy->tiling = state->tiling;
460 copy->format = state->format;
461 copy->swap = state->swap;
462
463 return ©->base;
464}
465
466static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
467 struct drm_plane_state *state)
468{
469 __drm_atomic_helper_plane_destroy_state(plane, state);
470 kfree(state);
471}
472
473static const struct drm_plane_funcs tegra_primary_plane_funcs = {
474 .update_plane = drm_atomic_helper_update_plane,
475 .disable_plane = drm_atomic_helper_disable_plane,
476 .destroy = tegra_primary_plane_destroy,
477 .reset = tegra_plane_reset,
478 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
479 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
480};
481
482static int tegra_plane_prepare_fb(struct drm_plane *plane,
483 const struct drm_plane_state *new_state)
484{
485 return 0;
486}
487
488static void tegra_plane_cleanup_fb(struct drm_plane *plane,
489 const struct drm_plane_state *old_fb)
490{
491}
492
493static int tegra_plane_state_add(struct tegra_plane *plane,
494 struct drm_plane_state *state)
495{
496 struct drm_crtc_state *crtc_state;
497 struct tegra_dc_state *tegra;
498
499 /* Propagate errors from allocation or locking failures. */
500 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
501 if (IS_ERR(crtc_state))
502 return PTR_ERR(crtc_state);
503
504 tegra = to_dc_state(crtc_state);
505
506 tegra->planes |= WIN_A_ACT_REQ << plane->index;
507
508 return 0;
509}
510
511static int tegra_plane_atomic_check(struct drm_plane *plane,
512 struct drm_plane_state *state)
513{
514 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
515 struct tegra_bo_tiling *tiling = &plane_state->tiling;
516 struct tegra_plane *tegra = to_tegra_plane(plane);
517 struct tegra_dc *dc = to_tegra_dc(state->crtc);
518 int err;
519
520 /* no need for further checks if the plane is being disabled */
521 if (!state->crtc)
522 return 0;
523
524 err = tegra_dc_format(state->fb->pixel_format, &plane_state->format,
525 &plane_state->swap);
526 if (err < 0)
527 return err;
528
529 err = tegra_fb_get_tiling(state->fb, tiling);
530 if (err < 0)
531 return err;
532
533 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
534 !dc->soc->supports_block_linear) {
535 DRM_ERROR("hardware doesn't support block linear mode\n");
536 return -EINVAL;
537 }
538
539 /*
540 * Tegra doesn't support different strides for U and V planes so we
541 * error out if the user tries to display a framebuffer with such a
542 * configuration.
543 */
544 if (drm_format_num_planes(state->fb->pixel_format) > 2) {
545 if (state->fb->pitches[2] != state->fb->pitches[1]) {
546 DRM_ERROR("unsupported UV-plane configuration\n");
547 return -EINVAL;
548 }
549 }
550
551 err = tegra_plane_state_add(tegra, state);
552 if (err < 0)
553 return err;
554
555 return 0;
556}
557
558static void tegra_plane_atomic_update(struct drm_plane *plane,
559 struct drm_plane_state *old_state)
560{
561 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
562 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
563 struct drm_framebuffer *fb = plane->state->fb;
564 struct tegra_plane *p = to_tegra_plane(plane);
565 struct tegra_dc_window window;
566 unsigned int i;
567
568 /* rien ne va plus */
569 if (!plane->state->crtc || !plane->state->fb)
570 return;
571
572 memset(&window, 0, sizeof(window));
573 window.src.x = plane->state->src_x >> 16;
574 window.src.y = plane->state->src_y >> 16;
575 window.src.w = plane->state->src_w >> 16;
576 window.src.h = plane->state->src_h >> 16;
577 window.dst.x = plane->state->crtc_x;
578 window.dst.y = plane->state->crtc_y;
579 window.dst.w = plane->state->crtc_w;
580 window.dst.h = plane->state->crtc_h;
581 window.bits_per_pixel = fb->bits_per_pixel;
582 window.bottom_up = tegra_fb_is_bottom_up(fb);
583
584 /* copy from state */
585 window.tiling = state->tiling;
586 window.format = state->format;
587 window.swap = state->swap;
588
589 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
590 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
591
592 window.base[i] = bo->paddr + fb->offsets[i];
593 window.stride[i] = fb->pitches[i];
594 }
595
596 tegra_dc_setup_window(dc, p->index, &window);
597}
598
599static void tegra_plane_atomic_disable(struct drm_plane *plane,
600 struct drm_plane_state *old_state)
601{
602 struct tegra_plane *p = to_tegra_plane(plane);
603 struct tegra_dc *dc;
604 unsigned long flags;
605 u32 value;
606
607 /* rien ne va plus */
608 if (!old_state || !old_state->crtc)
609 return;
610
611 dc = to_tegra_dc(old_state->crtc);
612
613 spin_lock_irqsave(&dc->lock, flags);
614
615 value = WINDOW_A_SELECT << p->index;
616 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
617
618 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
619 value &= ~WIN_ENABLE;
620 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
621
622 spin_unlock_irqrestore(&dc->lock, flags);
623}
624
625static const struct drm_plane_helper_funcs tegra_primary_plane_helper_funcs = {
626 .prepare_fb = tegra_plane_prepare_fb,
627 .cleanup_fb = tegra_plane_cleanup_fb,
628 .atomic_check = tegra_plane_atomic_check,
629 .atomic_update = tegra_plane_atomic_update,
630 .atomic_disable = tegra_plane_atomic_disable,
631};
632
633static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
634 struct tegra_dc *dc)
635{
636 /*
637 * Ideally this would use drm_crtc_mask(), but that would require the
638 * CRTC to already be in the mode_config's list of CRTCs. However, it
639 * will only be added to that list in the drm_crtc_init_with_planes()
640 * (in tegra_dc_init()), which in turn requires registration of these
641 * planes. So we have ourselves a nice little chicken and egg problem
642 * here.
643 *
644 * We work around this by manually creating the mask from the number
645 * of CRTCs that have been registered, and should therefore always be
646 * the same as drm_crtc_index() after registration.
647 */
648 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
649 struct tegra_plane *plane;
650 unsigned int num_formats;
651 const u32 *formats;
652 int err;
653
654 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
655 if (!plane)
656 return ERR_PTR(-ENOMEM);
657
658 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
659 formats = tegra_primary_plane_formats;
660
661 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
662 &tegra_primary_plane_funcs, formats,
663 num_formats, DRM_PLANE_TYPE_PRIMARY,
664 NULL);
665 if (err < 0) {
666 kfree(plane);
667 return ERR_PTR(err);
668 }
669
670 drm_plane_helper_add(&plane->base, &tegra_primary_plane_helper_funcs);
671
672 return &plane->base;
673}
674
675static const u32 tegra_cursor_plane_formats[] = {
676 DRM_FORMAT_RGBA8888,
677};
678
679static int tegra_cursor_atomic_check(struct drm_plane *plane,
680 struct drm_plane_state *state)
681{
682 struct tegra_plane *tegra = to_tegra_plane(plane);
683 int err;
684
685 /* no need for further checks if the plane is being disabled */
686 if (!state->crtc)
687 return 0;
688
689 /* scaling not supported for cursor */
690 if ((state->src_w >> 16 != state->crtc_w) ||
691 (state->src_h >> 16 != state->crtc_h))
692 return -EINVAL;
693
694 /* only square cursors supported */
695 if (state->src_w != state->src_h)
696 return -EINVAL;
697
698 if (state->crtc_w != 32 && state->crtc_w != 64 &&
699 state->crtc_w != 128 && state->crtc_w != 256)
700 return -EINVAL;
701
702 err = tegra_plane_state_add(tegra, state);
703 if (err < 0)
704 return err;
705
706 return 0;
707}
708
709static void tegra_cursor_atomic_update(struct drm_plane *plane,
710 struct drm_plane_state *old_state)
711{
712 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
713 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
714 struct drm_plane_state *state = plane->state;
715 u32 value = CURSOR_CLIP_DISPLAY;
716
717 /* rien ne va plus */
718 if (!plane->state->crtc || !plane->state->fb)
719 return;
720
721 switch (state->crtc_w) {
722 case 32:
723 value |= CURSOR_SIZE_32x32;
724 break;
725
726 case 64:
727 value |= CURSOR_SIZE_64x64;
728 break;
729
730 case 128:
731 value |= CURSOR_SIZE_128x128;
732 break;
733
734 case 256:
735 value |= CURSOR_SIZE_256x256;
736 break;
737
738 default:
739 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
740 state->crtc_h);
741 return;
742 }
743
744 value |= (bo->paddr >> 10) & 0x3fffff;
745 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
746
747#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
748 value = (bo->paddr >> 32) & 0x3;
749 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
750#endif
751
752 /* enable cursor and set blend mode */
753 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
754 value |= CURSOR_ENABLE;
755 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
756
757 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
758 value &= ~CURSOR_DST_BLEND_MASK;
759 value &= ~CURSOR_SRC_BLEND_MASK;
760 value |= CURSOR_MODE_NORMAL;
761 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
762 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
763 value |= CURSOR_ALPHA;
764 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
765
766 /* position the cursor */
767 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
768 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
769}
770
771static void tegra_cursor_atomic_disable(struct drm_plane *plane,
772 struct drm_plane_state *old_state)
773{
774 struct tegra_dc *dc;
775 u32 value;
776
777 /* rien ne va plus */
778 if (!old_state || !old_state->crtc)
779 return;
780
781 dc = to_tegra_dc(old_state->crtc);
782
783 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
784 value &= ~CURSOR_ENABLE;
785 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
786}
787
788static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
789 .update_plane = drm_atomic_helper_update_plane,
790 .disable_plane = drm_atomic_helper_disable_plane,
791 .destroy = tegra_plane_destroy,
792 .reset = tegra_plane_reset,
793 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
794 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
795};
796
797static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
798 .prepare_fb = tegra_plane_prepare_fb,
799 .cleanup_fb = tegra_plane_cleanup_fb,
800 .atomic_check = tegra_cursor_atomic_check,
801 .atomic_update = tegra_cursor_atomic_update,
802 .atomic_disable = tegra_cursor_atomic_disable,
803};
804
805static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
806 struct tegra_dc *dc)
807{
808 struct tegra_plane *plane;
809 unsigned int num_formats;
810 const u32 *formats;
811 int err;
812
813 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
814 if (!plane)
815 return ERR_PTR(-ENOMEM);
816
817 /*
818 * This index is kind of fake. The cursor isn't a regular plane, but
819 * its update and activation request bits in DC_CMD_STATE_CONTROL do
820 * use the same programming. Setting this fake index here allows the
821 * code in tegra_add_plane_state() to do the right thing without the
822 * need to special-casing the cursor plane.
823 */
824 plane->index = 6;
825
826 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
827 formats = tegra_cursor_plane_formats;
828
829 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
830 &tegra_cursor_plane_funcs, formats,
831 num_formats, DRM_PLANE_TYPE_CURSOR,
832 NULL);
833 if (err < 0) {
834 kfree(plane);
835 return ERR_PTR(err);
836 }
837
838 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
839
840 return &plane->base;
841}
842
843static void tegra_overlay_plane_destroy(struct drm_plane *plane)
844{
845 tegra_plane_destroy(plane);
846}
847
848static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
849 .update_plane = drm_atomic_helper_update_plane,
850 .disable_plane = drm_atomic_helper_disable_plane,
851 .destroy = tegra_overlay_plane_destroy,
852 .reset = tegra_plane_reset,
853 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
854 .atomic_destroy_state = tegra_plane_atomic_destroy_state,
855};
856
857static const uint32_t tegra_overlay_plane_formats[] = {
858 DRM_FORMAT_XBGR8888,
859 DRM_FORMAT_XRGB8888,
860 DRM_FORMAT_RGB565,
861 DRM_FORMAT_UYVY,
862 DRM_FORMAT_YUYV,
863 DRM_FORMAT_YUV420,
864 DRM_FORMAT_YUV422,
865};
866
867static const struct drm_plane_helper_funcs tegra_overlay_plane_helper_funcs = {
868 .prepare_fb = tegra_plane_prepare_fb,
869 .cleanup_fb = tegra_plane_cleanup_fb,
870 .atomic_check = tegra_plane_atomic_check,
871 .atomic_update = tegra_plane_atomic_update,
872 .atomic_disable = tegra_plane_atomic_disable,
873};
874
875static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
876 struct tegra_dc *dc,
877 unsigned int index)
878{
879 struct tegra_plane *plane;
880 unsigned int num_formats;
881 const u32 *formats;
882 int err;
883
884 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
885 if (!plane)
886 return ERR_PTR(-ENOMEM);
887
888 plane->index = index;
889
890 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
891 formats = tegra_overlay_plane_formats;
892
893 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
894 &tegra_overlay_plane_funcs, formats,
895 num_formats, DRM_PLANE_TYPE_OVERLAY,
896 NULL);
897 if (err < 0) {
898 kfree(plane);
899 return ERR_PTR(err);
900 }
901
902 drm_plane_helper_add(&plane->base, &tegra_overlay_plane_helper_funcs);
903
904 return &plane->base;
905}
906
907static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
908{
909 struct drm_plane *plane;
910 unsigned int i;
911
912 for (i = 0; i < 2; i++) {
913 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
914 if (IS_ERR(plane))
915 return PTR_ERR(plane);
916 }
917
918 return 0;
919}
920
921u32 tegra_dc_get_vblank_counter(struct tegra_dc *dc)
922{
923 if (dc->syncpt)
924 return host1x_syncpt_read(dc->syncpt);
925
926 /* fallback to software emulated VBLANK counter */
927 return drm_crtc_vblank_count(&dc->base);
928}
929
930void tegra_dc_enable_vblank(struct tegra_dc *dc)
931{
932 unsigned long value, flags;
933
934 spin_lock_irqsave(&dc->lock, flags);
935
936 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
937 value |= VBLANK_INT;
938 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
939
940 spin_unlock_irqrestore(&dc->lock, flags);
941}
942
943void tegra_dc_disable_vblank(struct tegra_dc *dc)
944{
945 unsigned long value, flags;
946
947 spin_lock_irqsave(&dc->lock, flags);
948
949 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
950 value &= ~VBLANK_INT;
951 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
952
953 spin_unlock_irqrestore(&dc->lock, flags);
954}
955
956static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
957{
958 struct drm_device *drm = dc->base.dev;
959 struct drm_crtc *crtc = &dc->base;
960 unsigned long flags, base;
961 struct tegra_bo *bo;
962
963 spin_lock_irqsave(&drm->event_lock, flags);
964
965 if (!dc->event) {
966 spin_unlock_irqrestore(&drm->event_lock, flags);
967 return;
968 }
969
970 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
971
972 spin_lock(&dc->lock);
973
974 /* check if new start address has been latched */
975 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
976 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
977 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
978 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
979
980 spin_unlock(&dc->lock);
981
982 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
983 drm_crtc_send_vblank_event(crtc, dc->event);
984 drm_crtc_vblank_put(crtc);
985 dc->event = NULL;
986 }
987
988 spin_unlock_irqrestore(&drm->event_lock, flags);
989}
990
991static void tegra_dc_destroy(struct drm_crtc *crtc)
992{
993 drm_crtc_cleanup(crtc);
994}
995
996static void tegra_crtc_reset(struct drm_crtc *crtc)
997{
998 struct tegra_dc_state *state;
999
1000 if (crtc->state)
1001 __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
1002
1003 kfree(crtc->state);
1004 crtc->state = NULL;
1005
1006 state = kzalloc(sizeof(*state), GFP_KERNEL);
1007 if (state) {
1008 crtc->state = &state->base;
1009 crtc->state->crtc = crtc;
1010 }
1011
1012 drm_crtc_vblank_reset(crtc);
1013}
1014
1015static struct drm_crtc_state *
1016tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1017{
1018 struct tegra_dc_state *state = to_dc_state(crtc->state);
1019 struct tegra_dc_state *copy;
1020
1021 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1022 if (!copy)
1023 return NULL;
1024
1025 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1026 copy->clk = state->clk;
1027 copy->pclk = state->pclk;
1028 copy->div = state->div;
1029 copy->planes = state->planes;
1030
1031 return ©->base;
1032}
1033
1034static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1035 struct drm_crtc_state *state)
1036{
1037 __drm_atomic_helper_crtc_destroy_state(crtc, state);
1038 kfree(state);
1039}
1040
1041static const struct drm_crtc_funcs tegra_crtc_funcs = {
1042 .page_flip = drm_atomic_helper_page_flip,
1043 .set_config = drm_atomic_helper_set_config,
1044 .destroy = tegra_dc_destroy,
1045 .reset = tegra_crtc_reset,
1046 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1047 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1048};
1049
1050static int tegra_dc_set_timings(struct tegra_dc *dc,
1051 struct drm_display_mode *mode)
1052{
1053 unsigned int h_ref_to_sync = 1;
1054 unsigned int v_ref_to_sync = 1;
1055 unsigned long value;
1056
1057 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1058
1059 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1060 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1061
1062 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1063 ((mode->hsync_end - mode->hsync_start) << 0);
1064 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1065
1066 value = ((mode->vtotal - mode->vsync_end) << 16) |
1067 ((mode->htotal - mode->hsync_end) << 0);
1068 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1069
1070 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1071 ((mode->hsync_start - mode->hdisplay) << 0);
1072 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1073
1074 value = (mode->vdisplay << 16) | mode->hdisplay;
1075 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1076
1077 return 0;
1078}
1079
1080/**
1081 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1082 * state
1083 * @dc: display controller
1084 * @crtc_state: CRTC atomic state
1085 * @clk: parent clock for display controller
1086 * @pclk: pixel clock
1087 * @div: shift clock divider
1088 *
1089 * Returns:
1090 * 0 on success or a negative error-code on failure.
1091 */
1092int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1093 struct drm_crtc_state *crtc_state,
1094 struct clk *clk, unsigned long pclk,
1095 unsigned int div)
1096{
1097 struct tegra_dc_state *state = to_dc_state(crtc_state);
1098
1099 if (!clk_has_parent(dc->clk, clk))
1100 return -EINVAL;
1101
1102 state->clk = clk;
1103 state->pclk = pclk;
1104 state->div = div;
1105
1106 return 0;
1107}
1108
1109static void tegra_dc_commit_state(struct tegra_dc *dc,
1110 struct tegra_dc_state *state)
1111{
1112 u32 value;
1113 int err;
1114
1115 err = clk_set_parent(dc->clk, state->clk);
1116 if (err < 0)
1117 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1118
1119 /*
1120 * Outputs may not want to change the parent clock rate. This is only
1121 * relevant to Tegra20 where only a single display PLL is available.
1122 * Since that PLL would typically be used for HDMI, an internal LVDS
1123 * panel would need to be driven by some other clock such as PLL_P
1124 * which is shared with other peripherals. Changing the clock rate
1125 * should therefore be avoided.
1126 */
1127 if (state->pclk > 0) {
1128 err = clk_set_rate(state->clk, state->pclk);
1129 if (err < 0)
1130 dev_err(dc->dev,
1131 "failed to set clock rate to %lu Hz\n",
1132 state->pclk);
1133 }
1134
1135 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1136 state->div);
1137 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1138
1139 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1140 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1141}
1142
1143static void tegra_dc_stop(struct tegra_dc *dc)
1144{
1145 u32 value;
1146
1147 /* stop the display controller */
1148 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1149 value &= ~DISP_CTRL_MODE_MASK;
1150 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1151
1152 tegra_dc_commit(dc);
1153}
1154
1155static bool tegra_dc_idle(struct tegra_dc *dc)
1156{
1157 u32 value;
1158
1159 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1160
1161 return (value & DISP_CTRL_MODE_MASK) == 0;
1162}
1163
1164static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1165{
1166 timeout = jiffies + msecs_to_jiffies(timeout);
1167
1168 while (time_before(jiffies, timeout)) {
1169 if (tegra_dc_idle(dc))
1170 return 0;
1171
1172 usleep_range(1000, 2000);
1173 }
1174
1175 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1176 return -ETIMEDOUT;
1177}
1178
1179static void tegra_crtc_disable(struct drm_crtc *crtc)
1180{
1181 struct tegra_dc *dc = to_tegra_dc(crtc);
1182 u32 value;
1183
1184 if (!tegra_dc_idle(dc)) {
1185 tegra_dc_stop(dc);
1186
1187 /*
1188 * Ignore the return value, there isn't anything useful to do
1189 * in case this fails.
1190 */
1191 tegra_dc_wait_idle(dc, 100);
1192 }
1193
1194 /*
1195 * This should really be part of the RGB encoder driver, but clearing
1196 * these bits has the side-effect of stopping the display controller.
1197 * When that happens no VBLANK interrupts will be raised. At the same
1198 * time the encoder is disabled before the display controller, so the
1199 * above code is always going to timeout waiting for the controller
1200 * to go idle.
1201 *
1202 * Given the close coupling between the RGB encoder and the display
1203 * controller doing it here is still kind of okay. None of the other
1204 * encoder drivers require these bits to be cleared.
1205 *
1206 * XXX: Perhaps given that the display controller is switched off at
1207 * this point anyway maybe clearing these bits isn't even useful for
1208 * the RGB encoder?
1209 */
1210 if (dc->rgb) {
1211 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1212 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1213 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1214 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1215 }
1216
1217 tegra_dc_stats_reset(&dc->stats);
1218 drm_crtc_vblank_off(crtc);
1219}
1220
1221static void tegra_crtc_enable(struct drm_crtc *crtc)
1222{
1223 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1224 struct tegra_dc_state *state = to_dc_state(crtc->state);
1225 struct tegra_dc *dc = to_tegra_dc(crtc);
1226 u32 value;
1227
1228 tegra_dc_commit_state(dc, state);
1229
1230 /* program display mode */
1231 tegra_dc_set_timings(dc, mode);
1232
1233 /* interlacing isn't supported yet, so disable it */
1234 if (dc->soc->supports_interlacing) {
1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1236 value &= ~INTERLACE_ENABLE;
1237 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1238 }
1239
1240 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1241 value &= ~DISP_CTRL_MODE_MASK;
1242 value |= DISP_CTRL_MODE_C_DISPLAY;
1243 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1244
1245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1246 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1247 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1249
1250 tegra_dc_commit(dc);
1251
1252 drm_crtc_vblank_on(crtc);
1253}
1254
1255static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1256 struct drm_crtc_state *state)
1257{
1258 return 0;
1259}
1260
1261static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1262 struct drm_crtc_state *old_crtc_state)
1263{
1264 struct tegra_dc *dc = to_tegra_dc(crtc);
1265
1266 if (crtc->state->event) {
1267 crtc->state->event->pipe = drm_crtc_index(crtc);
1268
1269 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1270
1271 dc->event = crtc->state->event;
1272 crtc->state->event = NULL;
1273 }
1274}
1275
1276static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1277 struct drm_crtc_state *old_crtc_state)
1278{
1279 struct tegra_dc_state *state = to_dc_state(crtc->state);
1280 struct tegra_dc *dc = to_tegra_dc(crtc);
1281
1282 tegra_dc_writel(dc, state->planes << 8, DC_CMD_STATE_CONTROL);
1283 tegra_dc_writel(dc, state->planes, DC_CMD_STATE_CONTROL);
1284}
1285
1286static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1287 .disable = tegra_crtc_disable,
1288 .enable = tegra_crtc_enable,
1289 .atomic_check = tegra_crtc_atomic_check,
1290 .atomic_begin = tegra_crtc_atomic_begin,
1291 .atomic_flush = tegra_crtc_atomic_flush,
1292};
1293
1294static irqreturn_t tegra_dc_irq(int irq, void *data)
1295{
1296 struct tegra_dc *dc = data;
1297 unsigned long status;
1298
1299 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1300 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1301
1302 if (status & FRAME_END_INT) {
1303 /*
1304 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1305 */
1306 dc->stats.frames++;
1307 }
1308
1309 if (status & VBLANK_INT) {
1310 /*
1311 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1312 */
1313 drm_crtc_handle_vblank(&dc->base);
1314 tegra_dc_finish_page_flip(dc);
1315 dc->stats.vblank++;
1316 }
1317
1318 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1319 /*
1320 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1321 */
1322 dc->stats.underflow++;
1323 }
1324
1325 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1326 /*
1327 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1328 */
1329 dc->stats.overflow++;
1330 }
1331
1332 return IRQ_HANDLED;
1333}
1334
1335static int tegra_dc_show_regs(struct seq_file *s, void *data)
1336{
1337 struct drm_info_node *node = s->private;
1338 struct tegra_dc *dc = node->info_ent->data;
1339 int err = 0;
1340
1341 drm_modeset_lock_crtc(&dc->base, NULL);
1342
1343 if (!dc->base.state->active) {
1344 err = -EBUSY;
1345 goto unlock;
1346 }
1347
1348#define DUMP_REG(name) \
1349 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1350 tegra_dc_readl(dc, name))
1351
1352 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1353 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1354 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1355 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1356 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1357 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1358 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1359 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1360 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1361 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1362 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1363 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1364 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1365 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1366 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1367 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1368 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1369 DUMP_REG(DC_CMD_INT_STATUS);
1370 DUMP_REG(DC_CMD_INT_MASK);
1371 DUMP_REG(DC_CMD_INT_ENABLE);
1372 DUMP_REG(DC_CMD_INT_TYPE);
1373 DUMP_REG(DC_CMD_INT_POLARITY);
1374 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1375 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1376 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1377 DUMP_REG(DC_CMD_STATE_ACCESS);
1378 DUMP_REG(DC_CMD_STATE_CONTROL);
1379 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1380 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1381 DUMP_REG(DC_COM_CRC_CONTROL);
1382 DUMP_REG(DC_COM_CRC_CHECKSUM);
1383 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1384 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1385 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1386 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1387 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1388 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1389 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1390 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1391 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1392 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1393 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1394 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1395 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1396 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1397 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1398 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1399 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1400 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1401 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1402 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1403 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1404 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1405 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1406 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1407 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1408 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1409 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1410 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1411 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1412 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1413 DUMP_REG(DC_COM_SPI_CONTROL);
1414 DUMP_REG(DC_COM_SPI_START_BYTE);
1415 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1416 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1417 DUMP_REG(DC_COM_HSPI_CS_DC);
1418 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1419 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1420 DUMP_REG(DC_COM_GPIO_CTRL);
1421 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1422 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1423 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1424 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1425 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1426 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1427 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1428 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1429 DUMP_REG(DC_DISP_REF_TO_SYNC);
1430 DUMP_REG(DC_DISP_SYNC_WIDTH);
1431 DUMP_REG(DC_DISP_BACK_PORCH);
1432 DUMP_REG(DC_DISP_ACTIVE);
1433 DUMP_REG(DC_DISP_FRONT_PORCH);
1434 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1435 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1436 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1437 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1438 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1439 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1440 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1441 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1442 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1443 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1444 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1445 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1446 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1447 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1448 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1449 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1450 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1451 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1452 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1453 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1454 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1455 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1456 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1457 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1458 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1459 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1460 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1461 DUMP_REG(DC_DISP_M0_CONTROL);
1462 DUMP_REG(DC_DISP_M1_CONTROL);
1463 DUMP_REG(DC_DISP_DI_CONTROL);
1464 DUMP_REG(DC_DISP_PP_CONTROL);
1465 DUMP_REG(DC_DISP_PP_SELECT_A);
1466 DUMP_REG(DC_DISP_PP_SELECT_B);
1467 DUMP_REG(DC_DISP_PP_SELECT_C);
1468 DUMP_REG(DC_DISP_PP_SELECT_D);
1469 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1470 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1471 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1472 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1473 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1474 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1475 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1476 DUMP_REG(DC_DISP_BORDER_COLOR);
1477 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1478 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1479 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1480 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1481 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1482 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1483 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1484 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1485 DUMP_REG(DC_DISP_CURSOR_POSITION);
1486 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1487 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1488 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1489 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1490 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1491 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1492 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1493 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1494 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1495 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1496 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1497 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1498 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1499 DUMP_REG(DC_DISP_SD_CONTROL);
1500 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1501 DUMP_REG(DC_DISP_SD_LUT(0));
1502 DUMP_REG(DC_DISP_SD_LUT(1));
1503 DUMP_REG(DC_DISP_SD_LUT(2));
1504 DUMP_REG(DC_DISP_SD_LUT(3));
1505 DUMP_REG(DC_DISP_SD_LUT(4));
1506 DUMP_REG(DC_DISP_SD_LUT(5));
1507 DUMP_REG(DC_DISP_SD_LUT(6));
1508 DUMP_REG(DC_DISP_SD_LUT(7));
1509 DUMP_REG(DC_DISP_SD_LUT(8));
1510 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1511 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1512 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1513 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1514 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1515 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1516 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1517 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1518 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1519 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1520 DUMP_REG(DC_DISP_SD_BL_TF(0));
1521 DUMP_REG(DC_DISP_SD_BL_TF(1));
1522 DUMP_REG(DC_DISP_SD_BL_TF(2));
1523 DUMP_REG(DC_DISP_SD_BL_TF(3));
1524 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1525 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1526 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1527 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1528 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1529 DUMP_REG(DC_WIN_WIN_OPTIONS);
1530 DUMP_REG(DC_WIN_BYTE_SWAP);
1531 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1532 DUMP_REG(DC_WIN_COLOR_DEPTH);
1533 DUMP_REG(DC_WIN_POSITION);
1534 DUMP_REG(DC_WIN_SIZE);
1535 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1536 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1537 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1538 DUMP_REG(DC_WIN_DDA_INC);
1539 DUMP_REG(DC_WIN_LINE_STRIDE);
1540 DUMP_REG(DC_WIN_BUF_STRIDE);
1541 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1542 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1543 DUMP_REG(DC_WIN_DV_CONTROL);
1544 DUMP_REG(DC_WIN_BLEND_NOKEY);
1545 DUMP_REG(DC_WIN_BLEND_1WIN);
1546 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1547 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1548 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1549 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1550 DUMP_REG(DC_WINBUF_START_ADDR);
1551 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1552 DUMP_REG(DC_WINBUF_START_ADDR_U);
1553 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1554 DUMP_REG(DC_WINBUF_START_ADDR_V);
1555 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1556 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1557 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1558 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1559 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1560 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1561 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1562 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1563 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1564
1565#undef DUMP_REG
1566
1567unlock:
1568 drm_modeset_unlock_crtc(&dc->base);
1569 return err;
1570}
1571
1572static int tegra_dc_show_crc(struct seq_file *s, void *data)
1573{
1574 struct drm_info_node *node = s->private;
1575 struct tegra_dc *dc = node->info_ent->data;
1576 int err = 0;
1577 u32 value;
1578
1579 drm_modeset_lock_crtc(&dc->base, NULL);
1580
1581 if (!dc->base.state->active) {
1582 err = -EBUSY;
1583 goto unlock;
1584 }
1585
1586 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1587 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1588 tegra_dc_commit(dc);
1589
1590 drm_crtc_wait_one_vblank(&dc->base);
1591 drm_crtc_wait_one_vblank(&dc->base);
1592
1593 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1594 seq_printf(s, "%08x\n", value);
1595
1596 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1597
1598unlock:
1599 drm_modeset_unlock_crtc(&dc->base);
1600 return err;
1601}
1602
1603static int tegra_dc_show_stats(struct seq_file *s, void *data)
1604{
1605 struct drm_info_node *node = s->private;
1606 struct tegra_dc *dc = node->info_ent->data;
1607
1608 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1609 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1610 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1611 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1612
1613 return 0;
1614}
1615
1616static struct drm_info_list debugfs_files[] = {
1617 { "regs", tegra_dc_show_regs, 0, NULL },
1618 { "crc", tegra_dc_show_crc, 0, NULL },
1619 { "stats", tegra_dc_show_stats, 0, NULL },
1620};
1621
1622static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1623{
1624 unsigned int i;
1625 char *name;
1626 int err;
1627
1628 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1629 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1630 kfree(name);
1631
1632 if (!dc->debugfs)
1633 return -ENOMEM;
1634
1635 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1636 GFP_KERNEL);
1637 if (!dc->debugfs_files) {
1638 err = -ENOMEM;
1639 goto remove;
1640 }
1641
1642 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1643 dc->debugfs_files[i].data = dc;
1644
1645 err = drm_debugfs_create_files(dc->debugfs_files,
1646 ARRAY_SIZE(debugfs_files),
1647 dc->debugfs, minor);
1648 if (err < 0)
1649 goto free;
1650
1651 dc->minor = minor;
1652
1653 return 0;
1654
1655free:
1656 kfree(dc->debugfs_files);
1657 dc->debugfs_files = NULL;
1658remove:
1659 debugfs_remove(dc->debugfs);
1660 dc->debugfs = NULL;
1661
1662 return err;
1663}
1664
1665static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1666{
1667 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1668 dc->minor);
1669 dc->minor = NULL;
1670
1671 kfree(dc->debugfs_files);
1672 dc->debugfs_files = NULL;
1673
1674 debugfs_remove(dc->debugfs);
1675 dc->debugfs = NULL;
1676
1677 return 0;
1678}
1679
1680static int tegra_dc_init(struct host1x_client *client)
1681{
1682 struct drm_device *drm = dev_get_drvdata(client->parent);
1683 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1684 struct tegra_dc *dc = host1x_client_to_dc(client);
1685 struct tegra_drm *tegra = drm->dev_private;
1686 struct drm_plane *primary = NULL;
1687 struct drm_plane *cursor = NULL;
1688 u32 value;
1689 int err;
1690
1691 dc->syncpt = host1x_syncpt_request(dc->dev, flags);
1692 if (!dc->syncpt)
1693 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1694
1695 if (tegra->domain) {
1696 err = iommu_attach_device(tegra->domain, dc->dev);
1697 if (err < 0) {
1698 dev_err(dc->dev, "failed to attach to domain: %d\n",
1699 err);
1700 return err;
1701 }
1702
1703 dc->domain = tegra->domain;
1704 }
1705
1706 primary = tegra_dc_primary_plane_create(drm, dc);
1707 if (IS_ERR(primary)) {
1708 err = PTR_ERR(primary);
1709 goto cleanup;
1710 }
1711
1712 if (dc->soc->supports_cursor) {
1713 cursor = tegra_dc_cursor_plane_create(drm, dc);
1714 if (IS_ERR(cursor)) {
1715 err = PTR_ERR(cursor);
1716 goto cleanup;
1717 }
1718 }
1719
1720 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1721 &tegra_crtc_funcs, NULL);
1722 if (err < 0)
1723 goto cleanup;
1724
1725 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1726 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1727
1728 /*
1729 * Keep track of the minimum pitch alignment across all display
1730 * controllers.
1731 */
1732 if (dc->soc->pitch_align > tegra->pitch_align)
1733 tegra->pitch_align = dc->soc->pitch_align;
1734
1735 err = tegra_dc_rgb_init(drm, dc);
1736 if (err < 0 && err != -ENODEV) {
1737 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1738 goto cleanup;
1739 }
1740
1741 err = tegra_dc_add_planes(drm, dc);
1742 if (err < 0)
1743 goto cleanup;
1744
1745 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1746 err = tegra_dc_debugfs_init(dc, drm->primary);
1747 if (err < 0)
1748 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1749 }
1750
1751 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1752 dev_name(dc->dev), dc);
1753 if (err < 0) {
1754 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1755 err);
1756 goto cleanup;
1757 }
1758
1759 /* initialize display controller */
1760 if (dc->syncpt) {
1761 u32 syncpt = host1x_syncpt_id(dc->syncpt);
1762
1763 value = SYNCPT_CNTRL_NO_STALL;
1764 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1765
1766 value = SYNCPT_VSYNC_ENABLE | syncpt;
1767 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1768 }
1769
1770 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1771 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1772 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1773
1774 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1775 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1776 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1777
1778 /* initialize timer */
1779 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1780 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1781 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1782
1783 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1784 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1785 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1786
1787 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1788 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1789 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1790
1791 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1792 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1793 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1794
1795 if (dc->soc->supports_border_color)
1796 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1797
1798 tegra_dc_stats_reset(&dc->stats);
1799
1800 return 0;
1801
1802cleanup:
1803 if (cursor)
1804 drm_plane_cleanup(cursor);
1805
1806 if (primary)
1807 drm_plane_cleanup(primary);
1808
1809 if (tegra->domain) {
1810 iommu_detach_device(tegra->domain, dc->dev);
1811 dc->domain = NULL;
1812 }
1813
1814 return err;
1815}
1816
1817static int tegra_dc_exit(struct host1x_client *client)
1818{
1819 struct tegra_dc *dc = host1x_client_to_dc(client);
1820 int err;
1821
1822 devm_free_irq(dc->dev, dc->irq, dc);
1823
1824 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1825 err = tegra_dc_debugfs_exit(dc);
1826 if (err < 0)
1827 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1828 }
1829
1830 err = tegra_dc_rgb_exit(dc);
1831 if (err) {
1832 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1833 return err;
1834 }
1835
1836 if (dc->domain) {
1837 iommu_detach_device(dc->domain, dc->dev);
1838 dc->domain = NULL;
1839 }
1840
1841 host1x_syncpt_free(dc->syncpt);
1842
1843 return 0;
1844}
1845
1846static const struct host1x_client_ops dc_client_ops = {
1847 .init = tegra_dc_init,
1848 .exit = tegra_dc_exit,
1849};
1850
1851static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1852 .supports_border_color = true,
1853 .supports_interlacing = false,
1854 .supports_cursor = false,
1855 .supports_block_linear = false,
1856 .pitch_align = 8,
1857 .has_powergate = false,
1858};
1859
1860static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1861 .supports_border_color = true,
1862 .supports_interlacing = false,
1863 .supports_cursor = false,
1864 .supports_block_linear = false,
1865 .pitch_align = 8,
1866 .has_powergate = false,
1867};
1868
1869static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1870 .supports_border_color = true,
1871 .supports_interlacing = false,
1872 .supports_cursor = false,
1873 .supports_block_linear = false,
1874 .pitch_align = 64,
1875 .has_powergate = true,
1876};
1877
1878static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1879 .supports_border_color = false,
1880 .supports_interlacing = true,
1881 .supports_cursor = true,
1882 .supports_block_linear = true,
1883 .pitch_align = 64,
1884 .has_powergate = true,
1885};
1886
1887static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1888 .supports_border_color = false,
1889 .supports_interlacing = true,
1890 .supports_cursor = true,
1891 .supports_block_linear = true,
1892 .pitch_align = 64,
1893 .has_powergate = true,
1894};
1895
1896static const struct of_device_id tegra_dc_of_match[] = {
1897 {
1898 .compatible = "nvidia,tegra210-dc",
1899 .data = &tegra210_dc_soc_info,
1900 }, {
1901 .compatible = "nvidia,tegra124-dc",
1902 .data = &tegra124_dc_soc_info,
1903 }, {
1904 .compatible = "nvidia,tegra114-dc",
1905 .data = &tegra114_dc_soc_info,
1906 }, {
1907 .compatible = "nvidia,tegra30-dc",
1908 .data = &tegra30_dc_soc_info,
1909 }, {
1910 .compatible = "nvidia,tegra20-dc",
1911 .data = &tegra20_dc_soc_info,
1912 }, {
1913 /* sentinel */
1914 }
1915};
1916MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1917
1918static int tegra_dc_parse_dt(struct tegra_dc *dc)
1919{
1920 struct device_node *np;
1921 u32 value = 0;
1922 int err;
1923
1924 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1925 if (err < 0) {
1926 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1927
1928 /*
1929 * If the nvidia,head property isn't present, try to find the
1930 * correct head number by looking up the position of this
1931 * display controller's node within the device tree. Assuming
1932 * that the nodes are ordered properly in the DTS file and
1933 * that the translation into a flattened device tree blob
1934 * preserves that ordering this will actually yield the right
1935 * head number.
1936 *
1937 * If those assumptions don't hold, this will still work for
1938 * cases where only a single display controller is used.
1939 */
1940 for_each_matching_node(np, tegra_dc_of_match) {
1941 if (np == dc->dev->of_node) {
1942 of_node_put(np);
1943 break;
1944 }
1945
1946 value++;
1947 }
1948 }
1949
1950 dc->pipe = value;
1951
1952 return 0;
1953}
1954
1955static int tegra_dc_probe(struct platform_device *pdev)
1956{
1957 const struct of_device_id *id;
1958 struct resource *regs;
1959 struct tegra_dc *dc;
1960 int err;
1961
1962 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1963 if (!dc)
1964 return -ENOMEM;
1965
1966 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1967 if (!id)
1968 return -ENODEV;
1969
1970 spin_lock_init(&dc->lock);
1971 INIT_LIST_HEAD(&dc->list);
1972 dc->dev = &pdev->dev;
1973 dc->soc = id->data;
1974
1975 err = tegra_dc_parse_dt(dc);
1976 if (err < 0)
1977 return err;
1978
1979 dc->clk = devm_clk_get(&pdev->dev, NULL);
1980 if (IS_ERR(dc->clk)) {
1981 dev_err(&pdev->dev, "failed to get clock\n");
1982 return PTR_ERR(dc->clk);
1983 }
1984
1985 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1986 if (IS_ERR(dc->rst)) {
1987 dev_err(&pdev->dev, "failed to get reset\n");
1988 return PTR_ERR(dc->rst);
1989 }
1990
1991 if (dc->soc->has_powergate) {
1992 if (dc->pipe == 0)
1993 dc->powergate = TEGRA_POWERGATE_DIS;
1994 else
1995 dc->powergate = TEGRA_POWERGATE_DISB;
1996
1997 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1998 dc->rst);
1999 if (err < 0) {
2000 dev_err(&pdev->dev, "failed to power partition: %d\n",
2001 err);
2002 return err;
2003 }
2004 } else {
2005 err = clk_prepare_enable(dc->clk);
2006 if (err < 0) {
2007 dev_err(&pdev->dev, "failed to enable clock: %d\n",
2008 err);
2009 return err;
2010 }
2011
2012 err = reset_control_deassert(dc->rst);
2013 if (err < 0) {
2014 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
2015 err);
2016 return err;
2017 }
2018 }
2019
2020 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2021 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2022 if (IS_ERR(dc->regs))
2023 return PTR_ERR(dc->regs);
2024
2025 dc->irq = platform_get_irq(pdev, 0);
2026 if (dc->irq < 0) {
2027 dev_err(&pdev->dev, "failed to get IRQ\n");
2028 return -ENXIO;
2029 }
2030
2031 INIT_LIST_HEAD(&dc->client.list);
2032 dc->client.ops = &dc_client_ops;
2033 dc->client.dev = &pdev->dev;
2034
2035 err = tegra_dc_rgb_probe(dc);
2036 if (err < 0 && err != -ENODEV) {
2037 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2038 return err;
2039 }
2040
2041 err = host1x_client_register(&dc->client);
2042 if (err < 0) {
2043 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2044 err);
2045 return err;
2046 }
2047
2048 platform_set_drvdata(pdev, dc);
2049
2050 return 0;
2051}
2052
2053static int tegra_dc_remove(struct platform_device *pdev)
2054{
2055 struct tegra_dc *dc = platform_get_drvdata(pdev);
2056 int err;
2057
2058 err = host1x_client_unregister(&dc->client);
2059 if (err < 0) {
2060 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2061 err);
2062 return err;
2063 }
2064
2065 err = tegra_dc_rgb_remove(dc);
2066 if (err < 0) {
2067 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2068 return err;
2069 }
2070
2071 reset_control_assert(dc->rst);
2072
2073 if (dc->soc->has_powergate)
2074 tegra_powergate_power_off(dc->powergate);
2075
2076 clk_disable_unprepare(dc->clk);
2077
2078 return 0;
2079}
2080
2081struct platform_driver tegra_dc_driver = {
2082 .driver = {
2083 .name = "tegra-dc",
2084 .of_match_table = tegra_dc_of_match,
2085 },
2086 .probe = tegra_dc_probe,
2087 .remove = tegra_dc_remove,
2088};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/iommu.h>
11#include <linux/module.h>
12#include <linux/of_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/reset.h>
15
16#include <soc/tegra/pmc.h>
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_debugfs.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_plane_helper.h>
23#include <drm/drm_vblank.h>
24
25#include "dc.h"
26#include "drm.h"
27#include "gem.h"
28#include "hub.h"
29#include "plane.h"
30
31static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
32 struct drm_crtc_state *state);
33
34static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
35{
36 stats->frames = 0;
37 stats->vblank = 0;
38 stats->underflow = 0;
39 stats->overflow = 0;
40}
41
42/* Reads the active copy of a register. */
43static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
44{
45 u32 value;
46
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
48 value = tegra_dc_readl(dc, offset);
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
50
51 return value;
52}
53
54static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
55 unsigned int offset)
56{
57 if (offset >= 0x500 && offset <= 0x638) {
58 offset = 0x000 + (offset - 0x500);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x700 && offset <= 0x719) {
63 offset = 0x180 + (offset - 0x700);
64 return plane->offset + offset;
65 }
66
67 if (offset >= 0x800 && offset <= 0x839) {
68 offset = 0x1c0 + (offset - 0x800);
69 return plane->offset + offset;
70 }
71
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
73
74 return plane->offset + offset;
75}
76
77static inline u32 tegra_plane_readl(struct tegra_plane *plane,
78 unsigned int offset)
79{
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
81}
82
83static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
84 unsigned int offset)
85{
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
87}
88
89bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
90{
91 struct device_node *np = dc->dev->of_node;
92 struct of_phandle_iterator it;
93 int err;
94
95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
96 if (it.node == dev->of_node)
97 return true;
98
99 return false;
100}
101
102/*
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
105 * Latching happens mmediately if the display controller is in STOP mode or
106 * on the next frame boundary otherwise.
107 *
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
111 * into the ACTIVE copy, either immediately if the display controller is in
112 * STOP mode, or at the next frame boundary otherwise.
113 */
114void tegra_dc_commit(struct tegra_dc *dc)
115{
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
118}
119
120static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
121 unsigned int bpp)
122{
123 fixed20_12 outf = dfixed_init(out);
124 fixed20_12 inf = dfixed_init(in);
125 u32 dda_inc;
126 int max;
127
128 if (v)
129 max = 15;
130 else {
131 switch (bpp) {
132 case 2:
133 max = 8;
134 break;
135
136 default:
137 WARN_ON_ONCE(1);
138 fallthrough;
139 case 4:
140 max = 4;
141 break;
142 }
143 }
144
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
146 inf.full -= dfixed_const(1);
147
148 dda_inc = dfixed_div(inf, outf);
149 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
150
151 return dda_inc;
152}
153
154static inline u32 compute_initial_dda(unsigned int in)
155{
156 fixed20_12 inf = dfixed_init(in);
157 return dfixed_frac(inf);
158}
159
160static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
161{
162 u32 background[3] = {
163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
166 };
167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
168 BLEND_COLOR_KEY_NONE;
169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
170 struct tegra_plane_state *state;
171 u32 blending[2];
172 unsigned int i;
173
174 /* disable blending for non-overlapping case */
175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
177
178 state = to_tegra_plane_state(plane->base.state);
179
180 if (state->opaque) {
181 /*
182 * Since custom fix-weight blending isn't utilized and weight
183 * of top window is set to max, we can enforce dependent
184 * blending which in this case results in transparent bottom
185 * window if top window is opaque and if top window enables
186 * alpha blending, then bottom window is getting alpha value
187 * of 1 minus the sum of alpha components of the overlapping
188 * plane.
189 */
190 background[0] |= BLEND_CONTROL_DEPENDENT;
191 background[1] |= BLEND_CONTROL_DEPENDENT;
192
193 /*
194 * The region where three windows overlap is the intersection
195 * of the two regions where two windows overlap. It contributes
196 * to the area if all of the windows on top of it have an alpha
197 * component.
198 */
199 switch (state->base.normalized_zpos) {
200 case 0:
201 if (state->blending[0].alpha &&
202 state->blending[1].alpha)
203 background[2] |= BLEND_CONTROL_DEPENDENT;
204 break;
205
206 case 1:
207 background[2] |= BLEND_CONTROL_DEPENDENT;
208 break;
209 }
210 } else {
211 /*
212 * Enable alpha blending if pixel format has an alpha
213 * component.
214 */
215 foreground |= BLEND_CONTROL_ALPHA;
216
217 /*
218 * If any of the windows on top of this window is opaque, it
219 * will completely conceal this window within that area. If
220 * top window has an alpha component, it is blended over the
221 * bottom window.
222 */
223 for (i = 0; i < 2; i++) {
224 if (state->blending[i].alpha &&
225 state->blending[i].top)
226 background[i] |= BLEND_CONTROL_DEPENDENT;
227 }
228
229 switch (state->base.normalized_zpos) {
230 case 0:
231 if (state->blending[0].alpha &&
232 state->blending[1].alpha)
233 background[2] |= BLEND_CONTROL_DEPENDENT;
234 break;
235
236 case 1:
237 /*
238 * When both middle and topmost windows have an alpha,
239 * these windows a mixed together and then the result
240 * is blended over the bottom window.
241 */
242 if (state->blending[0].alpha &&
243 state->blending[0].top)
244 background[2] |= BLEND_CONTROL_ALPHA;
245
246 if (state->blending[1].alpha &&
247 state->blending[1].top)
248 background[2] |= BLEND_CONTROL_ALPHA;
249 break;
250 }
251 }
252
253 switch (state->base.normalized_zpos) {
254 case 0:
255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
258 break;
259
260 case 1:
261 /*
262 * If window B / C is topmost, then X / Y registers are
263 * matching the order of blending[...] state indices,
264 * otherwise a swap is required.
265 */
266 if (!state->blending[0].top && state->blending[1].top) {
267 blending[0] = foreground;
268 blending[1] = background[1];
269 } else {
270 blending[0] = background[0];
271 blending[1] = foreground;
272 }
273
274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
277 break;
278
279 case 2:
280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
283 break;
284 }
285}
286
287static void tegra_plane_setup_blending(struct tegra_plane *plane,
288 const struct tegra_dc_window *window)
289{
290 u32 value;
291
292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
296
297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
301
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
304}
305
306static bool
307tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
308 const struct tegra_dc_window *window)
309{
310 struct tegra_dc *dc = plane->dc;
311
312 if (window->src.w == window->dst.w)
313 return false;
314
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
316 return false;
317
318 return true;
319}
320
321static bool
322tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
323 const struct tegra_dc_window *window)
324{
325 struct tegra_dc *dc = plane->dc;
326
327 if (window->src.h == window->dst.h)
328 return false;
329
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
331 return false;
332
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
334 return false;
335
336 return true;
337}
338
339static void tegra_dc_setup_window(struct tegra_plane *plane,
340 const struct tegra_dc_window *window)
341{
342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
343 struct tegra_dc *dc = plane->dc;
344 bool yuv, planar;
345 u32 value;
346
347 /*
348 * For YUV planar modes, the number of bytes per pixel takes into
349 * account only the luma component and therefore is 1.
350 */
351 yuv = tegra_plane_format_is_yuv(window->format, &planar);
352 if (!yuv)
353 bpp = window->bits_per_pixel / 8;
354 else
355 bpp = planar ? 1 : 2;
356
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
359
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
361 tegra_plane_writel(plane, value, DC_WIN_POSITION);
362
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
364 tegra_plane_writel(plane, value, DC_WIN_SIZE);
365
366 h_offset = window->src.x * bpp;
367 v_offset = window->src.y;
368 h_size = window->src.w * bpp;
369 v_size = window->src.h;
370
371 if (window->reflect_x)
372 h_offset += (window->src.w - 1) * bpp;
373
374 if (window->reflect_y)
375 v_offset += window->src.h - 1;
376
377 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
378 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
379
380 /*
381 * For DDA computations the number of bytes per pixel for YUV planar
382 * modes needs to take into account all Y, U and V components.
383 */
384 if (yuv && planar)
385 bpp = 2;
386
387 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
388 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
389
390 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
391 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
392
393 h_dda = compute_initial_dda(window->src.x);
394 v_dda = compute_initial_dda(window->src.y);
395
396 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
397 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
398
399 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
400 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
401
402 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
403
404 if (yuv && planar) {
405 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
406 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
407 value = window->stride[1] << 16 | window->stride[0];
408 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
409 } else {
410 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
411 }
412
413 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
414 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
415
416 if (dc->soc->supports_block_linear) {
417 unsigned long height = window->tiling.value;
418
419 switch (window->tiling.mode) {
420 case TEGRA_BO_TILING_MODE_PITCH:
421 value = DC_WINBUF_SURFACE_KIND_PITCH;
422 break;
423
424 case TEGRA_BO_TILING_MODE_TILED:
425 value = DC_WINBUF_SURFACE_KIND_TILED;
426 break;
427
428 case TEGRA_BO_TILING_MODE_BLOCK:
429 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
430 DC_WINBUF_SURFACE_KIND_BLOCK;
431 break;
432 }
433
434 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
435 } else {
436 switch (window->tiling.mode) {
437 case TEGRA_BO_TILING_MODE_PITCH:
438 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
439 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
440 break;
441
442 case TEGRA_BO_TILING_MODE_TILED:
443 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
444 DC_WIN_BUFFER_ADDR_MODE_TILE;
445 break;
446
447 case TEGRA_BO_TILING_MODE_BLOCK:
448 /*
449 * No need to handle this here because ->atomic_check
450 * will already have filtered it out.
451 */
452 break;
453 }
454
455 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
456 }
457
458 value = WIN_ENABLE;
459
460 if (yuv) {
461 /* setup default colorspace conversion coefficients */
462 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
463 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
464 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
465 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
466 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
467 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
468 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
469 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
470
471 value |= CSC_ENABLE;
472 } else if (window->bits_per_pixel < 24) {
473 value |= COLOR_EXPAND;
474 }
475
476 if (window->reflect_x)
477 value |= H_DIRECTION;
478
479 if (window->reflect_y)
480 value |= V_DIRECTION;
481
482 if (tegra_plane_use_horizontal_filtering(plane, window)) {
483 /*
484 * Enable horizontal 6-tap filter and set filtering
485 * coefficients to the default values defined in TRM.
486 */
487 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
488 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
489 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
490 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
491 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
492 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
493 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
494 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
495 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
496 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
497 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
498 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
499 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
500 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
501 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
502 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
503
504 value |= H_FILTER;
505 }
506
507 if (tegra_plane_use_vertical_filtering(plane, window)) {
508 unsigned int i, k;
509
510 /*
511 * Enable vertical 2-tap filter and set filtering
512 * coefficients to the default values defined in TRM.
513 */
514 for (i = 0, k = 128; i < 16; i++, k -= 8)
515 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
516
517 value |= V_FILTER;
518 }
519
520 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
521
522 if (dc->soc->has_legacy_blending)
523 tegra_plane_setup_blending_legacy(plane);
524 else
525 tegra_plane_setup_blending(plane, window);
526}
527
528static const u32 tegra20_primary_formats[] = {
529 DRM_FORMAT_ARGB4444,
530 DRM_FORMAT_ARGB1555,
531 DRM_FORMAT_RGB565,
532 DRM_FORMAT_RGBA5551,
533 DRM_FORMAT_ABGR8888,
534 DRM_FORMAT_ARGB8888,
535 /* non-native formats */
536 DRM_FORMAT_XRGB1555,
537 DRM_FORMAT_RGBX5551,
538 DRM_FORMAT_XBGR8888,
539 DRM_FORMAT_XRGB8888,
540};
541
542static const u64 tegra20_modifiers[] = {
543 DRM_FORMAT_MOD_LINEAR,
544 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
545 DRM_FORMAT_MOD_INVALID
546};
547
548static const u32 tegra114_primary_formats[] = {
549 DRM_FORMAT_ARGB4444,
550 DRM_FORMAT_ARGB1555,
551 DRM_FORMAT_RGB565,
552 DRM_FORMAT_RGBA5551,
553 DRM_FORMAT_ABGR8888,
554 DRM_FORMAT_ARGB8888,
555 /* new on Tegra114 */
556 DRM_FORMAT_ABGR4444,
557 DRM_FORMAT_ABGR1555,
558 DRM_FORMAT_BGRA5551,
559 DRM_FORMAT_XRGB1555,
560 DRM_FORMAT_RGBX5551,
561 DRM_FORMAT_XBGR1555,
562 DRM_FORMAT_BGRX5551,
563 DRM_FORMAT_BGR565,
564 DRM_FORMAT_BGRA8888,
565 DRM_FORMAT_RGBA8888,
566 DRM_FORMAT_XRGB8888,
567 DRM_FORMAT_XBGR8888,
568};
569
570static const u32 tegra124_primary_formats[] = {
571 DRM_FORMAT_ARGB4444,
572 DRM_FORMAT_ARGB1555,
573 DRM_FORMAT_RGB565,
574 DRM_FORMAT_RGBA5551,
575 DRM_FORMAT_ABGR8888,
576 DRM_FORMAT_ARGB8888,
577 /* new on Tegra114 */
578 DRM_FORMAT_ABGR4444,
579 DRM_FORMAT_ABGR1555,
580 DRM_FORMAT_BGRA5551,
581 DRM_FORMAT_XRGB1555,
582 DRM_FORMAT_RGBX5551,
583 DRM_FORMAT_XBGR1555,
584 DRM_FORMAT_BGRX5551,
585 DRM_FORMAT_BGR565,
586 DRM_FORMAT_BGRA8888,
587 DRM_FORMAT_RGBA8888,
588 DRM_FORMAT_XRGB8888,
589 DRM_FORMAT_XBGR8888,
590 /* new on Tegra124 */
591 DRM_FORMAT_RGBX8888,
592 DRM_FORMAT_BGRX8888,
593};
594
595static const u64 tegra124_modifiers[] = {
596 DRM_FORMAT_MOD_LINEAR,
597 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
598 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
599 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
600 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
601 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
602 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
603 DRM_FORMAT_MOD_INVALID
604};
605
606static int tegra_plane_atomic_check(struct drm_plane *plane,
607 struct drm_plane_state *state)
608{
609 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
610 unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
611 DRM_MODE_REFLECT_X |
612 DRM_MODE_REFLECT_Y;
613 unsigned int rotation = state->rotation;
614 struct tegra_bo_tiling *tiling = &plane_state->tiling;
615 struct tegra_plane *tegra = to_tegra_plane(plane);
616 struct tegra_dc *dc = to_tegra_dc(state->crtc);
617 int err;
618
619 /* no need for further checks if the plane is being disabled */
620 if (!state->crtc)
621 return 0;
622
623 err = tegra_plane_format(state->fb->format->format,
624 &plane_state->format,
625 &plane_state->swap);
626 if (err < 0)
627 return err;
628
629 /*
630 * Tegra20 and Tegra30 are special cases here because they support
631 * only variants of specific formats with an alpha component, but not
632 * the corresponding opaque formats. However, the opaque formats can
633 * be emulated by disabling alpha blending for the plane.
634 */
635 if (dc->soc->has_legacy_blending) {
636 err = tegra_plane_setup_legacy_state(tegra, plane_state);
637 if (err < 0)
638 return err;
639 }
640
641 err = tegra_fb_get_tiling(state->fb, tiling);
642 if (err < 0)
643 return err;
644
645 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
646 !dc->soc->supports_block_linear) {
647 DRM_ERROR("hardware doesn't support block linear mode\n");
648 return -EINVAL;
649 }
650
651 /*
652 * Older userspace used custom BO flag in order to specify the Y
653 * reflection, while modern userspace uses the generic DRM rotation
654 * property in order to achieve the same result. The legacy BO flag
655 * duplicates the DRM rotation property when both are set.
656 */
657 if (tegra_fb_is_bottom_up(state->fb))
658 rotation |= DRM_MODE_REFLECT_Y;
659
660 rotation = drm_rotation_simplify(rotation, supported_rotation);
661
662 if (rotation & DRM_MODE_REFLECT_X)
663 plane_state->reflect_x = true;
664 else
665 plane_state->reflect_x = false;
666
667 if (rotation & DRM_MODE_REFLECT_Y)
668 plane_state->reflect_y = true;
669 else
670 plane_state->reflect_y = false;
671
672 /*
673 * Tegra doesn't support different strides for U and V planes so we
674 * error out if the user tries to display a framebuffer with such a
675 * configuration.
676 */
677 if (state->fb->format->num_planes > 2) {
678 if (state->fb->pitches[2] != state->fb->pitches[1]) {
679 DRM_ERROR("unsupported UV-plane configuration\n");
680 return -EINVAL;
681 }
682 }
683
684 err = tegra_plane_state_add(tegra, state);
685 if (err < 0)
686 return err;
687
688 return 0;
689}
690
691static void tegra_plane_atomic_disable(struct drm_plane *plane,
692 struct drm_plane_state *old_state)
693{
694 struct tegra_plane *p = to_tegra_plane(plane);
695 u32 value;
696
697 /* rien ne va plus */
698 if (!old_state || !old_state->crtc)
699 return;
700
701 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
702 value &= ~WIN_ENABLE;
703 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
704}
705
706static void tegra_plane_atomic_update(struct drm_plane *plane,
707 struct drm_plane_state *old_state)
708{
709 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
710 struct drm_framebuffer *fb = plane->state->fb;
711 struct tegra_plane *p = to_tegra_plane(plane);
712 struct tegra_dc_window window;
713 unsigned int i;
714
715 /* rien ne va plus */
716 if (!plane->state->crtc || !plane->state->fb)
717 return;
718
719 if (!plane->state->visible)
720 return tegra_plane_atomic_disable(plane, old_state);
721
722 memset(&window, 0, sizeof(window));
723 window.src.x = plane->state->src.x1 >> 16;
724 window.src.y = plane->state->src.y1 >> 16;
725 window.src.w = drm_rect_width(&plane->state->src) >> 16;
726 window.src.h = drm_rect_height(&plane->state->src) >> 16;
727 window.dst.x = plane->state->dst.x1;
728 window.dst.y = plane->state->dst.y1;
729 window.dst.w = drm_rect_width(&plane->state->dst);
730 window.dst.h = drm_rect_height(&plane->state->dst);
731 window.bits_per_pixel = fb->format->cpp[0] * 8;
732 window.reflect_x = state->reflect_x;
733 window.reflect_y = state->reflect_y;
734
735 /* copy from state */
736 window.zpos = plane->state->normalized_zpos;
737 window.tiling = state->tiling;
738 window.format = state->format;
739 window.swap = state->swap;
740
741 for (i = 0; i < fb->format->num_planes; i++) {
742 window.base[i] = state->iova[i] + fb->offsets[i];
743
744 /*
745 * Tegra uses a shared stride for UV planes. Framebuffers are
746 * already checked for this in the tegra_plane_atomic_check()
747 * function, so it's safe to ignore the V-plane pitch here.
748 */
749 if (i < 2)
750 window.stride[i] = fb->pitches[i];
751 }
752
753 tegra_dc_setup_window(p, &window);
754}
755
756static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
757 .prepare_fb = tegra_plane_prepare_fb,
758 .cleanup_fb = tegra_plane_cleanup_fb,
759 .atomic_check = tegra_plane_atomic_check,
760 .atomic_disable = tegra_plane_atomic_disable,
761 .atomic_update = tegra_plane_atomic_update,
762};
763
764static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
765{
766 /*
767 * Ideally this would use drm_crtc_mask(), but that would require the
768 * CRTC to already be in the mode_config's list of CRTCs. However, it
769 * will only be added to that list in the drm_crtc_init_with_planes()
770 * (in tegra_dc_init()), which in turn requires registration of these
771 * planes. So we have ourselves a nice little chicken and egg problem
772 * here.
773 *
774 * We work around this by manually creating the mask from the number
775 * of CRTCs that have been registered, and should therefore always be
776 * the same as drm_crtc_index() after registration.
777 */
778 return 1 << drm->mode_config.num_crtc;
779}
780
781static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
782 struct tegra_dc *dc)
783{
784 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
785 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
786 struct tegra_plane *plane;
787 unsigned int num_formats;
788 const u64 *modifiers;
789 const u32 *formats;
790 int err;
791
792 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
793 if (!plane)
794 return ERR_PTR(-ENOMEM);
795
796 /* Always use window A as primary window */
797 plane->offset = 0xa00;
798 plane->index = 0;
799 plane->dc = dc;
800
801 num_formats = dc->soc->num_primary_formats;
802 formats = dc->soc->primary_formats;
803 modifiers = dc->soc->modifiers;
804
805 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
806 &tegra_plane_funcs, formats,
807 num_formats, modifiers, type, NULL);
808 if (err < 0) {
809 kfree(plane);
810 return ERR_PTR(err);
811 }
812
813 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
814 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
815
816 err = drm_plane_create_rotation_property(&plane->base,
817 DRM_MODE_ROTATE_0,
818 DRM_MODE_ROTATE_0 |
819 DRM_MODE_ROTATE_180 |
820 DRM_MODE_REFLECT_X |
821 DRM_MODE_REFLECT_Y);
822 if (err < 0)
823 dev_err(dc->dev, "failed to create rotation property: %d\n",
824 err);
825
826 return &plane->base;
827}
828
829static const u32 tegra_cursor_plane_formats[] = {
830 DRM_FORMAT_RGBA8888,
831};
832
833static int tegra_cursor_atomic_check(struct drm_plane *plane,
834 struct drm_plane_state *state)
835{
836 struct tegra_plane *tegra = to_tegra_plane(plane);
837 int err;
838
839 /* no need for further checks if the plane is being disabled */
840 if (!state->crtc)
841 return 0;
842
843 /* scaling not supported for cursor */
844 if ((state->src_w >> 16 != state->crtc_w) ||
845 (state->src_h >> 16 != state->crtc_h))
846 return -EINVAL;
847
848 /* only square cursors supported */
849 if (state->src_w != state->src_h)
850 return -EINVAL;
851
852 if (state->crtc_w != 32 && state->crtc_w != 64 &&
853 state->crtc_w != 128 && state->crtc_w != 256)
854 return -EINVAL;
855
856 err = tegra_plane_state_add(tegra, state);
857 if (err < 0)
858 return err;
859
860 return 0;
861}
862
863static void tegra_cursor_atomic_update(struct drm_plane *plane,
864 struct drm_plane_state *old_state)
865{
866 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
867 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
868 u32 value = CURSOR_CLIP_DISPLAY;
869
870 /* rien ne va plus */
871 if (!plane->state->crtc || !plane->state->fb)
872 return;
873
874 switch (plane->state->crtc_w) {
875 case 32:
876 value |= CURSOR_SIZE_32x32;
877 break;
878
879 case 64:
880 value |= CURSOR_SIZE_64x64;
881 break;
882
883 case 128:
884 value |= CURSOR_SIZE_128x128;
885 break;
886
887 case 256:
888 value |= CURSOR_SIZE_256x256;
889 break;
890
891 default:
892 WARN(1, "cursor size %ux%u not supported\n",
893 plane->state->crtc_w, plane->state->crtc_h);
894 return;
895 }
896
897 value |= (state->iova[0] >> 10) & 0x3fffff;
898 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
899
900#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
901 value = (state->iova[0] >> 32) & 0x3;
902 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
903#endif
904
905 /* enable cursor and set blend mode */
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
907 value |= CURSOR_ENABLE;
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
909
910 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
911 value &= ~CURSOR_DST_BLEND_MASK;
912 value &= ~CURSOR_SRC_BLEND_MASK;
913 value |= CURSOR_MODE_NORMAL;
914 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
915 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
916 value |= CURSOR_ALPHA;
917 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
918
919 /* position the cursor */
920 value = (plane->state->crtc_y & 0x3fff) << 16 |
921 (plane->state->crtc_x & 0x3fff);
922 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
923}
924
925static void tegra_cursor_atomic_disable(struct drm_plane *plane,
926 struct drm_plane_state *old_state)
927{
928 struct tegra_dc *dc;
929 u32 value;
930
931 /* rien ne va plus */
932 if (!old_state || !old_state->crtc)
933 return;
934
935 dc = to_tegra_dc(old_state->crtc);
936
937 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
938 value &= ~CURSOR_ENABLE;
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
940}
941
942static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
943 .prepare_fb = tegra_plane_prepare_fb,
944 .cleanup_fb = tegra_plane_cleanup_fb,
945 .atomic_check = tegra_cursor_atomic_check,
946 .atomic_update = tegra_cursor_atomic_update,
947 .atomic_disable = tegra_cursor_atomic_disable,
948};
949
950static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
951 struct tegra_dc *dc)
952{
953 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
954 struct tegra_plane *plane;
955 unsigned int num_formats;
956 const u32 *formats;
957 int err;
958
959 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
960 if (!plane)
961 return ERR_PTR(-ENOMEM);
962
963 /*
964 * This index is kind of fake. The cursor isn't a regular plane, but
965 * its update and activation request bits in DC_CMD_STATE_CONTROL do
966 * use the same programming. Setting this fake index here allows the
967 * code in tegra_add_plane_state() to do the right thing without the
968 * need to special-casing the cursor plane.
969 */
970 plane->index = 6;
971 plane->dc = dc;
972
973 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
974 formats = tegra_cursor_plane_formats;
975
976 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
977 &tegra_plane_funcs, formats,
978 num_formats, NULL,
979 DRM_PLANE_TYPE_CURSOR, NULL);
980 if (err < 0) {
981 kfree(plane);
982 return ERR_PTR(err);
983 }
984
985 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
986 drm_plane_create_zpos_immutable_property(&plane->base, 255);
987
988 return &plane->base;
989}
990
991static const u32 tegra20_overlay_formats[] = {
992 DRM_FORMAT_ARGB4444,
993 DRM_FORMAT_ARGB1555,
994 DRM_FORMAT_RGB565,
995 DRM_FORMAT_RGBA5551,
996 DRM_FORMAT_ABGR8888,
997 DRM_FORMAT_ARGB8888,
998 /* non-native formats */
999 DRM_FORMAT_XRGB1555,
1000 DRM_FORMAT_RGBX5551,
1001 DRM_FORMAT_XBGR8888,
1002 DRM_FORMAT_XRGB8888,
1003 /* planar formats */
1004 DRM_FORMAT_UYVY,
1005 DRM_FORMAT_YUYV,
1006 DRM_FORMAT_YUV420,
1007 DRM_FORMAT_YUV422,
1008};
1009
1010static const u32 tegra114_overlay_formats[] = {
1011 DRM_FORMAT_ARGB4444,
1012 DRM_FORMAT_ARGB1555,
1013 DRM_FORMAT_RGB565,
1014 DRM_FORMAT_RGBA5551,
1015 DRM_FORMAT_ABGR8888,
1016 DRM_FORMAT_ARGB8888,
1017 /* new on Tegra114 */
1018 DRM_FORMAT_ABGR4444,
1019 DRM_FORMAT_ABGR1555,
1020 DRM_FORMAT_BGRA5551,
1021 DRM_FORMAT_XRGB1555,
1022 DRM_FORMAT_RGBX5551,
1023 DRM_FORMAT_XBGR1555,
1024 DRM_FORMAT_BGRX5551,
1025 DRM_FORMAT_BGR565,
1026 DRM_FORMAT_BGRA8888,
1027 DRM_FORMAT_RGBA8888,
1028 DRM_FORMAT_XRGB8888,
1029 DRM_FORMAT_XBGR8888,
1030 /* planar formats */
1031 DRM_FORMAT_UYVY,
1032 DRM_FORMAT_YUYV,
1033 DRM_FORMAT_YUV420,
1034 DRM_FORMAT_YUV422,
1035};
1036
1037static const u32 tegra124_overlay_formats[] = {
1038 DRM_FORMAT_ARGB4444,
1039 DRM_FORMAT_ARGB1555,
1040 DRM_FORMAT_RGB565,
1041 DRM_FORMAT_RGBA5551,
1042 DRM_FORMAT_ABGR8888,
1043 DRM_FORMAT_ARGB8888,
1044 /* new on Tegra114 */
1045 DRM_FORMAT_ABGR4444,
1046 DRM_FORMAT_ABGR1555,
1047 DRM_FORMAT_BGRA5551,
1048 DRM_FORMAT_XRGB1555,
1049 DRM_FORMAT_RGBX5551,
1050 DRM_FORMAT_XBGR1555,
1051 DRM_FORMAT_BGRX5551,
1052 DRM_FORMAT_BGR565,
1053 DRM_FORMAT_BGRA8888,
1054 DRM_FORMAT_RGBA8888,
1055 DRM_FORMAT_XRGB8888,
1056 DRM_FORMAT_XBGR8888,
1057 /* new on Tegra124 */
1058 DRM_FORMAT_RGBX8888,
1059 DRM_FORMAT_BGRX8888,
1060 /* planar formats */
1061 DRM_FORMAT_UYVY,
1062 DRM_FORMAT_YUYV,
1063 DRM_FORMAT_YUV420,
1064 DRM_FORMAT_YUV422,
1065};
1066
1067static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1068 struct tegra_dc *dc,
1069 unsigned int index,
1070 bool cursor)
1071{
1072 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1073 struct tegra_plane *plane;
1074 unsigned int num_formats;
1075 enum drm_plane_type type;
1076 const u32 *formats;
1077 int err;
1078
1079 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1080 if (!plane)
1081 return ERR_PTR(-ENOMEM);
1082
1083 plane->offset = 0xa00 + 0x200 * index;
1084 plane->index = index;
1085 plane->dc = dc;
1086
1087 num_formats = dc->soc->num_overlay_formats;
1088 formats = dc->soc->overlay_formats;
1089
1090 if (!cursor)
1091 type = DRM_PLANE_TYPE_OVERLAY;
1092 else
1093 type = DRM_PLANE_TYPE_CURSOR;
1094
1095 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1096 &tegra_plane_funcs, formats,
1097 num_formats, NULL, type, NULL);
1098 if (err < 0) {
1099 kfree(plane);
1100 return ERR_PTR(err);
1101 }
1102
1103 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1104 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1105
1106 err = drm_plane_create_rotation_property(&plane->base,
1107 DRM_MODE_ROTATE_0,
1108 DRM_MODE_ROTATE_0 |
1109 DRM_MODE_ROTATE_180 |
1110 DRM_MODE_REFLECT_X |
1111 DRM_MODE_REFLECT_Y);
1112 if (err < 0)
1113 dev_err(dc->dev, "failed to create rotation property: %d\n",
1114 err);
1115
1116 return &plane->base;
1117}
1118
1119static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1120 struct tegra_dc *dc)
1121{
1122 struct drm_plane *plane, *primary = NULL;
1123 unsigned int i, j;
1124
1125 for (i = 0; i < dc->soc->num_wgrps; i++) {
1126 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1127
1128 if (wgrp->dc == dc->pipe) {
1129 for (j = 0; j < wgrp->num_windows; j++) {
1130 unsigned int index = wgrp->windows[j];
1131
1132 plane = tegra_shared_plane_create(drm, dc,
1133 wgrp->index,
1134 index);
1135 if (IS_ERR(plane))
1136 return plane;
1137
1138 /*
1139 * Choose the first shared plane owned by this
1140 * head as the primary plane.
1141 */
1142 if (!primary) {
1143 plane->type = DRM_PLANE_TYPE_PRIMARY;
1144 primary = plane;
1145 }
1146 }
1147 }
1148 }
1149
1150 return primary;
1151}
1152
1153static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1154 struct tegra_dc *dc)
1155{
1156 struct drm_plane *planes[2], *primary;
1157 unsigned int planes_num;
1158 unsigned int i;
1159 int err;
1160
1161 primary = tegra_primary_plane_create(drm, dc);
1162 if (IS_ERR(primary))
1163 return primary;
1164
1165 if (dc->soc->supports_cursor)
1166 planes_num = 2;
1167 else
1168 planes_num = 1;
1169
1170 for (i = 0; i < planes_num; i++) {
1171 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1172 false);
1173 if (IS_ERR(planes[i])) {
1174 err = PTR_ERR(planes[i]);
1175
1176 while (i--)
1177 tegra_plane_funcs.destroy(planes[i]);
1178
1179 tegra_plane_funcs.destroy(primary);
1180 return ERR_PTR(err);
1181 }
1182 }
1183
1184 return primary;
1185}
1186
1187static void tegra_dc_destroy(struct drm_crtc *crtc)
1188{
1189 drm_crtc_cleanup(crtc);
1190}
1191
1192static void tegra_crtc_reset(struct drm_crtc *crtc)
1193{
1194 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1195
1196 if (crtc->state)
1197 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1198
1199 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1200}
1201
1202static struct drm_crtc_state *
1203tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1204{
1205 struct tegra_dc_state *state = to_dc_state(crtc->state);
1206 struct tegra_dc_state *copy;
1207
1208 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1209 if (!copy)
1210 return NULL;
1211
1212 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1213 copy->clk = state->clk;
1214 copy->pclk = state->pclk;
1215 copy->div = state->div;
1216 copy->planes = state->planes;
1217
1218 return ©->base;
1219}
1220
1221static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1222 struct drm_crtc_state *state)
1223{
1224 __drm_atomic_helper_crtc_destroy_state(state);
1225 kfree(state);
1226}
1227
1228#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1229
1230static const struct debugfs_reg32 tegra_dc_regs[] = {
1231 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1232 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1233 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1234 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1235 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1236 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1237 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1238 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1239 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1240 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1241 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1242 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1243 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1244 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1245 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1246 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1247 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1248 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1249 DEBUGFS_REG32(DC_CMD_INT_MASK),
1250 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1251 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1252 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1253 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1254 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1255 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1256 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1257 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1258 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1259 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1260 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1261 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1262 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1263 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1264 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1265 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1266 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1267 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1268 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1269 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1270 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1271 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1272 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1273 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1274 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1275 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1276 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1277 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1278 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1279 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1280 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1281 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1282 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1283 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1284 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1285 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1286 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1287 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1288 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1289 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1290 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1291 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1292 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1293 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1294 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1295 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1296 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1297 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1298 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1299 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1300 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1301 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1302 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1303 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1304 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1305 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1306 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1307 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1308 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1309 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1310 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1311 DEBUGFS_REG32(DC_DISP_ACTIVE),
1312 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1313 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1314 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1315 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1316 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1317 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1318 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1319 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1320 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1321 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1322 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1323 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1324 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1325 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1326 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1327 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1328 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1329 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1330 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1331 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1332 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1333 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1334 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1335 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1336 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1337 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1338 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1339 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1340 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1341 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1342 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1343 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1344 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1345 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1346 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1347 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1348 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1349 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1350 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1351 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1352 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1353 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1354 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1355 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1356 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1357 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1358 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1359 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1360 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1361 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1362 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1363 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1364 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1365 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1366 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1367 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1368 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1369 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1370 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1371 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1372 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1373 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1374 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1375 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1376 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1377 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1378 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1379 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1380 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1381 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1382 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1383 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1384 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1385 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1386 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1387 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1388 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1389 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1390 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1391 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1392 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1393 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1394 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1395 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1396 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1397 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1398 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1399 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1400 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1401 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1402 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1403 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1404 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1405 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1406 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1407 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1408 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1409 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1410 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1411 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1412 DEBUGFS_REG32(DC_WIN_POSITION),
1413 DEBUGFS_REG32(DC_WIN_SIZE),
1414 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1415 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1416 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1417 DEBUGFS_REG32(DC_WIN_DDA_INC),
1418 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1419 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1420 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1421 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1422 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1423 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1424 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1425 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1426 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1427 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1428 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1429 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1430 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1431 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1432 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1433 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1434 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1435 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1436 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1437 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1438 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1439 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1440 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1441 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1442 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1443};
1444
1445static int tegra_dc_show_regs(struct seq_file *s, void *data)
1446{
1447 struct drm_info_node *node = s->private;
1448 struct tegra_dc *dc = node->info_ent->data;
1449 unsigned int i;
1450 int err = 0;
1451
1452 drm_modeset_lock(&dc->base.mutex, NULL);
1453
1454 if (!dc->base.state->active) {
1455 err = -EBUSY;
1456 goto unlock;
1457 }
1458
1459 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1460 unsigned int offset = tegra_dc_regs[i].offset;
1461
1462 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1463 offset, tegra_dc_readl(dc, offset));
1464 }
1465
1466unlock:
1467 drm_modeset_unlock(&dc->base.mutex);
1468 return err;
1469}
1470
1471static int tegra_dc_show_crc(struct seq_file *s, void *data)
1472{
1473 struct drm_info_node *node = s->private;
1474 struct tegra_dc *dc = node->info_ent->data;
1475 int err = 0;
1476 u32 value;
1477
1478 drm_modeset_lock(&dc->base.mutex, NULL);
1479
1480 if (!dc->base.state->active) {
1481 err = -EBUSY;
1482 goto unlock;
1483 }
1484
1485 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1486 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1487 tegra_dc_commit(dc);
1488
1489 drm_crtc_wait_one_vblank(&dc->base);
1490 drm_crtc_wait_one_vblank(&dc->base);
1491
1492 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1493 seq_printf(s, "%08x\n", value);
1494
1495 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1496
1497unlock:
1498 drm_modeset_unlock(&dc->base.mutex);
1499 return err;
1500}
1501
1502static int tegra_dc_show_stats(struct seq_file *s, void *data)
1503{
1504 struct drm_info_node *node = s->private;
1505 struct tegra_dc *dc = node->info_ent->data;
1506
1507 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1508 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1509 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1510 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1511
1512 return 0;
1513}
1514
1515static struct drm_info_list debugfs_files[] = {
1516 { "regs", tegra_dc_show_regs, 0, NULL },
1517 { "crc", tegra_dc_show_crc, 0, NULL },
1518 { "stats", tegra_dc_show_stats, 0, NULL },
1519};
1520
1521static int tegra_dc_late_register(struct drm_crtc *crtc)
1522{
1523 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1524 struct drm_minor *minor = crtc->dev->primary;
1525 struct dentry *root;
1526 struct tegra_dc *dc = to_tegra_dc(crtc);
1527
1528#ifdef CONFIG_DEBUG_FS
1529 root = crtc->debugfs_entry;
1530#else
1531 root = NULL;
1532#endif
1533
1534 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1535 GFP_KERNEL);
1536 if (!dc->debugfs_files)
1537 return -ENOMEM;
1538
1539 for (i = 0; i < count; i++)
1540 dc->debugfs_files[i].data = dc;
1541
1542 drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1543
1544 return 0;
1545}
1546
1547static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1548{
1549 unsigned int count = ARRAY_SIZE(debugfs_files);
1550 struct drm_minor *minor = crtc->dev->primary;
1551 struct tegra_dc *dc = to_tegra_dc(crtc);
1552
1553 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1554 kfree(dc->debugfs_files);
1555 dc->debugfs_files = NULL;
1556}
1557
1558static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1559{
1560 struct tegra_dc *dc = to_tegra_dc(crtc);
1561
1562 /* XXX vblank syncpoints don't work with nvdisplay yet */
1563 if (dc->syncpt && !dc->soc->has_nvdisplay)
1564 return host1x_syncpt_read(dc->syncpt);
1565
1566 /* fallback to software emulated VBLANK counter */
1567 return (u32)drm_crtc_vblank_count(&dc->base);
1568}
1569
1570static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1571{
1572 struct tegra_dc *dc = to_tegra_dc(crtc);
1573 u32 value;
1574
1575 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1576 value |= VBLANK_INT;
1577 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1578
1579 return 0;
1580}
1581
1582static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1583{
1584 struct tegra_dc *dc = to_tegra_dc(crtc);
1585 u32 value;
1586
1587 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1588 value &= ~VBLANK_INT;
1589 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1590}
1591
1592static const struct drm_crtc_funcs tegra_crtc_funcs = {
1593 .page_flip = drm_atomic_helper_page_flip,
1594 .set_config = drm_atomic_helper_set_config,
1595 .destroy = tegra_dc_destroy,
1596 .reset = tegra_crtc_reset,
1597 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1598 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1599 .late_register = tegra_dc_late_register,
1600 .early_unregister = tegra_dc_early_unregister,
1601 .get_vblank_counter = tegra_dc_get_vblank_counter,
1602 .enable_vblank = tegra_dc_enable_vblank,
1603 .disable_vblank = tegra_dc_disable_vblank,
1604};
1605
1606static int tegra_dc_set_timings(struct tegra_dc *dc,
1607 struct drm_display_mode *mode)
1608{
1609 unsigned int h_ref_to_sync = 1;
1610 unsigned int v_ref_to_sync = 1;
1611 unsigned long value;
1612
1613 if (!dc->soc->has_nvdisplay) {
1614 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1615
1616 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1617 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1618 }
1619
1620 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1621 ((mode->hsync_end - mode->hsync_start) << 0);
1622 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1623
1624 value = ((mode->vtotal - mode->vsync_end) << 16) |
1625 ((mode->htotal - mode->hsync_end) << 0);
1626 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1627
1628 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1629 ((mode->hsync_start - mode->hdisplay) << 0);
1630 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1631
1632 value = (mode->vdisplay << 16) | mode->hdisplay;
1633 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1634
1635 return 0;
1636}
1637
1638/**
1639 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1640 * state
1641 * @dc: display controller
1642 * @crtc_state: CRTC atomic state
1643 * @clk: parent clock for display controller
1644 * @pclk: pixel clock
1645 * @div: shift clock divider
1646 *
1647 * Returns:
1648 * 0 on success or a negative error-code on failure.
1649 */
1650int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1651 struct drm_crtc_state *crtc_state,
1652 struct clk *clk, unsigned long pclk,
1653 unsigned int div)
1654{
1655 struct tegra_dc_state *state = to_dc_state(crtc_state);
1656
1657 if (!clk_has_parent(dc->clk, clk))
1658 return -EINVAL;
1659
1660 state->clk = clk;
1661 state->pclk = pclk;
1662 state->div = div;
1663
1664 return 0;
1665}
1666
1667static void tegra_dc_commit_state(struct tegra_dc *dc,
1668 struct tegra_dc_state *state)
1669{
1670 u32 value;
1671 int err;
1672
1673 err = clk_set_parent(dc->clk, state->clk);
1674 if (err < 0)
1675 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1676
1677 /*
1678 * Outputs may not want to change the parent clock rate. This is only
1679 * relevant to Tegra20 where only a single display PLL is available.
1680 * Since that PLL would typically be used for HDMI, an internal LVDS
1681 * panel would need to be driven by some other clock such as PLL_P
1682 * which is shared with other peripherals. Changing the clock rate
1683 * should therefore be avoided.
1684 */
1685 if (state->pclk > 0) {
1686 err = clk_set_rate(state->clk, state->pclk);
1687 if (err < 0)
1688 dev_err(dc->dev,
1689 "failed to set clock rate to %lu Hz\n",
1690 state->pclk);
1691 }
1692
1693 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1694 state->div);
1695 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1696
1697 if (!dc->soc->has_nvdisplay) {
1698 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1699 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1700 }
1701
1702 err = clk_set_rate(dc->clk, state->pclk);
1703 if (err < 0)
1704 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1705 dc->clk, state->pclk, err);
1706}
1707
1708static void tegra_dc_stop(struct tegra_dc *dc)
1709{
1710 u32 value;
1711
1712 /* stop the display controller */
1713 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1714 value &= ~DISP_CTRL_MODE_MASK;
1715 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1716
1717 tegra_dc_commit(dc);
1718}
1719
1720static bool tegra_dc_idle(struct tegra_dc *dc)
1721{
1722 u32 value;
1723
1724 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1725
1726 return (value & DISP_CTRL_MODE_MASK) == 0;
1727}
1728
1729static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1730{
1731 timeout = jiffies + msecs_to_jiffies(timeout);
1732
1733 while (time_before(jiffies, timeout)) {
1734 if (tegra_dc_idle(dc))
1735 return 0;
1736
1737 usleep_range(1000, 2000);
1738 }
1739
1740 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1741 return -ETIMEDOUT;
1742}
1743
1744static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1745 struct drm_crtc_state *old_state)
1746{
1747 struct tegra_dc *dc = to_tegra_dc(crtc);
1748 u32 value;
1749 int err;
1750
1751 if (!tegra_dc_idle(dc)) {
1752 tegra_dc_stop(dc);
1753
1754 /*
1755 * Ignore the return value, there isn't anything useful to do
1756 * in case this fails.
1757 */
1758 tegra_dc_wait_idle(dc, 100);
1759 }
1760
1761 /*
1762 * This should really be part of the RGB encoder driver, but clearing
1763 * these bits has the side-effect of stopping the display controller.
1764 * When that happens no VBLANK interrupts will be raised. At the same
1765 * time the encoder is disabled before the display controller, so the
1766 * above code is always going to timeout waiting for the controller
1767 * to go idle.
1768 *
1769 * Given the close coupling between the RGB encoder and the display
1770 * controller doing it here is still kind of okay. None of the other
1771 * encoder drivers require these bits to be cleared.
1772 *
1773 * XXX: Perhaps given that the display controller is switched off at
1774 * this point anyway maybe clearing these bits isn't even useful for
1775 * the RGB encoder?
1776 */
1777 if (dc->rgb) {
1778 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1779 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1780 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1781 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1782 }
1783
1784 tegra_dc_stats_reset(&dc->stats);
1785 drm_crtc_vblank_off(crtc);
1786
1787 spin_lock_irq(&crtc->dev->event_lock);
1788
1789 if (crtc->state->event) {
1790 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1791 crtc->state->event = NULL;
1792 }
1793
1794 spin_unlock_irq(&crtc->dev->event_lock);
1795
1796 err = host1x_client_suspend(&dc->client);
1797 if (err < 0)
1798 dev_err(dc->dev, "failed to suspend: %d\n", err);
1799}
1800
1801static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1802 struct drm_crtc_state *old_state)
1803{
1804 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1805 struct tegra_dc_state *state = to_dc_state(crtc->state);
1806 struct tegra_dc *dc = to_tegra_dc(crtc);
1807 u32 value;
1808 int err;
1809
1810 err = host1x_client_resume(&dc->client);
1811 if (err < 0) {
1812 dev_err(dc->dev, "failed to resume: %d\n", err);
1813 return;
1814 }
1815
1816 /* initialize display controller */
1817 if (dc->syncpt) {
1818 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1819
1820 if (dc->soc->has_nvdisplay)
1821 enable = 1 << 31;
1822 else
1823 enable = 1 << 8;
1824
1825 value = SYNCPT_CNTRL_NO_STALL;
1826 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1827
1828 value = enable | syncpt;
1829 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1830 }
1831
1832 if (dc->soc->has_nvdisplay) {
1833 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1834 DSC_OBUF_UF_INT;
1835 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1836
1837 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1838 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1839 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1840 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1841 VBLANK_INT | FRAME_END_INT;
1842 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1843
1844 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1845 FRAME_END_INT;
1846 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1847
1848 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1849 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1850
1851 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1852 } else {
1853 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1854 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1855 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1856
1857 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1858 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1859 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1860
1861 /* initialize timer */
1862 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1863 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1864 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1865
1866 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1867 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1868 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1869
1870 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1871 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1872 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1873
1874 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1875 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1876 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1877 }
1878
1879 if (dc->soc->supports_background_color)
1880 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1881 else
1882 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1883
1884 /* apply PLL and pixel clock changes */
1885 tegra_dc_commit_state(dc, state);
1886
1887 /* program display mode */
1888 tegra_dc_set_timings(dc, mode);
1889
1890 /* interlacing isn't supported yet, so disable it */
1891 if (dc->soc->supports_interlacing) {
1892 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1893 value &= ~INTERLACE_ENABLE;
1894 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1895 }
1896
1897 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1898 value &= ~DISP_CTRL_MODE_MASK;
1899 value |= DISP_CTRL_MODE_C_DISPLAY;
1900 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1901
1902 if (!dc->soc->has_nvdisplay) {
1903 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1904 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1905 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1906 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1907 }
1908
1909 /* enable underflow reporting and display red for missing pixels */
1910 if (dc->soc->has_nvdisplay) {
1911 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1912 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1913 }
1914
1915 tegra_dc_commit(dc);
1916
1917 drm_crtc_vblank_on(crtc);
1918}
1919
1920static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1921 struct drm_crtc_state *old_crtc_state)
1922{
1923 unsigned long flags;
1924
1925 if (crtc->state->event) {
1926 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1927
1928 if (drm_crtc_vblank_get(crtc) != 0)
1929 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1930 else
1931 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1932
1933 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1934
1935 crtc->state->event = NULL;
1936 }
1937}
1938
1939static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1940 struct drm_crtc_state *old_crtc_state)
1941{
1942 struct tegra_dc_state *state = to_dc_state(crtc->state);
1943 struct tegra_dc *dc = to_tegra_dc(crtc);
1944 u32 value;
1945
1946 value = state->planes << 8 | GENERAL_UPDATE;
1947 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1948 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1949
1950 value = state->planes | GENERAL_ACT_REQ;
1951 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1952 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1953}
1954
1955static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1956 .atomic_begin = tegra_crtc_atomic_begin,
1957 .atomic_flush = tegra_crtc_atomic_flush,
1958 .atomic_enable = tegra_crtc_atomic_enable,
1959 .atomic_disable = tegra_crtc_atomic_disable,
1960};
1961
1962static irqreturn_t tegra_dc_irq(int irq, void *data)
1963{
1964 struct tegra_dc *dc = data;
1965 unsigned long status;
1966
1967 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1968 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1969
1970 if (status & FRAME_END_INT) {
1971 /*
1972 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1973 */
1974 dc->stats.frames++;
1975 }
1976
1977 if (status & VBLANK_INT) {
1978 /*
1979 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1980 */
1981 drm_crtc_handle_vblank(&dc->base);
1982 dc->stats.vblank++;
1983 }
1984
1985 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1986 /*
1987 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1988 */
1989 dc->stats.underflow++;
1990 }
1991
1992 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1993 /*
1994 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1995 */
1996 dc->stats.overflow++;
1997 }
1998
1999 if (status & HEAD_UF_INT) {
2000 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2001 dc->stats.underflow++;
2002 }
2003
2004 return IRQ_HANDLED;
2005}
2006
2007static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2008{
2009 unsigned int i;
2010
2011 if (!dc->soc->wgrps)
2012 return true;
2013
2014 for (i = 0; i < dc->soc->num_wgrps; i++) {
2015 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2016
2017 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2018 return true;
2019 }
2020
2021 return false;
2022}
2023
2024static int tegra_dc_init(struct host1x_client *client)
2025{
2026 struct drm_device *drm = dev_get_drvdata(client->host);
2027 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2028 struct tegra_dc *dc = host1x_client_to_dc(client);
2029 struct tegra_drm *tegra = drm->dev_private;
2030 struct drm_plane *primary = NULL;
2031 struct drm_plane *cursor = NULL;
2032 int err;
2033
2034 /*
2035 * XXX do not register DCs with no window groups because we cannot
2036 * assign a primary plane to them, which in turn will cause KMS to
2037 * crash.
2038 */
2039 if (!tegra_dc_has_window_groups(dc))
2040 return 0;
2041
2042 /*
2043 * Set the display hub as the host1x client parent for the display
2044 * controller. This is needed for the runtime reference counting that
2045 * ensures the display hub is always powered when any of the display
2046 * controllers are.
2047 */
2048 if (dc->soc->has_nvdisplay)
2049 client->parent = &tegra->hub->client;
2050
2051 dc->syncpt = host1x_syncpt_request(client, flags);
2052 if (!dc->syncpt)
2053 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2054
2055 err = host1x_client_iommu_attach(client);
2056 if (err < 0 && err != -ENODEV) {
2057 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2058 return err;
2059 }
2060
2061 if (dc->soc->wgrps)
2062 primary = tegra_dc_add_shared_planes(drm, dc);
2063 else
2064 primary = tegra_dc_add_planes(drm, dc);
2065
2066 if (IS_ERR(primary)) {
2067 err = PTR_ERR(primary);
2068 goto cleanup;
2069 }
2070
2071 if (dc->soc->supports_cursor) {
2072 cursor = tegra_dc_cursor_plane_create(drm, dc);
2073 if (IS_ERR(cursor)) {
2074 err = PTR_ERR(cursor);
2075 goto cleanup;
2076 }
2077 } else {
2078 /* dedicate one overlay to mouse cursor */
2079 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2080 if (IS_ERR(cursor)) {
2081 err = PTR_ERR(cursor);
2082 goto cleanup;
2083 }
2084 }
2085
2086 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2087 &tegra_crtc_funcs, NULL);
2088 if (err < 0)
2089 goto cleanup;
2090
2091 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2092
2093 /*
2094 * Keep track of the minimum pitch alignment across all display
2095 * controllers.
2096 */
2097 if (dc->soc->pitch_align > tegra->pitch_align)
2098 tegra->pitch_align = dc->soc->pitch_align;
2099
2100 err = tegra_dc_rgb_init(drm, dc);
2101 if (err < 0 && err != -ENODEV) {
2102 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2103 goto cleanup;
2104 }
2105
2106 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2107 dev_name(dc->dev), dc);
2108 if (err < 0) {
2109 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2110 err);
2111 goto cleanup;
2112 }
2113
2114 /*
2115 * Inherit the DMA parameters (such as maximum segment size) from the
2116 * parent host1x device.
2117 */
2118 client->dev->dma_parms = client->host->dma_parms;
2119
2120 return 0;
2121
2122cleanup:
2123 if (!IS_ERR_OR_NULL(cursor))
2124 drm_plane_cleanup(cursor);
2125
2126 if (!IS_ERR(primary))
2127 drm_plane_cleanup(primary);
2128
2129 host1x_client_iommu_detach(client);
2130 host1x_syncpt_free(dc->syncpt);
2131
2132 return err;
2133}
2134
2135static int tegra_dc_exit(struct host1x_client *client)
2136{
2137 struct tegra_dc *dc = host1x_client_to_dc(client);
2138 int err;
2139
2140 if (!tegra_dc_has_window_groups(dc))
2141 return 0;
2142
2143 /* avoid a dangling pointer just in case this disappears */
2144 client->dev->dma_parms = NULL;
2145
2146 devm_free_irq(dc->dev, dc->irq, dc);
2147
2148 err = tegra_dc_rgb_exit(dc);
2149 if (err) {
2150 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2151 return err;
2152 }
2153
2154 host1x_client_iommu_detach(client);
2155 host1x_syncpt_free(dc->syncpt);
2156
2157 return 0;
2158}
2159
2160static int tegra_dc_runtime_suspend(struct host1x_client *client)
2161{
2162 struct tegra_dc *dc = host1x_client_to_dc(client);
2163 struct device *dev = client->dev;
2164 int err;
2165
2166 err = reset_control_assert(dc->rst);
2167 if (err < 0) {
2168 dev_err(dev, "failed to assert reset: %d\n", err);
2169 return err;
2170 }
2171
2172 if (dc->soc->has_powergate)
2173 tegra_powergate_power_off(dc->powergate);
2174
2175 clk_disable_unprepare(dc->clk);
2176 pm_runtime_put_sync(dev);
2177
2178 return 0;
2179}
2180
2181static int tegra_dc_runtime_resume(struct host1x_client *client)
2182{
2183 struct tegra_dc *dc = host1x_client_to_dc(client);
2184 struct device *dev = client->dev;
2185 int err;
2186
2187 err = pm_runtime_get_sync(dev);
2188 if (err < 0) {
2189 dev_err(dev, "failed to get runtime PM: %d\n", err);
2190 return err;
2191 }
2192
2193 if (dc->soc->has_powergate) {
2194 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2195 dc->rst);
2196 if (err < 0) {
2197 dev_err(dev, "failed to power partition: %d\n", err);
2198 goto put_rpm;
2199 }
2200 } else {
2201 err = clk_prepare_enable(dc->clk);
2202 if (err < 0) {
2203 dev_err(dev, "failed to enable clock: %d\n", err);
2204 goto put_rpm;
2205 }
2206
2207 err = reset_control_deassert(dc->rst);
2208 if (err < 0) {
2209 dev_err(dev, "failed to deassert reset: %d\n", err);
2210 goto disable_clk;
2211 }
2212 }
2213
2214 return 0;
2215
2216disable_clk:
2217 clk_disable_unprepare(dc->clk);
2218put_rpm:
2219 pm_runtime_put_sync(dev);
2220 return err;
2221}
2222
2223static const struct host1x_client_ops dc_client_ops = {
2224 .init = tegra_dc_init,
2225 .exit = tegra_dc_exit,
2226 .suspend = tegra_dc_runtime_suspend,
2227 .resume = tegra_dc_runtime_resume,
2228};
2229
2230static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2231 .supports_background_color = false,
2232 .supports_interlacing = false,
2233 .supports_cursor = false,
2234 .supports_block_linear = false,
2235 .has_legacy_blending = true,
2236 .pitch_align = 8,
2237 .has_powergate = false,
2238 .coupled_pm = true,
2239 .has_nvdisplay = false,
2240 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2241 .primary_formats = tegra20_primary_formats,
2242 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2243 .overlay_formats = tegra20_overlay_formats,
2244 .modifiers = tegra20_modifiers,
2245 .has_win_a_without_filters = true,
2246 .has_win_c_without_vert_filter = true,
2247};
2248
2249static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2250 .supports_background_color = false,
2251 .supports_interlacing = false,
2252 .supports_cursor = false,
2253 .supports_block_linear = false,
2254 .has_legacy_blending = true,
2255 .pitch_align = 8,
2256 .has_powergate = false,
2257 .coupled_pm = false,
2258 .has_nvdisplay = false,
2259 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2260 .primary_formats = tegra20_primary_formats,
2261 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2262 .overlay_formats = tegra20_overlay_formats,
2263 .modifiers = tegra20_modifiers,
2264 .has_win_a_without_filters = false,
2265 .has_win_c_without_vert_filter = false,
2266};
2267
2268static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2269 .supports_background_color = false,
2270 .supports_interlacing = false,
2271 .supports_cursor = false,
2272 .supports_block_linear = false,
2273 .has_legacy_blending = true,
2274 .pitch_align = 64,
2275 .has_powergate = true,
2276 .coupled_pm = false,
2277 .has_nvdisplay = false,
2278 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2279 .primary_formats = tegra114_primary_formats,
2280 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2281 .overlay_formats = tegra114_overlay_formats,
2282 .modifiers = tegra20_modifiers,
2283 .has_win_a_without_filters = false,
2284 .has_win_c_without_vert_filter = false,
2285};
2286
2287static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2288 .supports_background_color = true,
2289 .supports_interlacing = true,
2290 .supports_cursor = true,
2291 .supports_block_linear = true,
2292 .has_legacy_blending = false,
2293 .pitch_align = 64,
2294 .has_powergate = true,
2295 .coupled_pm = false,
2296 .has_nvdisplay = false,
2297 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2298 .primary_formats = tegra124_primary_formats,
2299 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2300 .overlay_formats = tegra124_overlay_formats,
2301 .modifiers = tegra124_modifiers,
2302 .has_win_a_without_filters = false,
2303 .has_win_c_without_vert_filter = false,
2304};
2305
2306static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2307 .supports_background_color = true,
2308 .supports_interlacing = true,
2309 .supports_cursor = true,
2310 .supports_block_linear = true,
2311 .has_legacy_blending = false,
2312 .pitch_align = 64,
2313 .has_powergate = true,
2314 .coupled_pm = false,
2315 .has_nvdisplay = false,
2316 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2317 .primary_formats = tegra114_primary_formats,
2318 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2319 .overlay_formats = tegra114_overlay_formats,
2320 .modifiers = tegra124_modifiers,
2321 .has_win_a_without_filters = false,
2322 .has_win_c_without_vert_filter = false,
2323};
2324
2325static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2326 {
2327 .index = 0,
2328 .dc = 0,
2329 .windows = (const unsigned int[]) { 0 },
2330 .num_windows = 1,
2331 }, {
2332 .index = 1,
2333 .dc = 1,
2334 .windows = (const unsigned int[]) { 1 },
2335 .num_windows = 1,
2336 }, {
2337 .index = 2,
2338 .dc = 1,
2339 .windows = (const unsigned int[]) { 2 },
2340 .num_windows = 1,
2341 }, {
2342 .index = 3,
2343 .dc = 2,
2344 .windows = (const unsigned int[]) { 3 },
2345 .num_windows = 1,
2346 }, {
2347 .index = 4,
2348 .dc = 2,
2349 .windows = (const unsigned int[]) { 4 },
2350 .num_windows = 1,
2351 }, {
2352 .index = 5,
2353 .dc = 2,
2354 .windows = (const unsigned int[]) { 5 },
2355 .num_windows = 1,
2356 },
2357};
2358
2359static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2360 .supports_background_color = true,
2361 .supports_interlacing = true,
2362 .supports_cursor = true,
2363 .supports_block_linear = true,
2364 .has_legacy_blending = false,
2365 .pitch_align = 64,
2366 .has_powergate = false,
2367 .coupled_pm = false,
2368 .has_nvdisplay = true,
2369 .wgrps = tegra186_dc_wgrps,
2370 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2371};
2372
2373static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2374 {
2375 .index = 0,
2376 .dc = 0,
2377 .windows = (const unsigned int[]) { 0 },
2378 .num_windows = 1,
2379 }, {
2380 .index = 1,
2381 .dc = 1,
2382 .windows = (const unsigned int[]) { 1 },
2383 .num_windows = 1,
2384 }, {
2385 .index = 2,
2386 .dc = 1,
2387 .windows = (const unsigned int[]) { 2 },
2388 .num_windows = 1,
2389 }, {
2390 .index = 3,
2391 .dc = 2,
2392 .windows = (const unsigned int[]) { 3 },
2393 .num_windows = 1,
2394 }, {
2395 .index = 4,
2396 .dc = 2,
2397 .windows = (const unsigned int[]) { 4 },
2398 .num_windows = 1,
2399 }, {
2400 .index = 5,
2401 .dc = 2,
2402 .windows = (const unsigned int[]) { 5 },
2403 .num_windows = 1,
2404 },
2405};
2406
2407static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
2408 .supports_background_color = true,
2409 .supports_interlacing = true,
2410 .supports_cursor = true,
2411 .supports_block_linear = true,
2412 .has_legacy_blending = false,
2413 .pitch_align = 64,
2414 .has_powergate = false,
2415 .coupled_pm = false,
2416 .has_nvdisplay = true,
2417 .wgrps = tegra194_dc_wgrps,
2418 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
2419};
2420
2421static const struct of_device_id tegra_dc_of_match[] = {
2422 {
2423 .compatible = "nvidia,tegra194-dc",
2424 .data = &tegra194_dc_soc_info,
2425 }, {
2426 .compatible = "nvidia,tegra186-dc",
2427 .data = &tegra186_dc_soc_info,
2428 }, {
2429 .compatible = "nvidia,tegra210-dc",
2430 .data = &tegra210_dc_soc_info,
2431 }, {
2432 .compatible = "nvidia,tegra124-dc",
2433 .data = &tegra124_dc_soc_info,
2434 }, {
2435 .compatible = "nvidia,tegra114-dc",
2436 .data = &tegra114_dc_soc_info,
2437 }, {
2438 .compatible = "nvidia,tegra30-dc",
2439 .data = &tegra30_dc_soc_info,
2440 }, {
2441 .compatible = "nvidia,tegra20-dc",
2442 .data = &tegra20_dc_soc_info,
2443 }, {
2444 /* sentinel */
2445 }
2446};
2447MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
2448
2449static int tegra_dc_parse_dt(struct tegra_dc *dc)
2450{
2451 struct device_node *np;
2452 u32 value = 0;
2453 int err;
2454
2455 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
2456 if (err < 0) {
2457 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
2458
2459 /*
2460 * If the nvidia,head property isn't present, try to find the
2461 * correct head number by looking up the position of this
2462 * display controller's node within the device tree. Assuming
2463 * that the nodes are ordered properly in the DTS file and
2464 * that the translation into a flattened device tree blob
2465 * preserves that ordering this will actually yield the right
2466 * head number.
2467 *
2468 * If those assumptions don't hold, this will still work for
2469 * cases where only a single display controller is used.
2470 */
2471 for_each_matching_node(np, tegra_dc_of_match) {
2472 if (np == dc->dev->of_node) {
2473 of_node_put(np);
2474 break;
2475 }
2476
2477 value++;
2478 }
2479 }
2480
2481 dc->pipe = value;
2482
2483 return 0;
2484}
2485
2486static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
2487{
2488 struct tegra_dc *dc = dev_get_drvdata(dev);
2489 unsigned int pipe = (unsigned long)(void *)data;
2490
2491 return dc->pipe == pipe;
2492}
2493
2494static int tegra_dc_couple(struct tegra_dc *dc)
2495{
2496 /*
2497 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
2498 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
2499 * POWER_CONTROL registers during CRTC enabling.
2500 */
2501 if (dc->soc->coupled_pm && dc->pipe == 1) {
2502 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
2503 struct device_link *link;
2504 struct device *partner;
2505
2506 partner = driver_find_device(dc->dev->driver, NULL, NULL,
2507 tegra_dc_match_by_pipe);
2508 if (!partner)
2509 return -EPROBE_DEFER;
2510
2511 link = device_link_add(dc->dev, partner, flags);
2512 if (!link) {
2513 dev_err(dc->dev, "failed to link controllers\n");
2514 return -EINVAL;
2515 }
2516
2517 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
2518 }
2519
2520 return 0;
2521}
2522
2523static int tegra_dc_probe(struct platform_device *pdev)
2524{
2525 struct tegra_dc *dc;
2526 int err;
2527
2528 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2529 if (!dc)
2530 return -ENOMEM;
2531
2532 dc->soc = of_device_get_match_data(&pdev->dev);
2533
2534 INIT_LIST_HEAD(&dc->list);
2535 dc->dev = &pdev->dev;
2536
2537 err = tegra_dc_parse_dt(dc);
2538 if (err < 0)
2539 return err;
2540
2541 err = tegra_dc_couple(dc);
2542 if (err < 0)
2543 return err;
2544
2545 dc->clk = devm_clk_get(&pdev->dev, NULL);
2546 if (IS_ERR(dc->clk)) {
2547 dev_err(&pdev->dev, "failed to get clock\n");
2548 return PTR_ERR(dc->clk);
2549 }
2550
2551 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2552 if (IS_ERR(dc->rst)) {
2553 dev_err(&pdev->dev, "failed to get reset\n");
2554 return PTR_ERR(dc->rst);
2555 }
2556
2557 /* assert reset and disable clock */
2558 err = clk_prepare_enable(dc->clk);
2559 if (err < 0)
2560 return err;
2561
2562 usleep_range(2000, 4000);
2563
2564 err = reset_control_assert(dc->rst);
2565 if (err < 0)
2566 return err;
2567
2568 usleep_range(2000, 4000);
2569
2570 clk_disable_unprepare(dc->clk);
2571
2572 if (dc->soc->has_powergate) {
2573 if (dc->pipe == 0)
2574 dc->powergate = TEGRA_POWERGATE_DIS;
2575 else
2576 dc->powergate = TEGRA_POWERGATE_DISB;
2577
2578 tegra_powergate_power_off(dc->powergate);
2579 }
2580
2581 dc->regs = devm_platform_ioremap_resource(pdev, 0);
2582 if (IS_ERR(dc->regs))
2583 return PTR_ERR(dc->regs);
2584
2585 dc->irq = platform_get_irq(pdev, 0);
2586 if (dc->irq < 0)
2587 return -ENXIO;
2588
2589 err = tegra_dc_rgb_probe(dc);
2590 if (err < 0 && err != -ENODEV) {
2591 const char *level = KERN_ERR;
2592
2593 if (err == -EPROBE_DEFER)
2594 level = KERN_DEBUG;
2595
2596 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n",
2597 err);
2598 return err;
2599 }
2600
2601 platform_set_drvdata(pdev, dc);
2602 pm_runtime_enable(&pdev->dev);
2603
2604 INIT_LIST_HEAD(&dc->client.list);
2605 dc->client.ops = &dc_client_ops;
2606 dc->client.dev = &pdev->dev;
2607
2608 err = host1x_client_register(&dc->client);
2609 if (err < 0) {
2610 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2611 err);
2612 goto disable_pm;
2613 }
2614
2615 return 0;
2616
2617disable_pm:
2618 pm_runtime_disable(&pdev->dev);
2619 tegra_dc_rgb_remove(dc);
2620
2621 return err;
2622}
2623
2624static int tegra_dc_remove(struct platform_device *pdev)
2625{
2626 struct tegra_dc *dc = platform_get_drvdata(pdev);
2627 int err;
2628
2629 err = host1x_client_unregister(&dc->client);
2630 if (err < 0) {
2631 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2632 err);
2633 return err;
2634 }
2635
2636 err = tegra_dc_rgb_remove(dc);
2637 if (err < 0) {
2638 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2639 return err;
2640 }
2641
2642 pm_runtime_disable(&pdev->dev);
2643
2644 return 0;
2645}
2646
2647struct platform_driver tegra_dc_driver = {
2648 .driver = {
2649 .name = "tegra-dc",
2650 .of_match_table = tegra_dc_of_match,
2651 },
2652 .probe = tegra_dc_probe,
2653 .remove = tegra_dc_remove,
2654};