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1
2/*
3 * Texas Instruments AM35x "glue layer"
4 *
5 * Copyright (c) 2010, by Texas Instruments
6 *
7 * Based on the DA8xx "glue layer" code.
8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 *
10 * This file is part of the Inventra Controller Driver for Linux.
11 *
12 * The Inventra Controller Driver for Linux is free software; you
13 * can redistribute it and/or modify it under the terms of the GNU
14 * General Public License version 2 as published by the Free Software
15 * Foundation.
16 *
17 * The Inventra Controller Driver for Linux is distributed in
18 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
19 * without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
21 * License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with The Inventra Controller Driver for Linux ; if not,
25 * write to the Free Software Foundation, Inc., 59 Temple Place,
26 * Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30#include <linux/module.h>
31#include <linux/clk.h>
32#include <linux/err.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/dma-mapping.h>
36#include <linux/usb/usb_phy_generic.h>
37#include <linux/platform_data/usb-omap.h>
38
39#include "musb_core.h"
40
41/*
42 * AM35x specific definitions
43 */
44/* USB 2.0 OTG module registers */
45#define USB_REVISION_REG 0x00
46#define USB_CTRL_REG 0x04
47#define USB_STAT_REG 0x08
48#define USB_EMULATION_REG 0x0c
49/* 0x10 Reserved */
50#define USB_AUTOREQ_REG 0x14
51#define USB_SRP_FIX_TIME_REG 0x18
52#define USB_TEARDOWN_REG 0x1c
53#define EP_INTR_SRC_REG 0x20
54#define EP_INTR_SRC_SET_REG 0x24
55#define EP_INTR_SRC_CLEAR_REG 0x28
56#define EP_INTR_MASK_REG 0x2c
57#define EP_INTR_MASK_SET_REG 0x30
58#define EP_INTR_MASK_CLEAR_REG 0x34
59#define EP_INTR_SRC_MASKED_REG 0x38
60#define CORE_INTR_SRC_REG 0x40
61#define CORE_INTR_SRC_SET_REG 0x44
62#define CORE_INTR_SRC_CLEAR_REG 0x48
63#define CORE_INTR_MASK_REG 0x4c
64#define CORE_INTR_MASK_SET_REG 0x50
65#define CORE_INTR_MASK_CLEAR_REG 0x54
66#define CORE_INTR_SRC_MASKED_REG 0x58
67/* 0x5c Reserved */
68#define USB_END_OF_INTR_REG 0x60
69
70/* Control register bits */
71#define AM35X_SOFT_RESET_MASK 1
72
73/* USB interrupt register bits */
74#define AM35X_INTR_USB_SHIFT 16
75#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
76#define AM35X_INTR_DRVVBUS 0x100
77#define AM35X_INTR_RX_SHIFT 16
78#define AM35X_INTR_TX_SHIFT 0
79#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
80#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
81#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
82#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
83
84#define USB_MENTOR_CORE_OFFSET 0x400
85
86struct am35x_glue {
87 struct device *dev;
88 struct platform_device *musb;
89 struct platform_device *phy;
90 struct clk *phy_clk;
91 struct clk *clk;
92};
93
94/*
95 * am35x_musb_enable - enable interrupts
96 */
97static void am35x_musb_enable(struct musb *musb)
98{
99 void __iomem *reg_base = musb->ctrl_base;
100 u32 epmask;
101
102 /* Workaround: setup IRQs through both register sets. */
103 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
104 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
105
106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
108
109 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
111 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
112}
113
114/*
115 * am35x_musb_disable - disable HDRC and flush interrupts
116 */
117static void am35x_musb_disable(struct musb *musb)
118{
119 void __iomem *reg_base = musb->ctrl_base;
120
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
123 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
126}
127
128#define portstate(stmt) stmt
129
130static void am35x_musb_set_vbus(struct musb *musb, int is_on)
131{
132 WARN_ON(is_on && is_peripheral_active(musb));
133}
134
135#define POLL_SECONDS 2
136
137static struct timer_list otg_workaround;
138
139static void otg_timer(unsigned long _musb)
140{
141 struct musb *musb = (void *)_musb;
142 void __iomem *mregs = musb->mregs;
143 u8 devctl;
144 unsigned long flags;
145
146 /*
147 * We poll because AM35x's won't expose several OTG-critical
148 * status change events (from the transceiver) otherwise.
149 */
150 devctl = musb_readb(mregs, MUSB_DEVCTL);
151 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
152 usb_otg_state_string(musb->xceiv->otg->state));
153
154 spin_lock_irqsave(&musb->lock, flags);
155 switch (musb->xceiv->otg->state) {
156 case OTG_STATE_A_WAIT_BCON:
157 devctl &= ~MUSB_DEVCTL_SESSION;
158 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
159
160 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
161 if (devctl & MUSB_DEVCTL_BDEVICE) {
162 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
163 MUSB_DEV_MODE(musb);
164 } else {
165 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
166 MUSB_HST_MODE(musb);
167 }
168 break;
169 case OTG_STATE_A_WAIT_VFALL:
170 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
171 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
172 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
173 break;
174 case OTG_STATE_B_IDLE:
175 devctl = musb_readb(mregs, MUSB_DEVCTL);
176 if (devctl & MUSB_DEVCTL_BDEVICE)
177 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
178 else
179 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
180 break;
181 default:
182 break;
183 }
184 spin_unlock_irqrestore(&musb->lock, flags);
185}
186
187static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
188{
189 static unsigned long last_timer;
190
191 if (timeout == 0)
192 timeout = jiffies + msecs_to_jiffies(3);
193
194 /* Never idle if active, or when VBUS timeout is not set as host */
195 if (musb->is_active || (musb->a_wait_bcon == 0 &&
196 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
197 dev_dbg(musb->controller, "%s active, deleting timer\n",
198 usb_otg_state_string(musb->xceiv->otg->state));
199 del_timer(&otg_workaround);
200 last_timer = jiffies;
201 return;
202 }
203
204 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
205 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
206 return;
207 }
208 last_timer = timeout;
209
210 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
211 usb_otg_state_string(musb->xceiv->otg->state),
212 jiffies_to_msecs(timeout - jiffies));
213 mod_timer(&otg_workaround, timeout);
214}
215
216static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
217{
218 struct musb *musb = hci;
219 void __iomem *reg_base = musb->ctrl_base;
220 struct device *dev = musb->controller;
221 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
222 struct omap_musb_board_data *data = plat->board_data;
223 struct usb_otg *otg = musb->xceiv->otg;
224 unsigned long flags;
225 irqreturn_t ret = IRQ_NONE;
226 u32 epintr, usbintr;
227
228 spin_lock_irqsave(&musb->lock, flags);
229
230 /* Get endpoint interrupts */
231 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
232
233 if (epintr) {
234 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
235
236 musb->int_rx =
237 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
238 musb->int_tx =
239 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
240 }
241
242 /* Get usb core interrupts */
243 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
244 if (!usbintr && !epintr)
245 goto eoi;
246
247 if (usbintr) {
248 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
249
250 musb->int_usb =
251 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
252 }
253 /*
254 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
255 * AM35x's missing ID change IRQ. We need an ID change IRQ to
256 * switch appropriately between halves of the OTG state machine.
257 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
258 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
259 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
260 */
261 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
262 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
263 void __iomem *mregs = musb->mregs;
264 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
265 int err;
266
267 err = musb->int_usb & MUSB_INTR_VBUSERROR;
268 if (err) {
269 /*
270 * The Mentor core doesn't debounce VBUS as needed
271 * to cope with device connect current spikes. This
272 * means it's not uncommon for bus-powered devices
273 * to get VBUS errors during enumeration.
274 *
275 * This is a workaround, but newer RTL from Mentor
276 * seems to allow a better one: "re"-starting sessions
277 * without waiting for VBUS to stop registering in
278 * devctl.
279 */
280 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
281 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
282 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
283 WARNING("VBUS error workaround (delay coming)\n");
284 } else if (drvvbus) {
285 MUSB_HST_MODE(musb);
286 otg->default_a = 1;
287 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
288 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
289 del_timer(&otg_workaround);
290 } else {
291 musb->is_active = 0;
292 MUSB_DEV_MODE(musb);
293 otg->default_a = 0;
294 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
295 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
296 }
297
298 /* NOTE: this must complete power-on within 100 ms. */
299 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
300 drvvbus ? "on" : "off",
301 usb_otg_state_string(musb->xceiv->otg->state),
302 err ? " ERROR" : "",
303 devctl);
304 ret = IRQ_HANDLED;
305 }
306
307 /* Drop spurious RX and TX if device is disconnected */
308 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
309 musb->int_tx = 0;
310 musb->int_rx = 0;
311 }
312
313 if (musb->int_tx || musb->int_rx || musb->int_usb)
314 ret |= musb_interrupt(musb);
315
316eoi:
317 /* EOI needs to be written for the IRQ to be re-asserted. */
318 if (ret == IRQ_HANDLED || epintr || usbintr) {
319 /* clear level interrupt */
320 if (data->clear_irq)
321 data->clear_irq();
322 /* write EOI */
323 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
324 }
325
326 /* Poll for ID change */
327 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
328 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
329
330 spin_unlock_irqrestore(&musb->lock, flags);
331
332 return ret;
333}
334
335static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
336{
337 struct device *dev = musb->controller;
338 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
339 struct omap_musb_board_data *data = plat->board_data;
340 int retval = 0;
341
342 if (data->set_mode)
343 data->set_mode(musb_mode);
344 else
345 retval = -EIO;
346
347 return retval;
348}
349
350static int am35x_musb_init(struct musb *musb)
351{
352 struct device *dev = musb->controller;
353 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
354 struct omap_musb_board_data *data = plat->board_data;
355 void __iomem *reg_base = musb->ctrl_base;
356 u32 rev;
357
358 musb->mregs += USB_MENTOR_CORE_OFFSET;
359
360 /* Returns zero if e.g. not clocked */
361 rev = musb_readl(reg_base, USB_REVISION_REG);
362 if (!rev)
363 return -ENODEV;
364
365 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
366 if (IS_ERR_OR_NULL(musb->xceiv))
367 return -EPROBE_DEFER;
368
369 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
370
371 /* Reset the musb */
372 if (data->reset)
373 data->reset();
374
375 /* Reset the controller */
376 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
377
378 /* Start the on-chip PHY and its PLL. */
379 if (data->set_phy_power)
380 data->set_phy_power(1);
381
382 msleep(5);
383
384 musb->isr = am35x_musb_interrupt;
385
386 /* clear level interrupt */
387 if (data->clear_irq)
388 data->clear_irq();
389
390 return 0;
391}
392
393static int am35x_musb_exit(struct musb *musb)
394{
395 struct device *dev = musb->controller;
396 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
397 struct omap_musb_board_data *data = plat->board_data;
398
399 del_timer_sync(&otg_workaround);
400
401 /* Shutdown the on-chip PHY and its PLL. */
402 if (data->set_phy_power)
403 data->set_phy_power(0);
404
405 usb_put_phy(musb->xceiv);
406
407 return 0;
408}
409
410/* AM35x supports only 32bit read operation */
411static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
412{
413 void __iomem *fifo = hw_ep->fifo;
414 u32 val;
415 int i;
416
417 /* Read for 32bit-aligned destination address */
418 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
419 readsl(fifo, dst, len >> 2);
420 dst += len & ~0x03;
421 len &= 0x03;
422 }
423 /*
424 * Now read the remaining 1 to 3 byte or complete length if
425 * unaligned address.
426 */
427 if (len > 4) {
428 for (i = 0; i < (len >> 2); i++) {
429 *(u32 *) dst = musb_readl(fifo, 0);
430 dst += 4;
431 }
432 len &= 0x03;
433 }
434 if (len > 0) {
435 val = musb_readl(fifo, 0);
436 memcpy(dst, &val, len);
437 }
438}
439
440static const struct musb_platform_ops am35x_ops = {
441 .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
442 .init = am35x_musb_init,
443 .exit = am35x_musb_exit,
444
445 .read_fifo = am35x_read_fifo,
446#ifdef CONFIG_USB_INVENTRA_DMA
447 .dma_init = musbhs_dma_controller_create,
448 .dma_exit = musbhs_dma_controller_destroy,
449#endif
450 .enable = am35x_musb_enable,
451 .disable = am35x_musb_disable,
452
453 .set_mode = am35x_musb_set_mode,
454 .try_idle = am35x_musb_try_idle,
455
456 .set_vbus = am35x_musb_set_vbus,
457};
458
459static const struct platform_device_info am35x_dev_info = {
460 .name = "musb-hdrc",
461 .id = PLATFORM_DEVID_AUTO,
462 .dma_mask = DMA_BIT_MASK(32),
463};
464
465static int am35x_probe(struct platform_device *pdev)
466{
467 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
468 struct platform_device *musb;
469 struct am35x_glue *glue;
470 struct platform_device_info pinfo;
471 struct clk *phy_clk;
472 struct clk *clk;
473
474 int ret = -ENOMEM;
475
476 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
477 if (!glue) {
478 dev_err(&pdev->dev, "failed to allocate glue context\n");
479 goto err0;
480 }
481
482 phy_clk = clk_get(&pdev->dev, "fck");
483 if (IS_ERR(phy_clk)) {
484 dev_err(&pdev->dev, "failed to get PHY clock\n");
485 ret = PTR_ERR(phy_clk);
486 goto err3;
487 }
488
489 clk = clk_get(&pdev->dev, "ick");
490 if (IS_ERR(clk)) {
491 dev_err(&pdev->dev, "failed to get clock\n");
492 ret = PTR_ERR(clk);
493 goto err4;
494 }
495
496 ret = clk_enable(phy_clk);
497 if (ret) {
498 dev_err(&pdev->dev, "failed to enable PHY clock\n");
499 goto err5;
500 }
501
502 ret = clk_enable(clk);
503 if (ret) {
504 dev_err(&pdev->dev, "failed to enable clock\n");
505 goto err6;
506 }
507
508 glue->dev = &pdev->dev;
509 glue->phy_clk = phy_clk;
510 glue->clk = clk;
511
512 pdata->platform_ops = &am35x_ops;
513
514 glue->phy = usb_phy_generic_register();
515 if (IS_ERR(glue->phy))
516 goto err7;
517 platform_set_drvdata(pdev, glue);
518
519 pinfo = am35x_dev_info;
520 pinfo.parent = &pdev->dev;
521 pinfo.res = pdev->resource;
522 pinfo.num_res = pdev->num_resources;
523 pinfo.data = pdata;
524 pinfo.size_data = sizeof(*pdata);
525
526 glue->musb = musb = platform_device_register_full(&pinfo);
527 if (IS_ERR(musb)) {
528 ret = PTR_ERR(musb);
529 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
530 goto err8;
531 }
532
533 return 0;
534
535err8:
536 usb_phy_generic_unregister(glue->phy);
537
538err7:
539 clk_disable(clk);
540
541err6:
542 clk_disable(phy_clk);
543
544err5:
545 clk_put(clk);
546
547err4:
548 clk_put(phy_clk);
549
550err3:
551 kfree(glue);
552
553err0:
554 return ret;
555}
556
557static int am35x_remove(struct platform_device *pdev)
558{
559 struct am35x_glue *glue = platform_get_drvdata(pdev);
560
561 platform_device_unregister(glue->musb);
562 usb_phy_generic_unregister(glue->phy);
563 clk_disable(glue->clk);
564 clk_disable(glue->phy_clk);
565 clk_put(glue->clk);
566 clk_put(glue->phy_clk);
567 kfree(glue);
568
569 return 0;
570}
571
572#ifdef CONFIG_PM_SLEEP
573static int am35x_suspend(struct device *dev)
574{
575 struct am35x_glue *glue = dev_get_drvdata(dev);
576 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
577 struct omap_musb_board_data *data = plat->board_data;
578
579 /* Shutdown the on-chip PHY and its PLL. */
580 if (data->set_phy_power)
581 data->set_phy_power(0);
582
583 clk_disable(glue->phy_clk);
584 clk_disable(glue->clk);
585
586 return 0;
587}
588
589static int am35x_resume(struct device *dev)
590{
591 struct am35x_glue *glue = dev_get_drvdata(dev);
592 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
593 struct omap_musb_board_data *data = plat->board_data;
594 int ret;
595
596 /* Start the on-chip PHY and its PLL. */
597 if (data->set_phy_power)
598 data->set_phy_power(1);
599
600 ret = clk_enable(glue->phy_clk);
601 if (ret) {
602 dev_err(dev, "failed to enable PHY clock\n");
603 return ret;
604 }
605
606 ret = clk_enable(glue->clk);
607 if (ret) {
608 dev_err(dev, "failed to enable clock\n");
609 return ret;
610 }
611
612 return 0;
613}
614#endif
615
616static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
617
618static struct platform_driver am35x_driver = {
619 .probe = am35x_probe,
620 .remove = am35x_remove,
621 .driver = {
622 .name = "musb-am35x",
623 .pm = &am35x_pm_ops,
624 },
625};
626
627MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
628MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
629MODULE_LICENSE("GPL v2");
630module_platform_driver(am35x_driver);
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Texas Instruments AM35x "glue layer"
5 *
6 * Copyright (c) 2010, by Texas Instruments
7 *
8 * Based on the DA8xx "glue layer" code.
9 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
10 *
11 * This file is part of the Inventra Controller Driver for Linux.
12 */
13
14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/usb/usb_phy_generic.h>
21#include <linux/platform_data/usb-omap.h>
22
23#include "musb_core.h"
24
25/*
26 * AM35x specific definitions
27 */
28/* USB 2.0 OTG module registers */
29#define USB_REVISION_REG 0x00
30#define USB_CTRL_REG 0x04
31#define USB_STAT_REG 0x08
32#define USB_EMULATION_REG 0x0c
33/* 0x10 Reserved */
34#define USB_AUTOREQ_REG 0x14
35#define USB_SRP_FIX_TIME_REG 0x18
36#define USB_TEARDOWN_REG 0x1c
37#define EP_INTR_SRC_REG 0x20
38#define EP_INTR_SRC_SET_REG 0x24
39#define EP_INTR_SRC_CLEAR_REG 0x28
40#define EP_INTR_MASK_REG 0x2c
41#define EP_INTR_MASK_SET_REG 0x30
42#define EP_INTR_MASK_CLEAR_REG 0x34
43#define EP_INTR_SRC_MASKED_REG 0x38
44#define CORE_INTR_SRC_REG 0x40
45#define CORE_INTR_SRC_SET_REG 0x44
46#define CORE_INTR_SRC_CLEAR_REG 0x48
47#define CORE_INTR_MASK_REG 0x4c
48#define CORE_INTR_MASK_SET_REG 0x50
49#define CORE_INTR_MASK_CLEAR_REG 0x54
50#define CORE_INTR_SRC_MASKED_REG 0x58
51/* 0x5c Reserved */
52#define USB_END_OF_INTR_REG 0x60
53
54/* Control register bits */
55#define AM35X_SOFT_RESET_MASK 1
56
57/* USB interrupt register bits */
58#define AM35X_INTR_USB_SHIFT 16
59#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
60#define AM35X_INTR_DRVVBUS 0x100
61#define AM35X_INTR_RX_SHIFT 16
62#define AM35X_INTR_TX_SHIFT 0
63#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
64#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
65#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
66#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
67
68#define USB_MENTOR_CORE_OFFSET 0x400
69
70struct am35x_glue {
71 struct device *dev;
72 struct platform_device *musb;
73 struct platform_device *phy;
74 struct clk *phy_clk;
75 struct clk *clk;
76};
77
78/*
79 * am35x_musb_enable - enable interrupts
80 */
81static void am35x_musb_enable(struct musb *musb)
82{
83 void __iomem *reg_base = musb->ctrl_base;
84 u32 epmask;
85
86 /* Workaround: setup IRQs through both register sets. */
87 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
88 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
89
90 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
91 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
92
93 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
94 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
95 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
96}
97
98/*
99 * am35x_musb_disable - disable HDRC and flush interrupts
100 */
101static void am35x_musb_disable(struct musb *musb)
102{
103 void __iomem *reg_base = musb->ctrl_base;
104
105 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
106 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
107 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
108 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
109}
110
111#define portstate(stmt) stmt
112
113static void am35x_musb_set_vbus(struct musb *musb, int is_on)
114{
115 WARN_ON(is_on && is_peripheral_active(musb));
116}
117
118#define POLL_SECONDS 2
119
120static void otg_timer(struct timer_list *t)
121{
122 struct musb *musb = from_timer(musb, t, dev_timer);
123 void __iomem *mregs = musb->mregs;
124 u8 devctl;
125 unsigned long flags;
126
127 /*
128 * We poll because AM35x's won't expose several OTG-critical
129 * status change events (from the transceiver) otherwise.
130 */
131 devctl = musb_readb(mregs, MUSB_DEVCTL);
132 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
133 usb_otg_state_string(musb->xceiv->otg->state));
134
135 spin_lock_irqsave(&musb->lock, flags);
136 switch (musb->xceiv->otg->state) {
137 case OTG_STATE_A_WAIT_BCON:
138 devctl &= ~MUSB_DEVCTL_SESSION;
139 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
140
141 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
142 if (devctl & MUSB_DEVCTL_BDEVICE) {
143 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
144 MUSB_DEV_MODE(musb);
145 } else {
146 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
147 MUSB_HST_MODE(musb);
148 }
149 break;
150 case OTG_STATE_A_WAIT_VFALL:
151 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
152 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
153 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
154 break;
155 case OTG_STATE_B_IDLE:
156 devctl = musb_readb(mregs, MUSB_DEVCTL);
157 if (devctl & MUSB_DEVCTL_BDEVICE)
158 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
159 else
160 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
161 break;
162 default:
163 break;
164 }
165 spin_unlock_irqrestore(&musb->lock, flags);
166}
167
168static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
169{
170 static unsigned long last_timer;
171
172 if (timeout == 0)
173 timeout = jiffies + msecs_to_jiffies(3);
174
175 /* Never idle if active, or when VBUS timeout is not set as host */
176 if (musb->is_active || (musb->a_wait_bcon == 0 &&
177 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
178 dev_dbg(musb->controller, "%s active, deleting timer\n",
179 usb_otg_state_string(musb->xceiv->otg->state));
180 del_timer(&musb->dev_timer);
181 last_timer = jiffies;
182 return;
183 }
184
185 if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) {
186 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
187 return;
188 }
189 last_timer = timeout;
190
191 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
192 usb_otg_state_string(musb->xceiv->otg->state),
193 jiffies_to_msecs(timeout - jiffies));
194 mod_timer(&musb->dev_timer, timeout);
195}
196
197static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
198{
199 struct musb *musb = hci;
200 void __iomem *reg_base = musb->ctrl_base;
201 struct device *dev = musb->controller;
202 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
203 struct omap_musb_board_data *data = plat->board_data;
204 unsigned long flags;
205 irqreturn_t ret = IRQ_NONE;
206 u32 epintr, usbintr;
207
208 spin_lock_irqsave(&musb->lock, flags);
209
210 /* Get endpoint interrupts */
211 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
212
213 if (epintr) {
214 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
215
216 musb->int_rx =
217 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
218 musb->int_tx =
219 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
220 }
221
222 /* Get usb core interrupts */
223 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
224 if (!usbintr && !epintr)
225 goto eoi;
226
227 if (usbintr) {
228 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
229
230 musb->int_usb =
231 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
232 }
233 /*
234 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
235 * AM35x's missing ID change IRQ. We need an ID change IRQ to
236 * switch appropriately between halves of the OTG state machine.
237 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
238 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
239 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
240 */
241 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
242 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
243 void __iomem *mregs = musb->mregs;
244 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
245 int err;
246
247 err = musb->int_usb & MUSB_INTR_VBUSERROR;
248 if (err) {
249 /*
250 * The Mentor core doesn't debounce VBUS as needed
251 * to cope with device connect current spikes. This
252 * means it's not uncommon for bus-powered devices
253 * to get VBUS errors during enumeration.
254 *
255 * This is a workaround, but newer RTL from Mentor
256 * seems to allow a better one: "re"-starting sessions
257 * without waiting for VBUS to stop registering in
258 * devctl.
259 */
260 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
261 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
262 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
263 WARNING("VBUS error workaround (delay coming)\n");
264 } else if (drvvbus) {
265 MUSB_HST_MODE(musb);
266 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
267 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
268 del_timer(&musb->dev_timer);
269 } else {
270 musb->is_active = 0;
271 MUSB_DEV_MODE(musb);
272 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
273 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
274 }
275
276 /* NOTE: this must complete power-on within 100 ms. */
277 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
278 drvvbus ? "on" : "off",
279 usb_otg_state_string(musb->xceiv->otg->state),
280 err ? " ERROR" : "",
281 devctl);
282 ret = IRQ_HANDLED;
283 }
284
285 /* Drop spurious RX and TX if device is disconnected */
286 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
287 musb->int_tx = 0;
288 musb->int_rx = 0;
289 }
290
291 if (musb->int_tx || musb->int_rx || musb->int_usb)
292 ret |= musb_interrupt(musb);
293
294eoi:
295 /* EOI needs to be written for the IRQ to be re-asserted. */
296 if (ret == IRQ_HANDLED || epintr || usbintr) {
297 /* clear level interrupt */
298 if (data->clear_irq)
299 data->clear_irq();
300 /* write EOI */
301 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
302 }
303
304 /* Poll for ID change */
305 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
306 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
307
308 spin_unlock_irqrestore(&musb->lock, flags);
309
310 return ret;
311}
312
313static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
314{
315 struct device *dev = musb->controller;
316 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
317 struct omap_musb_board_data *data = plat->board_data;
318 int retval = 0;
319
320 if (data->set_mode)
321 data->set_mode(musb_mode);
322 else
323 retval = -EIO;
324
325 return retval;
326}
327
328static int am35x_musb_init(struct musb *musb)
329{
330 struct device *dev = musb->controller;
331 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
332 struct omap_musb_board_data *data = plat->board_data;
333 void __iomem *reg_base = musb->ctrl_base;
334 u32 rev;
335
336 musb->mregs += USB_MENTOR_CORE_OFFSET;
337
338 /* Returns zero if e.g. not clocked */
339 rev = musb_readl(reg_base, USB_REVISION_REG);
340 if (!rev)
341 return -ENODEV;
342
343 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
344 if (IS_ERR_OR_NULL(musb->xceiv))
345 return -EPROBE_DEFER;
346
347 timer_setup(&musb->dev_timer, otg_timer, 0);
348
349 /* Reset the musb */
350 if (data->reset)
351 data->reset();
352
353 /* Reset the controller */
354 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
355
356 /* Start the on-chip PHY and its PLL. */
357 if (data->set_phy_power)
358 data->set_phy_power(1);
359
360 msleep(5);
361
362 musb->isr = am35x_musb_interrupt;
363
364 /* clear level interrupt */
365 if (data->clear_irq)
366 data->clear_irq();
367
368 return 0;
369}
370
371static int am35x_musb_exit(struct musb *musb)
372{
373 struct device *dev = musb->controller;
374 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
375 struct omap_musb_board_data *data = plat->board_data;
376
377 del_timer_sync(&musb->dev_timer);
378
379 /* Shutdown the on-chip PHY and its PLL. */
380 if (data->set_phy_power)
381 data->set_phy_power(0);
382
383 usb_put_phy(musb->xceiv);
384
385 return 0;
386}
387
388/* AM35x supports only 32bit read operation */
389static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
390{
391 void __iomem *fifo = hw_ep->fifo;
392 u32 val;
393 int i;
394
395 /* Read for 32bit-aligned destination address */
396 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
397 readsl(fifo, dst, len >> 2);
398 dst += len & ~0x03;
399 len &= 0x03;
400 }
401 /*
402 * Now read the remaining 1 to 3 byte or complete length if
403 * unaligned address.
404 */
405 if (len > 4) {
406 for (i = 0; i < (len >> 2); i++) {
407 *(u32 *) dst = musb_readl(fifo, 0);
408 dst += 4;
409 }
410 len &= 0x03;
411 }
412 if (len > 0) {
413 val = musb_readl(fifo, 0);
414 memcpy(dst, &val, len);
415 }
416}
417
418static const struct musb_platform_ops am35x_ops = {
419 .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
420 .init = am35x_musb_init,
421 .exit = am35x_musb_exit,
422
423 .read_fifo = am35x_read_fifo,
424#ifdef CONFIG_USB_INVENTRA_DMA
425 .dma_init = musbhs_dma_controller_create,
426 .dma_exit = musbhs_dma_controller_destroy,
427#endif
428 .enable = am35x_musb_enable,
429 .disable = am35x_musb_disable,
430
431 .set_mode = am35x_musb_set_mode,
432 .try_idle = am35x_musb_try_idle,
433
434 .set_vbus = am35x_musb_set_vbus,
435};
436
437static const struct platform_device_info am35x_dev_info = {
438 .name = "musb-hdrc",
439 .id = PLATFORM_DEVID_AUTO,
440 .dma_mask = DMA_BIT_MASK(32),
441};
442
443static int am35x_probe(struct platform_device *pdev)
444{
445 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
446 struct platform_device *musb;
447 struct am35x_glue *glue;
448 struct platform_device_info pinfo;
449 struct clk *phy_clk;
450 struct clk *clk;
451
452 int ret = -ENOMEM;
453
454 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
455 if (!glue)
456 goto err0;
457
458 phy_clk = clk_get(&pdev->dev, "fck");
459 if (IS_ERR(phy_clk)) {
460 dev_err(&pdev->dev, "failed to get PHY clock\n");
461 ret = PTR_ERR(phy_clk);
462 goto err3;
463 }
464
465 clk = clk_get(&pdev->dev, "ick");
466 if (IS_ERR(clk)) {
467 dev_err(&pdev->dev, "failed to get clock\n");
468 ret = PTR_ERR(clk);
469 goto err4;
470 }
471
472 ret = clk_enable(phy_clk);
473 if (ret) {
474 dev_err(&pdev->dev, "failed to enable PHY clock\n");
475 goto err5;
476 }
477
478 ret = clk_enable(clk);
479 if (ret) {
480 dev_err(&pdev->dev, "failed to enable clock\n");
481 goto err6;
482 }
483
484 glue->dev = &pdev->dev;
485 glue->phy_clk = phy_clk;
486 glue->clk = clk;
487
488 pdata->platform_ops = &am35x_ops;
489
490 glue->phy = usb_phy_generic_register();
491 if (IS_ERR(glue->phy)) {
492 ret = PTR_ERR(glue->phy);
493 goto err7;
494 }
495 platform_set_drvdata(pdev, glue);
496
497 pinfo = am35x_dev_info;
498 pinfo.parent = &pdev->dev;
499 pinfo.res = pdev->resource;
500 pinfo.num_res = pdev->num_resources;
501 pinfo.data = pdata;
502 pinfo.size_data = sizeof(*pdata);
503
504 glue->musb = musb = platform_device_register_full(&pinfo);
505 if (IS_ERR(musb)) {
506 ret = PTR_ERR(musb);
507 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
508 goto err8;
509 }
510
511 return 0;
512
513err8:
514 usb_phy_generic_unregister(glue->phy);
515
516err7:
517 clk_disable(clk);
518
519err6:
520 clk_disable(phy_clk);
521
522err5:
523 clk_put(clk);
524
525err4:
526 clk_put(phy_clk);
527
528err3:
529 kfree(glue);
530
531err0:
532 return ret;
533}
534
535static int am35x_remove(struct platform_device *pdev)
536{
537 struct am35x_glue *glue = platform_get_drvdata(pdev);
538
539 platform_device_unregister(glue->musb);
540 usb_phy_generic_unregister(glue->phy);
541 clk_disable(glue->clk);
542 clk_disable(glue->phy_clk);
543 clk_put(glue->clk);
544 clk_put(glue->phy_clk);
545 kfree(glue);
546
547 return 0;
548}
549
550#ifdef CONFIG_PM_SLEEP
551static int am35x_suspend(struct device *dev)
552{
553 struct am35x_glue *glue = dev_get_drvdata(dev);
554 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
555 struct omap_musb_board_data *data = plat->board_data;
556
557 /* Shutdown the on-chip PHY and its PLL. */
558 if (data->set_phy_power)
559 data->set_phy_power(0);
560
561 clk_disable(glue->phy_clk);
562 clk_disable(glue->clk);
563
564 return 0;
565}
566
567static int am35x_resume(struct device *dev)
568{
569 struct am35x_glue *glue = dev_get_drvdata(dev);
570 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
571 struct omap_musb_board_data *data = plat->board_data;
572 int ret;
573
574 /* Start the on-chip PHY and its PLL. */
575 if (data->set_phy_power)
576 data->set_phy_power(1);
577
578 ret = clk_enable(glue->phy_clk);
579 if (ret) {
580 dev_err(dev, "failed to enable PHY clock\n");
581 return ret;
582 }
583
584 ret = clk_enable(glue->clk);
585 if (ret) {
586 dev_err(dev, "failed to enable clock\n");
587 return ret;
588 }
589
590 return 0;
591}
592#endif
593
594static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
595
596static struct platform_driver am35x_driver = {
597 .probe = am35x_probe,
598 .remove = am35x_remove,
599 .driver = {
600 .name = "musb-am35x",
601 .pm = &am35x_pm_ops,
602 },
603};
604
605MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
606MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
607MODULE_LICENSE("GPL v2");
608module_platform_driver(am35x_driver);